JP4494451B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a structure of a semiconductor device including a semiconductor circuit made of a semiconductor element such as an insulated gate transistor and a manufacturing method thereof. In particular, the present invention relates to a structure of a semiconductor device including a semiconductor circuit including a semiconductor element having an LDD structure formed using an organic resin and a manufacturing method thereof. The semiconductor device of the present invention includes not only an element such as a thin film transistor (TFT) and a MOS transistor but also an electro-optical device such as a display device and an image sensor having a semiconductor circuit composed of these insulated gate transistors. In addition, the semiconductor device of the present invention includes an electronic apparatus in which these display device and electro-optical device are mounted.

  An active matrix liquid crystal display in which a pixel matrix circuit and a driving circuit are formed by thin film transistors (TFTs) formed over an insulating substrate has been attracting attention. Liquid crystal displays of up to about 0.5 to 20 inches are used as display displays.

  At present, in order to realize a liquid crystal display capable of high-definition display, a TFT using a crystalline semiconductor film typified by polysilicon as an active layer is attracting attention. However, TFTs that use a crystalline semiconductor film as an active layer have higher operating speed and drive capability than TFTs that use an amorphous semiconductor film as an active layer, but there is a problem that variations in individual TFT characteristics are large. It was.

  One of the causes of this variation in TFT characteristics is the interface between the active layer and the gate insulating film. If this interface is contaminated, the TFT characteristics are adversely affected. Therefore, it is important to clean the interface between the active layer and the insulating film in contact with the active layer.

  Currently, high mobility is required for TFTs, and it is considered promising to use a crystalline semiconductor film having higher mobility than an amorphous semiconductor film as an active layer of the TFT. A conventional TFT manufacturing method will be briefly and briefly described below.

  First, a gate wiring is formed on an insulating substrate, a gate insulating film and an amorphous silicon film are laminated thereon, and this amorphous silicon film is subjected to crystallization treatment such as heating or laser light irradiation to form a polysilicon film. To do. Next, the polysilicon film is patterned into a desired shape to form an active layer. Next, an impurity imparting P-type or N-type conductivity is selectively introduced into the polysilicon film to form impurity regions that serve as a source region and a drain region. Subsequently, after depositing an interlayer insulating film and forming contact holes that expose the source and drain regions, a metal film is formed and patterned to form metal wiring that contacts the source and drain regions. To do. Thus, the TFT manufacturing process is completed.

  As described above, since the insulating film is conventionally formed after several steps (for example, a crystallization step and a patterning step) after the formation of the amorphous semiconductor film, the amorphous semiconductor film is formed. Was exposed to the atmosphere.

In particular, the atmosphere in the clean room mainly contains boron (boron) from a HEPA filter generally used for cleaning, and when the active layer is exposed to the atmosphere, it is mixed in an indefinite amount in the active layer. Conventionally, the active layer is produced by exposing the active layer to the atmosphere. When SIMS analysis is performed, the concentration peak of boron (dotted line B in FIG. 14) is present at the interface (main surface side or back side) of the active layer of the TFT. The maximum value was 1 × 10 ¹⁸ atoms / cm ³ or more. If boron is mixed in the active layer in this way, it becomes difficult to control the impurity concentration in the active layer, which causes variations in the threshold value of the TFT. In addition, the use of other filters is not suitable because of high cost.

  As described above, conventionally, after the semiconductor film is formed, the surface of the semiconductor film is exposed to the atmosphere, and the semiconductor film which becomes the active layer is contaminated by impurities (boron, oxygen, moisture, sodium, etc.) in the atmosphere. It was. In addition, after the gate insulating film is formed, a semiconductor film serving as an active layer is formed on the gate insulating film that has been exposed to the air and contaminated, so that the semiconductor film has impurities in the atmosphere (boron, oxygen, moisture, Sodium). When a semiconductor element such as a TFT is manufactured using such a contaminated semiconductor film, the interface characteristics between the active layer, in particular, the channel formation region and the gate insulating film are deteriorated, which causes variation and deterioration in the electrical characteristics of the TFT. It was. Further, in the crystallization process, impurities (boron, oxygen, moisture, sodium, etc.) hinder crystallization of the semiconductor film.

  The present invention includes a semiconductor circuit composed of a semiconductor element having improved characteristics and uniform characteristics by improving the interface between the active layer, particularly the region forming the channel formation region and the insulating film. A semiconductor device and a manufacturing method thereof are provided.

Conventionally, a structure of a thin film transistor having an LDD region is known. Examples of a thin film transistor having an LDD region are described in Japanese Patent Publication No. 3-38755 and Japanese Patent Application Laid-Open No. 7-226515. The LDD region relaxes the strength of the electric field formed between the channel formation region and the drain region, and plays a role of reducing the OFF current of the transistor and preventing deterioration. However, the manufacturing method of the LDD structure using the prior art is complicated and requires many steps.

  In addition, the present invention provides a semiconductor device including a semiconductor circuit including a semiconductor element having an LDD structure with high reproducibility, improved stability of transistor characteristics, and high productivity, and a manufacturing method thereof.

In order to solve the above-described object, the present invention forms at least a gate insulating film and a semiconductor film on an insulating surface on which a gate wiring is formed without touching the atmosphere, and then uses infrared light or ultraviolet light (laser light). One of the features is that after crystallization by irradiation), impurities are doped to form a source region and a drain region. This impurity doping is performed through an insulating film covering the semiconductor film. That is, according to the present invention, when forming a TFT having a bottom gate structure (typically, an inverted staggered structure), a semiconductor film which becomes an active layer using the same chamber or multi-chamber apparatus, for example, a system as shown in FIG. It is in the point that does not touch the atmosphere.
Such a configuration prevents contamination at the interface of the active layer and realizes stable and good electrical characteristics.

A first configuration of the invention disclosed in this specification includes a gate wiring on an insulating surface, a gate insulating film in contact with the gate wiring, an active layer in contact with the gate insulating film, and a protection in contact with the active layer. And an organic resin to which a trivalent or pentavalent impurity is added in contact with the protective film, and the protective film includes a source region, a drain region, and the source region and the drain constituting the active layer A semiconductor device including a semiconductor circuit including a semiconductor element covering at least a part of a channel formation region formed between the regions.

In the above structure, the trivalent or pentavalent impurity is phosphorus or boron.

In the above structure, the organic resin has photosensitivity.

In the above structure, the organic resin has a light shielding property.

In the above structure, the protective film is formed through at least a step of forming the semiconductor film by irradiating the semiconductor film with infrared light or ultraviolet light.

In the above structure, the active layer is a crystalline semiconductor film formed through at least a step of crystallizing the semiconductor film by irradiating infrared light or ultraviolet light through the protective film. It is said.

Further, the gate insulating film, the semiconductor film, and the protective film are formed through at least a step of stacking without sequentially contacting with the atmosphere.

In each of the above structures, the concentration of the trivalent or pentavalent impurity in the organic resin is 1 × 10 ¹⁹ atoms / cm ³ or more.

In each of the above structures, the concentration of boron in the semiconductor film at the interface between the gate insulating film and the channel formation region or the interface between the protective film and the channel formation region is 3 × 10 ¹⁷ atoms / cm ³ or less. It is characterized by that.

In each of the above structures, the concentration of oxygen in the semiconductor film at the interface between the gate insulating film and the channel formation region or the interface between the protective film and the channel formation region is 2 × 10 ¹⁹ atoms / cm ³ or less. It is characterized by being.

In each of the above structures, the concentration of carbon or nitrogen in the semiconductor film at the interface between the gate insulating film and the channel formation region or the interface between the protective film and the channel formation region is 5 × 10 ¹⁸ atoms / cm 3. It is characterized by ³ or less.

In each of the above structures, the gate wiring has a single-layer structure or a stacked structure, and is doped with one element selected from aluminum, tantalum, molybdenum, titanium, chromium, and silicon, or a P-type or N-type impurity. It is characterized by being made of a material mainly composed of silicon.

In each of the above structures, the protective film has a thickness of 5 to 50 nm.

Note that in this specification, the “semiconductor film” is typically a semiconductor film having an amorphous structure such as an amorphous semiconductor film (such as an amorphous silicon film) or an amorphous semiconductor having a microcrystal. These films refer to Si films, Ge films, compound semiconductor films [for example, Si _x Ge _1-x (0 <X <1), typically X = 0.3 to Amorphous silicon germanium film or the like indicated by 0.95])). This semiconductor film can be formed using a known technique such as a low pressure CVD method, a thermal CVD method, a PCVD method, or a sputtering method.

Note that in this specification, a “crystalline semiconductor film” refers to a single crystal semiconductor film, a semiconductor film including a crystal grain boundary (including a polycrystalline semiconductor film and a microcrystalline semiconductor film), and is amorphous over the entire region. The distinction from the state semiconductor (amorphous semiconductor film) is made clear. Needless to say, the term “semiconductor film” in this specification includes an amorphous semiconductor film in addition to a crystalline semiconductor film.

In this specification, the “semiconductor element” refers to a switching element or a memory element, such as a thin film transistor (TFT) or a thin film diode (TFD).

  Another feature of the present invention is that an LDD region is formed on a protective film by using, for example, a photosensitive organic material, a silicon oxide film, or the like as a mask. In addition, the mask used for forming the LDD structure is used as a light-shielding film to protect the active layer, particularly the channel formation region from light deterioration, and omit the mask removal step. In addition, the mask functions as an insulating film at the intersection between the gate wiring and another wiring, and the capacitance between the wirings can be reduced.

In addition, the structure of the first manufacturing method for manufacturing the semiconductor device of the present invention includes a step of sequentially stacking a gate insulating film and a semiconductor film on an insulating surface on which a gate wiring is formed without being exposed to the atmosphere, A step of crystallizing the semiconductor film by irradiating with external light or ultraviolet light to form a crystalline semiconductor film and simultaneously forming an oxide film, and covering a region to be a channel formation region of the crystalline semiconductor film with a mask And a step of adding a trivalent or pentavalent impurity element to a region to be a source region or a drain region of the crystalline semiconductor film through the oxide film, and a semiconductor device comprising a semiconductor circuit comprising a semiconductor element This is a manufacturing method.

The second manufacturing method for manufacturing the semiconductor device of the present invention is a process in which a gate insulating film, a semiconductor film, and an insulating film are sequentially stacked on an insulating surface where a gate wiring is formed without being exposed to the atmosphere. Irradiating infrared light or ultraviolet light through the insulating film to crystallize the semiconductor film to obtain a crystalline semiconductor film, and masking a region to be a channel formation region of the crystalline semiconductor film And a step of adding a trivalent or pentavalent impurity element to a region to be a source region or a drain region of the crystalline semiconductor film through the insulating film, and a semiconductor circuit including a semiconductor element. A method for manufacturing a semiconductor device.

In each of the manufacturing methods, the gate insulating film, the semiconductor film, and the protective film are formed using different chambers.
In each of the manufacturing methods, the gate insulating film, the semiconductor film, and the protective film are formed using the same chamber.

In each of the manufacturing methods, the gate insulating film and the protective film are formed using a first chamber, and the semiconductor film is formed using a second chamber.

In each of the above manufacturing methods, a contaminant is reduced on the film formation surface by active hydrogen or a hydrogen compound before forming the semiconductor film.

The structure of each manufacturing method described above includes a step of forming a silicon nitride film before forming the gate insulating film.

The structure of each manufacturing method is characterized in that it includes a step of forming a stacked film containing BCB (benzocyclobutene) as part of the gate insulating film.

  By implementing the present invention using the apparatus shown in FIG. 13, the process is completed without once contacting the interface (main surface side or back surface side) of the active layer of the TFT with the atmosphere. Can be realized.

  With such a configuration, the interface between the active layer and the gate insulating film, which particularly affects the electrical characteristics of the TFT, can be made clean, so that a TFT with little variation and excellent electrical characteristics can be realized. The

In addition, contamination of the atmosphere, especially boron, is prevented by a protective film, and an impurity imparting conductivity is added through the protective film, so that accurate threshold control can be realized. Conventionally, when SIMS analysis is performed, it has a boron concentration peak (indicated by a dotted line B in FIG. 14) at the interface (main surface side or back surface side) of the active layer (channel formation region) of the TFT. The peak value was 1 × 10 ¹⁸ atoms / cm ³ or more. However, the concentration peak of boron is present at the interface (main surface side or back surface side) of the active layer (channel formation region) of the TFT fabricated using the present invention. The concentration profile is almost uniform (dotted line A in FIG. 14), and the maximum boron concentration is 3 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³ or less. Can be realized. The oxygen concentration in the active layer (channel formation region) is 2 × 10 ¹⁹ atoms / cm ³ or less, the carbon concentration is 5 × 10 ¹⁸ atoms / cm ³ or less, and the nitrogen concentration is 5 × 10 ¹⁸ atoms / cm 3. ³ or less can be realized. The concentration of sodium in the active layer (channel formation region) can be 3 × 10 ¹⁶ atoms / cm ³ or less.

At this time, the threshold voltage, which is a typical parameter of the TFT, can be realized as -0.5 to 2 V for the N-channel TFT and 0.5 to -2 V for the P-channel TFT. The subthreshold coefficient (S value) can be 0.1 to 0.3 V / decade.

  Further, as shown in the above embodiment, a TFT having an LDD structure with high reproducibility and improved TFT stability and high productivity can be obtained. By utilizing the present invention, the mask used for forming the LDD structure can be used as it is as a light-shielding film, and the active layer, particularly the channel formation region can be protected from light deterioration to improve reliability. . Further, by omitting the mask removal step, the TFT can be manufactured in a short time. In addition, since the mask functions as an insulating film at the intersection between the gate wiring and another wiring, it is possible to reduce the capacitance between the wirings and improve the electrical characteristics of the TFT.

  The embodiment of the present invention will be described in detail with the following examples.

  Examples of the present invention will be described below, but it is needless to say that the present invention is not particularly limited to these examples.

  In this embodiment, an example of manufacturing an inverted staggered TFT using the present invention will be described. In this embodiment, description is made using a CMOS circuit composed of an N-channel TFT and a P-channel TFT.

  The semiconductor device of the present invention and a method for manufacturing the semiconductor device will be briefly described with reference to FIGS.

  First, the substrate 100 is prepared. As the substrate 100, a glass substrate, a quartz substrate, an insulating substrate such as crystalline glass, a ceramic substrate, a stainless steel substrate, a metal (tantalum, tungsten, molybdenum, etc.) substrate, a semiconductor substrate, a plastic substrate (polyethylene terephthalate substrate), or the like is used. be able to. In this example, a glass substrate (Corning 1737; strain point 667 ° C.) was used as the substrate 100.

Next, a base film 101 is formed on the substrate 100. As the base film 101, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiO _x N _y ), or a stacked film of these can be used. The base film 101 can be used in a film thickness range of 200 to 500 nm. In this embodiment, a silicon nitride film having a thickness of 300 nm is formed as the base film 101 to prevent diffusion of contaminants from the glass substrate. Although the present invention can be implemented without providing a base film, it is preferable to provide a base film in order to improve TFT characteristics.

  Next, the gate wiring 102 having a single layer structure or a stacked structure is formed. (FIG. 1A) As the gate wiring 102, a conductive material or a semiconductor material such as aluminum (Al), tantalum (Ta), niobium (Nb), hafnium (Hf), zirconium (Zr), titanium (Ti ), Chromium (Cr), silicon (Si) doped with P-type or N-type impurities, silicide, or the like as a main component. In this embodiment, the gate wiring 102 has a laminated structure in which a tantalum film is sandwiched between tantalum nitride films (not shown for simplification). Since tantalum has a work function close to that of silicon, tantalum is a preferable material with little shift of the threshold value of TFT. The gate wiring 102 can be used in a film thickness range of 10 to 1000 nm, preferably 30 to 300 nm. Note that a step of forming an anodic oxide film or an oxide film may be added to protect the gate wiring. In addition, in the manufacturing process, an insulating film that covers the gate wiring and the substrate may be added in order to prevent impurities from diffusing from the substrate or the gate wiring to the gate insulating film.

  Next, the gate insulating film 103, the semiconductor film 104, and the insulating film 105 are sequentially stacked without being exposed to the atmosphere. At this time, any means such as a plasma CVD method or a sputtering method may be used as a forming means. However, by preventing exposure to the atmosphere, contaminants from the atmosphere do not adhere to the interface of any layer. It is important to do so. In this embodiment, a high vacuum is used by using a multi-chamber (apparatus shown in FIG. 13) including a chamber dedicated to forming a gate insulating film, a chamber dedicated to forming a semiconductor film, and a chamber dedicated to forming an insulating film. While maintaining the above, each chamber is moved to form a stacked layer.

  FIG. 13 shows an outline of the apparatus (continuous film forming system) shown in this embodiment as viewed from the upper surface. In FIG. 13, reference numerals 12 to 16 denote airtight chambers. Each chamber is provided with a vacuum exhaust pump and an inert gas introduction system.

Chambers 12 and 13 are load lock chambers for loading the sample (processing substrate) 10 into the system. Reference numeral 14 denotes a first chamber for forming a gate insulating film (silicon oxynitride film) 103. Reference numeral 15 denotes a second chamber for forming a semiconductor film (amorphous silicon film) 104. Reference numeral 16 denotes a third chamber for forming an insulating film (silicon oxynitride film) 105. Reference numeral 11 denotes a common room for samples arranged in common for each chamber.

An example of the operation is shown below.

  Initially, all the chambers are once evacuated to a high vacuum state, and then are further purged with an inert gas, here nitrogen (normal pressure). All gate valves are closed.

  First, the processing substrate is carried into the load lock chamber 13 together with a cassette 34 in which a large number of substrates are stored. After loading the cassette, the door of the load lock chamber (not shown) is closed. In this state, the gate valve 23 is opened, one processing substrate 10 is taken out from the cassette, and taken out into the common chamber 11 by the robot arm 31. At this time, the substrate is aligned in the common chamber.

Here, the gate valve 23 is closed, and then the gate valve 24 is opened. Then, the processing substrate 10 is transferred to the first chamber 14. In the first chamber, film formation is performed at a temperature of 150 ° C. to 300 ° C. to obtain the gate insulating film 103. As the gate insulating film 103, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiO _x N _y )
Alternatively, these stacked films can be used in a film thickness range of 100 to 400 nm (typically 150 to 250 nm). In this embodiment, a single-layer insulating film is used as the gate insulating film, but a laminated structure of two layers or three or more layers may be used.

After the formation of the gate insulating film, the processing substrate 10 is pulled out to the common chamber by the robot arm 31 and transferred to the second chamber 15. In the second chamber, a film formation process is performed at a temperature of 150 ° C. to 300 ° C. similarly to the first chamber, and the semiconductor film 104 is obtained. As the semiconductor film 104, an amorphous silicon film, an amorphous semiconductor film having microcrystals, a microcrystalline semiconductor film, an amorphous germanium film, or Si _x Ge _1-x (0 <X <1) is shown. An amorphous silicon germanium film or a stacked film thereof can be used in a film thickness range of 20 to 70 nm (typically 40 to 50 nm).

Note that the formation temperature of the semiconductor film 104 may be 350 ° C. to 500 ° C. (typically 450 ° C.), and the heat treatment for reducing the hydrogen concentration in the semiconductor film may be omitted.

Further, the forming temperature is 80 ° C. to 300 ° C., preferably 140 to 200 ° C., silane gas diluted with hydrogen (SiH ₄ : H ₂ = 1: 10 to 100) is used as a reaction gas, and the gas pressure is set to 0.1 to 100 ° C. A microcrystalline semiconductor film formed by 10 Torr and a discharge power of 10 to 300 mW / cm ² has a low hydrogen concentration in the film. Therefore, when used as a semiconductor film, a heat treatment for reducing the hydrogen concentration can be omitted. it can.

After completion of the semiconductor film formation, the processing substrate 10 is pulled out to the common chamber by the robot arm 31 and transferred to the third chamber 16. In the third chamber, a film formation process is performed at a temperature of 150 ° C. to 300 ° C. similarly to the first chamber to obtain an insulating film. As the insulating film 105, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (indicated by SiO _x N _y ), or a stacked film of these is a film thickness range of 5 to 50 nm (typically 10 to 20 nm). Can be used. This insulating film 105 is provided to protect the surface of the semiconductor film 104 from contamination by impurities contained in the atmosphere. Further, since the insulating film 105 is excellent in adhesiveness with a resist, it is preferable for forming a resist later.

The substrate to be processed on which the three layers are continuously formed in this manner is transferred to the load lock chamber 12 by the robot arm and stored in the cassette 33.

As described above, in this embodiment, the apparatus shown in FIG. 13 is used to form a stack in different chambers in order to prevent contamination (mainly inhibition of crystallization by oxygen) that occurs during the formation of the insulating film. Of course, the apparatus shown in FIG. 13 is merely an example.

In this embodiment, a silicon nitride oxide film with a thickness of 125 nm is formed as the gate insulating film 103, an amorphous silicon film with a thickness of 50 nm is formed as the semiconductor film 104, and a silicon nitride oxide film with a thickness of 15 nm is formed as the insulating film 105. (FIG. 1 (B)) Of course, each film thickness is not limited to this embodiment, and the practitioner may determine it appropriately. Alternatively, a stack may be formed by exchanging the reaction gas in the same chamber. Further, it is preferable that the surface on which the film is formed is configured to reduce contaminants with active hydrogen or a hydrogen compound before forming the semiconductor film.

1B is obtained, the semiconductor film 104 is crystallized by irradiation with infrared light or ultraviolet light (hereinafter referred to as laser crystallization). When ultraviolet light is used as the crystallization technique, excimer laser light or strong light generated from an ultraviolet lamp may be used, and when infrared light is used, infrared laser light or strong light generated from an infrared lamp may be used. In this embodiment, excimer laser light was formed into a linear beam and irradiated. As the irradiation condition, the pulse frequency is 150 Hz, an overlap ratio 80 to 98%, 96% in the present embodiment, the laser energy density is 100 to 500 mJ / cm ^2, preferably 150~200mJ / cm ² present In the example, it was set to 175 mJ / cm ² . Note that the conditions for laser crystallization (laser light wavelength, overlap rate, irradiation intensity, pulse width, repetition frequency, irradiation time, etc.) depend on the film thickness of the insulating film 105, the film thickness of the semiconductor film 104, the substrate temperature, and the like. The practitioner may determine as appropriate in consideration. Also, depending on the laser crystallization conditions, the semiconductor film may be crystallized after passing through a molten state, or the semiconductor film may be crystallized in a solid state or an intermediate state between a solid phase and a liquid phase without melting. There is. Further, the laser beam was continuously moved at a constant speed to make it constant in any region within a range of ± 10% of the overlap rate.

Through this process, the semiconductor film 104 is crystallized and changed into a crystalline semiconductor film (a semiconductor film including a crystal) 106. (FIG. 1C) In this embodiment, the crystalline semiconductor film is a polycrystalline silicon film. In this step, since the laser beam is irradiated from above the insulating film 105, there is no possibility that contaminants from the atmosphere are mixed into the semiconductor film.
That is, the semiconductor film can be crystallized while maintaining the cleanability of the interface of the semiconductor film.

  Note that after the step of FIG. 1C, an impurity may be added to control a threshold value, and a step of adding the impurity through a protective film may be added to a region to be a channel formation region.

Next, a first mask (resist mask in this embodiment) 109a having a thickness of 1 to 3 μm was formed in contact with the insulating film 105 above the gate wiring by exposure from the back surface. As a material of (FIG. 1 (D)) mask, positive or negative photosensitive organic material (e.g. resist), a silicon oxide film, a silicon nitride film, (represented by SiO _X N _y) a silicon nitride oxide film Can be used. Since the formation of the resist by exposure from the back surface does not require a mask, the number of manufacturing masks can be reduced. Actually, the width of the first mask may be slightly smaller than the width of the gate wiring due to the wraparound of light, but it is not shown for simplicity.

  Note that in this specification, when the substrate 100 is cut along a plane perpendicular to the substrate surface, the direction away from the substrate is defined as the upward direction, and the direction approaching the substrate is defined as the downward direction.

Then, using this first mask 109a, a first impurity was added through the insulating film 105 to form a low concentration impurity region (n ⁻ type region) 110. (FIG. 1E) In this example, phosphorus element is used as an impurity imparting N-type conductivity, and the phosphorus concentration in the n ⁻ -type region indicated by 110 is 1 × 10 ¹⁵ to 1 × in SIMS analysis. The adjustment was made to be 10 ¹⁷ atoms / cm ³ . At this time, a phosphorus element is added to the first mask, so that the first mask 109b containing the phosphorus element at a low concentration is obtained.

Next, a second impurity is added through the protective film 108 using the second mask 112 having a thickness of 1 to 3 μm formed so as to cover the first mask 109b of the N-channel TFT. An (n ⁺ -type region) 201 was formed. (Fig. 2 (A))
In this example, the phosphorus concentration in the n ⁺ -type region indicated by 201 was adjusted to be 1 × 10 ²⁰ to 8 × 10 ²¹ atoms / cm ³ by SIMS analysis. A phosphorus element was added at a high concentration to the first mask 109c in the P-channel TFT. Similarly, phosphorus element is added to the second mask 112 at a higher concentration than the first mask. By making the first mask 109b on the channel formation region side of the N-channel TFT low in concentration, phosphorus is prevented from being erroneously added to the channel formation region. In this embodiment, a photosensitive polyimide resin is used as the material of the second mask 112.

An LDD structure is formed by the first and second impurity addition steps. The boundary between the n ⁻ type region and the n ⁺ type region is determined by the shape of the second mask 112. Note that in the N-channel TFT, the n ⁺ -type region 201 becomes a source region or a drain region, and the n ⁻ -type region becomes a low-concentration impurity region 114.

  In the first and second impurity addition steps, the first masks 109b and 109c to which phosphorus is added and the second mask 112 are blackened. Further, a step of further blackening the first mask and the second mask may be added.

Next, the N-channel TFT was covered with a third mask 115, and a third impurity was added through the protective film 108, whereby a high concentration impurity region (P-type region) 202 was formed.
(FIG. 2B) In this embodiment, boron element is used as an impurity imparting P-type conductivity, and the boron dose is such that the concentration of boron ions in the P-type region is added to the n ⁺ -type region. The concentration is about 1.3 to 2 times the phosphorus ion concentration. Boron element was added at a high concentration to the first mask 109d in the P-channel TFT. Similarly, boron element is added to the third mask 115. Note that the concentration of trivalent (boron in this embodiment) or pentavalent (phosphorus in this embodiment) impurity in the first to third masks, that is, organic resin, is 1 × 10 ¹⁹ atoms / cm ³ or more. included.

  In the P-channel TFT, the P-type region 202 becomes a source region or a drain region. In addition, a region where phosphorus ions and boron ions are not implanted becomes an intrinsic or substantially intrinsic channel formation region 111 which later becomes a carrier movement path.

In this specification, intrinsic refers to a region that does not contain any impurities that can change the Fermi level of silicon, and the substantially intrinsic region is a balance between electrons and holes that offset the conductivity type. A region including an impurity imparting N-type or P-type in a concentration range (1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ^{3 in} SIMS analysis) in which threshold control is possible, or intentional A region in which the conductivity type is offset by adding a reverse conductivity type impurity is shown.

  The first to third impurities may be added using a known means such as an ion implantation method, a plasma doping method, or a laser doping method. However, the doping conditions, dose, acceleration voltage, and the like are adjusted so that a desired amount of impurity ions is added to a predetermined region of the active layer through the protective film 108.

  Further, in the first to third impurity addition steps, since impurities are implanted from above the insulating film 105, there is no possibility that contaminants from the atmosphere, particularly boron, will be mixed into the active layer. Therefore, since the concentration of impurities in the active layer can be controlled, variations in threshold value can be suppressed.

Further, it is relatively easy to obtain an n ⁻ -type region, an n ⁺ -type region, a P-type region, and a channel formation region having desired widths by appropriately setting the patterns of the first to third masks. Easy to do.

  Thus, after the high concentration impurity regions 201 and 202 to be the source region or the drain region and the low concentration impurity region 114 were formed, only the third mask 115 was selectively removed. (FIG. 2C) The material used for the third mask may be different from the materials of the first and second masks, and may be selectively removed. In this mask removal process, the insulating film 105 serves as an etching stopper. Further, since an insulating film is formed also in this mask removal step, contaminants do not enter the crystalline semiconductor film, particularly the channel formation region 111.

  Next, a known technique such as thermal annealing or laser annealing is performed to obtain an impurity activation effect in the source region and the drain region, or a recovery effect of the crystal structure of the active layer damaged in the doping process.

Next, the crystalline silicon film and the insulating film 105 are patterned using the same mask (fourth mask not shown), and active layers (n ⁻ type region 114, n ⁺ type region 113, P type region 116, And a protective film 108 was formed. (FIG. 2D) Also in this step, only the mask (fourth mask) used in the patterning of the active layer was selectively removed. Thus, as much as possible, the crystalline silicon film was kept covered with the insulating film 105 to protect it from air pollution. In addition, an insulating film for protecting the side surface of the active layer 107 may be formed.
Alternatively, the gate insulating film may be selectively removed using the same mask (fourth mask). Alternatively, patterning may be performed before the impurity region adding step.

Finally, an interlayer insulating film 117 made of an organic resin such as polyimide, polyimide amide, polyamide, acrylic, or a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (indicated by SiO _X N _y ), or a laminated film thereof is formed. After forming a film and forming contact holes exposing the source region and the drain region, a metal film is formed and patterned to form metal wirings 118 to 120 in contact with the source region and the drain region. (FIG. 2E) Thus, the manufacture of the CMOS circuit composed of the N-channel TFT and the P-channel TFT in the embodiment of the present invention is completed.

By using the apparatus shown in FIG. 13, the oxygen concentration at the interface between the gate insulating film and the channel formation region or the interface between the protective film and the channel formation region is 2 × 10 ¹⁹ atoms / cm ³ or less. The concentration of carbon and nitrogen could be 5 × 10 ¹⁸ atoms / cm ³ or less.

  An example of a structure of a semiconductor device including a semiconductor circuit including a semiconductor element using the above manufacturing process will be described with reference to FIGS. The semiconductor device according to the present invention includes a peripheral drive circuit unit and a pixel matrix circuit unit on the same substrate. In this embodiment, for ease of illustration, a CMOS circuit forming a part of the peripheral drive circuit unit and a pixel TFT (N-channel TFT) forming a part of the pixel matrix circuit unit are shown on the same substrate. Has been.

4 (A) and 4 (B) are views corresponding to the top view of FIG. 3, and in FIG. 4 (A) and FIG. 4 (B), the portion cut by the thick line AA ′ is 3 corresponds to the cross-sectional structure of the pixel matrix circuit of FIG. 3, and a portion cut by a thick line BB ′ corresponds to the cross-sectional structure of the CMOS circuit of FIG. The reference numerals used in FIGS. 3 and 4 are the same as those in FIG. 1 or FIG.

  In FIG. 3, any TFT (thin film transistor) is formed on the base film 101 provided on the substrate 100. In the case of a P-channel TFT of a CMOS circuit, a gate wiring 102 is formed on a base film, and a gate insulating film 103 is provided thereon. A P-type region 116 (source region or drain region) and a channel formation region 111 are formed as active layers on the gate insulating film. Note that the active layer is protected by a protective film 108 having the same shape. A contact hole is formed in the first interlayer insulating film 117 covering the protective film 108, wirings 118 and 119 are connected to the P-type region 116, and a second interlayer insulating film 123 is further formed thereon, and wiring is formed. A lead wiring 124 is connected to 118, and a third interlayer insulating film 127 is formed so as to cover it. Note that a light-shielding first mask 109d is formed on at least the protective film above the channel formation region to protect the channel formation region from light degradation.

On the other hand, an N channel type TFT has an n ⁺ type region 113 (source region or drain region) as an active layer, a channel formation region 111, and an n ⁻ type region 114 between the n ⁺ type region and the channel formation region. It is formed. Wirings 119 and 120 are formed in the n ⁺ -type region 113, and a lead-out wiring 125 is connected to the wiring 120. Portions other than the active layer have substantially the same structure as the P-channel TFT. Note that a first mask 109b having a light shielding property is formed on at least the protective film above the channel formation region 111, and a second mask 112 is formed on the protective film above the n ⁻ -type region 114. The formation region and the n ⁻ -type region are protected from light deterioration.

The N-channel TFT formed in the pixel matrix circuit has the same structure as the N-channel TFT of the CMOS circuit up to the portion where the first interlayer insulating film 117 is formed. Then, wirings 121 and 122 are connected to the n ⁺ -type region 129, and a second interlayer insulating film 123 and a black mask 126 are formed thereon. This black mask covers the pixel TFT and forms a wiring 122 and an auxiliary capacitor.
Further, a third interlayer insulating film 127 is formed thereon, and a pixel electrode 128 made of a transparent conductive film such as ITO or SnO ₂ is connected thereto.

  The pixel matrix circuit of this embodiment has a TFT structure in which the interwiring capacitance generated between the gate wiring 102 and the wirings 121 and 122 is reduced by the first or second mask. In addition to the pixel matrix circuit, in this embodiment, the resist mask is formed by backside exposure. Therefore, a mask is provided above the gate wiring, and the wiring capacitance with other wiring is reduced.

In this embodiment, a transmissive LCD is manufactured as an example, but is not particularly limited. For example, a reflective LCD can be manufactured by using a reflective metal material as a material for the pixel electrode and appropriately changing the patterning of the pixel electrode or adding / deleting some processes as appropriate.

In this embodiment, the gate wiring of the pixel TFT of the pixel matrix circuit has a double gate structure. However, a multi-gate structure such as a triple gate structure may be used in order to reduce variation in off current. Further, a single gate structure may be used in order to improve the aperture ratio.

In this embodiment, a crystalline silicon film is obtained by a method different from that in the first embodiment. In this embodiment, a laser element is formed into a rectangle or a square by using a catalytic element that promotes crystallization of silicon, and uniform laser crystallization in a region of several cm ² to several hundred cm ² by one irradiation. The present invention relates to a method for obtaining a crystalline silicon film by treatment.
Since the basic configuration is substantially the same as that of the first embodiment, only the differences will be described.

In this embodiment, excimer laser light is processed into a planar shape and irradiated in the process of FIG. When processing a laser beam into a planar shape, it is necessary to process the laser beam so that an area of about several tens of cm ² (preferably 10 cm ² or more) can be collectively irradiated.
In order to anneal the entire irradiated surface with a desired laser energy density, a laser device having an output with a total energy of 5 J or more, preferably 10 J or more is used.

In that case, the energy density is set to 100 to 800 mJ / cm ² , and the output pulse width is set to 100 nsec or more, preferably 200 nsec to 1 msec. In order to realize a pulse width of 200 nsec to 1 msec, a plurality of laser devices are connected, and a state in which a plurality of pulses are mixed is created by shifting the synchronization of the laser devices.

  By irradiating a laser beam having a planar beam shape as in this embodiment, it is possible to perform uniform laser irradiation over a large area. That is, the crystallinity (including crystal grain size and defect density) of the active layer becomes uniform, and variations in electrical characteristics between TFTs can be reduced.

  The present embodiment can be easily combined with the first embodiment, and the combination is free.

  In this embodiment, an example in which a TFT having a structure different from that in Embodiment 1 is manufactured will be described with reference to FIGS. 5 is substantially the same as FIG. 4 although the reference numerals are different.

  In this embodiment, a glass substrate is formed as the substrate 500, silicon oxynitride (indicated by SiOxNy) is formed as the base film 501, and a tantalum film is formed as the gate wiring 502.

  Next, as the first insulating film 503, an organic material, for example, a BCB (benzocyclobutene) film that flattens the unevenness between the region having the gate electrode and the region not having the gate electrode is formed to a thickness of 100 nm to 1 μm (preferably 500 to 800 nm). Form with thickness. In this step, a film thickness that can completely flatten the step due to the gate wiring 502 is required. Since the BCB film has a great flattening effect, it can be sufficiently flattened without increasing the film thickness.

After the formation of the first insulating film 503, the second insulating film (silicon nitride oxide film) 504, the semiconductor film (microcrystalline silicon film), and the insulating film (silicon nitride oxide film) to be the protective film 509 are not sequentially released to the atmosphere. Are stacked. The microcrystalline silicon film has a formation temperature of 80 ° C. to 300 ° C., preferably 140 ° C. to 200 ° C., a silane gas diluted with hydrogen (SiH ₄ : H ₂ = 1: 10 to 100) as a reaction gas, and a gas pressure of It is formed by setting the discharge power to 10 to 300 mW / cm ² at 0.1 to 10 Torr. Since the microcrystalline silicon film has a low hydrogen concentration in the film, if it is used as a semiconductor film, heat treatment for reducing the hydrogen concentration can be omitted. In this embodiment, a chamber dedicated to the formation of the second insulating film, a chamber dedicated to the formation of the semiconductor film, and a chamber dedicated to the formation of the protective film are prepared, and each chamber is moved while maintaining a high vacuum. Thus, a film was continuously formed. Since the insulating film and the semiconductor film continuously formed in this manner are formed on a flat surface, they are all flat.

  Next, by irradiating excimer laser light from above the protective film, the semiconductor film changes to a semiconductor film containing crystals (polycrystalline silicon film). The conditions for this laser crystallization process may be the same as in Example 1. At this time, since the semiconductor film is flat, a polycrystalline silicon film having a uniform crystal grain size can be obtained. Further, instead of laser light irradiation, strong light irradiation, for example, RTA or RTP may be used.

  As described above, a semiconductor film having a flat surface can be obtained by using a BCB film advantageous for planarization as the first insulating film 503. Therefore, uniform crystallinity can be ensured over the entire area of the semiconductor film.

  If the subsequent steps are in accordance with the first embodiment, the semiconductor device obtained in FIG. 5 is completed.

In FIG. 5, any TFT (thin film transistor) is formed on the base film 501 provided on the substrate 500. In the case of a P-channel TFT of a CMOS circuit, a gate wiring 502 is formed on a base film, and a first insulating film 503 and a second insulating film 504 made of BCB are provided thereon. On the second insulating film, a P-type region 508 (source region or drain region) and a channel formation region 505 are formed as active layers. Note that the active layer is protected by a protective film 509 having the same shape. A contact hole is formed in the first interlayer insulating film 510 covering the protective film 509, wirings 511 and 512 are connected to the P-type region 508, and a second interlayer insulating film 516 is formed thereon, and wiring A lead wiring 517 is connected to 511, and a third interlayer insulating film 520 is formed to cover the lead wiring 517. Note that a first light-shielding mask is formed on at least the protective film above the channel formation region to protect the channel formation region from light deterioration.

On the other hand, an N channel type TFT has an n ⁺ type region 507 (source region or drain region) as an active layer, a channel formation region 505, and an n ⁻ type region 506 between the n ⁺ type region and the channel formation region. It is formed. Wirings 512 and 513 are formed in the n ⁺ -type region 507, and a lead-out wiring 518 is connected to the wiring 513. Portions other than the active layer have substantially the same structure as the P-channel TFT. Note that a first mask having a light shielding property is formed at least on the protective film above the channel formation region 505, and a second mask is formed on the protective film above the n ⁻ -type region 506, thereby forming a channel. The region and the n ⁻ -type region are protected from light degradation.

The N-channel TFT formed in the pixel matrix circuit has the same structure as the N-channel TFT of the CMOS circuit up to the portion where the first interlayer insulating film 510 is formed. Then, wirings 514 and 515 are connected to the n ⁺ -type region 507, and a second interlayer insulating film 516 and a black mask 519 are formed thereon. This black mask covers the pixel TFT and forms a wiring 515 and an auxiliary capacitor.
Further, a third interlayer insulating film 520 is formed thereon, and a pixel electrode 521 made of a transparent conductive film such as ITO is connected thereto.

  The pixel matrix circuit of this embodiment has a TFT structure in which the interwiring capacitance generated between the gate wiring 502 and the wirings 514 and 515 is reduced by the first or second mask. In addition to the pixel matrix circuit, in this embodiment, the resist mask is formed by backside exposure. Therefore, a mask is provided above the gate wiring, and the wiring capacitance with other wiring is reduced.

A TFT manufactured by implementing this embodiment shows electric characteristics with less variation. In addition, this embodiment can be combined with Embodiments 1 and 2.

  In this embodiment, an example in which a TFT having a structure different from that in Embodiment 1 is manufactured will be described with reference to FIGS. Since the configuration of the CMOS circuit is almost the same as that of the first embodiment, only the differences will be described. The reference numerals used in FIG. 6 are the same as those in FIG. The top view of FIG. 6 corresponds to FIG.

  This embodiment is the same as Embodiment 1 up to the step of forming a glass substrate as the substrate 100, a silicon oxynitride film (indicated by SiOxNy) as the base film 101, and the gate wiring 102.

  Next, in this embodiment, the first insulating film 132 is selectively formed in the pixel matrix circuit.

  Thereafter, similarly to the first embodiment, the second insulating film 103 (corresponding to the gate insulating film in the first embodiment) 103, the semiconductor film 104, and the insulating film 105 are sequentially stacked without being exposed to the atmosphere. In this embodiment, while maintaining a high vacuum in the same chamber, the second insulating film 103 is a silicon nitride oxide film having a thickness of 10 to 100 nm, the semiconductor film 104 is an amorphous silicon film having a thickness of 50 nm, and the insulating film 105 As a film, a silicon nitride oxide film having a thickness of 15 nm was continuously stacked using a plasma CVD method. Of course, each film thickness is not limited to the present embodiment, and the practitioner may determine it appropriately. In this embodiment, in the pixel matrix circuit, the total thickness of the gate insulating films (the first insulating film 132 and the second insulating film 103) is 100 to 300 nm.

Further, when continuous film formation is performed in the same chamber as in this embodiment, contaminants, particularly oxygen, are reduced on the film formation surface by active hydrogen or a hydrogen compound before forming the semiconductor film. Oxygen contained in the semiconductor film inhibits crystallization. Here, the active hydrogen or hydrogen compound generated by the plasma treatment using a reaction gas such as NH ₃ , H ₂ , Ar, and He is used to degas the oxygen attached to the inner wall of the chamber and the electrode based on the OH group, Oxygen contamination during the formation of the semiconductor film was prevented. Furthermore, it is preferable that the film forming temperature of each film be the same (± 50 ° C.) and the same pressure (± 20%) while maintaining a high vacuum in the same chamber.

  If the subsequent steps are in accordance with the first embodiment, the semiconductor device obtained in FIG. 6 is completed.

In FIG. 6, the configuration of the CMOS circuit is substantially the same as that of FIG. The N-channel TFT formed in the pixel matrix circuit is almost the same as FIG. 3 of the first embodiment except for the portion where the gate insulating film has a two-layer structure (the first insulating film 132 and the second insulating film 103). Are the same. By selectively increasing the thickness of the gate insulating film in this way, the reliability in a circuit (pixel matrix circuit, buffer circuit, etc.) that requires high breakdown voltage is improved.

  Further, in this embodiment, as in the first embodiment, in the pixel matrix circuit, the inter-wiring capacitance generated between the gate wiring 102 and the wiring 121 and 122 is reduced by the first or second mask. Yes. In addition to the pixel matrix circuit, in this embodiment, the resist mask is formed by backside exposure. Therefore, a mask is provided above the gate wiring, and the wiring capacitance with other wiring is reduced.

A TFT manufactured by implementing this embodiment shows electric characteristics with less variation. In addition, this embodiment can be combined with any one of Embodiments 1 to 3.

  In this embodiment, an example in which a TFT having a structure different from that in Embodiment 1 is manufactured will be described with reference to FIGS. The difference in the configuration of the CMOS circuit is only that the gate insulating film has a two-layer structure, and is almost the same as that of the first embodiment. The reference numerals used in FIG. 7 are the same as those in FIG. The top view of FIG. 7 corresponds to FIG.

  This embodiment is the same as Embodiment 1 up to the step of forming a glass substrate as the substrate 100, a silicon oxynitride film (indicated by SiOxNy) as the base film 101, and the gate wiring 102.

  Next, in this embodiment, after the first insulating film 133 made of a silicon nitride film is formed on the entire surface, the second insulating film 134 is selectively formed in the pixel matrix circuit.

  Thereafter, similarly to the first embodiment, a third insulating film 103 (corresponding to a gate insulating film in the first embodiment) 103, a semiconductor film, and an insulating film are sequentially stacked without being exposed to the atmosphere. In this embodiment, using the apparatus shown in FIG. 13, a silicon nitride oxide film having a thickness of 10 to 100 nm as the third insulating film 103, an amorphous silicon film having a thickness of 50 nm as the semiconductor film, and a 15 nm film as the insulating film. A silicon nitride oxide film was stacked. Of course, each film thickness is not limited to the present embodiment, and the practitioner may determine it appropriately. In this embodiment, in the pixel matrix circuit, the total thickness of the gate insulating films (the first insulating film 133, the second insulating film 134, and the third insulating film 103) is formed to be 100 to 300 nm.

  If the subsequent steps are in accordance with the first embodiment, the semiconductor device obtained in FIG. 7 is completed.

In FIG. 7, the configuration in the CMOS circuit is almost the same as that in FIG. 3 of the first embodiment except for the portion where the gate insulating film has a two-layer structure (the first insulating film 133 and the third insulating film 103). To do. For the N-channel TFT formed in the pixel matrix circuit, except for the part where the gate insulating film has a three-layer structure (the first insulating film 133, the second insulating film 134, and the third insulating film 103). 1 is almost the same as FIG. By selectively increasing the thickness of the gate insulating film in this way, the reliability in a circuit (pixel matrix circuit, buffer circuit, etc.) that requires high breakdown voltage is improved.

  Further, in this embodiment, as in the first embodiment, in the pixel matrix circuit, the inter-wiring capacitance generated between the gate wiring 102 and the wiring 121 and 122 is reduced by the first or second mask. Yes. In addition to the pixel matrix circuit, in this embodiment, the resist mask is formed by backside exposure. Therefore, a mask is provided above the gate wiring, and the wiring capacitance with other wiring is reduced.

A TFT manufactured by implementing this embodiment shows electric characteristics with less variation. In addition, this embodiment can be combined with any one of Embodiments 1 to 3.

  In this embodiment, an example in which a TFT having an LDD structure different from that in Embodiment 1 is manufactured will be described with reference to FIGS. Note that this example is the same as Example 1 up to the process of FIG. 1C, and FIG. 8A shows a diagram corresponding to FIG. The reference numerals used in FIGS. 8 and 9 are the same as those in FIG. 1 or FIG. Further, the top view of FIG. 9 is almost the same as FIG.

As shown in FIG. 8C, this embodiment is characterized in that a low concentration impurity region (n ⁻ region) 614 is formed above the gate wiring.

  In this embodiment, the process up to the state of FIG.

Next, as in the first embodiment, a first mask 609 having substantially the same shape as the gate wiring is formed by exposure from the back surface, and then an impurity is added to form a high concentration impurity region (n ⁺ region) 610. To do. A phosphorus element is also added to the first mask 609.
(Fig. 8 (B))

Then, after the first mask 609 patterning or removal, after the formation of the small second mask 612a in width than the gate wiring, by adding an impurity low concentration impurity regions ^- forming the (n region) 614. In this embodiment, the second mask 612a having a width smaller than that of the gate wiring is formed using a normal patterning method. In this way, an LDD structure is formed. Similarly, phosphorus element is added to the second mask. (Fig. 8 (C))

As a method for forming the first mask 608 or the second mask 612a, a resist mask formation method by a normal patterning method or a resist mask formation method in which light from the back surface intentionally wraps around the gate wiring is used. Can do.

Next, the N-channel TFT was covered with a third mask 615, and a third impurity was added through the insulating film 105, whereby a high-concentration impurity region (P-type region) 617 was formed. In (FIG. 8 (D)) This example, using boron element as an impurity imparting P-type conductivity, boron dose is the concentration of boron ions in the P-type region is added to the n ⁺ -type region The concentration is about 1.3 to 2 times the phosphorus ion concentration. At this time, boron ions are added, and the second mask 612b contains a phosphorus element and a boron element. Similarly, boron element is added to the third mask.

  Similarly to the first embodiment, in the first to third impurity addition steps, impurities are implanted from above the insulating film 105, so that contaminants from the atmosphere, particularly boron, are mixed in the active layer. There is no fear. Therefore, since the concentration of impurities in the active layer can be controlled, variations in threshold value can be suppressed.

Further, it is relatively easy to obtain an n ⁻ -type region, an n ⁺ -type region, a P-type region, and a channel formation region having desired widths by appropriately setting the patterns of the first to third masks. Easy to do.

Note that in the case where the first mask 609 and the second mask 612a are formed using a resist mask formation method by exposure from the back surface, an LDD structure can be manufactured by self-alignment, and the number of manufacturing masks can be reduced. Therefore, it is preferable.

Thus, after obtaining an LDD structure in which the low-concentration impurity region 614 overlaps above the gate wiring 102, only the third mask was removed and patterned into a desired shape. The region indicated by 613 is an n ⁺ type region, and the region indicated by 616 (FIG. 8E)

  If the subsequent steps are in accordance with the first embodiment, the semiconductor device obtained in FIG. 9 is completed.

FIG. 9 is omitted because it is substantially the same as FIG. 3 of the first embodiment except for the active layer portion formed by overlapping the low concentration impurity region above the gate wiring.

A TFT manufactured by implementing this embodiment shows electric characteristics with less variation. In addition, this embodiment can be combined with any one of Embodiments 1 to 5.

  As shown in FIG. 10, in this embodiment, an example in which a protective film is formed by a method different from that in Embodiment 1 is shown.

  The process shown in FIG. 10A corresponds to FIG. The difference between this embodiment and Embodiment 1 is that laser crystallization is performed in the atmosphere, oxygen, or oxidizing atmosphere after the gate insulating film 103 and the semiconductor film 104 are continuously formed as shown in FIG. In the process, an oxide film is formed on the surface at the same time as forming the crystalline semiconductor film. Further, in the step of FIG. 10B, a contaminant may be reduced on the film formation surface with active hydrogen or a hydrogen compound before the semiconductor film is formed.

As shown in FIG. 10C, the oxide film 105 formed under the above laser conditions in air, oxygen, or an oxidizing atmosphere is used as a protective film. Laser irradiation conditions, the pulse frequency is 150 Hz, an overlap ratio 80 to 98%, 96% in the present embodiment, the laser energy density is 100 to 500 mJ / cm ^2, preferably present embodiment be 280~380mJ / cm ² In this case, it was set to 350 mJ / cm ² . Note that laser crystallization conditions (laser light wavelength, overlap rate, irradiation intensity, pulse width, repetition frequency, irradiation time, etc.) are appropriately determined by the practitioner in consideration of the film thickness of the semiconductor film 104, the substrate temperature, and the like. Just decide. This oxide film is suitable as a base film for mask formation.

  Subsequent steps follow the first embodiment to complete the semiconductor device. In addition, this embodiment can be combined with any one of Embodiments 1 to 6.

  In this example, a semiconductor device is manufactured using a device different from that in Example 1.

In this embodiment, each chamber is maintained while maintaining a high vacuum by using an apparatus including a first chamber dedicated to forming a gate insulating film and an insulating film and a second chamber dedicated to forming a semiconductor film. A stack is formed by moving.

This example is the same as Example 1 up to the step of forming a glass substrate as a substrate, a silicon oxynitride film (indicated by SiOxNy) as a base film, and a gate wiring.
Next, three layers (gate insulating film / semiconductor film / insulating film) are stacked.

  First, after forming a gate insulating film made of a silicon nitride oxide film in the first chamber, a semiconductor film is formed in the second chamber. Then, an insulating film (protective film) made of a silicon nitride oxide film thinner than the gate insulating film was formed again in the first chamber. In this embodiment, before the semiconductor film is formed, contaminants are reduced on the film forming surface by active hydrogen or a hydrogen compound. Subsequent steps follow the first embodiment to complete the semiconductor device. By using such an apparatus, the number of chambers is less than that of the apparatus shown in FIG. 13 and the equipment cost is low, so that productivity can be improved.

In addition, this embodiment can be combined with any one of Embodiments 1 to 7.

  In this embodiment, a semiconductor device is manufactured using a mask different from that in Embodiment 1. Since the basic configuration is substantially the same as that of the first embodiment, only the differences will be described.

In Example 1, since the same mask was used when adding phosphorus element, it was also added to the source region and drain region of the P-channel TFT. However, in this example, the addition process of phosphorus element, boron element The addition process was performed using separate masks. That is, the P-channel TFT was covered with a mask during the phosphorus element addition step. For this reason, it is not necessary to add a dose of boron that is about 1.3 to 2 times the concentration of phosphorus ions added to the n ⁺ -type region as in the first embodiment, and a P-channel TFT with good controllability. Was able to be produced.

In addition, this embodiment can be combined with any one of Embodiments 1 to 8.

  In this embodiment, an example of a liquid crystal display device manufactured according to the present invention is shown in FIG. Since a known method may be used for a manufacturing method of a pixel TFT (pixel switching element) and a cell assembly process, detailed description thereof is omitted.

  11, 800 is a substrate having an insulating surface (a glass substrate provided with a silicon oxide film), 801 is a pixel matrix circuit, 802 is a scanning line driver circuit, 803 is a signal line driver circuit, 830 is a counter substrate, 810 is an FPC (FPC) 820 is a logic circuit. As the logic circuit 820, a circuit that performs processing such as a D / A converter, a γ correction circuit, a signal division circuit, or the like that has been substituted for a conventional IC can be formed. Of course, it is also possible to provide an IC chip on the substrate and perform signal processing on the IC chip.

  Further, in this embodiment, the liquid crystal display device is described as an example, but the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromic) display device as long as it is an active matrix display device. It goes without saying that it is also possible to do.

  Further, the liquid crystal display device that can be manufactured using the present invention does not matter whether it is a transmissive type or a reflective type. It is up to the practitioner to choose either. Thus, the present invention can be applied to any active matrix type electro-optical device (semiconductor device).

  Note that in manufacturing the semiconductor device shown in this embodiment, any of the structures of Embodiments 1 to 9 may be adopted, and the embodiments can be used in any combination.

The present invention can be applied to all conventional IC technologies.
That is, it can be applied to all semiconductor circuits currently on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor integrated on one chip, and is represented by a liquid crystal driver circuit (D / A converter, γ correction circuit, signal dividing circuit, etc.). The present invention may be applied to a signal processing circuit and a high-frequency circuit for a portable device (mobile phone, PHS, mobile computer).

  A semiconductor circuit such as a microprocessor is mounted on various electronic devices and functions as a central circuit. Typical electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (such as an automobile or a train) may be used. The present invention is applicable to such a semiconductor device.

  Note that in manufacturing the semiconductor device shown in this embodiment, any of the structures of Embodiments 1 to 9 may be adopted, and the embodiments can be used in any combination.

  The CMOS circuit and the pixel matrix circuit formed by implementing the present invention can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display media.

  Examples of such an electronic device include a video camera, a digital camera, a head mounted display (goggles type display), a car navigation, a personal computer, a portable information terminal (mobile computer, mobile phone, electronic book, etc.), and the like. An example of them is shown in FIG.

  FIG. 12A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display device 2003, and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.

  FIG. 12B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the voice input unit 2103, and other signal control circuits.

  FIG. 12C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.

  FIG. 12D illustrates a goggle type display which includes a main body 2301, a display device 2302, and an arm portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 12E shows a player that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet.
The present invention can be applied to the display device 2402 and other signal control circuits.

  FIG. 12F illustrates a digital camera, which includes a main body 2501, a display device 2502, an eyepiece unit 2503, an operation switch 2504, and an image receiving unit (not illustrated). The present invention can be applied to the display device 2502 and other signal control circuits.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-10.

  The CMOS circuit and the pixel matrix circuit formed by implementing the present invention can be used for various electro-optical devices (active matrix liquid crystal display and the like). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display media.

  Examples of such an electronic device include a projector (rear type or front type). An example of these is shown in FIG.

  FIG. 15A illustrates a front type projector, which includes a display device 2601 and a screen 2602. The present invention can be applied to display devices and other signal control circuits.

  FIG. 15B shows a rear projector, which includes a main body 2701, a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.

  Note that FIG. 15C illustrates an example of the structure of the display devices 2601 and 2702 in FIGS. 15A and 15B. The display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. The present embodiment shows an example of a three-plate type, but is not particularly limited, and may be a single-plate type, for example. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.

  FIG. 15D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, light sources 2812, 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 15D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-10.

FIG. 10 shows a manufacturing process of a TFT (Example 1). FIG. 10 shows a manufacturing process of a TFT (Example 1). Sectional drawing which shows an example of the structure of a semiconductor device (Example 1). FIG. 3 is a top view of a pixel matrix circuit and a CMOS circuit (Example 1). Sectional drawing which shows an example of the structure of a semiconductor device (Example 3). Sectional drawing which shows an example of the structure of a semiconductor device (Example 4). Sectional drawing which shows an example of the structure of a semiconductor device (Example 5). FIG. 10 shows a manufacturing process of a TFT (Example 6). Sectional drawing which shows an example of the structure of a semiconductor device (Example 6). FIG. 10 shows a manufacturing process of a TFT (Example 7). FIG. 10 shows a configuration of a semiconductor device (liquid crystal display device) (Example 10). FIG. 12 illustrates an example of a semiconductor device (electronic device) (Example 12). FIG. 1 is a diagram illustrating an example of a film forming apparatus (Example 1). The figure which shows B density | concentration profile by SIMS analysis (comparative example with a prior art example and this invention). FIG. 18 is a diagram illustrating an example of a semiconductor device (electronic device) (Example 13);

Explanation of symbols

100 Substrate 101 Base film 102 Gate wiring 103 Gate insulating film 104 Semiconductor film 105 Insulating film 106 Crystalline semiconductor film 107 Active layer 108 Protective film 109 First mask 110, 114 n ⁻ region (low concentration impurity region)
111 channel formation region 112 second mask 113 n ⁺ region (high concentration impurity region)
115 Third mask 116 P-type region (high concentration impurity region)
117 1st interlayer insulation film 118-120 wiring

Claims (6)

Form gate wiring on the insulating surface,
A gate insulating film and a semiconductor film are sequentially stacked on the gate wiring without being exposed to the atmosphere,
By irradiating infrared light or ultraviolet light, the semiconductor film is crystallized to form a crystalline semiconductor film and simultaneously form an oxide film that functions as a protective film,
Forming a first mask made of a photosensitive organic material on a region to be a channel formation region of the crystalline semiconductor film;
A low concentration impurity region is formed by performing a first addition of an impurity element through the oxide film,
Forming a second mask made of a photosensitive organic material, wider than the first mask, on the channel formation region , the low-concentration impurity region , and the first mask of the crystalline semiconductor film;
Through the oxide film to form a source region or drain region by performing a second addition of the impurity element in the first heavily doped than added pressure,
A first and second method for manufacturing a semi-conductor device you forming an interlayer insulating film as a mask,
The method for manufacturing a semiconductor device, wherein the first and second masks are blackened by addition of the impurity element. Oite to claim 1,
A method for manufacturing a semiconductor device, wherein the atmosphere irradiated with infrared light or ultraviolet light is air. Oite to claim 1 or claim 2,
A method for manufacturing a semiconductor device, wherein the crystalline semiconductor film in which the source region or the drain region is formed and the oxide film are patterned after the second addition . In any one of Claim 1 thru | or 3 ,
The method for manufacturing a semiconductor device, wherein the impurity element is a trivalent or pentavalent impurity element. In any one of Claims 1 thru | or 4 ,
The method for manufacturing a semiconductor device, wherein the infrared light or ultraviolet light is laser light. In any one of Claims 1 thru | or 4 ,
The method for manufacturing a semiconductor device, wherein the irradiation with infrared light or ultraviolet light is RTA.

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