JP4641598B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Field of the Invention]
The present invention relates to a method for manufacturing a semiconductor device having a circuit including thin film transistors (hereinafter referred to as TFTs). For example, the present invention relates to an electro-optical device typified by a liquid crystal display device and a configuration of an electric apparatus in which the electro-optical device is mounted as a component. Further, the present invention relates to a method for manufacturing the device. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and the electro-optical device and the electric appliance are also included in the category.
[0002]
[Prior art]
In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. TFTs are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly urgently developed as switching elements for image display devices.
[0003]
A TFT using a crystalline semiconductor film as a semiconductor layer has very high mobility compared to an amorphous semiconductor film. Therefore, when a crystalline semiconductor film is used, for example, a monolithic liquid crystal electro-optical device (on a single substrate for pixel driving) that cannot be realized by a semiconductor device manufactured using a conventional amorphous semiconductor film. And a semiconductor device in which a thin film transistor (TFT) for a driver circuit is manufactured.
[0004]
As described above, the crystalline semiconductor film is a semiconductor film having extremely high characteristics as compared with the amorphous semiconductor film. This is the reason why the above research is conducted. For example, in order to crystallize an amorphous semiconductor film by heating, a heating temperature of 600 ° C. or more and a heating time of 10 hours or more are required. An example of a substrate that can withstand this crystallization condition is a synthetic quartz substrate. However, synthetic quartz substrates are expensive and have poor workability, and it has been extremely difficult to process particularly large areas. Increasing the area of the substrate is an indispensable element for increasing mass production efficiency. In recent years, there has been a remarkable movement to increase the area of a substrate for improving mass production efficiency, and the substrate size of 600 × 720 mm is becoming the standard for newly constructed mass production factory lines.
[0005]
It is difficult to process a synthetic quartz substrate into such a large-area substrate with the current technology, and even if it can be done, it will not decrease to a price that can be established as an industry. An example of a material capable of easily manufacturing a large-area substrate is a glass substrate. One glass substrate is called Corning 7059, for example. Corning 7059 is very inexpensive, has good workability, and is easy to increase in area. However, Corning 7059 has a strain point temperature of 593 ° C., and there is a problem with heating at 600 ° C. or higher.
[0006]
One glass substrate is Corning 1737, which has a relatively high strain point temperature. Corning 1737 has a strain point temperature of 667 ° C., which is higher than the strain point temperature of Corning 7059. Even when an amorphous semiconductor film was formed on the Corning 1737 and placed in an atmosphere of 600 ° C. for 20 hours, the substrate was not deformed so as to affect the manufacturing process. However, the heating time of 20 hours was too long for the mass production process.
[0007]
In order to solve such problems, a new crystallization method has been devised. Details of the method are described in JP-A-7-183540. Here, the method will be briefly described. First, a trace amount of a metal element such as nickel, palladium, or lead is added to the amorphous semiconductor film. As the addition method, a plasma treatment method, a vapor deposition method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used. After the addition, for example, when an amorphous semiconductor film is placed in a nitrogen atmosphere at 550 ° C. for 4 hours, a crystalline semiconductor film with good characteristics can be obtained. The optimal heating temperature, heating time, etc. for crystallization depend on the amount of the metal element added and the state of the amorphous semiconductor film.
[0008]
However, the technique has a problem that the metal element used for promoting crystallization remains locally as a metal compound in a high resistance layer (channel formation region or offset region). Since the metal compound tends to flow a current, the resistance of the region that should be a high resistance layer is locally lowered, which causes a deterioration in the stability and reliability of the electrical characteristics of the TFT.
[0009]
In order to solve this problem, the present applicant has developed a technique (gettering technique) for removing a metal element for promoting crystallization from a crystalline semiconductor film, which is disclosed in JP-A-10-270363. . The gettering technique is to perform heat treatment by selectively introducing an element belonging to Group 15 into the crystalline semiconductor film in which the metal element remains. By the heat treatment, the metal element in the region where the element belonging to Group 15 is not introduced (gettering region) is released from the gettering region, diffuses, and the element belonging to Group 15 is introduced. Is captured in the area (gettering area). As a result, the metal element can be removed or reduced in the gettering region.
[0010]
In the gettering technique, an element belonging to Group 15 is introduced into the source region and the drain region to remove the metal element from the channel formation region or the offset region or to an extent that does not adversely affect the electrical characteristics of the TFT. it can. An element belonging to Group 15 imparts n-type by doping the semiconductor layer, but the technique of gettering to the source region and the drain region can be applied to the semiconductor layer forming the n-channel TFT and the p-channel TFT. Here, not only an impurity element imparting n-type but also an impurity element imparting p-type is introduced into regions serving as a source region and a drain region in a semiconductor layer forming a p-channel TFT. However, it has been confirmed that a metal element is gettered in the source region and the drain region also in the semiconductor layer forming the p-channel TFT.
[0011]
In addition, in the doping process, the energy of ions implanted into the semiconductor layer is very large compared to the binding energy of the elements forming the semiconductor layer. For this reason, ions implanted into the semiconductor layer blow off elements forming the semiconductor film from lattice points to cause defects in the crystal. Therefore, heat treatment is often performed after the doping treatment in order to recover the defects and activate the implanted ions at the same time. In addition, since the said defect arises by ion implantation, it is called an implantation defect in this specification.
[0012]
On the other hand, one of the electrical characteristics of TFT is an off-current value. The off-current value is a drain current value that flows when the TFT is turned off, and it is desirable that the off-current value is sufficiently low in order to reduce power consumption.
[0013]
As a TFT structure for reducing the off-current value, a lightly doped drain (LDD) structure is known. In this structure, a region into which an impurity element is introduced at a low concentration is provided between a channel formation region and a source region or a drain region formed by introducing an impurity element at a high concentration. This region is referred to as an LDD region. I'm calling. A so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to be overlapped with a gate electrode through a gate insulating film is known as means for preventing deterioration of the on-current value due to hot carriers. . With such a structure, it is known that a high electric field in the vicinity of the drain region is relaxed, hot carrier injection is prevented, and deterioration is effectively prevented.
[0014]
The GOLD structure is also known as a LATID (Large-tilt-angle implanted drain) structure, an ITLDD (Inverse T LDD) structure, or the like. And, for example, “Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1997” has a GOLD structure with sidewalls made of silicon, but has extremely superior reliability compared to TFTs with other structures. It has been confirmed that sex is obtained.
[0015]
In order to form the GOLD structure, the end portion of the gate electrode has a tapered shape. By adopting such a shape, a step of introducing an impurity element imparting n-type into the semiconductor layer forming the n-channel TFT, and an impurity element imparting p-type to the semiconductor layer forming the p-channel TFT are formed. In the introduction step, a source region and a drain region are formed in a portion that does not overlap with the gate electrode in one doping process, and an LDD region having a concentration gradient along the taper shape is formed below the taper of the gate electrode. Can be formed.
[0016]
[Problems to be solved by the present invention]
However, using the method of forming the source region, the drain region, and the LDD region by a single doping process using the taper at the end of the gate electrode has the following problems. The ratio of the amount of impurity element introduced into the source region and the drain region and the LDD region is determined by the distribution profile of the impurity element concentration profile and the film thickness of the film existing above the semiconductor layer. Therefore, there was no degree of design freedom for the source and drain regions and the LDD region.
[0017]
Further, in a semiconductor layer forming a p-channel TFT, an impurity imparting n-type is first introduced into a region to be a source region and a drain region in order to getter a metal element used for promoting crystallization. It is necessary to introduce elements. Further, an impurity element imparting p-type conductivity has been introduced into the region to be the source region and the drain region in order to produce a p-channel TFT. Therefore, the semiconductor film has severe injection defects, and the injection defects have an adverse effect on the electrical characteristics when the TFT is manufactured. The semiconductor film injection defects due to the doping process are greatly affected by the acceleration voltage during the doping process, and it is desirable that the defects be as low as possible.
[0018]
Therefore, in the present invention, when the doping process is performed using a tapered gate electrode as a mask, the acceleration voltage at the time of forming the source region, the drain region, and the LDD region is changed at least in the semiconductor layer for forming the p-channel TFT. And at least two times. By doing so, implantation defects in the semiconductor film can be minimized. Furthermore, the amount of impurity element introduced can be changed for the source region, the drain region, and the LDD region, respectively, and the degree of freedom in design is improved.
[0019]
[Means for Solving the Problems]
FIG. 5A shows the acceleration voltage as a parameter, and the dose of boron (B) in the silicon film is 2 × 10. ¹³ / Cm ² The calculation result of the density | concentration profile when performing a doping process is shown. However, boron atom (B) and boron molecule (B ₂ ) Was driven at a 1: 1 ratio. FIG. 5A shows that the concentration profile varies depending on the acceleration voltage.
[0020]
On the other hand, since the film thickness of the source region and the drain region and the LDD region are different from each other, it is necessary to introduce an impurity element with an acceleration voltage suitable for each of them.
[0021]
The introduction amount of the impurity element required for the LDD region is smaller than the introduction amount required for the source region and the drain region. Therefore, the amount of impurity element introduced into the source region and the drain region when forming the LDD does not matter. Further, the acceleration voltage at the time of forming the source region and the drain region is set lower than the acceleration voltage at the time of forming the LDD region. In this case, the gate insulating film and the gate electrode existing above the LDD region sufficiently function as a mask, and no impurity element is implanted into the LDD region.
[0022]
An impurity element imparting n-type is first introduced into a source region and a drain region of a semiconductor layer forming a p-channel TFT, and then an impurity element imparting p-type at a high acceleration voltage is formed in order to form an LDD region. Then, an impurity element imparting p-type is introduced at a low acceleration voltage in order to form a source region and a drain region. Therefore, semiconductor layers corresponding to the source region and the drain region were prepared, and the sheet resistance value was measured by a four-terminal method. The result is shown in FIG. Here, phosphorous (P) is applied to a crystalline silicon film (film thickness 50 nm) at 1.7 keV at 80 keV. ²⁰ / Cm ^Three 2.3 × 10 ²⁰ / Cm ^Three 2.8 × 10 ²⁰ / Cm ^Three The conditions were introduced so as to obtain a concentration of. This doping process corresponds to a doping process for forming a source region and a drain region of an n-channel TFT. Next, boron (B) is 1.5 × 10 at 70 keV. ²⁰ / Cm ^Three Introduced. This doping process corresponds to a doping process for forming an LDD region of a p-channel TFT. Subsequently, boron (B) conditions were introduced. This doping process corresponds to a doping process for forming a source region and a drain region of a p-channel TFT. Experiments have shown that the sheet resistance of the source region and drain region may be 0.05-2 kΩ (preferably 0.05-1 kΩ). From FIG. 5B, it can be seen that even when boron is introduced at a high acceleration voltage to form the LDD region, the resistance values of the source region and the drain region are lowered to the extent that they function sufficiently as the source region and the drain region.
[0023]
In this way, implantation defects in the source region and the drain region can be minimized, and activation is facilitated. In addition, regarding the doping process to the source region, the drain region, and the LDD region, the acceleration voltage and the introduction amount can be set independently, so that the degree of freedom in design is greatly improved.
[0024]
Note that here, phosphorus has been described as an impurity element imparting n-type, boron as an impurity element imparting p-type, and a silicon film as an example of a semiconductor film. However, in the present invention, the impurity element imparting n-type, the impurity element imparting p-type, and the semiconductor film are not limited to these. For example, as a semiconductor film, there are an amorphous semiconductor film, a microcrystalline semiconductor film, and the like, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied, or an n-type is imparted. An element belonging to Group 15 other than phosphorus as an impurity element or an element belonging to Group 13 other than boron as an impurity element imparting p-type conductivity may be applied.
[0025]
The present invention relates to a method for manufacturing a semiconductor device having a p-channel TFT.
A first step of forming a gate insulating film on the crystalline semiconductor film;
A second step of forming at least one conductive film on the gate insulating film;
A third step of etching the conductive film at least once to form a tapered gate electrode;
A fourth step of forming first and second impurity regions by introducing a first impurity element into the crystalline semiconductor film using the gate electrode as a mask;
A fifth step of selectively introducing the first impurity element into the second impurity region to form a third impurity region;
A sixth step of forming a fourth impurity region by introducing a second impurity element into the first impurity region;
A seventh step of forming a fifth impurity region by introducing the second impurity element into the third impurity region;
A method for manufacturing a semiconductor device.
[0026]
The conductive film is made of a material selected from refractory metals such as tungsten, tantalum, titanium, and molybdenum, compounds containing these metals, or alloys containing these metals.
[0027]
For the etching, an apparatus capable of independently controlling the power of the plasma generation source and the bias power for generating a negative bias voltage on the substrate side is used. Since the taper angle at the end of the gate electrode depends on the bias voltage on the substrate side, it was found that the taper angle of the gate electrode becomes smaller when the bias power of the dry etching apparatus is set larger. By appropriately controlling the bias power, a taper angle of 5 to 70 ° can be formed at the end portion of the gate electrode, and this shape is used for a mask when forming an impurity region. In the sixth step, the gate electrode is formed by performing dry etching so that a taper angle of 5 to 60 ° is formed at the end of the gate electrode.
[0028]
In the fourth step, in order to form the first and second impurity regions, the ionized impurity element is accelerated by an electric field to form a gate insulating film (in this specification, close to the gate electrode and the semiconductor layer). And an insulating film provided between the insulating film and an insulating film extending from the insulating film to a peripheral region thereof is referred to as a gate insulating film) and introduced into the crystalline semiconductor film. Use. In this specification, this impurity element introduction method is referred to as a “through doping method” for convenience.
[0029]
By using the gate electrode having the above-described shape, the through-doping method is used in the fourth step, and the first conductive layer constituting the gate electrode is formed below the tapered portion (tapered portion). The present invention is characterized in that a first impurity region in which the concentration of the impurity element continuously increases as the distance from the channel formation region increases in a self-aligned manner in the existing crystalline semiconductor film.
[0030]
Immediately after the above step 4, the first impurity region overlapping the tapered portion of the first conductive layer constituting the gate electrode via the gate insulating film and the first conductive constituting the gate electrode via the gate insulating film A distinction can be made between the second impurity region which does not overlap the tapered portion of the layer.
[0031]
Subsequently, in the fifth step, in order to form the third impurity region in a self-aligning manner, an ionized impurity element is accelerated by an electric field, passed through the gate insulating film, and introduced into the crystalline semiconductor film. Is used. At this time, if the doping process is performed at a low acceleration voltage, the first conductive layer constituting the gate electrode serves as a mask, so that the third impurity region can be formed in a self-aligning manner.
[0032]
However, in the case of manufacturing a p-channel TFT, a resist is formed, and an impurity element is selectively introduced into the second impurity region to form a third impurity region.
[0033]
By using the through-doping method in the sixth step by using the gate electrode having the shape as described above, the crystalline semiconductor film existing below the tapered portion (tapered portion) of the gate electrode, A fourth impurity region is formed in a self-aligned manner in which the impurity element concentration increases continuously as the distance from the channel formation region increases.
[0034]
Subsequently, in a seventh step, in order to form the fifth impurity region in a self-aligning manner, an ionized impurity element is accelerated by an electric field and passed through the gate insulating film and added to the crystalline semiconductor film Is used. At this time, if the doping process is performed at a low acceleration voltage, the first conductive layer constituting the gate electrode serves as a mask, so that the fifth impurity region can be formed in a self-aligning manner.
[0035]
By reducing the number of masks using the above means, the number of manufacturing steps of the semiconductor device and the time required for manufacturing can be reduced, and the manufacturing cost can be reduced and the yield can be improved.
[0036]
In addition to the above processes, a GOLD structure is formed in a semiconductor device having a crystalline semiconductor film, a gate insulating film, and a gate electrode with the same number of masks by changing the order and conditions of dry etching and impurity element doping processes. can do.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to FIGS.
[0038]
First, the base insulating film 11 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.
[0039]
As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. The base insulating film may be a single layer film of the insulating film or a structure in which two or more layers are stacked. Note that the base insulating film is not necessarily formed.
[0040]
Next, the semiconductor film 12 is formed over the base insulating film. As the semiconductor film 12, a semiconductor film having an amorphous structure is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (such as sputtering, LPCVD, or plasma CVD). Examples of the semiconductor film 12 include an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
[0041]
Subsequently, a thermal crystallization method using a metal element such as nickel is performed. As a method for adding a metal element such as nickel, a plasma treatment method, a vapor deposition method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used, and the metal shown in FIG. The element containing layer 13 is formed. Thereafter, heat treatment is performed to crystallize the semiconductor film. By this crystallization method, a metal element remains in the semiconductor film. Thereafter, as shown in FIG. 1D, laser crystallization may be performed. As a laser oscillator used for laser crystallization, an excimer laser is widely used because it has a high output and can oscillate a high-frequency pulse of about 300 Hz at present. In addition to pulsed excimer lasers, continuous wave excimer lasers, Ar lasers, YAG lasers, YVOs _Four A laser, a YLF laser, or the like can also be used. Laser beam irradiation can be performed in a vacuum, in the air, in a nitrogen atmosphere, or the like. Further, the substrate may be heated to about 500 degrees when the laser beam is irradiated.
[0042]
The obtained crystalline semiconductor film is patterned into a desired shape using a photomask to form semiconductor layers 16a and 16b. Here, the semiconductor layer 16a is a semiconductor layer for forming an n-channel TFT, and the semiconductor layer 16b is a semiconductor layer for forming a p-channel TFT.
[0043]
In addition, after forming the semiconductor layers 16a and 16b, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.
[0044]
Next, a gate insulating film 17 that covers the semiconductor layers 16a and 16b is formed. The gate insulating film 17 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method.
[0045]
When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0046]
Next, a first conductive film 18 having a thickness of 20 to 100 nm and a second conductive film 19 having a thickness of 100 to 400 nm are stacked over the gate insulating film 17. Each of the first conductive film 18 and the second conductive film 19 is an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or compound containing the element as a main component. You may form with a material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used.
[0047]
Next, resist masks 20 and 21 are formed by photolithography, and a first etching process is performed to form electrodes and wirings. The first etching process is performed under the first and second etching conditions. The end portion of the first conductive layer is tapered according to the first etching condition.
[0048]
Thereafter, etching is performed by changing to the second etching condition without removing the masks 20 and 21 made of resist. Under the second etching condition, the first conductive film 18 and the second conductive film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0049]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 22 and 23 composed of the first conductive layer and the second conductive layer by the first etching process (first conductive layers 22a and 23a and second conductive layers 22b and 23b). Form. Reference numeral 24 denotes a gate insulating film, and regions that are not covered with the first shape conductive layers 22 and 23 are etched and thinned by about 20 to 50 nm.
[0050]
Next, a second etching process is performed without removing the resist mask. Here, the second conductive film is selectively etched. At this time, the second conductive layers 25b and 26b are formed by the second etching process. On the other hand, the first conductive layers 25a and 26a are hardly etched, and the second shape conductive layers 25 and 26 are formed.
[0051]
Then, a first doping process is performed to obtain the state of FIG. The doping process may be performed by ion doping or ion implantation. Conditions for the first doping process are an acceleration voltage of 60 to 120 keV and an average concentration of the impurity regions 28 and 29 of 1 × 10 6. ¹⁷ ~ 5x10 ²⁰ /cm ^Three To do so. As the impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In the first doping process, the second shape conductive layers 25 and 26 are used as masks against the impurity element so that the impurity element is also added to the semiconductor layer below the tapered portion of the second conductive layers 25a and 26a. Doping. The concentration of phosphorus (P) added to the impurity region has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer. Thus, of the impurity regions 28 and 29 formed in a self-aligned manner, the impurity regions overlapping with the conductive layers 25 and 26 are 28b and 29b, and the impurity regions not overlapping with the conductive layers 25 and 26 are 28a and 29a.
[0052]
Next, using the conductive layers 25 and 26 as a mask, the gate insulating film 27 is selectively removed to form insulating layers 30a and 30b. Alternatively, the resist mask used to form the second shape conductive layers 25 and 26 may be removed simultaneously with the formation of the insulating layers 30a and 30b. (Fig. 2 (B))
[0053]
A second doping process is performed to add an impurity element imparting n-type to the semiconductor layer. Doping uses the first conductive layer and the second conductive layer as a mask for the impurity element, and introduces the impurity element into the semiconductor layer. In the second doping process, a mask 31 made of resist is covered so that an impurity element is introduced into part of the source region and the drain region of the semiconductor layer forming the p-channel TFT. The conditions for the second doping process are an acceleration voltage of 5 to 40 keV and an average concentration of the impurity regions 32 and 33a of 1 × 10 6. ²⁰ ~ 5x10 ^{twenty one} /cm ^Three To do so. Thus, impurity regions 32 and 33a that do not overlap with the first conductive layer are formed in a self-aligning manner. By the mask 31, the impurity region 29a is divided into a region 33a into which the impurity element imparting n-type is introduced and a region 33b into which the impurity element is not introduced by the second doping process. Here, the impurity element imparting n-type conductivity is also introduced into the semiconductor layer forming the p-channel TFT because the metal element used for promoting crystallization is removed from the channel formation region or the electrical characteristics of the TFT. This is because it is necessary to reduce to a level that does not adversely affect
[0054]
Next, after removing the resist mask, a new resist mask 34 is formed and a third doping process is performed. In the third doping process, the semiconductor layer forming the n-channel TFT is covered with a mask 34 made of resist. In the third doping process, in order to form the LDD region of the p-channel TFT, an impurity element imparting p-type is introduced at a high acceleration voltage. The conditions for the third doping process are an acceleration voltage of 60 to 120 keV and an average concentration of the impurity region 35 of 1 × 10 6. ¹⁸ ~ 5x10 ^{twenty one} /cm ^Three To do so. At the same time, an impurity element imparting p-type is also introduced into the source region and the drain region. However, the introduction amount of the impurity element imparting the p-type necessary for the LDD region is several orders of magnitude less than the introduction amount required for the source region and the drain region. Therefore, the impurity element imparting p-type introduced into the source region and the drain region in the third doping process does not cause a problem. Further, an impurity element imparting n-type is added to the impurity region 35 by the first doping treatment, but the average concentration of the impurity element imparting p-type is 1 × 10. ¹⁸ ~ 5x10 ^{twenty one} /cm ^Three By performing the doping process so as to become, no problem arises because it functions as the LDD region of the p-channel TFT.
[0055]
Subsequently, a fourth doping process is performed without removing the mask 34. By the fourth doping treatment, an impurity region 36 is formed in which an impurity element imparting a conductivity type opposite to the one conductivity type is introduced into the semiconductor layer that becomes the active layer of the p-channel TFT. The fourth doping condition is that the acceleration voltage is 5 to 40 keV and the average concentration of the impurity region is 1 × 10 6. ²⁰ ~ 5x10 ^{twenty two} /cm ^Three To do so. The first conductive layer 26a and the second conductive layer 26b are used as masks against the impurity element, and an impurity element imparting p-type is added to form the impurity region 36 in a self-aligned manner. (FIG. 3 (A)). By the first doping process and the second doping process, an impurity element imparting n-type is added to the impurity regions 36a and 36b at different concentrations. Impurities imparting p-type in any of the regions. The average concentration of elements is 1 × 10 ²⁰ ~ 5x10 ^{twenty two} /cm ^Three By performing the doping treatment so as to become, no problem arises because it functions as the source region and drain region of the p-channel TFT. In this embodiment, since a part of the semiconductor layer serving as an active layer of the p-channel TFT is exposed, there is an advantage that an impurity element imparting p-type can be easily added.
[0056]
Through the above steps, impurity regions are formed in the respective semiconductor layers.
[0057]
Next, the resist mask 34 is removed, and a first interlayer insulating film 37 is formed. The interlayer insulating film 37 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using plasma CVD or sputtering. As the interlayer insulating film 37, another insulating film containing silicon may be used as a single layer or a laminated structure.
[0058]
Next, as shown in FIG. 3B, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, 550 ° C. for 4 hours. The activation treatment was performed by heat treatment. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0059]
In this embodiment, at the same time as the activation treatment, the metal element used as a catalyst during crystallization is gettered to the impurity regions 32 and 36 containing an impurity element imparting a high concentration of n-type, mainly. The concentration of the metal element in the semiconductor layer serving as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0060]
In addition, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak against heat, it is activated after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. It is preferable to perform the conversion treatment.
[0061]
The present invention having the above-described configuration will be described in more detail with the following embodiments.
[0062]
【Example】
[Example 1]
Embodiments of the present invention will be described below with reference to FIGS.
[0063]
First, the base insulating film 11 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.
[0064]
As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. The base insulating film may be a single layer film of the insulating film or a structure in which two or more layers are stacked. Note that the base insulating film is not necessarily formed.
[0065]
Next, the semiconductor film 12 is formed over the base insulating film. As the semiconductor film 12, a semiconductor film having an amorphous structure is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (such as sputtering, LPCVD, or plasma CVD). Examples of the semiconductor film 12 include an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
[0066]
Subsequently, a thermal crystallization method using a metal element such as nickel is performed. As a method for adding a metal element such as nickel, a plasma treatment method, a vapor deposition method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used, and the metal shown in FIG. The element containing layer 13 is formed. Thereafter, heat treatment is performed to crystallize the semiconductor film. By this crystallization method, a metal element remains in the semiconductor film. Thereafter, as shown in FIG. 1D, laser crystallization may be performed. As a laser oscillator used for laser crystallization, an excimer laser is widely used because it has a high output and can oscillate a high-frequency pulse of about 300 Hz at present. In addition to pulsed excimer lasers, continuous wave excimer lasers, Ar lasers, YAG lasers, YVOs _Four A laser, a YLF laser, or the like can also be used. Laser beam irradiation can be performed in a vacuum, in the air, in a nitrogen atmosphere, or the like. Further, the substrate may be heated to about 500 degrees when the laser beam is irradiated.
[0067]
The obtained crystalline semiconductor film is patterned into a desired shape using a photomask to form semiconductor layers 16a and 16b. Here, the semiconductor layer 16a is a semiconductor layer for forming an n-channel TFT, and the semiconductor layer 16b is a semiconductor layer for forming a p-channel TFT.
[0068]
In addition, after forming the semiconductor layers 16a and 16b, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.
[0069]
Next, a gate insulating film 17 that covers the semiconductor layers 16a and 16b is formed. The gate insulating film 17 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0070]
When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0071]
Next, a first conductive film 18 having a thickness of 20 to 100 nm and a second conductive film 19 having a thickness of 100 to 400 nm are stacked over the gate insulating film 17. In this example, a first conductive film 408 made of a TaN film with a thickness of 30 nm and a second conductive film 409 made of a W film with a thickness of 370 nm were stacked. The TaN film was formed by sputtering, and was sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by sputtering using a W target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, if the W film contains a large amount of impurity elements such as oxygen, crystallization is hindered and the resistance is increased. Therefore, in this embodiment, a sputtering method using a target of high purity W (purity 99.9999%) is used, and a W film is formed with sufficient consideration so that impurities are not mixed in the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.
[0072]
In this embodiment, the first conductive film 18 is TaN and the second conductive film 19 is W. However, the present invention is not particularly limited, and any of them is Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the element selected from these, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. In addition, the first conductive film is formed using a tantalum (Ta) film, the second conductive film is formed using a W film, the first conductive film is formed using a titanium nitride (TiN) film, and the second conductive film is formed. The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. The second conductive film may be a combination of Cu films.
[0073]
Next, resist masks 20 and 21 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ Each gas flow rate ratio was 25/25/10 (sccm), and 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. . Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the first etching condition, the end portion of the first conductive layer is tapered.
[0074]
Thereafter, the resist masks 20 and 21 are not removed and the second etching condition is changed, and the etching gas is changed to CF. _Four And Cl ₂ Each gas flow rate ratio is 30/30 (sccm), and plasma is generated by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa, and etching is performed for about 30 seconds. Went. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition, the first conductive film 18 and the second conductive film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0075]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 22 and 23 composed of the first conductive layer and the second conductive layer by the first etching process (first conductive layers 22a and 23a and second conductive layers 22b and 23b). Form. Reference numeral 24 denotes a gate insulating film, and regions that are not covered with the first shape conductive layers 22 and 23 are etched and thinned by about 20 to 50 nm.
[0076]
Next, a second etching process is performed without removing the resist mask. Here, CF is used as the etching gas here. _Four And Cl ₂ And O ₂ Then, the second conductive film made of the W film is selectively etched. At this time, the second conductive layers 25b and 26b are formed by the second etching process. On the other hand, the first conductive layers 25a and 26a are hardly etched, and the second shape conductive layers 25 and 26 are formed.
[0077]
Then, a first doping process is performed to obtain the state of FIG. The doping process may be performed by ion doping or ion implantation. The conditions for the first doping process are an acceleration voltage of 60 to 120 keV and a concentration of 1 × 10 6. ¹⁷ ~ 5x10 ²⁰ /cm ^Three To do so. In this embodiment, the acceleration voltage is 90 keV, and the average concentration of the impurity regions 28 and 29 is 2.5 × 10 6. ¹⁸ /cm ^Three The first doping process was performed so that As the impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In the first doping process, the second shape conductive layers 25 and 26 are used as masks against the impurity element so that the impurity element is also added to the semiconductor layer below the tapered portion of the second conductive layers 25a and 26a. Doping. The concentration of phosphorus (P) added to the impurity region has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer. Thus, of the impurity regions 28 and 29 formed in a self-aligned manner, the impurity regions overlapping with the conductive layers 25 and 26 are 28b and 29b, and the impurity regions not overlapping with the conductive layers 25 and 26 are 28a and 29a.
[0078]
Next, using the conductive layers 25 and 26 as a mask, the gate insulating film 27 is selectively removed to form insulating layers 30a and 30b. Alternatively, the resist mask used to form the second shape conductive layers 25 and 26 may be removed simultaneously with the formation of the insulating layers 30a and 30b. (Fig. 2 (B))
[0079]
A second doping process is performed to add an impurity element imparting n-type to the semiconductor layer. Doping uses the first conductive layer and the second conductive layer as a mask for the impurity element, and introduces the impurity element into the semiconductor layer. In the second doping process, a mask 31 made of resist is covered so that an impurity element is introduced into part of the source region and the drain region of the semiconductor layer forming the p-channel TFT. The conditions of the second doping process are an acceleration voltage of 5 to 40 keV and a concentration of 1 × 10 6. ²⁰ ~ 5x10 ^{twenty one} /cm ^Three To do so. In this embodiment, the acceleration voltage is set to 10 keV, and the average concentration of the impurity regions 32 and 33a is 2.0 × 10. ²⁰ /cm ^Three A second doping process was performed so that Thus, impurity regions 32 and 33a that do not overlap with the first conductive layer are formed in a self-aligning manner. By the mask 31, the impurity region 29a is divided into a region 33a into which the impurity element imparting n-type is introduced and a region 33b into which the impurity element is not introduced by the second doping process. Here, the impurity element imparting n-type conductivity is also introduced into the semiconductor layer forming the p-channel TFT because the metal element used for promoting crystallization is removed from the channel formation region or the electrical characteristics of the TFT. This is because it is necessary to reduce to a level that does not adversely affect
[0080]
Next, after removing the resist mask, a new resist mask 34 is formed and a third doping process is performed. In the third doping process, the semiconductor layer forming the n-channel TFT is covered with a mask 34 made of resist. In the third doping process, in order to form the LDD region of the p-channel TFT, an impurity element imparting p-type is introduced at a high acceleration voltage. The conditions for the third doping process are an acceleration voltage of 60 to 120 keV and a concentration of 1 × 10 6. ¹⁸ ~ 5x10 ^{twenty one} /cm ^Three To do so. In this embodiment, the acceleration voltage is 80 keV, and the average concentration of the impurity region 35 is 5.0 × 10 5. ¹⁹ /cm ^Three A third doping process was performed so that At the same time, an impurity element imparting p-type is also introduced into the source region and the drain region. However, the introduction amount of the impurity element imparting the p-type necessary for the LDD region is several orders of magnitude less than the introduction amount required for the source region and the drain region. Therefore, the impurity element imparting p-type introduced into the source region and the drain region in the third doping process does not cause a problem. Further, an impurity element imparting n-type is added to the impurity region 35 by the first doping treatment, but the average concentration of the impurity element imparting p-type is 1 × 10. ¹⁸ ~ 5x10 ^{twenty one} /cm ^Three By performing the doping process so as to become, no problem arises because it functions as the LDD region of the p-channel TFT.
[0081]
Subsequently, a fourth doping process is performed without removing the mask 34. By the fourth doping treatment, an impurity region 36 is formed in which an impurity element imparting a conductivity type opposite to the one conductivity type is introduced into the semiconductor layer that becomes the active layer of the p-channel TFT. The conditions for the fourth doping process are an acceleration voltage of 5 to 40 keV and a concentration of 1 × 10 6. ²⁰ ~ 5x10 ^{twenty two} /cm ^Three To do so. The first conductive layer 26a and the second conductive layer 26b are used as masks against the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligning manner. (FIG. 3 (A)). In this embodiment, the acceleration voltage is 10 keV, and the average concentration of the impurity regions 36 is 1.0 × 10 6. ^{twenty one} /cm ^Three A fourth doping process was performed so that By the first doping process and the second doping process, an impurity element imparting n-type is added to the impurity regions 36a and 36b at different concentrations. Impurities imparting p-type in any of the regions. Element concentration is 1 × 10 ²⁰ ~ 5x10 ^{twenty two} /cm ^Three By performing the doping treatment so as to become, no problem arises because it functions as the source region and drain region of the p-channel TFT. In this embodiment, since a part of the semiconductor layer serving as an active layer of the p-channel TFT is exposed, there is an advantage that an impurity element imparting p-type can be easily added.
[0082]
Through the above steps, impurity regions are formed in the respective semiconductor layers.
[0083]
Next, the resist mask 34 is removed, and a first interlayer insulating film 37 is formed. The interlayer insulating film 37 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using plasma CVD or sputtering. As the interlayer insulating film 37, another insulating film containing silicon may be used as a single layer or a laminated structure.
[0084]
Next, as shown in FIG. 3B, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, 550 ° C. for 4 hours. The activation treatment was performed by heat treatment. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0085]
In this embodiment, at the same time as the activation treatment, the metal element used as a catalyst during crystallization is gettered to the impurity regions 32 and 36 containing an impurity element imparting a high concentration of n-type, mainly. The concentration of the metal element in the semiconductor layer serving as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0086]
In addition, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak against heat, it is activated after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. It is preferable to perform the conversion treatment.
[0087]
[Example 2]
In this embodiment, a method for manufacturing a TFT without selectively removing the gate insulating film after the first doping process shown in Embodiment 1 will be described with reference to FIGS.
[0088]
According to Embodiment 1, the state of FIG.
[0089]
Subsequently, an impurity element imparting n-type conductivity is added to the semiconductor layer by performing a second doping process. Doping uses the first conductive layer and the second conductive layer as a mask for the impurity element, and introduces the impurity element into the semiconductor layer. In the second doping process, a mask 51 made of resist is covered so that an impurity element is introduced into part of the source region and the drain region of the semiconductor layer forming the p-channel TFT. The conditions for the second doping process are an acceleration voltage of 5 to 40 keV and an average concentration of the impurity regions 52 and 53a of 1 × 10 6. ²⁰ ~ 5x10 ^{twenty one} /cm ^Three To do so. In this embodiment, the acceleration voltage is 30 keV and the concentration is 2.0 × 10. ²⁰ /cm ^Three A second doping process was performed so that Thus, impurity regions 52 and 53a that do not overlap with the first conductive layer are formed in a self-aligning manner. By the mask 51, the impurity region 29a is divided into a region 53a into which an impurity element imparting n-type is introduced and a region 53b into which the impurity element is not introduced by the second doping process. Here, the impurity element imparting n-type conductivity is also introduced into the semiconductor layer forming the p-channel TFT because the metal element used for promoting crystallization is removed from the channel formation region or the electrical characteristics of the TFT. This is because it is necessary to reduce to a level that does not adversely affect
[0090]
Next, after removing the resist mask, a new resist mask 54 is formed and a third doping process is performed. In the third doping process, the semiconductor layer forming the n-channel TFT is covered with a mask 54 made of resist. In the third doping process, in order to form the LDD region of the p-channel TFT, an impurity element imparting p-type is introduced at a high acceleration voltage. The conditions for the third doping process are an acceleration voltage of 60 to 120 keV and a concentration of 1 × 10 6. ¹⁸ ~ 5x10 ^{twenty one} /cm ^Three To do so. In this embodiment, the acceleration voltage is 80 keV, and the average concentration of the impurity region 55 is 5.0 × 10 5. ¹⁹ /cm ^Three A third doping process was performed so that At the same time, an impurity element imparting p-type is also introduced into the source region and the drain region. However, the introduction amount of the impurity element imparting the p-type necessary for the LDD region is several orders of magnitude less than the introduction amount required for the source region and the drain region. Therefore, the impurity element imparting p-type introduced into the source region and the drain region in the third doping process does not cause a problem. Further, an impurity element imparting n-type conductivity is added to the impurity region 55 by the first doping treatment, but the average concentration of the impurity element imparting p-type conductivity is 1 × 10 6. ¹⁸ ~ 5x10 ^{twenty one} /cm ^Three By performing the doping process so as to become, no problem arises because it functions as the LDD region of the p-channel TFT.
[0091]
Subsequently, a fourth doping process is performed without removing the mask 54. By the fourth doping treatment, an impurity region 56 is formed in which an impurity element imparting a conductivity type opposite to the one conductivity type is introduced into the semiconductor layer that becomes an active layer of the p-channel TFT. The conditions for the fourth doping process are an acceleration voltage of 5 to 40 keV and an average concentration of the impurity region 56 of 1 × 10 6. ²⁰ ~ 5x10 ^{twenty two} /cm ^Three To do so. The first conductive layer 26a and the second conductive layer 26b are used as masks against the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligning manner. (FIG. 4C). In this embodiment, the acceleration voltage is 30 keV and the average concentration of the impurity region 56 is 1.0 × 10 6. ^{twenty one} /cm ^Three A fourth doping process was performed so that By the first doping process and the second doping process, an impurity element imparting n-type is added to the impurity regions 36a and 36b at different concentrations. Impurities imparting p-type in any of the regions. The average concentration of elements is 1 × 10 ²⁰ ~ 5x10 ^{twenty two} /cm ^Three By performing the doping treatment so as to become, no problem arises because it functions as the source region and drain region of the p-channel TFT. In this embodiment, since a part of the semiconductor layer serving as an active layer of the p-channel TFT is exposed, there is an advantage that an impurity element imparting p-type can be easily added.
[0092]
Through the above steps, impurity regions are formed in the respective semiconductor layers.
[0093]
Next, the resist mask 54 is removed, and a first interlayer insulating film 57 is formed. The interlayer insulating film 57 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using plasma CVD or sputtering. As the interlayer insulating film 57, another insulating film containing silicon may be used as a single layer or a laminated structure.
[0094]
Next, as shown in FIG. 4D, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, 550 ° C. for 4 hours. The activation treatment was performed by heat treatment. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0095]
In this embodiment, at the same time as the activation treatment, the metal element used as a catalyst during crystallization is gettered to the impurity regions 52 and 56 containing an impurity element imparting a high concentration of n-type, and mainly. The concentration of the metal element in the semiconductor layer serving as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0096]
In addition, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak against heat, it is activated after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. It is preferable to perform the conversion treatment.
[Example 4]
In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS.
[0097]
First, in this embodiment, a substrate 400 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. Note that as the substrate 300, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.
[0098]
Next, a base film 301 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 300. Although a two-layer structure is used as the base film 301 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 301, a plasma CVD method is used, and SiH _Four , NH _Three And N ₂ A silicon oxynitride film 301a formed using O as a reactive gas is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm). In this embodiment, a 50 nm thick silicon oxynitride film 301a (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) was formed. Next, as the second layer of the base film 401, a plasma CVD method is used, and SiH _Four And N ₂ A silicon oxynitride film 401b formed using O as a reactive gas is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). In this embodiment, a silicon oxynitride film 401b (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) having a thickness of 100 nm is formed.
[0099]
Next, semiconductor layers 402 to 406 are formed over the base film. As the semiconductor layers 402 to 406, a semiconductor film having an amorphous structure is formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Examples of the semiconductor film 12 include an amorphous semiconductor film, a microcrystalline semiconductor film, a polycrystalline semiconductor film, and the like, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In this example, a 55 nm amorphous silicon film was formed by plasma CVD.
[0100]
Subsequently, a thermal crystallization method using a metal element such as nickel is performed. As a method for adding a metal element such as nickel, a plasma treatment method, a vapor deposition method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used. The metal shown in FIG. The containing layer 303 is formed. Thereafter, heat treatment is performed to crystallize the semiconductor layer. In this embodiment, a solution containing nickel is held on an amorphous silicon film, and this amorphous silicon film is dehydrogenated (500 ° C., 1 hour) and then thermally crystallized (550 ° C., 4 hours Time).
[0101]
The obtained crystalline semiconductor film is formed by patterning into a desired shape. The semiconductor layers 402 to 406 are formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm). In this embodiment, the semiconductor layers 402 to 406 are formed by patterning the crystalline silicon film using a photolithography method.
[0102]
Further, after forming the semiconductor layers 402 to 406, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.
[0103]
When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO _Four A laser or the like can be used. In the case of using these lasers, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. Crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 400 mJ / cm. ² (Typically 200-300mJ / cm ² ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 300 Hz, and the laser energy density is 300 to 600 mJ / cm. ² (Typically 350-500mJ / cm ² ) Then, a laser beam condensed in a linear shape with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser beam at this time is 50 to 98%. Good.
[0104]
Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0105]
When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.
[0106]
Next, as illustrated in FIG. 6C, a first conductive film 408 with a thickness of 20 to 100 nm and a second conductive film 409 with a thickness of 100 to 400 nm are stacked over the gate insulating film 407. In this example, a first conductive film 408 made of a TaN film with a thickness of 30 nm and a second conductive film 409 made of a W film with a thickness of 370 nm were stacked. The TaN film was formed by sputtering, and was sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by sputtering using a W target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, if the W film contains a large amount of impurity elements such as oxygen, crystallization is hindered and the resistance is increased. Therefore, in this embodiment, a sputtering method using a target of high purity W (purity 99.9999%) is used, and a W film is formed with sufficient consideration so that impurities are not mixed in the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.
[0107]
In this embodiment, the first conductive film 408 is TaN and the second conductive film 409 is W. However, there is no particular limitation, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the element selected from these, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. In addition, the first conductive film is formed using a tantalum (Ta) film, the second conductive film is formed using a W film, the first conductive film is formed using a titanium nitride (TiN) film, and the second conductive film is formed. The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. The second conductive film may be a combination of Cu films.
[0108]
Next, resist masks 410 to 415 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ Each gas flow rate ratio was 25/25/10 (sccm), and 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. . Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered.
[0109]
Thereafter, the resist masks 410 to 415 are not removed and the second etching condition is changed, and the etching gas is changed to CF. _Four And Cl ₂ Each gas flow rate ratio is 30/30 (sccm), and plasma is generated by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa, and etching is performed for about 30 seconds. Went. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching condition in which is mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0110]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 417 to 422 (first conductive layers 417 a to 422 a and second conductive layers 417 b to 422 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form. Reference numeral 416 denotes a gate insulating film, and a region not covered with the first shape conductive layers 417 to 422 is etched and thinned by about 20 to 50 nm.
[0111]
Next, a second etching process is performed without removing the resist mask.
Here, the second conductive film is selectively etched. At this time, second conductive layers 428b to 433b are formed by a second etching process. On the other hand, the first conductive layers 428a to 433a are hardly etched, and the second shape conductive layers 428 to 433 are formed.
[0112]
Then, a first doping process is performed to obtain the state of FIG. The doping process may be performed by ion doping or ion implantation. The conditions for the first doping process are an acceleration voltage of 60 to 120 keV and a concentration of 1 × 10 6. ¹⁷ ~ 5x10 ²⁰ /cm ^Three To do so. In this embodiment, the acceleration voltage is 90 keV, and the average concentration of the impurity regions 423 to 427 is 2.5 × 10 5. ¹⁸ /cm ^Three The first doping process was performed so that As the impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In the first doping treatment, the second shape conductive layers 428 to 433 are used as masks against the impurity elements so that the impurity elements are also added to the semiconductor layers below the tapered portions of the second conductive layers 428a to 433a. Doping. The concentration of phosphorus (P) added to the impurity region has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer. Thus, among the impurity regions 423 to 427 formed in a self-aligning manner, the impurity regions overlapping with the second conductive layers 428b to 433b are 423b to 427b, and the impurity regions not overlapping with the second conductive layers 428b to 433b are included. 423a to 427a.
[0113]
Next, after removing the resist mask, the gate insulating film 338 is selectively removed using the second shape conductive layers 428 to 433 as masks to form insulating layers 339a to 339g. Alternatively, the resist mask used for forming the second shape conductive layers 428 to 433 may be removed simultaneously with the formation of 339a to 339g. (Fig. 7 (B))
[0114]
A second doping process is performed to add an impurity element imparting n-type to the semiconductor layer. Doping uses the first conductive layer and the second conductive layer as a mask for the impurity element, and introduces the impurity element into the semiconductor layer. In the second doping treatment, masks 441a to 441c made of resist are covered so that an impurity element is introduced into part of the source region and the drain region of the semiconductor layer forming the p-channel TFT. The conditions of the second doping process are an acceleration voltage of 5 to 40 keV and a concentration of 1 × 10 6. ²⁰ ~ 5x10 ^{twenty one} /cm ^Three To do so. Thus, impurity regions 434 to 438 that do not overlap with the first conductive layer in a self-aligning manner are formed. In this embodiment, the acceleration voltage is 10 keV, and the average concentration of the impurity regions 434 to 438 is 1.5 × 10 6. ²⁰ /cm ^Three A second doping process was performed so that By the masks 441a to 441c, the impurity regions 424a and 426a are divided into regions 435 and 437 into which the impurity element imparting n-type is introduced and regions 439 and 440 into which the impurity element is not introduced by the second doping treatment. Here, the impurity element imparting n-type conductivity is also introduced into the semiconductor layer forming the p-channel TFT because the metal element used for promoting crystallization is removed from the channel formation region or the electrical characteristics of the TFT. This is because it is necessary to reduce to a level that does not adversely affect
[0115]
Next, after removing the resist mask, a new resist mask is formed and a third doping process is performed. In the third doping process, the semiconductor layer forming the n-channel TFT is covered with masks 452-454 made of resist. In the third doping process, in order to form the LDD region of the p-channel TFT, an impurity element imparting p-type is introduced at a high acceleration voltage. The conditions for the third doping process are an acceleration voltage of 60 to 120 keV and a concentration of 1 × 10 6. ¹⁸ ~ 5x10 ^{twenty one} /cm ^Three To do so. In this embodiment, the acceleration voltage is 80 keV and the average concentration of the impurity regions is 5.0 × 10 5. ¹⁹ /cm ^Three And the third doping process was performed so that 455 and 456. At the same time, an impurity element imparting p-type is also introduced into the source region and the drain region. However, the introduction amount of the impurity element imparting the p-type necessary for the LDD region is several orders of magnitude less than the introduction amount required for the source region and the drain region. Therefore, the impurity element imparting p-type introduced into the source region and the drain region in the third doping process does not cause a problem. Further, an impurity element imparting n-type conductivity is added to the impurity regions 455 and 456 by the first doping treatment, and the concentration of the impurity element imparting p-type conductivity is 1 × 10 5 in any of the regions. ¹⁸ ~ 5x10 ^{twenty one} /cm ^Three By performing the doping process so as to become, no problem arises because it functions as the LDD region of the p-channel TFT.
[0116]
Subsequently, a fourth doping process is performed without removing the masks 452-454.
By the fourth doping treatment, impurity regions 457 to 459 in which an impurity element imparting a conductivity type opposite to the one conductivity type is introduced into the semiconductor layer that becomes an active layer of the p-channel TFT are formed. The conditions for the fourth doping process are an acceleration voltage of 5 to 40 keV and a concentration of 1 × 10 6. ²⁰ ~ 5x10 ^{twenty two} /cm ^Three To do so. The second shape conductive layers 428 to 433 are used as masks against the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligning manner. (FIG. 8C) In this embodiment, the acceleration voltage is set to 10 keV, and the average concentration of the impurity regions 457 to 459 is 1.0 × 10. ^{twenty one} /cm ^Three A fourth doping process was performed so that By the first doping process and the second doping process, impurity elements imparting n-type are added to the impurity regions 457 to 459 at different concentrations. Impurities imparting p-type in any of the regions. Element concentration is 1 × 10 ²⁰ ~ 5x10 ^{twenty two} /cm ^Three By performing the doping treatment so as to become, no problem arises because it functions as the source region and drain region of the p-channel TFT. In this embodiment, since a part of the semiconductor layer serving as an active layer of the p-channel TFT is exposed, there is an advantage that an impurity element imparting p-type can be easily added.
[0117]
Through the above steps, impurity regions are formed in the respective semiconductor layers.
[0118]
Next, the resist masks 452 to 454 are removed, and a first interlayer insulating film 461 is formed. The first interlayer insulating film 461 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 461 is not limited to the silicon oxynitride film, and an insulating film containing other silicon may be used as a single layer or a stacked structure.
[0119]
Next, as shown in FIG. 9A, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, 550 ° C. for 4 hours. The activation treatment was performed by heat treatment. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0120]
In this embodiment, simultaneously with the activation treatment, the impurity regions 434, 436 to 438, 457, and 459 in which nickel used as a catalyst in the crystallization contains phosphorus at a high concentration are crystallized. Therefore, the impurity region and the metal element are gettered to reduce the nickel concentration in the semiconductor layer mainly serving as a channel formation region. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0121]
In addition, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak against heat, it is activated after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. It is preferable to perform the conversion process.
[0122]
Further, a step of hydrogenating the semiconductor layer is performed by performing a heat treatment at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. In this embodiment, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0123]
In the case where a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after the hydrogenation.
[0124]
Next, a second interlayer insulating film 462 made of an inorganic insulating film material or an organic insulating material is formed over the first interlayer insulating film 461. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed, but is not particularly limited, and an insulating film containing silicon (a silicon oxynitride film, a silicon oxide film, a silicon nitride film, or the like) is a single layer or a stacked structure It may be used as
[0125]
In the driver circuit 506, wirings 463 to 467 that are electrically connected to the impurity regions are formed. Note that these wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm.
[0126]
In the pixel portion 507, a pixel electrode 470, a gate wiring 469, and a connection electrode 468 are formed. (FIG. 9B) With this connection electrode 468, the source wiring (lamination of 443b and 449) is electrically connected to the pixel TFT. In addition, the gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. In addition, the pixel electrode 470 is electrically connected to the drain region 442 of the pixel TFT and further electrically connected to the semiconductor layer 458 functioning as one electrode forming a storage capacitor. Further, as the pixel electrode 471, it is desirable to use a highly reflective material such as a film containing Al or Ag as a main component or a laminated film thereof.
[0127]
As described above, a CMOS circuit including an n-channel TFT 501 and a p-channel TFT 502, a driver circuit 506 having an n-channel TFT 503, and a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 are formed over the same substrate. can do. Thus, the active matrix substrate is completed.
[0128]
The n-channel TFT 501 of the driver circuit 506 includes a channel formation region 423c, a low-concentration impurity region 423b (GOLD region) that overlaps with the first conductive layer 428a that forms part of the gate electrode, and a high concentration functioning as a source region or a drain region. An impurity region 434 is provided. A p-channel TFT 502 which is connected to the n-channel TFT 501 and the electrode 466 to form a CMOS circuit has a channel formation region 424c, an impurity region 424b which overlaps with the first conductive layer 429a constituting a part of the gate electrode, and a source region. Alternatively, high-concentration impurity regions 457 and 458 functioning as drain regions are provided. The n-channel TFT 503 includes a channel formation region 425c, a low-concentration impurity region 425b (GOLD region) that overlaps with the first conductive layer 430a that forms part of the gate electrode, and a high-concentration impurity that functions as a source region or a drain region. A region 436 is included.
[0129]
A pixel TFT 504 in the pixel portion includes a channel formation region 426c, a low-concentration impurity region 426b (GOLD region) that overlaps with the first conductive layer 431a that forms part of the gate electrode, and a high-concentration impurity region that functions as a source region or a drain region. 437. In addition, an impurity element imparting p-type conductivity is added to each of the semiconductor layers 456 and 459 functioning as one electrode of the storage capacitor 505. The storage capacitor 505 is formed of an electrode (stack of 432a and 432b) and semiconductor layers 456, 459, and 427c using the insulating film 339g as a dielectric.
[0130]
In the pixel structure of this embodiment, the end of the pixel electrode overlaps with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.
[0131]
FIG. 10 is a top view of the pixel portion of the active matrix substrate manufactured in this embodiment. In addition, the same code | symbol is used for the part corresponding to FIGS. A chain line AA ′ in FIG. 9B corresponds to a cross-sectional view taken along the chain line AA ′ in FIG. Further, a chain line BB ′ in FIG. 9B corresponds to a cross-sectional view taken along the chain line BB ′ in FIG.
[0132]
[Example 5]
In this embodiment, a process of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 4 will be described below. FIG. 11 is used for the description.
[0133]
First, after obtaining an active matrix substrate in the state of FIG. 9B in accordance with Embodiment 4, an alignment film 471 is formed on at least the pixel electrode 470 on the active matrix substrate of FIG. In this embodiment, before forming the alignment film 471, an organic resin film such as an acrylic resin film is patterned to form columnar spacers (not shown) for maintaining the substrate interval at a desired position. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0134]
Next, a counter substrate 472 is prepared. Next, colored layers 473 and 474 and a planarization film 475 are formed over the counter substrate 472. The red colored layer 473 and the blue colored layer 474 are overlapped to form a light shielding portion. Further, the light shielding portion may be formed by partially overlapping the red colored layer and the green colored layer.
[0135]
In this example, the substrate shown in Example 4 is used. Therefore, in FIG. 10 showing a top view of the pixel portion of Example 4, at least the gap between the gate wiring 469 and the pixel electrode 470, the gap between the gate wiring 469 and the connection electrode 468, and the gap between the connection electrode 468 and the pixel electrode 470 are shown. It is necessary to shield the light. In this example, the respective colored layers were arranged so that the light-shielding portions formed by the lamination of the colored layers overlapped at the positions where light shielding should be performed, and the counter substrate was bonded.
[0136]
As described above, the number of steps can be reduced by shielding the gap between the pixels with the light shielding portion formed by the lamination of the colored layers without forming a light shielding layer such as a black mask.
[0137]
Next, a counter electrode 476 made of a transparent conductive film was formed over the planarization film 475 in at least the pixel portion, an alignment film 477 was formed over the entire surface of the counter substrate, and a rubbing process was performed.
[0138]
Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 478. Filler is mixed in the sealing material 478, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 479 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 479. In this way, the reflection type liquid crystal display device shown in FIG. 11 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. And FPC was affixed using the well-known technique.
[0139]
The liquid crystal display panel manufactured as described above can be used as a display portion of various electronic devices.
[0140]
[Example 6]
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described. FIG. 12 is a cross-sectional view of the EL display device of the present invention.
[0141]
In FIG. 12, a switching TFT 603 provided over a substrate 700 is formed using the n-channel TFT 503 in FIG. Therefore, the description of the n-channel TFT 503 may be referred to for the description of the structure.
[0142]
Note that although a double gate structure in which two channel formation regions are formed is used in this embodiment, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed may be used.
[0143]
A driver circuit provided over the substrate 700 is formed using the CMOS circuit of FIG. Therefore, for the description of the structure, the description of the n-channel TFT 501 and the p-channel TFT 502 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.
[0144]
Further, the wirings 701 and 703 function as source wirings of the CMOS circuit, and the wiring 702 functions as a drain wiring. The wiring 704 functions as a wiring that electrically connects the source wiring 708 and the source region of the switching TFT, and the wiring 705 functions as a wiring that electrically connects the drain wiring 709 and the drain region of the switching TFT.
[0145]
Note that the current control TFT 604 is formed using the p-channel TFT 502 of FIG. Accordingly, the description of the p-channel TFT 502 may be referred to for the description of the structure. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.
[0146]
A wiring 706 is a source wiring (corresponding to a current supply line) of the current control TFT, and 707 is an electrode that is electrically connected to the pixel electrode 710 by being overlaid on the pixel electrode 710 of the current control TFT.
[0147]
Reference numeral 710 denotes a pixel electrode (EL element anode) made of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 710 is formed on the flat interlayer insulating film 711 before forming the wiring. In this embodiment, it is very important to flatten the step due to the TFT using the flattening film 711 made of resin. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0148]
After the wirings 701 to 707 are formed, a bank 712 is formed as shown in FIG.
The bank 712 may be formed by patterning an insulating film or organic resin film containing silicon of 100 to 400 nm.
[0149]
Note that since the bank 712 is an insulating film, attention must be paid to electrostatic breakdown of elements during film formation. In this embodiment, carbon particles or metal particles are added to the insulating film that is the material of the bank 712 to reduce the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ ~ 1x10 ¹² Ωm (preferably 1 × 10 ⁸ ~ 1x10 ^Ten The added amount of carbon particles and metal particles may be adjusted so that the resistance becomes Ωm).
[0150]
An EL layer 713 is formed over the pixel electrode 710. Although only one pixel is shown in FIG. 12, in this embodiment, EL layers corresponding to each color of R (red), G (green), and B (blue) are separately formed. In this embodiment, a low molecular organic EL material is formed by a vapor deposition method. Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a tris-8-quinolinolato aluminum complex (Alq) having a thickness of 70 nm is formed thereon as a light emitting layer. _Three ) A laminated structure provided with a film. Alq _Three The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1.
[0151]
However, the above example is an example of an organic EL material that can be used as an EL layer, and is not necessarily limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a low molecular weight organic EL material is used as an EL layer is shown, but a high molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer.
As these organic EL materials and inorganic materials, known materials can be used.
[0152]
Next, a cathode 714 made of a conductive film is provided over the EL layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (magnesium and silver alloy film) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or Group 2 of the periodic table or a conductive film added with these elements may be used.
[0153]
When the cathode 714 is formed, the EL element 715 is completed. Note that the EL element 715 here refers to a capacitor formed by a pixel electrode (anode) 710, an EL layer 713, and a cathode 714.
[0154]
It is effective to provide a passivation film 716 so as to completely cover the EL element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a combination thereof.
[0155]
At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., it can be easily formed over the EL layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen and can suppress oxidation of the EL layer 713. Therefore, the problem that the EL layer 713 is oxidized during the subsequent sealing process can be prevented.
[0156]
Further, a sealing material 717 is provided over the passivation film 716 and a cover material 718 is attached thereto. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside. In this embodiment, the cover material 718 is formed by forming a carbon film (preferably a diamond-like carbon film) on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film).
[0157]
Thus, an EL display device having a structure as shown in FIG. 12 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 using a multi-chamber type (or in-line type) film formation apparatus without releasing to the atmosphere. . Further, it is possible to continuously process the process up to the step of bonding the cover material 718 without releasing to the atmosphere.
[0158]
Thus, the n-channel TFTs 601 and 602, the switching TFT (n-channel TFT) 603, and the current control TFT (n-channel TFT) 604 are formed on the insulator 501 having the plastic substrate as a base. The number of masks required in the manufacturing process so far is smaller than that of a general active matrix EL display device.
[0159]
That is, the TFT manufacturing process is greatly simplified, and the yield can be improved and the manufacturing cost can be reduced.
[0160]
Further, as described with reference to FIGS. 9A and 9B, an n-channel TFT which is resistant to deterioration due to the hot carrier effect can be formed by providing an impurity region overlapping with the gate electrode through an insulating film. Therefore, a highly reliable EL display device can be realized.
[0161]
Further, in this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other logic circuits such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit are provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.
[0162]
Further, the EL light-emitting device of this example after performing the sealing (or sealing) process for protecting the EL element will be described with reference to FIG. In addition, the code | symbol used in FIG. 12 is quoted as needed.
[0163]
FIG. 13A is a top view illustrating a state where the EL element is sealed, and FIG. 13B is a cross-sectional view taken along line AA ′ of FIG. 13A. Reference numeral 801 indicated by a dotted line denotes a source side driver circuit, 806 denotes a pixel portion, and 807 denotes a gate side driver circuit. Reference numeral 901 denotes a cover material, reference numeral 902 denotes a first sealing material, reference numeral 903 denotes a second sealing material, and a sealing material 907 is provided on the inner side surrounded by the first sealing material 902.
[0164]
Reference numeral 904 denotes a wiring for transmitting signals input to the source side driver circuit 801 and the gate side driver circuit 807, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 905 serving as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The EL display device in this specification includes not only the EL display device main body but also a state in which an FPC or PWB is attached thereto.
[0165]
Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate side driver circuit 807 are formed above the substrate 700, and the pixel portion 806 is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 710 electrically connected to a drain thereof. . The gate side driver circuit 807 is formed using a CMOS circuit (see FIG. 14) in which an n-channel TFT 601 and a p-channel TFT 602 are combined.
[0166]
The pixel electrode 710 functions as an anode of the EL element. A bank 712 is formed at both ends of the pixel electrode 710, and an EL layer 713 and a cathode 714 of the EL element are formed on the pixel electrode 710.
[0167]
The cathode 714 also functions as a wiring common to all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, all elements included in the pixel portion 806 and the gate side driver circuit 807 are covered with a cathode 714 and a passivation film 567.
[0168]
Further, a cover material 901 is bonded to the first seal material 902. Note that a spacer made of a resin film may be provided in order to secure a gap between the cover material 901 and the EL element. A sealing material 907 is filled inside the first sealing material 902. Note that an epoxy-based resin is preferably used as the first sealing material 902 and the sealing material 907. The first sealing material 902 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a hygroscopic effect or a substance having an antioxidant effect may be contained in the sealing material 907.
[0169]
The sealing material 907 provided so as to cover the EL element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, or acrylic can be used as the material of the plastic substrate 901a constituting the cover material 901.
[0170]
In addition, after the cover material 901 is bonded using the sealing material 907, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. The second sealing material 903 can use the same material as the first sealing material 902.
[0171]
By encapsulating the EL element in the sealing material 907 with the above structure, the EL element can be completely shut off from the outside, and a substance that promotes deterioration due to oxidation of the EL layer such as moisture or oxygen enters from the outside. Can be prevented. Therefore, an EL display device with high reliability can be obtained.
[0172]
[Example 7]
The TFT formed by implementing any one of the first to sixth embodiments can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated in the display unit.
[0173]
Such electronic devices include video cameras, digital cameras, projectors, head-mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples of these are shown in FIGS.
[0174]
FIG. 14A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the display portion 2003.
[0175]
FIG. 14B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be applied to the display portion 2102.
[0176]
FIG. 14C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like. The present invention can be applied to the display portion 2205.
[0177]
FIG. 14D shows a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like. The present invention can be applied to the display portion 2302.
[0178]
FIG. 14E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.
[0179]
FIG. 14F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, an operation switch 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502.
[0180]
FIG. 15A illustrates a front projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 constituting a part of the projection device 2601 and other driving circuits.
[0181]
FIG. 15B shows a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like. The present invention can be applied to the liquid crystal display device 2808 constituting a part of the projection device 2702 and other driving circuits.
[0182]
FIG. 15C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 15A and 15B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0183]
FIG. 15D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 15D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0184]
However, the projector shown in FIG. 15 shows a case where a transmissive electro-optical device is used, and an application example in a reflective electro-optical device and an EL display device is not shown.
[0185]
FIG. 16A illustrates a mobile phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, and the like. The present invention can be applied to the display portion 2904.
[0186]
FIG. 16B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003.
[0187]
FIG. 16C illustrates a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0188]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-5.
[0189]
[Effect of the present invention]
By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) It is a simple method adapted to a conventional TFT manufacturing process.
(B) Implant defects in the semiconductor film due to the doping process can be reduced.
(C) Since the impurity element is introduced into each of the source region, the drain region, and the LDD region by at least two doping processes, the degree of freedom in design is improved.
(D) This is a method capable of producing a TFT having excellent electrical characteristics while satisfying the above advantages.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a doping process disclosed by the present invention;
FIG. 2 is a diagram for explaining a doping process disclosed by the present invention;
FIG. 3 is a diagram for explaining a doping process disclosed by the present invention;
FIG. 4 is a diagram for explaining a doping process disclosed by the present invention;
FIG. 5A is a diagram showing a concentration profile of boron (B) in a silicon film using acceleration voltage as a parameter.
(B) The figure which shows the sheet resistance value with respect to the average density | concentration in the silicon film of boron (B).
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a driver circuit TFT;
FIG. 10 is a top view illustrating a structure of a pixel TFT.
FIG. 11 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 12 is a cross-sectional view illustrating an EL display device.
FIG. 13 shows an EL light-emitting device.
FIG 14 illustrates an example of a semiconductor device.
FIG 15 illustrates an example of a semiconductor device.
FIG 16 illustrates an example of a semiconductor device.

Claims (6)

And n-channel type TFT having a first semiconductor layer and a first gate electrode, a method for manufacturing a semiconductor device having a p-channel type TFT having a second semiconductor layer and the second gate electrode,
Add a metal element that promotes crystallization to the amorphous semiconductor film,
Crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film,
Processing the crystalline semiconductor film to form the first semiconductor layer and the second semiconductor layer;
Forming a gate insulating film on the first semiconductor layer and the second semiconductor layer ;
Forming a first conductive film on the gate insulating film and a second conductive film on the first conductive film;
By performing the first etching on the first conductive film and the second conductive film, the second conductive layer of a first conductive layer and the second conductive film made of the first conductive film A first electrode having a tapered portion, a third conductive layer made of the first conductive film, and a fourth conductive layer made of the second conductive film, and having a tapered portion. 2 electrodes ,
Etching a part of the second conductive layer and a part of the fourth conductive layer by performing a second etching on the first electrode and the second electrode ; The length of the second conductive layer in the channel length direction is shorter than that of the conductive layer, and the length of the fourth conductive layer in the channel length direction is shorter than that of the third conductive layer. Forming the second gate electrode;
By using the second conductive layer and the fourth conductive layer as a mask, by a first doping process for introducing a first impurity element into the first semiconductor layer and the second semiconductor layer,
A first region of the first semiconductor layer that does not overlap with the second conductive layer but does not overlap with the first conductive layer; and a second region that does not overlap with the first conductive layer and the second conductive layer Area,
A third region of the second semiconductor layer that does not overlap the fourth conductive layer but does not overlap the third conductive layer; and a fourth region that does not overlap the first conductive layer and the second conductive layer. And introducing the first impurity element into the region,
Forming a first resist mask on the second semiconductor layer and covering the second gate electrode and a part of the fourth region;
The first impurity element is introduced into the first semiconductor layer and the second semiconductor layer by using the first conductive layer, the second conductive layer, and the first resist mask as a mask. 2, the first impurity element is added to the second region of the first semiconductor layer and the fifth region that does not overlap the first resist mask of the second semiconductor layer. Introduced,
Removing the first resist mask;
Forming a second resist mask covering the first semiconductor layer;
Using the second resist mask and the fourth conductive layer as a mask, the second semiconductor layer is subjected to a third doping process for introducing a second impurity element into the second semiconductor layer. 3 and the fourth region, the second impurity element is introduced,
By using the second resist mask, the third conductive layer, and the fourth conductive layer as a mask, a fourth doping process for introducing the second impurity element into the second semiconductor layer is performed. Introducing the second impurity element into the fourth region of the second semiconductor layer;
Removing the second resist mask;
Gettering the metal element into the second region and the fifth region by heat treatment ;
Using at least one of the elements belonging to Group 15 as the first impurity element;
Using at least one of the elements belonging to Group 13 as the second impurity element;
The concentration of the first impurity element in the second region is higher than that in the first region,
The method for manufacturing a semiconductor device is characterized in that the concentration of the second impurity element in the fourth region is higher than that in the third region . Oite to claim 1, said first and said third concentration of said first impurity element realm of wherein a is 1 × ^{10 17} or more 5 × ¹⁰ 20 / cm ³ or less Manufacturing method. According to claim 1 or claim 2, wherein said second and said fifth concentration of the first impurity element realm of is 1 × ^{10 20} or more 5 × ¹⁰ 21 / cm ³ or less semiconductor Device fabrication method. In any one of claims 1 to 3, wherein the third concentration of said second impurity element realm of is 1 × ^{10 18} or more 5 × ¹⁰ 21 / cm ³ or less semiconductor Device fabrication method. In any one of claims 1 to 4, wherein the concentration of said second impurity element of said fourth realm is 1 × ^{10 20} or more 5 × ¹⁰ 22 / cm ³ or less semiconductor Device fabrication method.   6. The method for manufacturing a semiconductor device according to claim 1, wherein the order of the first to fourth doping processes can be changed.

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