JP2002050765A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally semiconductor devices, such as those for the implantation defect being caused by the doping treatment for leading in the impurity elements for gettering the metallic elements used for acceleration of crystallization and the impurity elements for giving P-type occurs in a semiconductor layer to form a p-channel type TFT, and that it exerts adverse influence on the electrical properties at manufacture of a TFT. SOLUTION: Accelerating voltage at doping treatment has a large influence on implantation defects. To reduce the above implantation defects, it is to be desired that the above acceleration voltage be even lower still. For its sake, the doping treatment is performed separately in two times by changing its accelerating voltage, when forming a low concentration impurity diffusion region and a high concentration diffusion region existing under the tapered section of a gate electrode. By so doing, the implantation defects in the semiconductor film can be minimized. Furthermore, the flexibility in design is improved, because the quantity of introduction of impurity elements can be changed for the above heavily-doped region and the lightly-doped region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, the present invention relates to a configuration of an electro-optical device typified by a liquid crystal display device, and an electric apparatus including the electro-optical device as a component. Further, the present invention relates to a method for manufacturing the device. Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics, and the above-described electro-optical device and electric device are also included in the category.

[0002]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. TFTs are widely applied to electronic devices such as ICs and electro-optical devices, and their development is particularly urgent as switching elements for image display devices.

[0003] T using a crystalline semiconductor film as a semiconductor layer
FT has much higher mobility than an amorphous semiconductor film. For this reason, if a crystalline semiconductor film is used, for example, a monolithic liquid crystal electro-optical device (a pixel driving device) cannot be realized with a semiconductor device manufactured using a conventional amorphous semiconductor film. And a semiconductor device in which a thin film transistor (TFT) for a driver circuit is manufactured.

[0004] As described above, a crystalline semiconductor film is a semiconductor film having extremely high characteristics as compared with an amorphous semiconductor film. This is the reason why the above studies are performed. For example, in order to crystallize an amorphous semiconductor film by heating, a heating temperature of 600 ° C. or more and a heating time of 10 hours or more are required. A substrate that can withstand this crystallization condition is, for example, a synthetic quartz substrate. However, a synthetic quartz substrate is expensive and poor in workability, and it is very difficult to process a large area in particular. Increasing the area of the substrate is an indispensable element particularly for increasing the mass production efficiency. In recent years, there has been a remarkable movement to increase the area of substrates to improve mass production efficiency, and the line of a newly constructed mass production plant has a substrate size of 600 × 720 mm.
Is becoming the norm.

[0005] It is difficult to process a synthetic quartz substrate into such a large-area substrate with the current technology, and even if it is possible, it is considered that the price does not decrease to a level that can be realized as an industry. For example, a glass substrate is a material that can be easily manufactured for a large-area substrate. On a glass substrate, for example, Corning 7
There is something called 059. Corning 7059
Is very inexpensive, has good workability, and is easy to enlarge.
However, Corning 7059 has a strain point temperature of 593.
° C, and there was a problem with heating at 600 ° C or higher.

[0006] One type of glass substrate is Corning 1737, which has a relatively high strain point temperature. Corning 1
The strain point temperature of 737 is 667 ° C., which is higher than that of Corning 7059. Even when an amorphous semiconductor film was formed on the Corning 1737 and was placed in an atmosphere of 600 ° C. for 20 hours, the substrate was not deformed so much as to affect the manufacturing process. However, the heating time of 20 hours was too long for a mass production process.

[0007] To solve such a problem, a new crystallization method has been devised. Details of the above method are described in
No. 183540. Here, the method will be briefly described. First, a small amount of a metal element such as nickel, palladium, or lead is added to an amorphous semiconductor film. As a method of addition, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used. After the addition, when the amorphous semiconductor film is placed in a nitrogen atmosphere at 550 ° C. for 4 hours, for example, a crystalline semiconductor film having good characteristics can be obtained. The optimal heating temperature and heating time for crystallization depend on the amount of the metal element added and the state of the amorphous semiconductor film.

However, the above technique has a problem that the metal element used to promote crystallization locally remains as a metal compound in a high-resistance layer (channel formation region or offset region). Since the metal compound easily flows an electric current, the metal compound locally lowers the resistance of a region to be a high-resistance layer, which causes a deterioration in stability and reliability of electric characteristics of the TFT.

In order to solve this problem, the present applicant has developed a technique (gettering technique) for removing a metal element for promoting crystallization from a crystalline semiconductor film.
It is disclosed in 270363. The gettering technique is to perform a heat treatment by selectively introducing an element belonging to Group 15 into the crystalline semiconductor film in which the metal element remains. Due to the heat treatment, the metal element in a region to which the element belonging to Group 15 is not introduced (the region to be gettered) is released from the region to be gettered, diffuses, and the element belonging to Group 15 is introduced. In the region (gettering region). As a result, the metal element can be removed or reduced in the gettering region.

The gettering technique removes the metal element from a channel forming region or an offset region by introducing an element belonging to Group 15 into a source region and a drain region, or removes the metal element to such an extent that the electrical characteristics of the TFT are not adversely affected. You can also. An element belonging to Group XV imparts n-type by doping a semiconductor layer, but a technique of gettering a source region and a drain region can be applied to a semiconductor layer forming an n-channel TFT and a p-channel TFT. Here, in the semiconductor layer forming the p-channel type TFT, the regions serving as the source region and the drain region include not only p-type impurity elements but also p-type impurities.
An impurity element for imparting a mold will also be introduced. However, it has been confirmed that a metal element is gettered in a source region and a drain region also in a semiconductor layer forming a p-channel TFT.

In addition, in the doping process, the energy of ions implanted into the semiconductor layer is much larger than the binding energy of elements forming the semiconductor layer. For this reason, ions implanted into the semiconductor layer repel elements forming the semiconductor film from lattice points, causing defects in the crystal. Therefore, after the doping process, a heating process is often performed to recover the defect and activate the implanted ions at the same time. In addition,
Since the defects are generated by ion implantation, they are referred to herein as implantation defects.

On the other hand, one of the electrical characteristics of a TFT is an off-current value. The off-state current value is a drain current value that flows when the TFT is turned off, and it is desirable that the off-state current value be sufficiently low in order to suppress power consumption.

As a structure of a TFT for reducing an off-current value, a lightly doped drain (LDD) is used.
n) Structure is known. In this structure, a region into which an impurity element is introduced at a low concentration is provided between a channel formation region and a source region or a drain region formed by introducing an impurity element at a high concentration. Calling. As means for preventing deterioration of the on-current value due to hot carriers, L
The so-called G in which the DD region is arranged so as to overlap the gate electrode
An OLD (Gate-drain Overlapped LDD) structure is known. With such a structure, it is known that a high electric field in the vicinity of the drain region is relieved, injection of hot carriers is prevented, and it is effective in preventing a deterioration phenomenon.

The GOLD structure is LATID (Larg
e-tilt-angle implanted drain) structure or ITLD
It is also known as a D (Inverse T LDD) structure or the like. And, for example, "Mutsuko Hatano, Hajime Akimoto and T
akeshi Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1
997 "has a GOLD structure with sidewalls formed of silicon, but it has been confirmed that extremely superior reliability is obtained as compared with TFTs of other structures.

In order to form a GOLD structure, the end of the gate electrode is tapered. With such a shape, a step of introducing an impurity element imparting n-type into a semiconductor layer forming an n-channel TFT and a step of introducing an impurity element imparting p-type into a semiconductor layer forming a p-channel TFT are performed. In the step of introducing, the source region and the drain region are formed in portions that do not overlap with the gate electrode by a single doping process, and an LDD region having a concentration gradient along the shape of the taper is formed below the taper of the gate electrode. Can be formed.

[0016]

However, when a method of forming a source region, a drain region, and an LDD region by a single doping process by utilizing the taper at the end of the gate electrode is used, the following problem occurs. There was a problem. The ratio of the introduction amount of the impurity element in the source region and the drain region and the introduction amount of the impurity element in the LDD region is determined by the distribution shape of the concentration profile of the impurity element and the thickness of the film existing above the semiconductor layer. Therefore, there is no design freedom for the source and drain regions and the LDD region.

In a semiconductor layer for forming a p-channel type TFT, first, an n-type is formed in a region to be a source region and a drain region in order to getter a metal element used for promoting crystallization. It is necessary to introduce an impurity element to be provided. Further, an impurity element imparting p-type has been introduced into the regions serving as the source region and the drain region in order to manufacture a p-channel TFT. For this reason, the injection defects in the semiconductor film were severe, and the injection defects had a bad influence on the electrical characteristics when the TFT was manufactured. The injection voltage of the semiconductor film due to the doping process is greatly affected by the acceleration voltage at the time of the doping process.

Therefore, in the present invention, when a doping process is performed using a gate electrode having a taper as a mask, at least a source region and a drain region and a LDD are formed in a semiconductor layer forming a p-channel TFT.
The acceleration is performed at least twice by changing the acceleration voltage when forming the region. By doing so, injection defects in the semiconductor film can be minimized. Furthermore, a source region and a drain region, and an LDD
The introduction amount of the impurity element can be changed for each region, and the degree of freedom in design is improved.

[0019]

FIG. 5A shows a concentration profile when a doping process is performed with an acceleration voltage as a parameter and a boron (B) dose of 2 × 10 ¹³ / cm ² in a silicon film. The calculation result of is shown. However, calculations were performed for the case where boron atoms (B) and boron molecules (B ₂ ) were implanted at a ratio of 1: 1. FIG. 5A shows that the concentration profile differs depending on the acceleration voltage.

On the other hand, a source region and a drain region,
Since the LDD regions have different thicknesses of the films above them, it is necessary to introduce an impurity element at an acceleration voltage suitable for each.

The amount of impurity element required for the LDD region is smaller than that required for the source region and the drain region. Therefore, the amount of the impurity element introduced into the source region and the drain region when the LDD is formed does not matter. Further, the acceleration voltage when forming the source region and the drain region is lower than the acceleration voltage when forming the LDD region. With this configuration, the gate insulating film and the gate electrode existing above the LDD region sufficiently function as a mask, and no impurity element is implanted in the LDD region.

An n-type impurity element is first introduced into the source and drain regions of the semiconductor layer forming the p-channel TFT, and then the p-type is applied at a high acceleration voltage to form an LDD region. Impurity elements are introduced,
Subsequently, an impurity element imparting p-type at a low acceleration voltage is introduced to form a source region and a drain region.
Therefore, a semiconductor layer corresponding to the source region and the drain region was manufactured, and the sheet resistance was measured by a four-terminal method.
The result is shown in FIG. Here, phosphorus (P) is applied to the crystalline silicon film (thickness: 50 nm) at 80 keV for 1.7 ×.
10 ²⁰ / cm ³ , 2.3 × 10 ²⁰ / cm ³ , 2.8 × 10
^The conditions were introduced so that the concentration became ²⁰ / cm ³ .
This doping process corresponds to a doping process for forming a source region and a drain region of an n-channel TFT. Next, boron (B) was added at 70 keV to 1.5 × 10 ^20.
/ Cm ^{3 was} introduced. This doping process corresponds to a doping process for forming an LDD region of a p-channel TFT. Subsequently, boron (B) was introduced under different conditions. This doping process corresponds to a doping process for forming a source region and a drain region of a p-channel TFT. According to experiments, the sheet resistance of the source region and the drain region is 0.05 to 2 kΩ (preferably 0.05 to 1 kΩ).
Then I know it's good. From FIG. 5B, even when boron is introduced at a high accelerating voltage to form an LDD region,
It can be seen that the resistance values of the source region and the drain region are low enough to function as the source region and the drain region.

In this way, implantation defects in the source region and the drain region can be minimized, and activation becomes easy. In addition, regarding the doping process for the source region, the drain region, and the LDD region, the acceleration voltage and the amount of introduction can be set independently, so that the degree of freedom in design is greatly improved.

Here, an example has been described in which phosphorus is used as an impurity element for imparting n-type, boron is used as an impurity element for imparting p-type, and a silicon film is used as a semiconductor film. However, in the present invention, the impurity element imparting n-type, the impurity element imparting p-type, and the semiconductor film are not limited to these. For example, as a semiconductor film, there is an amorphous semiconductor film, a microcrystalline semiconductor film, or the like, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used, or n-type may be provided. An element belonging to Group 15 other than phosphorus as an impurity element or an element belonging to Group 13 other than boron may be applied as an impurity element imparting p-type.

According to the present invention, in a method for manufacturing a semiconductor device having a p-channel TFT, a first step of forming a gate insulating film on a crystalline semiconductor film, and at least one conductive film on the gate insulating film A second step of forming a gate electrode having a taper by etching the conductive film at least once, and forming a first layer on the crystalline semiconductor film using the gate electrode as a mask. A fourth step of forming first and second impurity regions by introducing an impurity element, and forming a third impurity region by selectively introducing the first impurity element into the second impurity region A fifth step of forming a fourth impurity region by introducing a second impurity element into the first impurity region; and a second step of introducing the second impurity element into the third impurity region. Introduce the fifth A seventh step of forming a pure object region,
And a method for manufacturing a semiconductor device.

The conductive film is made of a material selected from refractory metals such as tungsten, tantalum, titanium and molybdenum, compounds containing these metals as components, or alloys containing these metals.

For the etching, an apparatus capable of independently controlling the power of the plasma generation source and the bias power for generating a negative bias voltage on the substrate side is used. Since the taper angle at the end of the gate electrode depends on the bias voltage on the substrate side, it has been found that the taper angle of the gate electrode becomes smaller by setting the bias power of the dry etching apparatus larger. By appropriately controlling the bias power, a taper angle of 5 to 70 ° can be formed at the end of the gate electrode, and this shape is used as a mask when forming an impurity region. In the sixth step, 5
Dry etching is performed to form a taper angle of about 60 ° to form a gate electrode.

In the fourth step, the first and second
In order to form an impurity region, an ionized impurity element is accelerated by an electric field to form a gate insulating film (in this specification,
A gate insulating film including an insulating film that is provided in close contact with and between the gate electrode and the semiconductor layer and an insulating film that extends from the insulating film to a peripheral region of the insulating film). A method of introducing into a high quality semiconductor film is used. In this specification, this method of introducing an impurity element is referred to as a “through doping method” for convenience.

By forming the gate electrode as described above, the first conductive layer constituting the gate electrode has a tapered portion (tapered portion) by using the through doping method in the fourth step. A first impurity region in which the concentration of the impurity element increases continuously as the distance from the channel formation region increases is formed in a self-aligned manner in the crystalline semiconductor film existing below the first region.

Immediately after the step 4, the first impurity region overlapping the tapered portion of the first conductive layer forming the gate electrode via the gate insulating film, and the first impurity region forming the gate electrode via the gate insulating film. It can be distinguished between the tapered portion of one conductive layer and the second impurity region which does not overlap.

Subsequently, in a fifth step, in order to form a third impurity region in a self-aligned manner, the ionized impurity element is accelerated by an electric field and passed through a gate insulating film.
A method for introducing into a crystalline semiconductor film is used. At this time, if the doping process is performed at a low acceleration voltage, the first conductive layer forming the gate electrode serves as a mask, so that the third impurity region can be formed in a self-aligned manner.

However, in the case of manufacturing a p-channel TFT, a resist is formed, and an impurity element is selectively introduced into the second impurity region to form a third impurity region.

By forming the gate electrode having the above-described shape, the crystalline semiconductor existing under the tapered portion (tapered portion) of the gate electrode by using the through doping method in the sixth step. A fourth impurity region in which the concentration of the impurity element continuously increases as the distance from the channel formation region increases is formed in the film in a self-aligned manner.

Subsequently, in a seventh step, in order to form a fifth impurity region in a self-aligned manner, the ionized impurity element is accelerated by an electric field and passed through a gate insulating film.
A method of adding to a crystalline semiconductor film is used. At this time, if the doping process is performed at a low acceleration voltage, the first conductive layer forming the gate electrode serves as a mask, so that the fifth impurity region can be formed in a self-aligned manner.

By using the above means to reduce the number of masks, the number of manufacturing steps and the time required for manufacturing the semiconductor device can be reduced, and the manufacturing cost can be reduced and the yield can be improved.

By changing the order and conditions of the dry etching and the doping of the impurity element in addition to the above-described processing, GOLD is applied to the semiconductor device having the crystalline semiconductor film, the gate insulating film and the gate electrode with the same number of masks.
A structure can be formed.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

First, a base insulating film 11 is formed on a substrate 10. The substrate 10 may be a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature may be used.

As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. The base insulating film may have a single-layer structure of the insulating film or a structure in which two or more layers are stacked. Note that the base insulating film need not be formed.

Next, a semiconductor film 12 is formed on the base insulating film. As the semiconductor film 12, a semiconductor film having an amorphous structure is formed to a thickness of 25 to 80 nm (preferably 3 nm) by a known means (sputtering, LPCVD, plasma CVD, or the like).
(0 to 60 nm). Examples of the semiconductor film 12 include an amorphous semiconductor film and a microcrystalline semiconductor film.
A compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used.

Subsequently, a thermal crystallization method using a metal element such as nickel is performed. As a method for adding a metal element such as nickel, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used, and the metal shown in FIG. The element containing layer 13 is formed. After that, heat treatment is performed to crystallize the semiconductor film. By this crystallization method, a metal element remains in the semiconductor film. After that, a laser crystallization method may be further performed as shown in FIG. An excimer laser is widely used as a laser oscillator used for laser crystallization because it has a large output and can oscillate a high-frequency pulse of about 300 Hz at present. In addition to a pulsed excimer laser, an excimer laser or a continuous wave, Ar laser, YAG laser, YVO ₄ laser, YL
An F laser or the like can also be used. The laser beam irradiation can be performed in a vacuum, in the air, in a nitrogen atmosphere, or the like. Further, the substrate may be heated to about 500 degrees when the laser beam is irradiated.

The obtained crystalline semiconductor film is patterned into a desired shape using a photomask to form a semiconductor layer 16a,
16b is formed. Here, the semiconductor layer 16a is a semiconductor layer for forming an n-channel TFT, and the semiconductor layer 1a
Reference numeral 6b denotes a semiconductor layer for forming a p-channel TFT.

After the formation of the semiconductor layers 16a and 16b, a small amount of impurity element (boron or phosphorus) may be doped to control the threshold value of the TFT.

Next, a gate insulating film 17 covering the semiconductor layers 16a and 16b is formed. The gate insulating film 17 has a thickness of 40 to 15 using a plasma CVD method or a sputtering method.
The insulating film containing silicon is formed to have a thickness of 0 nm.

When a silicon oxide film is used,
TEOS (Tetraethyl Orthosilica) by plasma CVD
te) and O ₂ , a reaction pressure of 40 Pa, and a substrate temperature of 30
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² at 0 to 400 ° C. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Next, a film having a thickness of 20 to
A first conductive film 18 having a thickness of 100 nm;
and a second conductive film 19 having a thickness of nm. Each of the first conductive film 18 and the second conductive film 19 is made of Ta, W,
It may be formed of an element selected from Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used.

Next, masks 20 and 21 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. First
Is performed under the first and second etching conditions. Under the first etching condition, the end of the first conductive layer is formed into a tapered shape.

Thereafter, the resist masks 20, 2
1 is changed to the second etching condition without removing 1 and etching is performed. Under the second etching condition, the first conductive film 18 and the second conductive film are also etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, the shape of the mask made of resist is made appropriate so that
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, the first shape conductive layers 22, 23 (the first conductive layers 22a, 23a and the second conductive layers 22b, 23b) composed of the first conductive layer and the second conductive layer by the first etching process. To form Reference numeral 24 denotes a gate insulating film, and a region which is not covered by the first shape conductive layers 22 and 23 is etched by about 20 to 50 nm to form a thinned region.

Next, a second etching process is performed without removing the resist mask. Here, the second conductive film is selectively etched. At this time, the second conductive layers 25b and 26b are formed by the second etching process. On the other hand, the first conductive layers 25a and 26a are hardly etched, and form the second shape conductive layers 25 and 26.

Then, a first doping process is performed,
The state shown in FIG. The doping treatment may be performed by an ion doping method or an ion implantation method. The conditions of the first doping process are as follows: the acceleration voltage is 60 to 120 keV, and the average concentration of the impurity regions 28 and 29 is 1 × 10 ^{17 to} 5
Perform so as to be × 10 ²⁰ / cm ³ . As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically, phosphorus (P) or arsenic (As) is used. In the first doping process, the second shape conductive layers 25a and 26a are used as masks for impurity elements using the second shape conductive layers 25 and 26.
Is doped so that the impurity element is also added to the semiconductor layer below the tapered portion. The concentration of phosphorus (P) added to the impurity region has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer. Thus, impurity regions 28 and 29 formed in a self-aligned manner.
Of these, the impurity region overlapping with the conductive layers 25 and 26 is 28
b and 29b, and the impurity regions which do not overlap with the conductive layers 25 and 26 are 28a and 29a.

Next, using the conductive layers 25 and 26 as a mask, the gate insulating film 27 is selectively removed and the insulating layer 30 is removed.
a and 30b are formed. Further, the resist mask used for forming the second shape conductive layers 25 and 26 may be removed simultaneously with the formation of the insulating layers 30a and 30b. (Figure 2
(B))

A second doping process is performed to add an impurity element imparting n-type to the semiconductor layer. In doping, the first conductive layer and the second conductive layer are used as masks for the impurity elements, and the impurity elements are introduced into the semiconductor layers.
During the second doping process, the p-channel type TF
The semiconductor layer forming T is covered with a resist mask 31 so that an impurity element is introduced into part of the source region and the drain region of the semiconductor layer. The conditions of the second doping process are as follows: the accelerating voltage is 5 to 40 keV, and the impurity regions 32 and 33 a
Is carried out so that the average concentration of 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ³ . Thus, impurity regions 32 and 33a which do not overlap with the first conductive layer are formed in a self-aligned manner. By the mask 31, the impurity region 29a is divided into a region 33a into which the impurity element imparting n-type is introduced by the second doping process and a region 33b into which the impurity element is not introduced. Here, the introduction of the impurity element imparting n-type into the semiconductor layer forming the p-channel TFT is performed by removing the metal element used to promote crystallization from the channel formation region or by using the electrical characteristics of the TFT. This is because it is necessary to reduce it to such an extent that it does not adversely affect the performance.

Next, after removing the mask made of resist, a new mask 34 made of resist is formed and a third doping process is performed. At the time of the third doping process, the semiconductor layer forming the n-channel TFT is covered with a resist mask. In the third doping process, in order to form an LDD region of a p-channel TFT, an impurity element imparting p-type is introduced at a high acceleration voltage. The condition of the third doping process is that the accelerating voltage is 6
0 to 120 keV, and the average concentration of the impurity region 35 is 1
It is carried out so as to be × 10 ^{18 to} 5 × 10 ²¹ / cm ³ . At this time, an impurity element imparting p-type is simultaneously introduced into the source region and the drain region. However, the introduction amount of the impurity element imparting the p-type required by the LDD region is several orders of magnitude smaller than the introduction amount required by the source region and the drain region. Therefore, the impurity element imparting the p-type introduced into the source region and the drain region in the third doping process does not matter. Although the impurity element imparting n-type is added to the impurity region 35 by the first doping process, the average concentration of the impurity element imparting p-type is 1 × 10 ^{18 to} 5 × 10 ²¹ / c.
By performing the doping treatment so as to obtain m ³ , there is no problem because it functions as an LDD region of a p-channel TFT.

Subsequently, a fourth doping process is performed without removing the mask 34. By the fourth doping process,
An impurity region is formed in a semiconductor layer serving as an active layer of a p-channel TFT, into which an impurity element imparting a conductivity type opposite to the one conductivity type is introduced. The fourth doping condition is performed so that the acceleration voltage is 5 to 40 keV and the average concentration of the impurity region is 1 × 10 ^{20 to} 5 × 10 ²² / cm ³ . Using the first conductive layer 26a and the second conductive layer 26b as a mask for an impurity element, an impurity element imparting p-type is added to form the impurity region 36 in a self-aligned manner. (FIG. 3A). First doping process and second doping
Impurity regions 36a, 36b
Are doped with n-type impurity elements at different concentrations, and the average concentration of the p-type impurity element is 1 × 10 ^{20 to} 5 × 10
By doping to ²² / cm ³ ,
There is no problem because it functions as the source and drain regions of the channel type TFT. In this embodiment,
Since a part of the semiconductor layer serving as the active layer of the p-channel TFT is exposed, there is an advantage that an impurity element imparting p-type conductivity can be easily added.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, the mask 34 made of resist is removed to form a first interlayer insulating film 37. The interlayer insulating film 37 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method. As the interlayer insulating film 37, another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 3B, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to
The activation treatment may be performed at 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In the present embodiment, at the same time as the activation treatment, the impurity region 32 containing the impurity element imparting a high concentration of n-type metal element used as a catalyst at the time of crystallization is used.
The concentration of the metal element in the semiconductor layer which is gettered at 36 and mainly becomes a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Further, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0062]

[Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS.

First, a base insulating film 11 is formed on a substrate 10. The substrate 10 may be a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature may be used.

As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. The base insulating film may have a single-layer structure of the insulating film or a structure in which two or more layers are stacked. Note that the base insulating film need not be formed.

Next, the semiconductor film 12 is formed on the base insulating film. As the semiconductor film 12, a semiconductor film having an amorphous structure is formed to a thickness of 25 to 80 nm (preferably 3 nm) by a known means (sputtering, LPCVD, plasma CVD, or the like).
(0 to 60 nm). Examples of the semiconductor film 12 include an amorphous semiconductor film and a microcrystalline semiconductor film.
A compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used.

Subsequently, a thermal crystallization method using a metal element such as nickel is performed. As a method for adding a metal element such as nickel, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used, and the metal shown in FIG. The element containing layer 13 is formed. After that, heat treatment is performed to crystallize the semiconductor film. By this crystallization method, a metal element remains in the semiconductor film. After that, a laser crystallization method may be further performed as shown in FIG. An excimer laser is widely used as a laser oscillator used for laser crystallization because it has a large output and can oscillate a high-frequency pulse of about 300 Hz at present. In addition to a pulsed excimer laser, an excimer laser or a continuous wave, Ar laser, YAG laser, YVO ₄ laser, YL
An F laser or the like can also be used. The laser beam irradiation can be performed in a vacuum, in the air, in a nitrogen atmosphere, or the like. Further, the substrate may be heated to about 500 degrees when the laser beam is irradiated.

The obtained crystalline semiconductor film is patterned into a desired shape using a photomask to form a semiconductor layer 16a,
16b is formed. Here, the semiconductor layer 16a is a semiconductor layer for forming an n-channel TFT, and the semiconductor layer 1a
Reference numeral 6b denotes a semiconductor layer for forming a p-channel TFT.

After the formation of the semiconductor layers 16a and 16b, a slight amount of impurity element (boron or phosphorus) may be doped to control the threshold value of the TFT.

Next, a gate insulating film 17 covering the semiconductor layers 16a and 16b is formed. The gate insulating film 17 has a thickness of 40 to 15 using a plasma CVD method or a sputtering method.
The insulating film containing silicon is formed to have a thickness of 0 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%,
N = 7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used,
TEOS (Tetraethyl Orthosilica) by plasma CVD
te) and O ₂ , a reaction pressure of 40 Pa, and a substrate temperature of 30
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² at 0 to 400 ° C. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Next, a film having a thickness of 20 to
A first conductive film 18 having a thickness of 100 nm;
and a second conductive film 19 having a thickness of nm. In this embodiment, the first conductive film 40 made of a 30 nm-thick TaN film is used.
8 and a second conductive film 40 made of a W film having a thickness of 370 nm.
9 was formed by lamination. The TaN film is formed by a sputtering method.
The target a was sputtered in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, tungsten hexafluoride (W
It can also be formed by a thermal CVD method using F ₆ ). In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, high-purity W (purity 99.
By forming a W film by sputtering using a target of 9999%) and further taking care not to mix impurities from the gas phase during film formation, the resistivity is 9 to 20 μm.
Ωcm was realized.

In this embodiment, the first conductive film 18 is made of TaN and the second conductive film 19 is made of W. However, the present invention is not particularly limited, and Ta, W, Ti, Mo, Al, Cu, C
It may be formed of an element selected from r and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, Ag
A PdCu alloy may be used. A first conductive film formed of a tantalum (Ta) film, a second conductive film formed of a W film, a first conductive film formed of a titanium nitride (TiN) film, and a second conductive film formed of a titanium nitride (TiN) film; Are combined with a W film, the first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. Alternatively, a combination of the second conductive film and the Cu film may be used.

Next, resist masks 20 and 21 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. First
Is performed under the first and second etching conditions. In this embodiment, as the first etching condition,
Using an ICP (Inductively Coupled Plasma) etching method, CF ₄ is used as an etching gas.
And Cl ₂ and O ₂ , and the respective gas flow ratios were 25 /
At 25/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the first etching condition, the end of the first conductive layer is formed into a tapered shape.

Thereafter, the resist masks 20, 2
1 was changed to the second etching condition without removing 1 and CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30/30 (sccm), and the coil type electrode was formed at a pressure of 1 Pa. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. 20W RF (13.56MH) on the substrate side (sample stage)
z) Turn on the power and apply a substantially negative self-bias voltage. The first conductive film 18 depends on the second etching condition.
Also, the second conductive film is etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the above-mentioned first etching process, by making the shape of the mask made of resist suitable,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, the first shape conductive layers 22, 23 (the first conductive layers 22a, 23a and the second conductive layers 22b, 23b) composed of the first conductive layer and the second conductive layer by the first etching process. To form Reference numeral 24 denotes a gate insulating film, and a region which is not covered by the first shape conductive layers 22 and 23 is etched by about 20 to 50 nm to form a thinned region.

Next, a second etching process is performed without removing the resist mask. Here, CF ₄ , Cl _2, and O ₂ are used as the etching gas, and W
The second conductive film made of a film is selectively etched. At this time, the second conductive layer 25 is formed by the second etching process.
b and 26b are formed. On the other hand, the first conductive layers 25a, 25
6a is hardly etched, and forms conductive layers 25 and 26 of the second shape.

Then, a first doping process is performed,
The state shown in FIG. The doping treatment may be performed by an ion doping method or an ion implantation method. The conditions of the first doping treatment are such that the acceleration voltage is 60 to 120 keV and the concentration is 1 × 10 ^{17 to} 5 × 10 ²⁰ / cm ³ . In this embodiment, the first doping process is performed so that the acceleration voltage is 90 keV and the average concentration of the impurity regions 28 and 29 is 2.5 × 10 ¹⁸ / cm ³ . As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically, phosphorus (P) or arsenic (As) is used. In the first doping process, the second shape conductive layers 25a and 26 are used as masks for impurity elements, and the second shape conductive layers 25a and 26
The semiconductor layer below the tapered portion a is also doped so that the impurity element is added. The concentration of phosphorus (P) added to the impurity region has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer.
Thus, the impurity regions 28, 2 formed in a self-aligned manner.
9, the impurity regions overlapping with the conductive layers 25 and 26 are 28
b and 29b, and the impurity regions which do not overlap with the conductive layers 25 and 26 are 28a and 29a.

Then, using the conductive layers 25 and 26 as a mask, the gate insulating film 27 is selectively removed to remove the insulating layer 30.
a and 30b are formed. Further, the resist mask used for forming the second shape conductive layers 25 and 26 may be removed simultaneously with the formation of the insulating layers 30a and 30b. (Figure 2
(B))

The semiconductor layer is formed by performing the second doping process.
Is added with an impurity element imparting n-type. Doping is
Forming a first conductive layer and a second conductive layer with respect to an impurity element;
As a mask, an impurity element is introduced into the semiconductor layer.
During the second doping process, the p-channel type TF
Source and drain regions of semiconductor layer forming T
The resist must be removed so that the impurity element is
Covered with a mask 31. The conditions for the second doping process are
The speed voltage is 5 to 40 keV and the concentration is 1 × 10 ²⁰~ 5x
10^{twenty one}/cm^ThreeAnd so on. In this embodiment, the acceleration voltage
Is 10 keV, and the average concentration of the impurity regions 32 and 33a is
Is 2.0 × 10²⁰/cm^ThreeSo that the second doping process
Was performed. Thus, the first conductive layer is self-aligned with the first conductive layer.
Non-overlapping impurity regions 32 and 33a are formed. mask
31, the impurity region 29a is subjected to the second doping process.
Region 3 into which an impurity element imparting n-type is introduced by
3a and an unintroduced region 33b. Where p
Add n-type to the semiconductor layer forming the channel type TFT
Introducing impurity elements to promote crystallization
Remove the used metal element from the channel formation region or use TF
T to a level that does not adversely affect the electrical characteristics of T
Because it is necessary for

Next, the resist mask is removed.
After that, a mask 34 made of a resist is newly formed and
3 is performed. This third doping process
In practice, the semiconductor layer forming the n-channel TFT is
It is covered with a mask 34 made of resist. Third de
In the topping process, the LDD region of the p-channel TFT is formed.
Therefore, the impurity element imparting p-type at a high accelerating voltage
Introduce. The condition of the third doping process is that the accelerating voltage is 6
0 to 120 keV and a concentration of 1 × 10¹⁸~ 5 × 10^{twenty one}
/cm^ThreeAnd so on. In this embodiment, the accelerating voltage is 80
keV, and the average concentration of the impurity region 35 is 5.0 × 10
¹⁹/cm^ThreeA third doping process was performed so that
At this time, p and p are also simultaneously applied to the source and drain regions.
An impurity element for imparting a mold is introduced. But LDD
Introducing the p-type impurity element required by the region
The amount is the amount of introduction required by the source and drain regions
Is several orders of magnitude less than. Therefore, the third doping
Introduced into the source and drain regions during processing
The impurity element imparting the p-type does not matter. Ma
In addition, the impurity region 35 is formed by the first doping process.
Is doped with an impurity element that imparts n-type,
Average concentration of the impurity element for imparting ¹⁸~ 5 × 1
0^{twenty one}/cm^ThreeBy doping so that
To function as LDD region of p-channel TFT
No problem arises.

Subsequently, the fourth dopant is applied without removing the mask 34.
Performs a grouping process. By the fourth doping process,
The above-described method is applied to a semiconductor layer serving as an active layer of a p-channel TFT.
Impurity element that imparts the opposite conductivity type to the conductivity type was introduced
An impurity region 36 is formed. Fourth Doping Article
The case is an acceleration voltage of 5 to 40 keV and a concentration of 1 × 10 ²⁰
~ 5 × 10^{twenty two}/cm^ThreeAnd so on. First conductive layer 2
6a and the second conductive layer 26b are
Add a p-type impurity element
Impurity regions are formed in a self-aligned manner. (FIG. 3A).
In this embodiment, the acceleration voltage is set to 10 keV and the impurity region 3
Average density of 1.0 × 10^{twenty one}/cm^ThreeThe fourth to be
A doping process was performed. A first doping process and
By the second doping process, the impurity regions 36a, 3a
6b is an impurity element imparting n-type at different concentrations.
Element is added, but p
The concentration of the impurity element giving the mold is 1 × 10²⁰~ 5 × 10
^{twenty two}/cm^ThreeBy doping so that
The source and drain regions of a channel TFT
There is no problem to work. In this embodiment,
Part of the semiconductor layer that becomes the active layer of the p-channel TFT is exposed.
, The addition of an impurity element that imparts p-type
It has the advantage of pan.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, the mask 34 made of resist is removed to form a first interlayer insulating film 37. The interlayer insulating film 37 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method. As the interlayer insulating film 37, another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 3B, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to
The activation treatment may be performed at 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the activation treatment, the impurity region 32 containing the impurity element imparting a high concentration of n-type metal element used as a catalyst during crystallization is used.
The concentration of the metal element in the semiconductor layer which is gettered at 36 and mainly becomes a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Further, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

[Embodiment 2] In this embodiment, a method of manufacturing a TFT without selectively removing a gate insulating film after the first doping treatment shown in Embodiment 1 will be described with reference to FIGS. Will be explained.

According to the first embodiment, the state shown in FIG.

Subsequently, a second doping process is performed to add an impurity element imparting n-type to the semiconductor layer. In doping, the first conductive layer and the second conductive layer are used as masks for the impurity elements, and the impurity elements are introduced into the semiconductor layers. In the second doping process, the semiconductor layer forming the p-channel TFT is covered with a resist mask 51 so that an impurity element is introduced into part of the source region and the drain region of the semiconductor layer. The condition of the second doping process is that the acceleration voltage is 5 to 40 keV and the impurity region 5
The process is performed such that the average concentration of 2,53a is 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ³ . In this embodiment, the accelerating voltage is 30 keV
And a second doping process was performed so that the concentration became 2.0 × 10 ²⁰ / cm ³ . In this way, the first
Impurity regions 52 and 53a which do not overlap with the conductive layer of FIG. By the mask 51, the impurity region 29a is divided into a region 53a into which an impurity element imparting n-type is introduced by the second doping process and a region 53b into which the impurity element imparting n-type is not introduced.
Here, the semiconductor layer forming the p-channel TFT also has n
The reason for introducing the impurity element that imparts the type is that it is necessary to remove the metal element used to promote crystallization from the channel formation region or reduce the metal element to a level that does not adversely affect the electrical characteristics of the TFT. is there.

Next, the resist mask is removed.
After that, a mask 54 made of resist is newly formed and
3 is performed. This third doping process
In practice, the semiconductor layer forming the n-channel TFT is
It is covered with a mask 54 made of resist. Third de
In the topping process, the LDD region of the p-channel TFT is formed.
Therefore, the impurity element imparting p-type at a high accelerating voltage
Introduce. The condition of the third doping process is that the accelerating voltage is 6
0 to 120 keV and a concentration of 1 × 10¹⁸~ 5 × 10^{twenty one}
/cm^ThreeAnd so on. In this embodiment, the accelerating voltage is 80
keV, and the average concentration of the impurity region 55 is 5.0 × 10
¹⁹/cm^ThreeA third doping process was performed so that
At this time, p and p are also simultaneously applied to the source and drain regions.
An impurity element for imparting a mold is introduced. But LDD
Introducing the p-type impurity element required by the region
The amount is the amount of introduction required by the source and drain regions
Is several orders of magnitude less than. Therefore, the third doping
Introduced into the source and drain regions during processing
The impurity element imparting the p-type does not matter. Ma
In addition, the impurity region 55
Is doped with an impurity element that imparts n-type,
Average concentration of the impurity element for imparting ¹⁸~ 5 × 1
0^{twenty one}/cm^ThreeBy doping so that
To function as LDD region of p-channel TFT
No problem arises.

Subsequently, the fourth dopant is applied without removing the mask 54.
Performs a grouping process. By the fourth doping process,
The above-described method is applied to a semiconductor layer serving as an active layer of a p-channel TFT.
Impurity element that imparts the opposite conductivity type to the conductivity type was introduced
An impurity region 56 is formed. Fourth Doping Article
In the case, the acceleration voltage is set to 5 to 40 keV,
Average density is 1 × 10²⁰~ 5 × 10^{twenty two}/cm^ThreeRow so that
Now. The first conductive layer 26a and the second conductive layer 26b
Used as a mask for impurity elements and given p-type
Add impurity elements to form impurity regions in a self-aligned manner
You. (FIG. 4C). In this embodiment, the acceleration voltage is set to 30 ke.
V and the average concentration of the impurity region 56 is 1.0 × 10^{twenty one}/ c
m^ThreeThe fourth doping process was performed so that First
By the doping process and the second doping process,
The impurity regions 36a and 36b have different concentrations of n
An impurity element that gives the mold is added,
Average concentration of impurity elements imparting p-type
Degree 1 × 10²⁰~ 5 × 10 ^{twenty two}/cm^ThreeDopin to be
The source region of the p-channel TFT can be
Problem to function as a drain and drain region
Does not occur. In this embodiment, an active layer of a p-channel TFT is used.
P-type is provided because part of the semiconductor layer to be exposed is exposed
This is advantageous in that an impurity element to be added can be easily added.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, the mask 54 made of resist is removed to form a first interlayer insulating film 57. The interlayer insulating film 57 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method. As the interlayer insulating film 57, another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 4D, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to
The activation treatment may be performed at 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the activation process, the impurity region 52 containing the impurity element imparting a high concentration of n-type metal element used as a catalyst during crystallization is used.
The concentration of the metal element in the semiconductor layer which is gettered at 56 and mainly becomes a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Further, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment. Embodiment 4 In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS.

First, in this embodiment, Corning # 70
A substrate 400 made of glass such as barium borosilicate glass typified by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that as the substrate 300, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a silicon oxide film is formed on the substrate 300,
A base film 301 including an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. Although a two-layer structure is used as the base film 301 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. For the first layer of the base film 301, a plasma CVD
iH _4, NH _3, a and N ₂ O silicon oxynitride film 301a is formed as the reaction gas 10 to 200 nm (preferably 50 to 100 nm) is formed. In this embodiment, the film thickness 5
0 nm silicon oxynitride film 301a (composition ratio Si = 3
2%, O = 27%, N = 24%, H = 17%). Next, as the second layer of the base film 401, a silicon oxynitride film 401b formed using SiH ₄ and N ₂ O as a reaction gas by plasma CVD is used to form a _second layer of 50 to 200.
nm (preferably 100 to 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 401b (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%).

Next, the semiconductor layers 402 to 40 are formed on the underlying film.
6 is formed. The semiconductor layers 402 to 406 are formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCV
D method or plasma CVD method). Examples of the semiconductor film 12 include an amorphous semiconductor film, a microcrystalline semiconductor film, and a polycrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by a plasma CVD method.

Subsequently, a thermal crystallization method using a metal element such as nickel is performed. As a method for adding a metal element such as nickel, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used. The containing layer 303 is formed. After that, heat treatment is performed to crystallize the semiconductor layer. In this embodiment, a solution containing nickel is held on an amorphous silicon film, and the amorphous silicon film is dehydrogenated (50%).
0 ° C., 1 hour), and then heat crystallization (550 ° C., 4 hours).
Hours).

The obtained crystalline semiconductor film is formed by patterning into a desired shape. These semiconductor layers 402 to 406
Has a thickness of 25 to 80 nm (preferably 30 to 60 nm)
Formed with a thickness of In this embodiment, the semiconductor layers 402 to 406 are formed by patterning the crystalline silicon film using a photolithography method.

After the formation of the semiconductor layers 402 to 406, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

In the case of manufacturing a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, a YVO ₄ laser, or the like can be used. In the case of using these lasers, a method in which a laser beam emitted from a laser oscillator is linearly condensed by an optical system and irradiated to a semiconductor film is preferably used. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 400 mJ / cm.
² (typically 200 to 300 mJ / cm ² ). Also, Y
When an AG laser is used, its second harmonic is used to make the pulse oscillation frequency 1 to 300 Hz, and the laser energy density is 300 to 600 mJ / cm ² (typically 350 to 50 mJ / cm ² ).
0 mJ / cm ² ). And width 100-1000μ
A laser beam condensed linearly at m, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time may be set to 50 to 98%.

Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59) having a thickness of 110 nm by a plasma CVD method.
%, N = 7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used,
TEOS (Tetraethyl Orthosilica) by plasma CVD
te) and O ₂ , a reaction pressure of 40 Pa, and a substrate temperature of 30
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² at 0 to 400 ° C. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Next, as shown in FIG. 6C, a first conductive film 408 having a thickness of 20 to 100 nm and a second conductive film 40 having a thickness of 100 to 400 nm are formed on the gate insulating film 407.
9 are laminated. In this embodiment, a 30 nm-thick T
a first conductive film 408 made of an aN film and a film thickness of 370 nm
A second conductive film 409 made of a W film was laminated. T
The aN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, thermal CV using tungsten hexafluoride (WF ₆ )
It can also be formed by Method D. In any case, it is necessary to lower the resistance in order to use it as a gate electrode,
It is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity of 99.9999%) target, and further taking care not to mix impurities from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 408
Is TaN and the second conductive film 409 is W, but there is no particular limitation, and any of Ta, W, Ti, Mo, Al, Cu,
It may be formed of an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, A
A gPdCu alloy may be used. A first conductive film formed of a tantalum (Ta) film, a second conductive film formed of a W film, a first conductive film formed of a titanium nitride (TiN) film, and a second conductive film formed of a titanium nitride (TiN) film; As a W film, the first
The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of a Cu film. May be combined.

Next, masks 410 to 415 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed.
The first etching process is performed under the first and second etching conditions. In this embodiment, as the first etching condition, an ICP (Inductively Coupled Plasma) etching method is used, and C is used as an etching gas.
Using F ₄ , Cl ₂ and O ₂ , each gas flow ratio was 2
At 5/25/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.
The W film is etched under the first etching conditions to make the end of the first conductive layer tapered.

Thereafter, a mask 410 made of resist is formed.
The second etching condition was changed without removing 415, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30/30 (sccm), and the pressure was 1 Pa to form a coil-type electrode. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the mask made of resist suitable,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, the first-shaped conductive layers 417 to 422 (the first conductive layers 417 a to 422 a and the second conductive layers 417 b to 422) formed of the first conductive layer and the second conductive layer by the first etching process.
2b) is formed. 416 is a gate insulating film,
The region not covered by the conductive layers 417 to 422 having the
A region that is etched and thinned by about 50 nm is formed.

Next, a second etching process is performed without removing the resist mask. Here, the second conductive film is selectively etched. At this time, second conductive layers 428b to 433b are formed by a second etching process. On the other hand, the first conductive layers 428a to 433a are hardly etched, and the second shape conductive layers 428a to 433a are not etched.
433 are formed.

Then, a first doping process is performed,
The state of FIG. 2B is obtained. The doping treatment may be performed by an ion doping method or an ion implantation method. The conditions of the first doping treatment are such that the acceleration voltage is 60 to 120 keV and the concentration is 1 × 10 ^{17 to} 5 × 10 ²⁰ / cm ³ . In this embodiment, the first doping process is performed so that the acceleration voltage is 90 keV and the average concentration of the impurity regions 423 to 427 is 2.5 × 10 ¹⁸ / cm ³ . As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically, phosphorus (P) or arsenic (As) is used. The first doping is performed using the second shape conductive layers 428 to 433 as masks for impurity elements.
The semiconductor layers below the tapered portions 8a to 433a are also doped so that the impurity element is added. The concentration of phosphorus (P) added to the impurity region has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer. Of the impurity regions 423 to 427 thus formed in a self-aligned manner, the second conductive layers 428 b to 428 b
Impurity regions overlapping with 33b are 423b to 427b, and impurity regions not overlapping with the second conductive layers 428b to 433b are 423a to 427a.

Next, after removing the resist mask, the gate insulating film 338 is selectively removed using the second shape conductive layers 428 to 433 as a mask to form insulating layers 339a to 339g. Also, 339a to 33
9g and at the same time forming the second shape conductive layers 428-4.
The resist mask used for forming 33 may be removed. (FIG. 7 (B))

A second doping process is performed to add an n-type impurity element to the semiconductor layer. In doping, the first conductive layer and the second conductive layer are used as masks for the impurity elements, and the impurity elements are introduced into the semiconductor layers.
During the second doping process, the p-channel type TF
The semiconductor layers forming T are covered with resist masks 441a to 441c so that an impurity element is introduced into part of the source region and the drain region. The conditions of the second doping treatment are as follows: an acceleration voltage of 5 to 40 keV and a concentration of 1
It is carried out so as to be × 10 ^{20 to} 5 × 10 ²¹ / cm ³ . Thus, impurity regions 434 to 438 that do not overlap with the first conductive layer are formed in a self-aligned manner. In this embodiment, the acceleration voltage is set to 1
The second doping treatment was performed at 0 keV so that the impurity regions 434 to 438 had an average concentration of 1.5 × 10 ²⁰ / cm ³ . By the masks 441a to 441c, the impurity regions 424a and 426a are converted into the regions 435 into which the impurity element imparting n-type is introduced by the second doping treatment.
437 and regions 439 and 440 not introduced.
Here, the semiconductor layer forming the p-channel TFT also has n
The reason for introducing the impurity element that imparts the type is that it is necessary to remove the metal element used to promote crystallization from the channel formation region or reduce the metal element to a level that does not adversely affect the electrical characteristics of the TFT. is there.

Next, the resist mask is removed.
After that, a mask made of a new resist is formed and the third
A doping process is performed. Of this third doping process
In some cases, the semiconductor layer forming the n-channel TFT is
It is covered with masks 452 to 454 made of strike. No.
In the doping process 3, the LDD region of the p-channel TFT is used.
To form p-type region at high accelerating voltage
Introduce the element. The condition of the third doping process is accelerating
The pressure is 60 to 120 keV and the concentration is 1 × 10 ¹⁸~ 5x
10^{twenty one}/cm^ThreeAnd so on. In this embodiment, the acceleration voltage
Is 80 keV, and the average concentration of the impurity region is 5.0 × 1
0¹⁹/cm^ThreeAnd the third doping to be 455, 456
Processing was performed. At this time, the source area and
An impurity element imparting p-type is also introduced into the rain region.
You. However, the p-type required by the LDD region is not added.
The amount of impurity element introduced is
Is several orders of magnitude less than the required introduction volume. That
In the third doping process, the source region and the dopant
The p-type imparting impurity element introduced into the rain region
Does not matter. In addition, the first doping process
In addition, the impurity regions 455 and 456 have an impurity imparting n-type.
Element is added, but in any region
Also, the concentration of the impurity element imparting p-type is set to 1 × 10¹⁸~ 5x
10^{twenty one}/cm^ThreeBy doping so that
Function as an LDD region of a p-channel TFT.
No problem arises.

Subsequently, a fourth doping process is performed without removing the masks 452 to 454. By the fourth doping treatment, impurity regions 457 to 459 in which an impurity element imparting a conductivity type opposite to the one conductivity type is introduced are formed in a semiconductor layer serving as an active layer of the p-channel TFT. 4th
The doping process is performed at an acceleration voltage of 5 to 40 keV and a concentration of 1 × 10 ^{20 to} 5 × 10 ²² / cm ³ . The second shape conductive layers 428 to 433 are used as masks for impurity elements, and an impurity element imparting p-type is added to form impurity regions in a self-aligned manner. (FIG. 8
(C) In this embodiment, the acceleration voltage is 10 keV, and the average concentration of the impurity regions 457 to 459 is 1.0 × 10 ²¹ / cm ^3.
The fourth doping process was performed so that By the first doping process and the second doping process, the impurity regions 457 to 459 are added with impurity elements imparting n-type at different concentrations, respectively. Element concentration of 1
By performing the doping treatment so as to be from × 10 ^{20 to} 5 × 10 ²² / cm ³ , no problem occurs because the p-type TFT functions as a source region and a drain region. In this embodiment, since a part of the semiconductor layer serving as the active layer of the p-channel TFT is exposed, there is an advantage that an impurity element imparting p-type conductivity can be easily added.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, a resist mask 452 to 452 is formed.
454 is removed to form a first interlayer insulating film 461.
As the first interlayer insulating film 461, plasma CVD
Thickness of 100 to 200 nm by using a sputtering method or a sputtering method
As an insulating film containing silicon. In this embodiment, a 150-nm-thick silicon oxynitride film is formed by a plasma CVD method. Of course, the first interlayer insulating film 461
Is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 9A, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm
400 to 700 ° C, typically 5 in the following nitrogen atmosphere
The temperature may be set at 00 to 550 ° C.
The activation treatment was performed by a heat treatment for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the activation treatment, the nickel used as a catalyst during crystallization is doped with impurity regions 434, 436-438,
57, 459 are crystallized. Therefore, the impurity region and the metal element are gettered, and the nickel concentration in the semiconductor layer mainly serving as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

The activation treatment may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

In the case where the laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, a second interlayer insulating film 462 made of an inorganic insulating material or an organic insulating material is formed on the first interlayer insulating film 461. In this embodiment, the film thickness is 1.6 μm
Although the acrylic resin film described above is formed, there is no particular limitation, and an insulating film containing silicon (such as a silicon oxynitride film, a silicon oxide film, or a silicon nitride film) may be used as a single layer or a stacked structure.

In the drive circuit 506, wirings 463 to 467 electrically connected to the respective impurity regions.
To form Note that these wirings are made of a 50 nm thick T
A laminated film of an i film and a 500 nm-thick alloy film (an alloy film of Al and Ti) is formed by patterning.

In the pixel portion 507, a pixel electrode 470, a gate wiring 469, and a connection electrode 468 are formed. (FIG. 9B) With this connection electrode 468, the source wiring (the lamination of 443b and 449) is electrically connected to the pixel TFT. Further, the gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. The pixel electrode 470 is connected to the drain region 44 of the pixel TFT.
2 and an electrical connection is formed with the semiconductor layer 458 functioning as one electrode forming a storage capacitor. The pixel electrode 471 has A
It is desirable to use a material having excellent reflectivity, such as a film containing l or Ag as a main component or a laminated film thereof.

As described above, the n-channel TFT 50
1 and a CMOS circuit comprising a p-channel TFT 502;
Circuit 50 having n-channel TFT 503 and n-channel TFT 503
6 and a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 can be formed over the same substrate. Thus, an active matrix substrate is completed.

The n-channel TFT 50 of the driving circuit 506
1 includes a channel formation region 423c, a low-concentration impurity region 423b (GOLD region) overlapping with a first conductive layer 428a which forms part of a gate electrode, and a high-concentration impurity region 434 functioning as a source or drain region. I have. A p-channel TFT 502 connected to the n-channel TFT 501 via an electrode 466 to form a CMOS circuit
The impurity region 424 that overlaps with the channel formation region 424c and the first conductive layer 429a that forms part of the gate electrode.
b, high-concentration impurity regions 457 and 458 functioning as a source region or a drain region. The n-channel TFT 503 has a channel formation region 425c,
A low-concentration impurity region 425b (a GOLD region) overlapping with the first conductive layer 430a which forms part of the gate electrode, and a high-concentration impurity region 436 functioning as a source or drain region are provided.

In the pixel TFT 504 in the pixel portion, a channel formation region 426c and a low-concentration impurity region 426b (GO) overlapping the first conductive layer 431a forming a part of the gate electrode are provided.
LD region) and a high-concentration impurity region 437 functioning as a source region or a drain region. The semiconductor layer 45 functioning as one electrode of the storage capacitor 505
6, 459 are added with an impurity element imparting a p-type. The storage capacitor 505 includes an electrode (a laminate of 432a and 432b) using the insulating film 339g as a dielectric,
The semiconductor layers 456, 459, and 427c are formed.

In the pixel structure of this embodiment, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

FIG. 10 is a top view of the pixel portion of the active matrix substrate manufactured in this embodiment. 6 to 9 are denoted by the same reference numerals. A chain line AA ′ in FIG. 9B corresponds to a cross-sectional view taken along a chain line AA ′ in FIG. A dashed line BB ′ in FIG. 9B corresponds to a cross-sectional view taken along a dashed line BB ′ in FIG.

[Embodiment 5] In this embodiment, a process of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 4 will be described below. FIG. 11 is used for the description.

First, according to the fourth embodiment, after obtaining the active matrix substrate in the state of FIG. 9B, an alignment film 471 is formed on at least the pixel electrode 470 on the active matrix substrate of FIG. . In this embodiment, before forming the alignment film 471, a columnar spacer (not shown) for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 472 is prepared. Next, the coloring layers 473 and 474 and the flattening film 475 are formed over the counter substrate 472. The red coloring layer 473 and the blue coloring layer 474 are overlapped to form a light-shielding portion. Alternatively, the light-blocking portion may be formed by partially overlapping the red coloring layer and the green coloring layer.

In this embodiment, the substrate shown in Embodiment 4 is used. Therefore, FIG. 1 shows a top view of the pixel portion of the fourth embodiment.
0, at least the gate wiring 469 and the pixel electrode 470
, The gap between the gate wiring 469 and the connection electrode 468, and the gap between the connection electrode 468 and the pixel electrode 470. In this embodiment, the colored layers are arranged such that the light-shielding portion formed of the colored layers is overlapped at the positions where the light is to be shielded, and the opposing substrates are bonded to each other.

As described above, the number of steps can be reduced by shielding the gap between each pixel with the light-shielding portion formed of the colored layers without forming a light-shielding layer such as a black mask.

Next, a counter electrode 476 made of a transparent conductive film was formed on at least the pixel portion on the flattening film 475, an alignment film 477 was formed on the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealing material 478.
Paste in. A filler is mixed in the sealant 478, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 479 is injected between the two substrates, and completely sealed with a sealant (not shown). As the liquid crystal material 479, a known liquid crystal material may be used. Thus, the reflection type liquid crystal display device shown in FIG. 11 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, using a known technique, F
PC was pasted.

The liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.

[Embodiment 6] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described. FIG. 12 is a cross-sectional view of the EL display device of the present invention.

In FIG. 12, the switching TFT 603 provided on the substrate 700 is an n-channel type TF shown in FIG.
It is formed using T503. Therefore, for the description of the structure, the description of the n-channel TFT 503 may be referred to.

Although the present embodiment has a double gate structure in which two channel formation regions are formed, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. good.

The driving circuit provided on the substrate 700 is shown in FIG.
Is formed using a CMOS circuit. Accordingly, the description of the structure will be made only for the n-channel TFT 501 and the p-channel TFT 5.
02 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The wirings 701 and 703 function as a source wiring of a CMOS circuit, and the wiring 702 functions as a drain wiring.
The wiring 704 is connected to the source wiring 708 and the switching T
The wiring 705 functions as a wiring for electrically connecting the source region of the FT to the source region.
It functions as a wiring for electrically connecting the drain region of the FT.

The current control TFT 604 is formed using the p-channel TFT 502 shown in FIG. Therefore, the description of the structure may be referred to the description of the p-channel TFT 502. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

A wiring 706 is a source wiring (corresponding to a current supply line) of the current control TFT, and an electrode 707 is electrically connected to the pixel electrode 710 by being superposed on the pixel electrode 710 of the current control TFT. is there.

Reference numeral 710 denotes a pixel electrode (anode of an EL element) made of a transparent conductive film. As a transparent conductive film,
A compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used. The pixel electrode 710 has a flat interlayer insulating film 7 before forming the wiring.
11 is formed. In this embodiment, it is very important to flatten the step due to the TFT using the flattening film 711 made of resin. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG. Bank 712 is 10
The insulating film or the organic resin film containing silicon having a thickness of 0 to 400 nm may be formed by patterning.

Since the bank 712 is an insulating film,
Attention must be paid to electrostatic breakdown of the element during film formation.
In this embodiment, the resistivity is reduced by adding carbon particles or metal particles to the insulating film used as the material of the bank 712 to suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of the carbon particles and metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

An EL layer 713 is formed on the pixel electrode 710. Although only one pixel is shown in FIG. 12, in this embodiment, EL layers corresponding to R (red), G (green), and B (blue) are separately formed. In this embodiment, a low-molecular organic EL material is formed by an evaporation method.
Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a light emitting layer is formed on the copper phthalocyanine film.
It has a laminated structure in which a 0 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

However, the above example is an example of the organic EL material that can be used for the EL layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, a low molecular organic EL material is
Although an example in which the layer is used as a layer has been described, a polymer organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the EL layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (an alloy film of magnesium and silver)
May be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

When the cathode 714 is formed, the EL
The element 715 is completed. Note that the EL element 71 here
Reference numeral 5 denotes a capacitor formed by the pixel electrode (anode) 710, the EL layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the EL element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used in a single layer or in a stacked layer.

At this time, a film having good coverage is preferably used as a passivation film, and a carbon film, particularly, a D film is preferably used.
It is effective to use an LC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or lower, it can be easily formed above the EL layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen, and the EL layer 713
Can be suppressed. Therefore, the problem that the EL layer 713 is oxidized during the subsequent sealing step can be prevented.

Furthermore, a sealing material 717 is provided on the passivation film 716, and a cover material 718 is attached. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, a cover material 718 having a carbon film (preferably a diamond-like carbon film) formed on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) is used.

Thus, an EL display device having a structure as shown in FIG. 12 is completed. After forming the bank 712,
It is effective to continuously process the steps up to the formation of the passivation film 716 without exposing to the atmosphere using a multi-chamber type (or in-line type) film forming apparatus. Further, by further developing, it is also possible to continuously perform processing up to the step of bonding the cover material 718 without releasing to the atmosphere.

In this manner, the n-channel TFTs 601 and 602 are formed on the insulator 501 whose base is a plastic substrate.
A switching TFT (n-channel TFT) 603 and a current control TFT (n-channel TFT) 604 are formed. The number of masks required in the manufacturing process up to this point is
The number is smaller than that of a general active matrix type EL display device.

That is, the manufacturing process of the TFT is greatly simplified, and an improvement in yield and a reduction in manufacturing cost can be realized.

Further, as described with reference to FIG. 9, an n-channel TFT which is resistant to deterioration due to a hot carrier effect can be formed by providing an impurity region overlapping a gate electrode with an insulating film interposed therebetween. Therefore, a highly reliable EL display device can be realized.

In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other components such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit are also provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, an EL light emitting device of this embodiment after performing a sealing (or enclosing) step for protecting the EL element will be described with reference to FIG. The reference numerals used in FIG. 12 will be referred to as needed.

FIG. 13A is a top view showing a state in which the process up to sealing of the EL element has been performed, and FIG. 13B is a cross-sectional view of FIG. 13A taken along the line AA ′. 80 shown by dotted line
Reference numeral 1 denotes a source side driving circuit, 806 denotes a pixel portion, and 807 denotes a gate side driving circuit. Reference numeral 901 denotes a cover material;
Denotes a first sealant, 903 denotes a second sealant, and a sealant 907 is provided inside the first sealant 902.

Reference numeral 904 denotes wiring for transmitting signals input to the source-side driving circuit 801 and the gate-side driving circuit 807, and a video signal or a clock signal from an FPC (flexible printed circuit) 905 serving as an external input terminal. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached. The EL display device in this specification includes not only the EL display device main body but also a state in which an FPC or a PWB is attached thereto.

Next, the cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate driver circuit 807 are formed above the substrate 700.
Is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 710 electrically connected to its drain. The gate side drive circuit 807 is an n-channel type TF
It is formed using a CMOS circuit (see FIG. 14) in which T601 and p-channel TFT 602 are combined.

The pixel electrode 710 functions as an anode of the EL element. Further, banks 712 are provided at both ends of the pixel electrode 710.
Are formed, and an EL layer 713 and a cathode 714 of an EL element are formed on the pixel electrode 710.

The cathode 714 also functions as a common wiring for all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, all elements included in the pixel portion 806 and the gate driver circuit 807 are covered with the cathode 714 and the passivation film 567.

Further, a cover member 901 is attached by a first seal member 902. Note that a spacer made of a resin film may be provided to secure an interval between the cover member 901 and the EL element. The inside of the first sealant 902 is filled with a sealant 907. Note that an epoxy resin is preferably used for the first sealant 902 and the sealant 907. Further, it is desirable that the first sealant 902 be a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a moisture absorbing effect or a substance having an antioxidant effect may be contained in the sealing material 907.

The sealing material 907 provided so as to cover the EL element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (FRP) is used as the material of the plastic substrate 901a constituting the cover member 901.
iberglass-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester or acrylic can be used.

The cover material 90 is formed by using the sealing material 907.
After bonding, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. Second sealing material 90
For 3, the same material as the first sealant 902 can be used.

The EL element having the above structure is sealed with the sealing material 90.
By encapsulating the EL element in the EL element, the EL element can be completely shut off from the outside, and it is possible to prevent a substance such as moisture or oxygen, which promotes the deterioration of the EL layer from being oxidized, from entering from the outside. Therefore, a highly reliable EL display device can be obtained.

[Embodiment 7] TFTs formed by carrying out any one of the above embodiments 1 to 6 can be used in various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC). Display). That is,
The invention of the present application can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector, a head-mounted display (goggle type display), a car navigation, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.). ). One example of them is shown in FIG.
FIG. 15 and FIG.

FIG. 14A shows a personal computer, which comprises a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 14B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102.

FIG. 14C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 14D shows a goggle type display, which comprises a main body 2301, a display section 2302, and an arm section 230.
3 and so on. The present invention can be applied to the display portion 2302.

FIG. 14E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display unit 2402, and a speaker unit 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 14F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502.

FIG. 15A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other driving circuits.

FIG. 15B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to a liquid crystal display device 2808 forming a part of the LCD 702 and other driving circuits.

Note that FIG. 15C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 15A and 15B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 15D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 15C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 15D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 15, a case where a transmission type electro-optical device is used is shown, and examples of application to a reflection type electro-optical device and an EL display device are not shown.

FIG. 16A shows a portable telephone, and the main body 29 is shown.
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904.

FIG. 16B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003.

FIG. 16C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to fifth embodiments.

[0189]

[Effect of the present invention] By adopting the configuration of the present invention,
Basic significance as shown below can be obtained. (A) This is a simple method adapted to a conventional TFT manufacturing process. (B) Injection defects in the semiconductor film due to doping can be reduced. (C) Since the impurity element is introduced into each of the source region, the drain region, and the LDD region by doping at least twice, the degree of freedom in design is improved. (D) This is a method capable of manufacturing a TFT having excellent electrical characteristics while satisfying the above advantages.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a doping process disclosed by the present invention.

FIG. 2 is a diagram illustrating a doping process disclosed by the present invention.

FIG. 3 is a diagram illustrating a doping process disclosed by the present invention.

FIG. 4 is a diagram illustrating a doping process disclosed by the present invention.

FIG. 5A is a diagram showing a concentration profile of boron (B) in a silicon film using an acceleration voltage as a parameter. FIG. 3B is a graph showing a sheet resistance value with respect to an average concentration of boron (B) in a silicon film.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 10 is a top view illustrating a configuration of a pixel TFT.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 12 is a cross-sectional view illustrating an EL display device.

FIG. 13 illustrates an EL light-emitting device.

FIG. 14 illustrates an example of a semiconductor device.

FIG. 15 illustrates an example of a semiconductor device.

FIG. 16 illustrates an example of a semiconductor device.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Makoto Endo 398 Hase, Hase, Atsugi, Kanagawa Prefecture Inside the Semi-Conductor Energy Laboratory Co., Ltd. 72) Inventor, Masayuki Kajiwara 398, Hase, Atsugi-shi, Kanagawa Pref. Inside the Semi-Conductor Energy Laboratory Co., Ltd. (72) Inventor Keiichi Sekiguchi 398, Hase, Atsugi-shi, Kanagawa Pref. JA38 JA42 JA44 JB13 JB23 JB32. EE04 EE06 EE09 EE14 EE23 EE44 EE45 FF02 FF04 FF09 FF28 F F30 GG01 GG02 GG13 GG25 GG32 GG43 GG45 GG47 HJ01 HJ04 HJ12 HJ13 HJ23 HL04 HL06 HL11 HM15 NN03 NN22 NN23 NN24 NN27 NN34 NN35 NN72 PP01 PP02 PP03 PP13 PP29 PP34 QQ04 QQ11Q24

Claims (14)

[Claims] 1. A method for manufacturing a semiconductor device having a p-channel TFT, comprising: a first step of forming a gate insulating film over a crystalline semiconductor film; and forming at least one conductive film over the gate insulating film. A second step of performing etching of the conductive film at least once to form a gate electrode having a tapered portion; and performing a first step on the crystalline semiconductor film using the gate electrode as a mask. A fourth step of forming first and second impurity regions by introducing an impurity element; and forming a third impurity region by selectively introducing the first impurity element into the second impurity region. A fifth step of forming a fourth impurity region by introducing a second impurity element into the first impurity region; and a second step of forming the fourth impurity region in the second impurity region. Introduce the fifth The method for manufacturing a semiconductor device, characterized in that it comprises a seventh step of forming a pure object region. 2. A method for manufacturing a semiconductor device having a p-channel type TFT, comprising: a first step of adding a metal element which promotes crystallization to an amorphous semiconductor film; A second step of crystallizing to form a crystalline semiconductor film; a third step of forming a gate insulating film on the crystalline semiconductor film; and forming at least one conductive film on the gate insulating film. A fourth step, a fifth step of etching the conductive film at least once to form a gate electrode having a tapered portion, and a first impurity element in the crystalline semiconductor film using the gate electrode as a mask. A sixth step of forming first and second impurity regions by introducing a first impurity element; and a third step of selectively introducing the first impurity element into the second impurity region to form a third impurity region. 7 steps and An eighth step of forming a fourth impurity region by introducing a second impurity element into the first impurity region; and a fifth step of introducing the second impurity element into the second impurity region. A method for manufacturing a semiconductor device, comprising: a ninth step of forming an impurity region; and a tenth step of gettering the metal element to the fifth impurity region by heat treatment. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first impurity element is at least one of elements belonging to Group XV. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the second impurity element uses at least one of elements belonging to Group 13. 5. The semiconductor according to claim 1, wherein the concentration of the first impurity element in the first and second impurity regions is 1 × 10 ^{17 to} 5 × 10 ²⁰ / cm ^3. Method for manufacturing the device. 6. The device according to claim 1, wherein the concentration of the first impurity element in the third impurity region is 1 × 10 ^20.
5 × 10 ²¹ / cm ³ . 7. The method according to claim 1, wherein the concentration of the second impurity element in the fourth impurity region is 1 × 10 ^18.
5 × 10 ²¹ / cm ³ . 8. The semiconductor device according to claim 1, wherein the concentration of the second impurity element in the fifth impurity region is 1 × 10 ^20.
5 × 10 ²² / cm ³ . 9. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device, an EL display device, or an image sensor. 10. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a digital camera, a projector, a goggle type display, a personal computer, a DVD player, an electronic dictionary, or portable information. A method for manufacturing a semiconductor device, which is a terminal. 11. A semiconductor layer formed on an insulating surface,
A semiconductor device including an insulating film formed over the semiconductor layer and a gate electrode formed over the insulating film, wherein the semiconductor layer has a channel formation region overlapping the gate electrode, An overlapping low concentration impurity region;
A high concentration impurity region, wherein the low concentration impurity region is 1 × 10 ^{17 to} 5 × 10 ²⁰ / cm.
Impurity element imparting n-type with a concentration of ³ and 1 × 10 ¹⁸
The high-concentration impurity region contains a p-type impurity element having a concentration of about 5 × 10 ²¹ / cm ³ , and the high-concentration impurity region is 1 × 10 ^{20 to} 5 × 10 ²¹ / cm 3.
Impurity element imparting n-type with a concentration of ³ and 1 × 10 ²⁰
A semiconductor device comprising a p-type impurity element having a concentration of about 5 × 10 ²² / cm ³ . 12. The semiconductor device according to claim 11, wherein an end of the gate electrode has a tapered shape. 13. The semiconductor device according to claim 11, wherein the semiconductor device is a liquid crystal display device, an EL display device, or an image sensor. 14. The semiconductor device according to claim 11, wherein the semiconductor device is a mobile phone, a video camera, a digital camera, a projector, a goggle type display, a personal computer, a DVD player, an electronic dictionary, or a portable information terminal. Characteristic semiconductor device.