JP2002057165A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a TFT provided with an LDD structure and a TFT provided with a GOLD structure in the manufacturing processes simpler than the conventional manufacturing processes of the TFTs and in the number of the processes fewer than the conventional number of the processes. SOLUTION: A semiconductor device is constituted in a structure that an electrode consisting of a laminating of a first conducting layer 18b and a second conducting layer 17c is formed. After high-concentration impurity regions 22 and 23 and low-concentration impurity regions 24 and 25 are formed by a first doping process or a second doping process, the layer 18b is selectively etched. The width of a low-concentration impurity region 25a which is superposed on a first conducting layer 18c, and the width of a low-concentration impurity region 25b which is not superposed on the layer 18c, are freely adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, a liquid crystal display panel,
The present invention relates to an electro-optical device typified by an EL (electroluminescence) display device, an EC display device, and the like, and to an electronic apparatus equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a thin film transistor (TFT) has been constructed using a semiconductor thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface, and a large-area integrated circuit formed by the TFT has been developed. The development of a semiconductor device having the same is progressing. Active matrix liquid crystal display devices, EL display devices, and contact image sensors are known as typical examples. In particular, a TFT using a crystalline silicon film (typically, a polysilicon film) as an active layer (hereinafter referred to as a polysilicon TFT) has a high field-effect mobility, so that various functional circuits can be formed. It is.

For example, an active matrix type liquid crystal display device controls a pixel circuit for displaying an image for each functional block, and a pixel circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit based on a CMOS circuit. Is formed on one substrate.

In a pixel circuit of an active matrix type liquid crystal display device, TFTs (pixel TFTs) are arranged for tens to millions of pixels, and each of the pixel TFTs is provided with a pixel electrode. A counter electrode is provided on the counter substrate side sandwiching the liquid crystal, and forms a kind of capacitor using the liquid crystal as a dielectric. Then, the voltage applied to each pixel is controlled by the switching function of the TFT, the liquid crystal is driven by controlling the charge to the capacitor, and the amount of transmitted light is controlled to display an image.

The pixel TFT is formed of an n-channel type TFT, and is a device that applies a voltage to a liquid crystal as a switching element to drive the liquid crystal. Since the liquid crystal is driven by alternating current, a method called frame inversion drive is often used. In this method, in order to suppress power consumption, it is important for the characteristics required for the pixel TFT to sufficiently reduce an off-current value (a drain current flowing when the TFT is turned off).

As a structure of a TFT for reducing an off-current value, a lightly doped drain (LDD) is used.
n) Structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration. This region is referred to as an LDD region. Calling. As means for preventing deterioration of the on-current value due to hot carriers, L
The so-called G in which the DD region is arranged so as to overlap the gate electrode
An OLD (Gate-drain Overlapped LDD) structure is known. With such a structure, it is known that a high electric field near the drain is relieved, hot carrier injection is prevented, and deterioration is effectively prevented.

Although the GOLD structure has a high effect of preventing the deterioration of the ON current value, it has a problem that the OFF current value becomes larger than that of the ordinary LDD structure. Therefore, it was not a preferable structure to be applied to the pixel TFT. Conversely, the ordinary LDD structure has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain to prevent deterioration due to hot carrier injection. As described above, in a semiconductor device having a plurality of integrated circuits, such as an active matrix type liquid crystal display device, such a problem is caused particularly by an increase in characteristics of a crystalline silicon TFT, and also in an active matrix type liquid crystal display device. It has become apparent as the required performance increases.

[0009]

Conventionally, when a TFT having an LDD structure or a TFT having a GOLD structure is to be formed, there has been a problem that the manufacturing steps are complicated and the number of steps is increased. . It is clear that an increase in the number of steps not only causes an increase in manufacturing cost but also causes a reduction in manufacturing yield.

The present invention is a technique for solving such a problem. In an electro-optical device and a semiconductor device represented by an active matrix type liquid crystal display device manufactured using a TFT, the operation characteristics of the semiconductor device are considered. And to improve reliability and reduce power consumption.
An object of the present invention is to reduce the number of processes to achieve a reduction in manufacturing cost and an improvement in yield.

[0011]

In order to reduce the manufacturing cost and improve the yield, it is conceivable to reduce the number of processes as one means. Specifically, TF
The number of photomasks required for manufacturing T is reduced. A photomask is used in a photolithography technique to form a resist pattern used as a mask on a substrate in an etching step. Therefore, the use of one photomask means that in addition to the steps such as film formation and etching in the preceding and subsequent steps, resist stripping, washing and drying steps are added, and in the photolithography step, This means that complicated processes such as resist coating, pre-baking, exposure, development, and post-baking are performed.

According to the present invention, the number of photomasks is further reduced as compared with the prior art, and the TFT is manufactured by the following manufacturing process.
Is produced. Note that an example of the manufacturing method of the present invention is shown in FIGS.

[0013] The production method of the present invention disclosed herein includes:
A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first conductive layer having a first width (W1) on the insulating film. Layer and the second
A third step of forming a first electrode made of a laminate with the first conductive layer, and etching the second conductive layer to form the first electrode.
A first conductive layer having a width (W1) and a second width (W1).
A fourth step of forming a second electrode composed of a stack of a second conductive layer having 2) and a high concentration impurity region by adding an impurity element to the semiconductor layer using the second electrode as a mask; Forming a low-concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer using the second conductive layer as a mask. And etching the first conductive layer to form a third
And a seventh step of forming a third electrode formed by laminating a first conductive layer having a width (W3) and a second conductive layer having a second width (W2). This is a method for manufacturing the device.

In the above manufacturing method, a heat-resistant conductive material is used as a material for forming the first conductive film and the second conductive film, and typically, tungsten (W), tantalum (Ta), and titanium ( It is formed from an element selected from Ti), or a compound or alloy containing the element as a component.

In the third step, the shape of the first electrode is a so-called tapered shape in which the thickness gradually increases from the end toward the inside at the end.

The first conductive film and the second conductive film made of a heat-resistant conductive material are etched at high speed and with high accuracy.
In order to further form a tapered end portion, a dry etching method using high-density plasma is applied. An etching apparatus using microwaves or inductively coupled plasma (ICP) is suitable for obtaining high-density plasma. In particular, an ICP etching apparatus can easily control plasma and can cope with an increase in the area of a processing substrate.

A plasma processing method and a plasma processing apparatus using ICP are disclosed in JP-A-9-293600. In this publication, as means for performing plasma processing with high accuracy, high-frequency power is applied to a multi-spiral coil having four spiral coil portions connected in parallel via an impedance matching device to form plasma. Method. Here, 1 of each coil part
The length per book is 1/4 times the wavelength of the high frequency. Further, a bias voltage is applied by separately applying a high-frequency power to the lower electrode holding the object to be processed.

When an etching apparatus using an ICP to which such a multi-spiral coil is applied is used, the angle of the tapered portion (taper angle) greatly changes depending on the bias power applied to the substrate side, and the bias power is further increased. By changing the pressure, the angle of the tapered portion can be changed from 5 to 45 °.

Further, in the fourth step, the second conductive layer is selectively etched by using an etching apparatus using ICP to form the second conductive layer 17c constituting the second electrode. The second width (W2) is equal to the first width (W1).
Make it narrower. In addition, the first electrode in the second electrode
The taper angle at the end of the conductive layer is smaller than the taper angle at the end of the second conductive layer.

In the fifth step, in order to form the high-concentration impurity regions 20 and 21 in a self-aligned manner, the ionized impurity element is accelerated by an electric field to form a gate insulating film (first in the present invention). A gate insulating film including an insulating film provided in close contact with and between the electrode and the semiconductor layer, and an insulating film extending from the insulating film to a peripheral region of the insulating film. The method of adding to a layer is used.
In this specification, the method of adding the impurity element is referred to as a “through doping method” for convenience.

In this specification, an impurity element is an impurity element (phosphorus, arsenic) that imparts n-type to a semiconductor.
Alternatively, it refers to an impurity element (boron) that imparts p-type.

Further, in the sixth step, the semiconductor layer existing below the tapered portion (tapered portion) of the first conductive layer constituting the second electrode is formed by using the through doping method. The low-concentration impurity regions 24 and 25 are formed in a self-aligned manner, and the low-concentration impurity regions 24 and 25 are continuously increased as the concentration of the impurity element is further away from the channel formation region. However, even if it is continuously increased, there is almost no difference in concentration in the low concentration impurity region.

In order to form the low-concentration impurity regions 24 and 25 having a gentle concentration gradient in a self-aligned manner, the ionized impurity element is accelerated by an electric field to form the first electrode forming the second electrode. It is added to the semiconductor layer through the tapered portion of the conductive layer and the gate insulating film. Thus, the second
By performing the through-doping method on the tapered portion of the first conductive layer constituting the electrode, the concentration of the impurity element added to the semiconductor layer can be controlled by the thickness of the tapered portion of the first conductive layer. Thus, low-concentration impurity regions 24 and 25 in which the concentration of the impurity element gradually changes in the channel length direction of the TFT can be formed.

Immediately after the sixth step in which the above-described through doping is performed, the low-concentration impurity regions 24 and 25 overlap with the tapered portion of the first conductive layer forming the second electrode via the gate insulating film. I have.

In the seventh step, the tapered portion of the first conductive layer is selectively etched. In the etching in the seventh step, the practitioner may perform etching using an RIE method, etching using an ICP method, or etching using the RIE method after using the ICP method as appropriate.
According to the seventh step, the taper angle of the first conductive layer in the third electrode becomes substantially the same as the taper angle of the first conductive layer in the second electrode. Also,
The third width (W3) is smaller than the first width (W1) and wider than the second width (W2). Here, an example is shown in which the insulating film is removed at the same time as the seventh step and a part of the high-concentration impurity region is exposed. However, the present invention is not particularly limited, and may remain thin.

Immediately after the step 7, the low-concentration impurity region includes a region 25a overlapping the tapered portion of the first conductive layer forming the third electrode with the gate insulating film interposed therebetween.
The tapered portion of the first conductive layer which forms the third electrode with the gate insulating film interposed therebetween can be distinguished from the region 25b which does not overlap.

The third width (W3) can be freely adjusted by appropriately changing the etching conditions. Therefore, according to the present invention, the width of the low-concentration impurity region overlapping the third electrode and the width of the low-concentration impurity region not overlapping the third electrode are changed by appropriately changing the etching conditions in the seventh step. Can be adjusted freely. However, the low concentration impurity region is
Irrespective of the width of the third electrode, it has a gradual concentration gradient, and in the region overlapping with the third electrode, the concentration of the electric field can be alleviated and the hot carrier can prevent the concentration. The off-current value can be suppressed in a region not overlapping with the electrode.

[0028] In the above manufacturing method, the first step includes the first step.
Photolithography step, and the third step
Photolithography process, but other
In the steps (fourth to seventh steps), the second photolithography
Use the resist mask used in the fee process as it is
The photolithography process is not
No.

Therefore, after the seventh step, a third photolithography step for forming a contact hole in the formed interlayer insulating film and a third photolithography step for forming a source electrode or a drain electrode reaching the semiconductor layer. By performing the photolithography process of No. 4, a TFT can be manufactured.

While reducing the number of photomasks in this way, the present invention was able to make the TFT configuration appropriate. The configuration of the present invention will be described below.

According to the present invention, as shown in FIG. 3, in a low-concentration impurity region 25 provided between a channel forming region 26 and a drain region 23, an impurity element which imparts a conductivity type gradually toward a drain region is provided. In the point where the concentration gradient is set so that the concentration is increased, and in the low concentration impurity region 25 having the gentle concentration gradient, the gate electrode 18 is formed.
This is characterized in that a region 25a (a GOLD region) overlapping with c and a region 25b (an LDD region) not overlapping with the gate electrode are provided.

In this specification, a low-concentration impurity region which overlaps with a gate electrode via an insulating film is called a GOLD region, and a low-concentration impurity region which does not overlap with the gate electrode is LDD.
It is called an area.

Further, the TFT formed by using the above steps
Is used to form an electro-optical device represented by a liquid crystal display device or an EL display device.

In the above manufacturing process, an example is shown in which high-concentration doping is performed in the fifth step and low-concentration doping is performed in the sixth step. However, low-concentration doping is performed in the fifth step. Alternatively, high concentration doping may be performed in the sixth step. In this case, the manufacturing method of the present invention includes a first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first step of forming a first layer on the insulating film. A third step of forming a first electrode formed by laminating a first conductive layer having a width (W1) and a second conductive layer; and etching the second conductive layer to form the first electrode. Width (W1)
Forming a second electrode formed by laminating a first conductive layer having a first width and a second conductive layer having a second width (W2).
Step, and using the second conductive layer as a mask,
A fifth step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer by passing through the conductive layer, and adding an impurity element to the semiconductor layer using the second electrode as a mask. A sixth step of forming a concentration impurity region, etching the first conductive layer to form a first conductive layer having a third width (W3), and forming a first conductive layer having a second width (W2). And a seventh step of forming a third electrode composed of a stack of two conductive layers.

FIGS. 4 and 5 show an example of the manufacturing method of the present invention.

As shown in FIGS. 4 and 5, another invention disclosed in this specification is a first step of forming a semiconductor layer on an insulating surface, and forming an insulating film on the semiconductor layer. Second
A third step of forming a first electrode comprising a stack of a first conductive layer having a first width (W1) and a second conductive layer on the insulating film; The second electrode is formed by stacking a first conductive layer having the first width (W1) and a second conductive layer having a second width (W2) by etching the second conductive layer. A fourth step of forming
A fifth step of forming a high-concentration impurity region and a low-concentration impurity region by adding an impurity element to the semiconductor layer using the conductive layer as a mask, and etching the first conductive layer to a third width. A sixth step of forming a third electrode formed by laminating a first conductive layer having (W3) and a second conductive layer having the second width (W2). It is a manufacturing method.

As described above, the practitioner can adjust the doping conditions as appropriate to form a step of forming the low concentration impurity region and the high concentration impurity region by one doping process.

FIG. 6 shows an example of the manufacturing method of the present invention.

As shown in FIGS. 4A to 4C and FIG. 6, another invention disclosed in this specification is a first step of forming a semiconductor layer on an insulating surface, A second step of forming an insulating film on the semiconductor layer, a third step of forming a first conductive film and a second conductive film on the insulating film,
A fourth step of forming a second conductive layer having a width of (X1), and adding an impurity element to the semiconductor layer using the second conductive layer having the first width (X1) as a mask. A fifth step of forming a high-concentration impurity region, and etching the first conductive film to form a first conductive layer having the second width (X2) and a third conductive layer having a third width (X3). A sixth step of forming a first electrode made of a laminate with a second conductive layer;
The second conductive layer is etched to have the second width (X
A seventh step of forming a second electrode formed by laminating a first conductive layer having the second width (2) and a second conductive layer having the fourth width (X4); An eighth step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer by passing through the first conductive layer using the second conductive layer having Etching the layer to form a third electrode comprising a stack of a first conductive layer having a fifth width (X5) and a second conductive layer having the fourth width (X4); 9 is a method for manufacturing a semiconductor device having the following steps:

In each of the above-described manufacturing methods, the third
Forming a first interlayer insulating film covering the third electrode after the step of forming the third electrode, performing a first heat treatment for activating an impurity element in the semiconductor layer, Forming a second interlayer insulating film covering the first interlayer insulating film, and performing a second heat treatment at a lower temperature than the first heat treatment after forming the second interlayer insulating film. It is characterized by having.

Another aspect of the invention disclosed in this specification is a first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, A third step of laminating a first conductive film and a second conductive film thereon, a fourth step of forming a second conductive layer having a first width (X1), A fifth step of forming a high-concentration impurity region by adding an impurity element to the semiconductor layer using the second conductive layer having the width (X1) as a mask; and etching the second conductive layer, Second width (Y2)
A sixth step of forming a second conductive layer having: a second conductive layer having a second width (Y2) as a mask;
A seventh step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer by passing through the first conductive film; and etching the first conductive film to form a third width (Y
An eighth step of forming an electrode formed by laminating a first conductive layer having 3) and a second conductive layer having the second width (Y2) is a method for manufacturing a semiconductor device. .

After the eighth step, a ninth step of forming a first interlayer insulating film covering the third electrode and a first heat treatment for activating an impurity element in the semiconductor layer are performed. A tenth step, an eleventh step of forming a second interlayer insulating film covering the first interlayer insulating film, and a twelfth step of performing a second heat treatment at a lower temperature than the first heat treatment. It is also characterized.

[0043]

(Embodiment 1) Embodiment 1 of the present invention will be described below with reference to FIGS.

First, a base insulating film 11 is formed on a substrate 10. The substrate 10 may be a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature may be used.

As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, an example is shown in which a two-layer structure (11a, 11b) is used as the base film 11, but a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. Note that the base insulating film need not be formed.

Next, the semiconductor layer 12 is formed on the base insulating film. The semiconductor layer 12 is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, or the like), and then performing a known crystallization treatment (laser crystallization method, thermal crystallization, or the like). , Or a thermal crystallization method using a catalyst such as nickel) is used to pattern the crystalline semiconductor film into a desired shape using a first photomask. The thickness of this semiconductor layer 12 is 2
It is formed with a thickness of 5 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon or silicon germanium (SiGe).
It is good to form with an alloy etc.

Next, an insulating film 13 covering the semiconductor layer 12 is formed.

The insulating film 13 is formed by a plasma CVD method or a sputtering method to have a thickness of 40 to 150 nm and a single layer or a laminated structure of an insulating film containing silicon. In addition,
This insulating film 13 becomes a gate insulating film.

Next, a film thickness of 20 to 100
A first conductive film 14 having a thickness of 100 nm and a second conductive film 15 having a thickness of 100 to 400 nm are stacked. (FIG. 1A) Here, a first conductive film 14 made of a TaN film and a second conductive film 15 made of a W film were formed by sputtering using a sputtering method. Note that, here, the first conductive film 14 is TaN, and the second conductive film 15 is W. However, the present invention is not particularly limited, and any element selected from Ta, W, Ti, Mo, Al, and Cu; Alternatively, it may be formed of an alloy material or a compound material containing the above element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used.

Next, a resist mask 16a is formed using a second photomask, and a first etching step is performed using an ICP etching apparatus. By the first etching step, the second conductive film 15 is etched,
As shown in FIG. 1B, a second conductive layer 17a having a tapered portion (tapered portion) at an end portion
Get. Note that the first conductive film is also slightly etched during the first etching, but is not shown here.

Here, the angle of the tapered portion (taper angle)
Is defined as the angle between the substrate surface (horizontal plane) and the inclined portion of the tapered portion. The taper angle of the second conductive layer 17a can be set to 5 by appropriately selecting etching conditions.
It can be in the range of up to 45 °.

Next, using the resist mask 16a as it is, a second etching step is performed using an ICP etching apparatus. By the second etching step, the first
Is etched to form a first conductive layer 18a as shown in FIG. First conductive layer 18a
Has a first width (W1). During the second etching step, a resist mask, a second conductive layer,
And the insulating film is also slightly etched, so that the resist mask 16b, the second conductive layer 17b, and the insulating film 19a are respectively obtained.
Is formed.

In this case, two etchings (a first etching step and a second etching step) are performed in order to suppress the thickness of the insulating film 13 from being reduced. However, as shown in FIG. There is no particular limitation as long as an electrode structure (a laminate of the second conductive layer 17b and the first conductive layer 18a) can be formed, and the etching may be performed in a single etching step.

Next, using the resist mask 16b,
A third etching step is performed using an ICP etching apparatus. In the third etching step, the second conductive layer 17b is etched to form a second conductive layer 17b as shown in FIG.
Of the conductive layer 17c is formed. The second conductive layer 17c has a second width (W2). At the time of the third etching, the resist mask, the first conductive layer, and the insulating film are also slightly etched, and the resist mask 16
c, a first conductive layer 18b and an insulating film 19b are formed.
(Fig. 1 (D))

Next, a first doping step is performed while the resist mask 16c is left as it is. In this first doping step, through doping is performed through the insulating film 19b using the first conductive layer as a mask to form high-concentration impurity regions 20 and 21. (Fig. 2 (A))

By performing through doping in this manner, the doping amount implanted into the semiconductor layer can be controlled to a desired value.

Next, a second doping step is performed while the resist mask 16c is left as it is. In this second doping step, through doping is performed via the tapered portion of the first conductive layer 18b and the insulating film 19b to form low-concentration impurity regions 24 and 25. (Figure 2
(B) During the second doping, the high-concentration impurity regions 20 and 21 are also doped, so that the high-concentration impurity regions 22 and 23 are formed.

Next, an RIE etching apparatus or an ICP
A fourth etching step is performed using an etching device.
By this fourth etching step, the first conductive layer 18 is formed.
Part of the tapered portion b is removed. Here, the first width (W
The first conductive layer 18b having 1) has a third width (W).
The first conductive layer 18c having 3) was obtained. (Figure 2
(C))

In the present embodiment, the first conductive layer 18
c and the second conductive layer 17c laminated thereon serve as a gate electrode. In the fourth etching, the insulating film 1
9b is also etched to form an insulating film 19c.
Here, an example in which a part of the insulating film is removed to expose the high-concentration impurity regions is shown; however, the present invention is not particularly limited. The high-concentration impurity regions may be covered with a thin insulating film.

Thereafter, the resist mask 16c is removed,
The impurity element added to the semiconductor layer is activated. Next, after an interlayer insulating film 27 is formed, a contact hole is formed using a third mask, a conductive film is formed, and then electrodes 28 and 29 are formed using a fourth mask.

In this way, with four photomasks, FIG.
A TFT having the structure shown in FIG. 3D can be formed.

The feature of the TFT formed according to the present invention is that the low concentration impurity region 25 provided between the channel formation region 26 and the drain region 23 has almost no concentration difference and has a gentle concentration gradient. And a region 25a (GOLD region) overlapping the gate electrodes (17c and 18c) and a region 25b (LDD region) not overlapping the gate electrode. The peripheral portion of the insulating film 19c, that is, the region 25b that does not overlap with the gate electrode and the regions above the high-concentration impurity regions 20 and 21 are tapered.

(Embodiment 2) Embodiment 2 of the present invention will be described below with reference to FIGS.

This embodiment is different from the first embodiment.
And the first etching step (FIG. 1B) is the same, and the same reference numerals are used. Also, FIG.
FIG. 4 (B) corresponds to FIG. 1 (B).

First, according to the first embodiment, FIG.
(B) state is obtained. (FIG. 4B) Note that the second conductive layer 17a having the first width (X1) is formed by this first etching step.

Next, a first doping step is performed with the resist mask 16a kept as it is. In the first doping step, through doping is performed through the first conductive film 14 and the insulating film 13 using the second conductive layer 17a as a mask to form the high concentration impurity regions 30 and 31. (FIG. 4 (C))

By performing the through doping in this manner, the doping amount implanted into the semiconductor layer can be controlled to a desired value.

Next, using the resist mask 16a as it is, a second etching step is performed using an ICP etching apparatus. By the second etching step, the first
Is etched to form a first conductive layer 34a as shown in FIG. First conductive layer 34a
Has a second width (X2). During the second etching step, a resist mask, a second conductive layer,
The resist and the insulating film are also slightly etched to form a resist mask 32a, a second conductive layer 33a having a third width (X3), and an insulating film 35a, respectively.

Next, using the resist mask 32a,
A third etching step is performed using an ICP etching apparatus. In the third etching step, the second conductive layer 33a is etched to form the second conductive layer 33a as shown in FIG.
Is formed. The second conductive layer 33b has a fourth width (X4). At the time of the third etching, the resist mask, the first conductive layer, and the insulating film are also slightly etched, and the resist mask 32
b, a first conductive layer 34b and an insulating film 35b are formed.
(FIG. 5 (A))

Next, a second doping step is performed while the resist mask 32b is left as it is. Through-doping is performed by the second doping step via the tapered portion of the first conductive layer 34b and the insulating film 35b to form low-concentration impurity regions 38 and 39. (FIG. 5
(B)) At the time of the second doping, the high concentration impurity regions 30 and 31 are also doped, and the high concentration impurity regions 36 and 37 are formed.

Next, an RIE etching device or an ICP
A fourth etching step is performed using an etching device.
By this fourth etching step, the first conductive layer 34
Part of the tapered portion b is removed. Here, the first width (X
The first conductive layer 34b having 2) has a fifth width (X
This resulted in a first conductive layer 34c having 5). (FIG. 5
(C))

In the present embodiment, the first conductive layer 34
c and the second conductive layer 33b laminated thereon serve as a gate electrode. In addition, at the time of this fourth etching, the insulating film 3
5b is also etched to form an insulating film 35c.
Here, an example in which a part of the insulating film is removed to expose the high-concentration impurity regions is shown; however, the present invention is not particularly limited. The high-concentration impurity regions may be covered with a thin insulating film.

Thereafter, the resist mask 32b is removed,
The impurity element added to the semiconductor layer is activated. Next, after forming an interlayer insulating film 41, a contact hole is formed using a third mask, and a conductive film is formed. Then, electrodes 42 and 43 are formed using a fourth mask.

In this manner, four photomasks are used to obtain FIG.
A TFT having the structure shown in FIG. 3D can be formed.

The feature of the TFT formed by the present invention is that the low concentration impurity region 39 provided between the channel formation region 40 and the drain region 37 has almost no concentration difference and has a gentle concentration gradient. And a region 39a (GOLD region) that overlaps with the gate electrodes (33b and 34c) and a region 39b (LDD region) that does not overlap with the gate electrode. The peripheral portion of the insulating film 35c, that is, the region 39b that does not overlap with the gate electrode and the regions above the high-concentration impurity regions 37 and 36 are tapered.

(Embodiment 3) Embodiment 3 of the present invention will be described below with reference to FIGS.

This embodiment is similar to the second embodiment.
And the first doping step (FIG. 4C) is the same, and the illustration is omitted. Also, here, the description will be made using the same reference numerals as those in FIG.

First, according to the first embodiment, FIG.
The state of (C) is obtained.

Next, using the resist mask 16a,
A second etching step is performed using an ICP etching apparatus. In this second etching step, the second conductive layer 17a is etched to form a second conductive layer 17a as shown in FIG.
Is formed. The second conductive layer 51 has a second width (Y2). Note that, during the second etching step, the resist mask and the first conductive film are also slightly etched to form the resist mask 50 and the first conductive film 52a, respectively. (FIG. 5A) Since a part of the first conductive film 52a has already been slightly etched in the first etching step, the thickness is further reduced by the second etching step. . In the first conductive film 52a which does not overlap with the second conductive layer, a portion which is not etched in the first etching step has a tapered shape.

Next, a second doping step is performed while the resist mask 50 is left as it is. In this second doping step, through doping is performed through the tapered portion of the first conductive film 52a and the insulating film 13 to form low-concentration impurity regions 55 and 56. (FIG. 6 (B))
During the second doping, the high-concentration impurity regions 3
0 and 31 are also doped, and the high-concentration impurity regions 55,
56 are formed.

By performing through doping in this manner, the doping amount implanted in the semiconductor layer can be controlled to a desired value.

Next, while the resist mask 50 is left as it is, a third etching step is performed using an RIE etching apparatus or an ICP etching apparatus. By the third etching step, of the exposed first conductive film 52a, a part thinned by the first etching step and a part of a tapered part are removed. Here, by appropriately adjusting the etching conditions in consideration of the thickness of the first conductive film, the thickness of the insulating film, and the like, the first film having a tapered shape and having the third width (Y3) is obtained. Of the conductive layer 52b is formed. (FIG. 6 (C))

In the present embodiment, the first conductive layer 52
b and the second conductive layer 51 laminated thereon serve as a gate electrode. During the third etching, the insulating film 13
Is also etched to form an insulating film 57.

After that, the resist mask 50 is removed, and the impurity element added to the semiconductor layer is activated. Next, after an interlayer insulating film 59 is formed, a contact hole is formed using a third mask, a conductive film is formed, and electrodes 60 and 61 are formed using a fourth mask.

In this manner, four photomasks are used to obtain FIG.
A TFT having the structure shown in FIG. 3D can be formed.

The feature of the TFT formed according to the present invention is that the low-concentration impurity region 54 provided between the channel formation region 58 and the drain region 56 has almost no concentration difference and has a gentle concentration gradient. And a region 54a (GOLD region) overlapping the gate electrode (51 and 52b) and a region 54b (LDD region) not overlapping the gate electrode.

The present invention having the above structure will be described in more detail with reference to the following embodiments.

[0088]

[Embodiment 1] Here, a method for simultaneously manufacturing a pixel portion and a TFT (n-channel TFT and p-channel TFT) of a driving circuit provided around the pixel portion on the same substrate is described in detail. This will be described with reference to FIGS.

First, in this embodiment, Corning # 70
A substrate 100 made of glass such as barium borosilicate glass represented by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that the substrate 100 is not limited as long as it is a light-transmitting substrate, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a silicon oxide film is formed on the substrate 100,
A base film 101 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. Although a two-layer structure is used as the base film 101 in this embodiment, a single-layer film of the insulating film or a structure in which two or more insulating films are stacked may be used. For the first layer of the base film 101, a plasma CVD
iH _4, NH _3, a and N ₂ O silicon oxynitride film 101a is formed as the reaction gas 10 to 200 nm (preferably 50 to 100 nm) is formed. In this embodiment, the film thickness 5
0 nm silicon oxynitride film 101a (composition ratio Si = 3
2%, O = 27%, N = 24%, H = 17%). Next, as the second layer of the base film 101, a silicon oxynitride film 101 b formed using SiH ₄ and N ₂ O as a reaction gas by plasma CVD is used to form a 50-200 layer.
nm (preferably 100 to 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 101b (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%).

Next, the semiconductor layers 102 to 10 are formed on the underlying film.
5 is formed. The semiconductor layers 102 to 105 are formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCV
D method or plasma CVD method)
A crystalline semiconductor film obtained by performing a known crystallization treatment (such as a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalyst such as nickel) is patterned and formed into a desired shape. . The thickness of the semiconductor layers 102 to 105 is 2
It is formed with a thickness of 5 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon or silicon germanium (Si _x Ge).
_1-X (0 <X <1, typically X = 0.0001 to 0.
05)) It is good to form with an alloy etc. When silicon germanium is formed, it may be formed by a plasma CVD method using a mixed gas of silane and germanium, germanium may be ion-implanted into a silicon film, or sputtered using a target made of silicon germanium. It may be formed by a method. In this embodiment, after a 55 nm amorphous silicon film is formed by a plasma CVD method, a solution containing nickel is held on the amorphous silicon film.
Dehydrogenation of this amorphous silicon film (500 ° C, 1 hour)
After that, thermal crystallization (550 ° C., 4 hours) was performed, and further, a laser annealing process for improving crystallization was performed to form a crystalline silicon film. Then, semiconductor layers 102 to 105 were formed by patterning the crystalline silicon film using a photolithography method.

After the semiconductor layers 102 to 105 are formed, a small amount of impurity element (boron or phosphorus) may be doped (also called channel doping) in order to control the threshold value of the TFT.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 40.
(Typically ^{200~300mJ / cm 2) 0mJ / cm} 2 to. When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 1 to 10 kHz, and the laser energy density is set to 300 to 600 mJ / cm ² (typically 35 to
0 to 500 mJ / cm ² ). And width 100-1
A laser beam condensed linearly at 000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is 80 to 98%.
What should be done.

Next, a gate insulating film 106 covering the semiconductor layers 102 to 105 is formed. It is preferable that the surface of the semiconductor layer be cleaned before forming the gate insulating film. To remove contaminant impurities (typically C, Na, etc.) on the surface of the coating, clean the surface of the coating with a fluorine-containing acidic solution after cleaning with pure water containing ozone. It can be done by: As a means for etching very thinly, a method of spinning a substrate using a spin device and scattering an acidic solution containing fluorine brought into contact with the surface of the coating film is effective. As the acidic solution containing fluorine, use hydrofluoric acid, dilute hydrofluoric acid, ammonium fluoride, buffered hydrofluoric acid (a mixed solution of hydrofluoric acid and ammonium fluoride), or a mixed solution of hydrofluoric acid and hydrogen peroxide water Can be. After the cleaning, the gate insulating film 106 is continuously formed to a thickness of 40 using a plasma CVD method or a sputtering method.
The insulating film containing silicon is formed to have a thickness of 150 nm, preferably 50 nm to 100 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2) with a thickness of 110 nm by a plasma CVD method.
%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used,
TEOS (Tetraethyl Orthosilica) by plasma CVD
te) and O ₂ , a reaction pressure of 40 Pa, and a substrate temperature of 30
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² at 0 to 400 ° C. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Next, as shown in FIG. 7A, a first conductive film 107 having a thickness of 20 to 100 nm and a second conductive film 10 having a thickness of 100 to 400 nm are formed on the gate insulating film 106.
8 are laminated. Further, it is preferable that the gate insulating film, the first conductive film, and the second conductive film be formed successively without exposure to the air in order to prevent contamination. In the case where the film is not continuously formed, the contamination at the film interface can be prevented by using a film forming apparatus with a cleaning machine. The cleaning method may be the same as that performed before forming the gate insulating film.
In this embodiment, a first conductive film 107 made of a TaN film having a thickness of 30 nm and a second conductive film 108 made of a W film having a thickness of 370 nm are formed continuously. The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set the resistance to Ωcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, high purity W
(Purity 99.9999%) by sputtering using a target, and further forming a W film with sufficient care so as not to mix impurities from the gas phase at the time of film formation, the resistivity becomes 9 to 20 μΩcm. Could be realized.

In this embodiment, the first conductive film 107
Is TaN, and the second conductive film 108 is W. However, the present invention is not particularly limited, and any of Ta, W, Ti, Mo, Al, Cu,
It may be formed of an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, A
A gPdCu alloy may be used. A first conductive film formed of a tantalum (Ta) film, a second conductive film formed of a W film, a first conductive film formed of a titanium nitride (TiN) film, and a second conductive film formed of a titanium nitride (TiN) film; As a W film, the first
The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of a Cu film. May be combined.

Next, masks 109 to 112 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, the first etching condition is I
Using a CP (Inductively Coupled Plasma) etching method, using CF ₄ , Cl _2, and O _{2 as} etching gases, and using a gas flow ratio of 25/2.
At 5/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching condition to form a second film.
Of the conductive layer is tapered. The etching rate for W under the first etching condition is 200.39 n.
m / min, etching rate for TaN is 80.3
At 2 nm / min, the selectivity ratio of W to TaN is about 2.5. Further, the taper angle of W is about 26 ° under the first etching condition. Note that the etching under the first etching condition here corresponds to the first etching step (FIG. 1B) described in Embodiment 1.

Thereafter, the masks 109 to 109 made of resist are formed.
The second etching condition was changed without removing 112, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30/30 (sccm), and the pressure was 1 Pa to form a coil-type electrode. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%. Note that the etching under the second etching condition here corresponds to the second etching step (FIG. 1C) described in Embodiment 1.

In the first etching process, the shape of the mask made of resist is made appropriate so that
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. (FIG. 7B) The angle of the tapered portion may be 15 to 45 °. Thus, the first shape conductive layer 11 composed of the first conductive layer and the second conductive layer is subjected to the first etching process.
3 to 116 (the first conductive layers 113a to 116a and the second conductive layers 113b to 116b) are formed. Here, the width of the first conductive layer in the channel length direction corresponds to W1 described in Embodiment 1 above. Reference numeral 117 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 113 to 116 is etched to about 20 to 50 nm to form a thinned region.

Next, a second etching process is performed without removing the resist mask. Note that an etching gas used for the first etching process or the second etching process is a chlorine compound-based gas such as Cl ₂ , BCl ₃ , SiCi ₄ or CCl ₄ , or a fluorine compound such as CF ₄ , SF ₆ or NF ₃ . A gas selected from a system gas and O ₂ , or a mixed gas containing these as a main component may be used. Here, CF ₄ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are 25/25/10 (sccm).
500W RF (13.56MHZ) on coil type electrode at pressure of Pa
z) Power was applied to generate plasma to perform etching. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate for W is 124.62 nm / min, and the etching rate for TaN is 20.67 nm / min.
The selectivity ratio of W to N is 6.05. Therefore, the W film is selectively etched. The taper angle of W became 70 ° by the second etching process. By this second etching process, the second conductive layers 122b to 125b
To form On the other hand, the first conductive layers 113a to 116a
Is hardly etched, and the first conductive layer 122a
To 125a. Note that the second etching treatment here corresponds to the third etching step (FIG. 1D) described in Embodiment 1. Further, the width of the second conductive layer in the channel length direction here corresponds to W2 described in Embodiment 1.

Then, the resist mask is removed.
First doping processing without adding an n-type semiconductor layer.
The added impurity element is added. (Fig. 7 (C)) Dopin
Can be done by ion doping or ion implantation
Good. The condition of the ion doping method is that the dose amount is 1 × 10¹³
~ 5 × 10^Fifteenatoms / cm^TwoAnd the acceleration voltage is 60 to 100
Performed as keV. In this embodiment, the dose is 1.5 × 1
0^Fifteenatoms / cm^TwoAnd the acceleration voltage is set to 80 keV.
Was. Element belonging to Group 15 as an impurity element imparting n-type
Using arsenic, typically phosphorus (P) or arsenic (As)
However, phosphorus (P) was used here. In this case, the conductive layer 1
13 to 116 are masses for the impurity element imparting the n-type.
And the high-concentration impurity regions 118 to 12 are self-aligned.
1 is formed. In the high concentration impurity regions 118 to 121,
1 × 10²⁰~ 1 × 10^{twenty one}atoms / cm ^ThreeN type in the concentration range of
An impurity element to be added is added. The first here
The doping is performed by the first dopant described in the first embodiment.
This corresponds to a ping step (FIG. 2A).

Next, a second doping process is performed to obtain the state shown in FIG. Doping is performed on the second conductive layer 12
Using 2b to 125b as a mask for the impurity element, doping is performed so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer. In this embodiment, P (phosphorus) is used as an impurity element, and a dose amount of 3.
Plasma doping was performed at 5 × 10 ¹² and an acceleration voltage of 90 keV. Thus, the low-concentration impurity regions 126 to 129 overlapping with the first conductive layer are formed in a self-aligned manner. The concentration of phosphorus (P) added to low-concentration impurity regions 126 to 129 is 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ , and depends on the thickness of the tapered portion of the first conductive layer. It has a gentle concentration gradient. Note that in the semiconductor layer overlapping with the tapered portion of the first conductive layer, the impurity concentration is slightly reduced from the end of the tapered portion of the first conductive layer toward the inside, but is approximately the same. . Further, an impurity element is also added to the high-concentration impurity regions 118 to 121 to form the high-concentration impurity regions 130 to 133. Note that the second doping process here corresponds to the second doping step (FIG. 2B) described in Embodiment 1.

In this embodiment, an example is shown in which the high concentration impurity region is formed by the first doping process and the low concentration impurity region is formed by the second doping process. The low concentration impurity region may be formed by the doping process, and the high concentration impurity region may be formed by the second doping process. Alternatively, the high-concentration impurity regions and the low-concentration impurity regions may be formed by one doping process by appropriately adjusting the thickness of the insulating film, the thickness of the first conductive layer, the doping conditions, and the like.

Next, a third etching process is performed without removing the resist mask. In the third etching treatment, the tapered portion of the first conductive layer is partially etched to reduce a region overlapping with the semiconductor layer. In the third etching process, CH gas is used as an etching gas.
This is performed using a reactive ion etching method (RIE method) using F ₃ . In this embodiment, the chamber pressure is 6.7P
a, RF power 800 W, CHF ₃ gas flow rate 35 sccm
A third etching process was performed. By the third etching, first conductive layers 138 to 141 are formed. (FIG. 8A) Note that the third etching process here is the fourth etching step described in Embodiment 1 (FIG. 2A).
(C)). Further, the width of the first conductive layer in the channel length direction here corresponds to W3 described in Embodiment 1.

At the time of the third etching process, the insulating film 117 is also etched at the same time, so that the high-concentration impurity region 130 is removed.
To 133 are exposed and the insulating films 143a to 143c,
144 are formed. In this embodiment, the etching conditions in which a part of the high-concentration impurity regions 130 to 133 are exposed are used. However, the present invention is not particularly limited. The insulating film may be left.

By the third etching, impurity regions (LDD regions) 134a to 137a which do not overlap with the first conductive layers 138 to 141 are formed. Note that the impurity regions (GOLD regions) 134b to 137b remain overlapped with the first conductive layers 138 to 141.

The electrode formed by the first conductive layer 138 and the second conductive layer 122b serves as a gate electrode of an n-channel TFT of a driving circuit formed in a later step, and the first conductive layer The electrode formed by the transistor 139 and the second conductive layer 123b serves as a gate electrode of a p-channel TFT of a driver circuit formed in a later step. Similarly, the first conductive layer 1
The electrode formed by the first conductive layer 141 and the second conductive layer 12b becomes a gate electrode of an n-channel TFT of a pixel portion formed in a later step.
5b becomes one electrode of the storage capacitor of the pixel portion formed in a later step.

In this manner, the present embodiment provides the first
Region (GOLD) overlapping conductive layers 138 to 141 of
Region) 134b to 137b and the first
Impurity regions that do not overlap with the conductive layers 138 to 141 (LD
The difference from the impurity concentration in the D regions 134a to 137a can be reduced, and the TFT characteristics can be improved.

Next, after removing the mask made of resist, masks 145 and 146 made of resist are newly formed, and a third doping process is performed. By the third doping process, the semiconductor layer serving as the active layer of the p-channel TFT has a conductivity type (p-type) opposite to the one conductivity type (n-type).
Region 14 to which an impurity element for imparting (type) is added
7 to 152 are formed. (FIG. 8B) First conductive layer 1
39 and 141 are used as masks for impurity elements,
An impurity element imparting p-type is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity regions 147 to
152 is formed by an ion doping method using diborane (B ₂ H ₆ ). In the third doping process,
The semiconductor layer forming the n-channel TFT is covered with resist masks 145 and 146. Phosphorus is added at different concentrations to the impurity regions 145 and 146 by the first doping process and the second doping process, and the concentration of the impurity element imparting p-type is 2 × in each of the regions. 10 ^{20 to} 2 × 10 ²¹ atom
By doping to s / cm ³ ,
There is no problem because it functions as the source and drain regions of the channel type TFT. In this embodiment,
Since the third etching treatment exposes a part of the semiconductor layer serving as the active layer of the p-channel TFT, there is an advantage that an impurity element (boron) can be easily added.

The third doping process may be performed once or a plurality of times. For example, when performing doping twice, the first doping condition is set to an acceleration voltage of 5 to 40 ke.
V, 147 and 150 are formed. The second doping condition is an acceleration voltage of 60 to 120 keV.
By forming 9, 151 and 152, implantation defects (defects due to ion doping or ion implantation) in the semiconductor film can be minimized. Further, if doping is performed a plurality of times as described above, the amount of boron element to be introduced into each of the source and drain regions 147 and the LDD regions 148 and 149 can be changed, so that the degree of freedom in design is improved.

Through the steps described above, desired impurity regions are formed in the respective semiconductor layers.

Next, a mask 145 made of resist is used.
146 is removed to form a first interlayer insulating film (a) 153a. The first interlayer insulating film (a) 153a is formed of an insulating film containing silicon with a thickness of 50 to 100 nm by using a plasma CVD method or a sputtering method. In this embodiment, the film thickness is 50 n by the plasma CVD method.
m of silicon oxynitride film was formed. Needless to say, the first interlayer insulating film (a) 153a is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, a step of activating the impurity element added to each semiconductor layer is performed. (FIG. 8
(C) This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, an oxygen concentration of 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to 55 ° C.
The activation may be performed at 0 ° C., and in this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the activation process, the impurity regions (130, 132, 147, and 147) containing high-concentration phosphorus containing nickel used as a catalyst during crystallization are used.
The nickel concentration in the semiconductor layer which is gettered 150) and mainly becomes a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Further, an activation process may be performed before forming the first interlayer insulating film 153. However, when the wiring material used is weak to heat, an interlayer insulating film (an insulating film containing silicon as a main component,
It is preferable to perform the activation process after forming the silicon nitride film).

As another activation treatment, a laser annealing method, for example, irradiation with a laser beam such as an excimer laser or a YAG laser can be performed.

Next, a first interlayer insulating film (b) 153b
To form The first interlayer insulating film (b) 153b is formed of an insulating film containing silicon with a thickness of 50 to 200 nm by using a plasma CVD method or a sputtering method. In this embodiment, a film thickness of 10
A 0-nm-thick silicon nitride film was formed. Needless to say, the first interlayer insulating film (b) 153b is not limited to the silicon nitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Next, 300 to 55 in an inert atmosphere.
A heat treatment is performed at 0 ° C. for 1 to 12 hours to hydrogenate the semiconductor layer. This hydrogenation is desirably at a temperature (400 to 500 ° C.) lower than the heat treatment temperature in the activation treatment. (FIG. 8D) In this example, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, 3
300 to 550 ° C in an atmosphere containing 100% to 100% hydrogen
And hydrogenation by heat treatment for 1 to 12 hours or plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Further, a mask 145, 1 made of resist is used.
After removing 46, thermal activation (typically at 500 to 550 ° C. in a nitrogen atmosphere) is performed to form a first interlayer insulating film (typically, having a thickness of 100 to 20) made of an insulating film containing silicon.
After forming a 0-nm-thick silicon nitride film), hydrogenation (at 300 to 500 ° C. in a nitrogen atmosphere) may be performed.

Next, a first interlayer insulating film (b) 153b
A second interlayer insulating film 154 made of an organic insulating material is formed thereon. In this embodiment, an acrylic resin film having a thickness of 1.6 μm was formed.

Next, a transparent conductive film is formed on the second interlayer insulating film 154 to a thickness of 80 to 120 nm, and is patterned to form a pixel electrode 162. The transparent conductive film is made of an indium zinc oxide alloy (In ₂ O ₃ —Zn
O) and zinc oxide (ZnO) are also suitable materials, and gallium (G) is used to further increase the transmittance and conductivity of visible light.
Zinc oxide (ZnO: Ga) to which a) is added can be suitably used.

Although an example in which a transparent conductive film is used as a pixel electrode is described here, a reflective display device can be manufactured by forming a pixel electrode using a conductive material having reflectivity. Can be.

Next, each of the impurity regions 130, 132, 1
Patterning for forming contact holes reaching 47 and 150 is performed.

Then, in the drive circuit 205, electrodes 155 to 161 electrically connected to the impurity regions 130 or 147 are formed. These electrodes are composed of a 50 nm thick Ti film and a 500 nm thick Ti film.
Is formed by patterning a laminated film of an alloy film (an alloy film of Al and Ti).

In the pixel portion 206, the connection electrode 160 in contact with the impurity region 132 or the source electrode 1
59, and the connection electrode 16 in contact with the impurity region 150 is formed.
Form one. Note that the connection electrode 160 is connected to the pixel electrode 16.
2 forms an electrical connection with the drain region of the pixel TFT, and further forms an electrical connection with the semiconductor layer (impurity region 150) functioning as one electrode forming a storage capacitor. Is done. (FIG. 9)

As described above, the n-channel type TFT 20
Drive circuit 20 having 1 and p-channel type TFT 202
5 and a pixel portion 206 having a pixel TFT 203 and a storage capacitor 204 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The n-channel TFT 20 of the drive circuit 205
Reference numeral 1 denotes a low-concentration impurity region 13 overlapping the channel formation region 163 and the first conductive layer 138 forming a part of the gate electrode.
4b (GOLD region), a low concentration impurity region 134a (LDD region) formed outside the gate electrode, and a high concentration impurity region 1 functioning as a source region or a drain region.
30. The p-channel type TFT 202 includes a channel forming region 164 and a first part forming a part of a gate electrode.
Impurity region 149 overlapping with the conductive layer 139, an impurity region 148 formed outside the gate electrode, and an impurity region 147 functioning as a source or drain region.

In the pixel TFT 203 of the pixel portion 206, the channel forming region 165 and the low concentration impurity region 136b (GOLD) overlapping the first conductive layer 140 forming the gate electrode are provided.
Region), a low-concentration impurity region 136a (LDD region) formed outside the gate electrode, and a high-concentration impurity region 132 functioning as a source or drain region. Each of the semiconductor layers 150 to 152 functioning as one electrode of the storage capacitor 204 is doped with an impurity element imparting p-type. The storage capacitor 204 includes the electrodes 125 and 141 and the semiconductor layers 150 to 152 and 166 using the insulating film 144 as a dielectric.

Further, according to the steps shown in this embodiment, the number of photomasks required for manufacturing the active matrix substrate can be six. As a result, the process is shortened,
This can contribute to reduction in manufacturing cost and improvement in yield.

[Embodiment 2] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below.
FIG. 10 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state shown in FIG. 9, an alignment film 167 is formed on the active matrix substrate shown in FIG. 9, and a rubbing process is performed. In this embodiment, before forming the alignment film 167,
An organic resin film such as an acrylic resin film was patterned to form columnar spacers at desired positions for maintaining a substrate interval. Also, instead of columnar spacers,
Spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 168 is prepared. The opposite substrate is provided with a color filter in which a coloring layer 174 and a light shielding layer 175 are arranged corresponding to each pixel.
Further, a light-blocking layer 177 was provided also in a portion of the driver circuit. A flattening film 176 covering the color filter and the light shielding layer 177
Was provided. Next, a counter electrode 169 made of a transparent conductive film was formed over the planarization film 176 in the pixel portion, an alignment film 170 was formed over the entire surface of the counter substrate, and rubbing treatment was performed.

The active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are sealed with a sealing material 171.
Paste in. A filler is mixed in the sealant 171, and the two substrates are bonded at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 173 is injected between the two substrates, and completely sealed with a sealing agent (not shown). As the liquid crystal material 173, a known liquid crystal material may be used. Thus, the active matrix liquid crystal display device shown in FIG. 10 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate and the like were appropriately provided using a known technique. Then, an FPC was attached using a known technique.

The configuration of the liquid crystal display panel thus obtained will be described with reference to the top view of FIG. Note that the same reference numerals are used for the portions corresponding to FIG.

A top view shown in FIG. 11A shows a pixel portion, a driving circuit, an FPC (Flexible Printed Wiring Board: Flexib
le Printed Circuit) external input terminal 20
7. an active matrix substrate on which wirings 208 connecting the external input terminals to the input portions of the respective circuits are formed;
An opposite substrate 168 provided with a color filter and the like is attached to each other with a sealant 171 interposed therebetween.

A light shielding layer 177a is provided on the counter substrate side so as to overlap with the gate wiring side driving circuit 205a, and a light shielding layer 177b is formed on the counter substrate side so as to overlap with the source wiring side driving circuit 205b. In the color filter 209 provided on the counter substrate side over the pixel portion 206, a light-shielding layer and colored layers of red (R), green (G), and blue (B) are provided for each pixel. Have been. When actually displaying, a red (R) colored layer, a green (G) colored layer,
A color display is formed by three colors of a blue (B) colored layer.
The arrangement of the colored layers of these colors is arbitrary.

[0138] Here, the color filter 209 is provided on the opposite substrate in order to achieve colorization. However, the present invention is not particularly limited. When an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.

Further, a light-shielding layer is provided between adjacent pixels in the color filter to shield portions other than the display area from light. Here, although the light-blocking layers 177a and 177b are provided also in a region covering the driving circuit, the region covering the driving circuit is covered with a cover when the liquid crystal display device is later incorporated as a display portion of an electronic device. A structure without a light-blocking layer may be employed. When an active matrix substrate is manufactured, a light-blocking layer may be formed on the active matrix substrate.

Further, without providing the above-mentioned light-shielding layer, a colored layer constituting a color filter is appropriately arranged between the opposing substrate and the opposing electrode so as to shield the light by a stacked layer of a plurality of layers, and the portion other than the display region ( The gap between each pixel electrode) and the driving circuit may be shielded from light.

Further, the base film 2 is connected to the external input terminal.
FPC made up of anisotropic conductive resin 2
12 are pasted together. Furthermore, the mechanical strength is enhanced by the reinforcing plate.

FIG. 11B is a sectional view taken along line EE ′ of the external input terminal 207 shown in FIG. 11A. Since the outer diameter of the conductive particles 214 is smaller than the pitch of the wiring 215, if the amount of dispersion in the adhesive 212 is made appropriate, the corresponding F can be formed without short-circuiting with the adjacent wiring.
An electrical connection can be formed with the wiring on the PC side.

The liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.

[Embodiment 3] In this embodiment, a method of manufacturing an active matrix substrate different from that in Embodiment 1 will be described with reference to FIGS.
This will be described with reference to FIG. In the first embodiment, a transmissive display device is formed. In the present embodiment, a reflective display device is formed.
The feature is that the number of masks is reduced as compared with the first embodiment.

The first embodiment differs from the first embodiment in that the second interlayer insulating film 15
Since the steps up to the step of forming No. 4 are the same, the description is omitted here. In FIG. 12, the same reference numerals are used for the same portions as in the first embodiment.

According to the first embodiment, after forming the second interlayer insulating film, patterning for forming contact holes reaching each impurity region is performed.

Next, in the drive circuit, as in the first embodiment, electrodes electrically connected to a part of the semiconductor layer (high-concentration impurity region) are formed. Note that these electrodes are formed by patterning a laminated film of a 50-nm-thick Ti film and a 500-nm-thick alloy film (an alloy film of Al and Ti).

In the pixel portion, a pixel electrode 1202 in contact with the high-concentration impurity region 1200 or a source electrode 1203 in contact with the high-concentration impurity region 1201 is formed. Note that the pixel electrode 1202 is electrically connected to the high-concentration impurity region 1200 of the pixel TFT, and is electrically connected to a semiconductor layer (high-concentration impurity region 1204) functioning as one electrode forming a storage capacitor. Is formed. (FIG. 12)

The material of the pixel electrode 1202 is as follows.
It is desirable to use a material having excellent reflectivity, such as a film containing Al or Ag as a main component or a stacked film thereof.

In addition, according to the steps described in this embodiment, the number of photomasks required for manufacturing an active matrix substrate can be reduced to five. As a result, the process is shortened,
This can contribute to reduction in manufacturing cost and improvement in yield.

After the formation of the pixel electrode, a known process such as a sandblasting method or an etching method is added to make the surface uneven, to prevent specular reflection and to scatter reflected light to increase whiteness. Is preferred. Also,
Before the pixel electrode is formed, the unevenness may be formed on the insulating film, and the pixel electrode may be formed thereon.

[Embodiment 4] In this embodiment, a process of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 3 will be described below. FIG. 13 is used for the description.

First, according to the third embodiment, after an active matrix substrate in the state shown in FIG. 12 is obtained, an alignment film is formed on at least the pixel electrode on the active matrix substrate shown in FIG. 12, and a rubbing process is performed. In this example, before forming the alignment film, a columnar spacer (not shown) for maintaining the substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 1304 is prepared. The opposite substrate is provided with a color filter in which a coloring layer and a light shielding layer are arranged corresponding to each pixel. Next, a flattening film that covers the color filters is formed.

Next, a counter electrode made of a transparent conductive film was formed on at least the pixel portion on the flattening film, an alignment film was formed on the entire surface of the counter substrate, and rubbing treatment was performed.

The pixel section 1301 and the driving circuit 130
The active matrix substrate 1303 on which the substrate 2 is formed and the opposing substrate 1304 are bonded with a sealant 1306.
A filler is mixed in the sealing material 1306.
Two substrates are bonded. Thereafter, a liquid crystal material 1305 is injected between the two substrates, and completely sealed with a sealant. As the liquid crystal material 1305, a known liquid crystal material may be used. Since the present embodiment is a reflection type, the distance between the substrates is about half as compared with the second embodiment. Thus, a reflective liquid crystal display device is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate 1307 was attached only to the counter substrate. Then, an FPC was attached using a known technique.

The reflection type liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.

Further, if the liquid crystal display panel alone is used in a dark place, there is a problem in visibility. Therefore,
It is desirable to have a configuration including a light source, a reflector, and a light guide plate as shown in FIG.

As the light source, one or more LEDs or cold cathode tubes may be used. As shown in FIG. 13, the light source is arranged along the side surface of the light guide plate, and a reflector is provided behind the light source.

When the light emitted from the light source efficiently enters the inside of the light guide plate from the side by the reflector, the light is reflected by a special prism processing surface provided on the surface, and enters the liquid crystal display panel.

By combining the liquid crystal display panel, the light source and the light guide plate in this manner, the light use efficiency can be improved.

[Embodiment 5] This embodiment shows an example of a manufacturing method different from that of Embodiment 1. This embodiment is different from the first embodiment only in the steps up to the formation of the semiconductor layers 102 to 105, and the subsequent steps are the same as the first embodiment.
Omitted.

First, a substrate is prepared as in the first embodiment.
In the case of manufacturing a transmissive display device, a glass substrate, a quartz substrate, or the like can be used as a substrate. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used. In the case of manufacturing a reflective display device, a reflective substrate in which an insulating film is formed over a surface of a ceramic substrate, a silicon substrate, a metal substrate, or a stainless steel substrate may be used.

Next, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film or a silicon oxynitride film is formed on the substrate. Although a two-layer structure is used as the base film in this embodiment, a single-layer film of the insulating film or a structure in which two or more insulating films are stacked may be used. In this embodiment, the first and second layers of the base film are continuously formed in a first film formation chamber by using a plasma CVD method. As the first layer of the base film, a silicon oxynitride film formed by using a plasma CVD method with SiH ₄ , NH ₃ , and N ₂ O as a reaction gas is 10-2.
A thickness of 00 nm (preferably 50 to 100 nm) is formed. In this embodiment, a 50 nm-thick silicon oxynitride film (composition ratio S
i = 32%, O = 27%, N = 24%, H = 17%). Next, as a second layer of the base film, a silicon oxynitride film to be formed with a thickness of 50 to 200 nm (preferably 100 to 150 nm) by using a plasma CVD method with SiH ₄ and N ₂ O as a reaction gas. To form a laminate. In this embodiment, a 100-nm-thick silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%)
Was formed.

Next, an amorphous semiconductor film is formed on the base film in the second film forming chamber. The amorphous semiconductor film has a thickness of 30 to 60.
It is formed with a thickness of nm. Although there is no limitation on the material of the amorphous semiconductor film, it is preferable to use silicon or a silicon-germanium alloy. In this embodiment, an amorphous silicon film is formed by a plasma CVD method using SiH ₄ gas.

Since the base film and the amorphous semiconductor film can be formed by the same film formation method, the base film and the amorphous semiconductor film can be formed continuously.

Next, Ni is added to the amorphous silicon film in the third film forming chamber. Using a plasma CVD method, an electrode containing Ni as a material is attached, argon gas or the like is introduced, plasma is generated, and Ni is added. Of course, an ultra-thin Ni film may be formed using a vapor deposition method or a sputtering method.

Next, a protective film is formed in the fourth film forming chamber. As the protective film, a silicon oxide film, a silicon oxynitride film, or the like is preferably used. It is better not to use a dense film such as a silicon nitride film because dehydrogenation in a later step is difficult to remove hydrogen. In this embodiment, the plasma C
Using the VD method, TEOS (Tetraethyl Orthosilicat
e) and O ₂ are mixed to form a silicon oxide film having a thickness of 100 to 150 nm. The present embodiment is characterized in that the process up to the formation of a silicon oxide film as a protective film is continuously performed without exposing the silicon oxide film to a clean room atmosphere.

The films formed in each of the above film forming chambers are:
Any known forming means such as a plasma CVD method, a thermal CVD method, a reduced pressure CVD method, an evaporation method, a sputtering method, and the like can be used.

Next, dehydrogenation of the amorphous silicon film (5
(At 00 ° C. for 1 hour) and thermal crystallization (at 550 ° C. for 4 hours). Note that the method is not limited to the method of adding a catalyst element such as Ni shown in this embodiment, and thermal crystallization may be performed by a known method.

Then, in order to control the threshold value (Vth) of the n-channel TFT, an impurity element imparting p-type is added. As the impurity element imparting p-type to the semiconductor, an element belonging to Group 13 of the periodic rule such as boron (B), aluminum (Al), and gallium (Ga) is known. In this embodiment, boron (B) is added.

After the addition of boron, the silicon oxide film serving as the protective film is removed using an etching solution such as hydrofluoric acid. Next, continuous processing of cleaning and laser annealing is performed. By adding boron (B), which is an impurity element imparting p-type, to the amorphous semiconductor film and then performing laser annealing, the boron also becomes part of the crystal structure of the crystalline semiconductor film and is crystallized. To do so, it is possible to prevent the destruction of the crystal structure that occurs in the prior art.

Here, by using pure water containing ozone and an acidic solution containing fluorine, an ultra-thin oxide film formed when washing with pure water containing ozone can be obtained. Contaminant impurities adhering to the coating surface can be removed. As a method for producing pure water containing ozone, there are a method of electrolyzing pure water and a method of directly dissolving ozone gas in pure water. The ozone concentration is 6
It is preferable to use it at mg / L or more. It should be noted that optimum conditions for the number of rotations and time of the spin device may be appropriately determined according to the substrate area, the coating material, and the like.

For the laser annealing, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The conditions for crystallization by laser annealing may be appropriately selected by the practitioner.

The crystalline semiconductor film obtained in this manner is patterned into a desired shape to form island-like semiconductor layers 102 to 10.
5 is formed.

In the following steps, according to the first embodiment, FIG.
Can be formed.

This embodiment can be freely combined with any one of Embodiments 1 to 4.

[Embodiment 6] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described. FIG. 14 is a sectional view of the EL display device of the present invention.

In FIG. 14, the switching TFT 603 provided on the substrate 700 is an n-channel type TF shown in FIG.
It is formed using T203. Therefore, the description of the structure is n
The description of the channel type TFT 203 may be referred to.

Although the embodiment has a double gate structure in which two channel formation regions are formed, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. good.

The driving circuit provided on the substrate 700 is shown in FIG.
Is formed using a CMOS circuit. Therefore, the description of the structure is made of the n-channel TFT 201 and the p-channel TFT 2
02 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

Further, wirings 701 and 703 are a source wiring of the CMOS circuit, 702 is a drain wiring, 704 is a source wiring for electrically connecting the source region of the switching TFT, and 705 is a wiring for the drain region of the switching TFT. Functions as a drain wiring to be connected.

The current control TFT 604 is formed using the p-channel TFT 202 shown in FIG. Therefore, for the description of the structure, the description of the p-channel TFT 202 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

A wiring 706 is a source wiring of the current control TFT (corresponding to a current supply line), and 707 is an electrode which is electrically connected to the pixel electrode 710 by being superposed on the pixel electrode 710 of the current control TFT. is there.

Incidentally, reference numeral 710 denotes a pixel electrode (anode of an EL element) made of a transparent conductive film. As a transparent conductive film,
A compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used. The pixel electrode 710 has a flat interlayer insulating film 7 before forming the wiring.
11 is formed. In this embodiment, it is very important to flatten the step due to the TFT using the flattening film 711 made of resin. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG. Bank 712 is 10
The insulating film or the organic resin film containing silicon having a thickness of 0 to 400 nm may be formed by patterning.

Note that since the bank 712 is an insulating film,
Attention must be paid to electrostatic breakdown of the element during film formation.
In this embodiment, the resistivity is reduced by adding carbon particles or metal particles to the insulating film used as the material of the bank 712 to suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of the carbon particles and metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

On the pixel electrode 710, an EL layer 713 is formed. Although only one pixel is shown in FIG. 14, in this embodiment, EL layers corresponding to R (red), G (green), and B (blue) are separately formed. In this embodiment, a low-molecular organic EL material is formed by an evaporation method.
Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a light emitting layer is formed on the copper phthalocyanine film.
It has a laminated structure in which a 0 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

However, the above example is an example of the organic EL material that can be used for the EL layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, a low molecular organic EL material is
Although an example in which the layer is used as a layer has been described, a polymer organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials. Further, as the EL layer, a thin film made of a light-emitting material (singlet compound) that emits light (fluorescence) by singlet excitation or a thin film made of a light-emitting material that emits light (phosphorescence) by triplet excitation can be used.

Next, a cathode 714 made of a conductive film is provided on the EL layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (an alloy film of magnesium and silver)
May be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

When the cathode 714 is formed, the EL
The element 715 is completed. Note that the EL element 71 here
Reference numeral 5 denotes a capacitor formed by the pixel electrode (anode) 710, the EL layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the EL element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used in a single layer or in a stacked layer.

At this time, a film having good coverage is preferably used as a passivation film, and a carbon film, particularly
It is effective to use an LC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or lower, it can be easily formed above the EL layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen, and the EL layer 713
Can be suppressed. Therefore, the problem that the EL layer 713 is oxidized during the subsequent sealing step can be prevented.

Further, a sealing material 717 is provided on the passivation film 716, and a cover material 718 is attached. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, a cover material 718 having a carbon film (preferably a diamond-like carbon film) formed on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) is used.

Thus, an EL display device having a structure as shown in FIG. 14 is completed. After forming the bank 712,
It is effective to continuously process the steps up to the formation of the passivation film 716 without exposing to the atmosphere using a multi-chamber type (or in-line type) film forming apparatus. Further, by further developing, it is also possible to continuously perform processing up to the step of bonding the cover material 718 without releasing to the atmosphere.

In this manner, the n-channel TFTs 601 and 602 are placed on the insulator 501 whose base is a plastic substrate.
A switching TFT (n-channel TFT) 603 and a current control TFT (n-channel TFT) 604 are formed. The number of masks required in the manufacturing process up to this point is
The number is smaller than that of a general active matrix type EL display device.

That is, the manufacturing process of the TFT is greatly simplified, and an improvement in yield and a reduction in manufacturing cost can be realized.

Further, as described with reference to FIG. 9, by providing an impurity region overlapping the gate electrode with an insulating film interposed therebetween, it is possible to form an n-channel TFT which is resistant to deterioration due to the hot carrier effect. Therefore, a highly reliable EL display device can be realized.

In this embodiment, only the configuration of the pixel portion and the driving circuit is shown. However, according to the manufacturing process of this embodiment, other components such as a signal dividing circuit, a D / A converter, an operational amplifier, a gamma correction circuit, and the like can be used. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, an EL light emitting device of this embodiment after performing a sealing (or enclosing) step for protecting the EL element will be described with reference to FIG. Note that the reference numerals used in FIG.

FIG. 15A is a top view showing a state in which the process up to sealing of the EL element has been performed, and FIG. 15B is a cross-sectional view taken along line AA ′ of FIG. 80 shown by dotted line
Reference numeral 1 denotes a source side driving circuit, 806 denotes a pixel portion, and 807 denotes a gate side driving circuit. Reference numeral 901 denotes a cover material;
Denotes a first sealant, 903 denotes a second sealant, and a sealant 907 is provided inside the first sealant 902.

Reference numeral 904 denotes wiring for transmitting signals input to the source-side drive circuit 801 and the gate-side drive circuit 807, and a video signal or a clock signal from an FPC (flexible print circuit) 905 serving as an external input terminal. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached. The EL display device in this specification includes not only the EL display device main body but also a state in which an FPC or a PWB is attached thereto.

Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate driver circuit 807 are formed above the substrate 700.
Is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 710 electrically connected to its drain. The gate side drive circuit 807 is an n-channel type TF
It is formed using a CMOS circuit (see FIG. 9) in which T601 and p-channel TFT 602 are combined.

The pixel electrode 710 functions as an anode of the EL element. Further, banks 712 are provided at both ends of the pixel electrode 710.
Are formed, and an EL layer 713 and a cathode 714 of an EL element are formed on the pixel electrode 710.

The cathode 714 also functions as a wiring common to all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, all elements included in the pixel portion 806 and the gate driver circuit 807 are covered with the cathode 714 and the passivation film 567.

The cover member 901 is attached by the first seal member 902. Note that a spacer made of a resin film may be provided to secure an interval between the cover member 901 and the EL element. The inside of the first sealant 902 is filled with a sealant 907. Note that an epoxy resin is preferably used for the first sealant 902 and the sealant 907. Further, it is desirable that the first sealant 902 be a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a moisture absorbing effect or a substance having an antioxidant effect may be contained in the sealing material 907.

[0207] The sealing material 907 provided so as to cover the EL element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (FRP) is used as the material of the plastic substrate 901a constituting the cover member 901.
iberglass-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester or acrylic can be used.

[0208] Further, the cover material 90 is formed by using the sealing material 907.
After bonding, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. Second sealing material 90
For 3, the same material as the first sealant 902 can be used.

With the above structure, the EL element is sealed with the sealing material 90.
By encapsulating the EL element in the EL element, the EL element can be completely shut off from the outside, and it is possible to prevent a substance such as moisture or oxygen, which promotes the deterioration of the EL layer from being oxidized, from entering from the outside. Therefore, a highly reliable EL display device can be obtained.

[Embodiment 7] TFTs formed by carrying out any one of Embodiments 1 to 6 can be used in various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC). Display). That is,
The present invention can be applied to all electronic apparatuses in which such an electro-optical device is incorporated in a display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector, a head-mounted display (goggle type display), a car navigation, a car stereo, a personal computer, and a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.). ). One example of them is shown in FIG.
FIG. 17 and FIG.

FIG. 16A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 16B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102.

FIG. 16C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 16D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302.

FIG. 16E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 16F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502.

FIG. 17A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other driving circuits.

FIG. 17B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to a liquid crystal display device 2808 forming a part of the LCD 702 and other driving circuits.

FIG. 17C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 17A and 17B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In this embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 17D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 17C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 17D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 17, a case where a transmission type electro-optical device is used is shown, and examples of application to a reflection type electro-optical device and an EL display device are not shown.

FIG. 18A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904.

FIG. 18B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003.

FIG. 18C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. FIG.
The display shown in FIG. 8 (C) is of a small, medium or large size, for example, a screen size of 5 to 20 inches.
Also, in order to form a display unit of such a size,
It is preferable to use a substrate having a side of 1 m and mass-produce it by performing multiple-paneling.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 6.

[0227]

According to the present invention, the width of the low concentration impurity region (GOLD region) overlapping the gate electrode under the fourth etching condition and the width of the low concentration impurity region (LDD region) not overlapping the gate electrode can be freely set. Can be adjusted. Further, there is almost no difference in concentration between the GOLD region and the LDD region of the TFT formed according to the present invention. Therefore, in the GOLD region overlapping with the gate electrode, relaxation of electric field concentration is achieved, which can be prevented by hot carriers, and in the LDD region not overlapping with the gate electrode, an off-current value can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a TFT. (Embodiment 1)

FIG. 2 is a diagram illustrating a manufacturing process of a TFT. (Embodiment 1)

FIG. 3 is a curve showing a concentration distribution of an impurity element.
(Embodiment 1)

FIG. 4 is a diagram showing a manufacturing process of a TFT. (Embodiment 2)

FIG. 5 is a diagram showing a manufacturing process of a TFT. (Embodiment 2)

FIG. 6 is a diagram showing a manufacturing process of a TFT. (Embodiment 3)

FIG. 7 is a view showing a process of manufacturing an AM-LCD.
(Example 1)

FIG. 8 is a diagram showing a manufacturing process of an AM-LCD.
(Example 1)

FIG. 9 is a view showing a process of manufacturing an AM-LCD.
(Example 1)

FIG. 10 is a sectional structural view of a transmission type liquid crystal display device.
(Example 1)

FIG. 11 is an external view of a liquid crystal display panel. (Example 2)

FIG. 12 is a sectional structural view of a reflective liquid crystal display device.
(Example 3)

FIG. 13 is a sectional structural view of a reflective liquid crystal display panel provided with a light source. (Example 4)

FIG. 14 illustrates a structure of an active matrix EL display device.

FIG. 15 illustrates a structure of an active matrix EL display device.

FIG. 16 illustrates an example of an electronic device.

FIG. 17 illustrates an example of an electronic device.

FIG. 18 illustrates an example of an electronic device.

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Toru Takayama 398 Hase, Hase, Atsugi-shi, Kanagawa Prefecture Inside the Semi-Conductor Energy Laboratory Co., Ltd. F-term (reference) 2H092 JA25 JA34 JA38 JA41 JB22 JB31 JB57 KB25 MA14 MA15 MA18 MA26 MA27 NA27 NA29 4M104 AA09 BB01 BB02 BB04 BB14 BB16 BB17 BB18 BB30 BB32 BB40 CC05 DD37 DD65 DD67 FF08 AFF DDB DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE06 EE09 EE14 EE23 EE28 EE44 EE45 FF02 FF04 FF09 FF12 FF28 FF30 FF35 FF36 GG01 GG02 GG13 NN25 HG43 GG45 NN73 PP01 PP03 PP06 PP10 PP29 PP34 PP35 QQ04 QQ09 QQ11 QQ23 QQ24 QQ25 QQ28

Claims (12)

[Claims] A first step of forming a semiconductor layer on an insulating surface; a second step of forming an insulating film on the semiconductor layer; and a first step having a first width on the insulating film. Forming a first electrode composed of a laminate of a conductive layer of
And etching the second conductive layer to form a second electrode comprising a stack of a first conductive layer having the first width and a second conductive layer having a second width. A fourth step of forming; a fifth step of forming a high-concentration impurity region by adding an impurity element to the semiconductor layer using the second electrode as a mask; and using the second conductive layer as a mask, A sixth step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer by passing through the first conductive layer, and etching the first conductive layer to have a third width. A method for manufacturing a semiconductor device, comprising: a seventh step of forming a third electrode formed by stacking a first conductive layer and a second conductive layer having the second width. 2. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first step having a first width on the insulating film. Forming a first electrode composed of a laminate of a conductive layer of
And etching the second conductive layer to form a second electrode comprising a stack of a first conductive layer having the first width and a second conductive layer having a second width. A fourth step of forming; a fifth step of forming a high concentration impurity region and a low concentration impurity region by adding an impurity element to the semiconductor layer using the second conductive layer as a mask; A sixth step of etching the conductive layer to form a third electrode formed by stacking a first conductive layer having a third width and a second conductive layer having the second width; A method for manufacturing a semiconductor device having: 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second width is smaller than the first width. 4. The method according to claim 1, wherein the third width is smaller than the first width and the second width is smaller than the first width.
A method for manufacturing a semiconductor device, wherein the width is wider than the width of the semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity element is an impurity element that imparts n-type or p-type to a semiconductor. 6. The semiconductor device according to claim 1, wherein the third step includes forming a first conductive film and a second conductive film on the insulating film.
After laminating the conductive film, a first etching process is performed on the second conductive film to form a second conductive layer, and a second etching process is performed on the first conductive film. A first conductive layer having a first width and a second conductive layer having a first width.
A method for manufacturing a semiconductor device, comprising forming a first electrode formed of a laminate with a conductive layer. 7. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first conductive film and a second conductive film on the insulating film. A third step of stacking and forming a conductive film, a fourth step of forming a second conductive layer having a first width, and the semiconductor using the second conductive layer having the first width as a mask. A fifth step of forming a high-concentration impurity region by adding an impurity element to the layer; a first conductive layer having the second width by etching the first conductive film; and a third width. A sixth step of forming a first electrode made of a laminate with a second conductive layer having: a first conductive layer having the second width by etching the second conductive layer; A seventh step of forming a second electrode made of a laminate with a second conductive layer having a fourth width, and a step of forming a second electrode having a fourth width. An eighth step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer by passing the first conductive layer using the second conductive layer as a mask; and etching the first conductive layer. A ninth step of forming a third electrode formed by stacking a first conductive layer having a fifth width and a second conductive layer having the fourth width. Production method. 8. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first step having a first width on the insulating film. Forming a first electrode composed of a laminate of a conductive layer of
And etching the second conductive layer to form a second electrode comprising a stack of a first conductive layer having the first width and a second conductive layer having a second width. A fourth step of forming; a fifth step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer by passing through the first conductive layer using the second conductive layer as a mask; A sixth step of forming a high-concentration impurity region by adding an impurity element to the semiconductor layer using the second electrode as a mask; and etching the first conductive layer to have a third width. A method for manufacturing a semiconductor device, comprising: a seventh step of forming a third electrode formed by stacking a first conductive layer and a second conductive layer having the second width. 9. A step of forming a first interlayer insulating film covering the third electrode after the step of forming the third electrode according to claim 1; Performing a first heat treatment for activating an impurity element in the semiconductor layer, forming a second interlayer insulating film covering the first interlayer insulating film, and forming the second interlayer insulating film. And thereafter performing a second heat treatment at a temperature lower than the first heat treatment. 10. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first conductive film and a second conductive film on the insulating film. A third step of stacking and forming a conductive film, a fourth step of forming a second conductive layer having a first width, and the semiconductor using the second conductive layer having the first width as a mask. A fifth step of forming a high-concentration impurity region by adding an impurity element to the layer; and a sixth step of etching the second conductive layer to form a second conductive layer having the second width. A step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer by passing the first conductive film using the second conductive layer having the second width as a mask, Etching the first conductive film to form a first conductive layer having a third width; An eighth step of forming an electrode composed of a laminate with a second conductive layer having a width. 11. A ninth step of forming a first interlayer insulating film covering the third electrode after the eighth step described in claim 10, and activating an impurity element in the semiconductor layer. A tenth step of performing a first heat treatment, and an eleventh step of forming a second interlayer insulating film covering the first interlayer insulating film.
A twelfth step of performing a second heat treatment at a lower temperature than the first heat treatment. 12. The semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera,
Projectors, goggle-type displays, car navigation, personal computers, portable information terminals,
A method for manufacturing a semiconductor device, which is a digital video disk player or an electronic game machine.