JP2002118074A - Method of forming semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problems of crystallinity not recovering and not yielding efficient activation of an impurity element, even though heat treatment is applied to a semiconductor film, to which the impurity element has been doped. SOLUTION: When doping an impurity element is doped to a semiconductor film is made at a temperature of 200 deg.C or lower, by doping the impurity element at a low temperature, and amorphous state can be created with a small amount of the impurity element. By applying a heat treatment thereafter, recovery of the crystallinity and activation of the impurity element can be efficiently performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, the present invention relates to an electro-optical device represented by a liquid crystal display device and a configuration of an electric device including the electro-optical device as a component. Further, the present invention relates to a method for manufacturing the device. Note that in this specification, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics, and the above-described electro-optical device and electric device are also included in the category.

[0002]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

A TFT using a crystalline semiconductor film (typically, polysilicon or the like) as a semiconductor layer has a higher mobility than an amorphous semiconductor film (typically, amorphous silicon or the like), and is therefore popular. It has been used for.

Generally, in an IC manufacturing process, impurity ions are selectively added using an ion implantation apparatus or an ion doping apparatus. Specifically, when an n-type or p-type impurity region is formed in a semiconductor layer, an impurity ion which gives an n-type impurity element or a p-type impurity element is added. This ion implantation apparatus accelerates the electric field of impurity ions, performs mass separation, and adds only the target ion species, and is characterized by high accuracy, but has low throughput and is very expensive. Device. The ion implantation apparatus is not particularly suitable for mass production of an active matrix display device for processing a large substrate. Therefore, for mass production of active matrix display devices that process large substrates, an ion doping device that adds impurity ions to a large-area semiconductor thin film at a time is used.

In this ion doping apparatus, a source gas is flowed into a chamber, the source gas is turned into plasma by a known method, and the impurity ions contained therein are ionized and added to the crystalline semiconductor film. Since mass separation is not performed, ions other than the target ion species are added, but the throughput is excellent.

[0006] In the doping process performed using such a doping apparatus, the energy of ions implanted into the semiconductor layer is much larger than the binding energy of elements forming the semiconductor layer. Therefore, the ions implanted into the semiconductor layer repel the elements forming the semiconductor film from the lattice points, causing defects in the crystal. Therefore, after the doping process, in order to recover the defect and activate the implanted ions at the same time,
Heat treatment is often performed. Activating ions is an important process for making a region to which ions are added a low-resistance region to function as a source region and a drain region.

Also, "S. Wolf and RN Tauber: Sil
icon Processing for the VLSI EraVolume 1-Process T
echnology., p. 303, describes the critical dose for amorphizing a semiconductor film with respect to the temperature at the time of adding an impurity element. Here, it is described that the semiconductor film is more likely to be amorphous when the doping process is performed at a low temperature than at a high temperature. It is also described that performing at a high temperature increases the amount of an impurity element required to make the amorphous state higher than performing at a low temperature.

[0008] Also, "JPN. J. Appl. Phys. Vol. 74, N
o.12., p. 7114-7117 (1993), shows a concentration profile in the depth direction of the semiconductor film when phosphorus is added to the semiconductor film at room temperature and 300 ° C. It is described that the shape of the concentration profile of the impurity element added to the semiconductor film changes depending on the temperature at the time of addition, and that the addition at a low temperature is more performed near the surface of the film.

[0009]

SUMMARY OF THE INVENTION An n-channel TFT
And in the step of adding an impurity element to the semiconductor layer of the p-channel TFT, when adding an impurity element imparting n-type to the semiconductor layer for manufacturing the n-channel TFT,
A mask is provided for a semiconductor layer for forming a channel TFT, and a mask is provided for a semiconductor layer for forming an n-channel TFT when an impurity element imparting p-type is added when a p-channel TFT is manufactured. I was

However, in order to reduce the number of steps, when an impurity element imparting n-type is added to a semiconductor layer for forming an n-channel TFT, doping is performed without providing a mask in the semiconductor layer for forming a p-channel TFT. Processing may be performed. This is because, when an impurity element imparting p-type is added, an amount sufficient to cancel out the impurity element imparting n-type is added to function as a p-channel TFT. However, the semiconductor layer of the p-channel TFT manufactured in this way has severe defects due to the addition of an impurity element, and it has been difficult to recover the crystallinity and activate the impurity element even when heat treatment is performed.

The present invention is a technique for solving such a problem, and is an electro-optical device and a semiconductor device typified by an active matrix type liquid crystal display device manufactured by using a TFT, in which activation efficiency is improved. In order to improve the operating characteristics and reliability of a semiconductor device, it is an object of the present invention to improve the operating characteristics and reliability of a semiconductor device.

[0012]

Therefore, the present inventor first conducted an experiment for studying a method of efficiently activating. The outline of the experiment will be described. 1737 as substrate
A substrate is prepared, and two layers of a silicon oxynitride film 50 nm and a silicon nitride oxide film 50 nm are stacked as a base film on the substrate,
An amorphous silicon film having a thickness of 54 nm was formed on the base film. To crystallize the amorphous silicon film, an aqueous solution of nickel acetate having a concentration of 10 ppm by weight is applied to the amorphous silicon film,
The substrate was heated at a temperature of 550 ° C. for 4 hours in a nitrogen atmosphere to form a crystalline silicon film, and crystallization was performed using a XeCl excimer laser. Subsequently, patterning is performed to form an island-shaped semiconductor film, and after forming a silicon oxide film 90 nm, phosphorus (P) is selectively added to the island-shaped semiconductor film, and the temperature is set to 550 ° C. in a nitrogen atmosphere for 4 hours. Was performed. This heat treatment activates phosphorus.
In this specification, the composition ratio of Si = 32% and O = 27
%, N = 24%, and H = 17% are silicon oxynitride films, with composition ratios of Si = 32%, O = 59%, N = 7%, and H =
A 2% film is a silicon nitride oxide film.

In this experiment, a silicon film was used as a semiconductor film, nickel was used as a metal element, and phosphorus was used as an impurity element. However, the metal element and the impurity element are not limited to these. For example, as a semiconductor film, there is an amorphous semiconductor film, a microcrystalline semiconductor film, or the like; a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used; The impurity element imparting n-type, the impurity element imparting p-type, and both the impurity element imparting n-type and the impurity element imparting p-type may be applied.

The conditions for adding phosphorus are as follows: a 5% hydrogen-diluted PH ₃ gas is used; a gas flow rate is 40 sccm; an acceleration voltage is 80 kV; a dose is 7.8 × 10 ¹⁵ / cm ² ; 1 μA / cm ² , 3 μA / cm ² , 5 μA
/ Cm ² and three conditions. FIG. 1 shows the relationship between the current density and the maximum temperature of the substrate at the time of addition. From FIG. 1, it is clear that lowering the current density also lowers the maximum temperature of the substrate at the time of addition, and changing the condition of the current density means changing the temperature condition of the substrate during processing. When the current density is 5 μA / cm ² , not only the entire dose is added at one time, but also a single dose is 1.3 × 10 ¹⁵ / cm 2.
² and divided into 6 portions, and the total dose is 7.8 ×
Addition of 10 ¹⁵ / cm ² was also performed. At this time, the maximum temperature of the substrate at the time of addition was also measured using a thermo label.

Since the color of the thermo label changes when it reaches a certain temperature, it can be determined whether or not the temperature has reached the temperature. Of course, the thermolabel used was irreversible. The temperature range that can be measured by the thermolabel used this time is 120 to 300 ° C, and measurement can be performed every 10 ° C. However, if the thermolabel was attached to the front surface of the substrate, an impurity element was also added to the thermolabel, making it impossible to measure the temperature correctly.

As a result of measuring the substrate temperature, the current density was 5 μm.
At A / cm ² , the maximum temperature when the addition was performed at one time was 280 ° C. In addition, the maximum temperature in the case of divided addition was 120 ° C., and the label color did not change.
Although it was confirmed that the temperature was 20 ° C. or less, accurate measurement was impossible. However, it can be seen that the temperature at the time of addition is clearly lower when added in portions than when added at once.
However, in the case of divisional addition, after each addition, the addition was performed again after waiting for the substrate to cool to room temperature.

The sheet resistance of the sample thus prepared was measured after adding phosphorus and after heat treatment. The result is shown in FIG. 2, the lower the current density is, the lower the sheet resistance value after the heat treatment is. this is,
The lower the current density, the better the activation. In addition, when divided and added, the resistance is highest after phosphorus addition, but is lowest after heat treatment. This indicates that the activation of the impurity element was performed best.

As described above, it has been found that when the doping process is performed at a low temperature, the activation of the impurity element is also favorably performed. The present inventors have noted that the crystallinity of the semiconductor film and the concentration profile of the added impurity element differ depending on the temperature of the substrate during the doping process. It was considered that the crystallinity and the concentration profile under conditions suitable for the formation were formed.

First, in order to check the crystallinity of the semiconductor film, the Raman spectrum of the semiconductor film after phosphorus addition and after the heat treatment was measured. The result is shown in FIG.
The Raman spectrum for a silicon film is 520.6 / cm
It is known that the higher the peak value is, the better the crystallinity is, and the lower the peak value is, the more the amorphous state is. From FIG. 3 (A),
It can be seen that the lower the current density, that is, the lower the temperature of the substrate during the doping process, the lower the peak value and the substrate is in an amorphous state. In addition, the peak value is lowest after the addition of phosphorus when divided and added. On the other hand, when the heat treatment was performed, the crystallinity was improved to the same degree under any condition (FIG. 3).
(B)).

Thus, from the results of the Raman spectrum measurement, a correlation was found between the crystal state after phosphorus addition and the activation efficiency, and it was found that the activation efficiency was higher in the amorphous state. It is generally known that the lower the temperature during the doping process, the more likely it is to become amorphous.
N. Tauber: Silicon Processing for the VLSI Era Vo
lume 1-Process Technology., p. 303 ".

Next, the fact that the concentration profile differs depending on the temperature during the doping process will be described. The fact that the concentration profile differs depending on the temperature during the doping process is referred to as “High Temperature Implantation of Polycrystal
line Silicon by Ion ShowerDoping ". It has been reported that the shape of the concentration profile of the impurity element added to the semiconductor film changes depending on the temperature during the doping process, and that the addition at a low temperature results in more addition near the surface of the film. In other words, the lower the temperature at the time of the doping treatment, the more the effective amount added to the semiconductor film increases, so that the impurity element can be effectively used.

As described above, the present invention is characterized in that a doping process is performed at a low substrate temperature in order to efficiently activate an impurity element. In the present specification, the low temperature is 200 ° C. or less from FIGS. From the above experiment, as a method for adding at a low temperature, there is a method of adding at a low current density, a method of adding in a divided manner, and the like. By performing the doping treatment at a low temperature, the amount of the impurity element added can be reduced. That is, by applying the present invention, the amount of the impurity element added can be reduced, crystal defects can be suppressed, and the recovery of crystallinity and the activation of the impurity element can be easily performed by heat treatment after the doping treatment. can do.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the sectional view of FIG.

In FIG. 4A, a glass substrate such as a non-alkali glass such as a synthetic quartz glass substrate, barium borosilicate glass, or aluminoborosilicate glass may be used as the substrate 10. For example, Corning 705
Nine glass, 1737 glass, or the like can be preferably used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

A base insulating film 11 is formed of a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or the like on the substrate 10 by a known means (LPCVD, plasma CVD, or the like).

Next, a semiconductor film is formed to a thickness of 10 to 200 nm (preferably 30 to 100 nm) by a known means such as a plasma CVD method or a sputtering method. Examples of the semiconductor film 12 include an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. Then, a known crystallization treatment (laser crystallization, thermal crystallization, thermal crystallization using a catalyst such as nickel, or a combination thereof) is performed. As thermal crystallization methods, thermal annealing using a furnace annealing furnace, laser annealing method, or rapid thermal annealing method (RTA
Law) can be applied.

The crystalline semiconductor film thus obtained is patterned into a desired shape to form semiconductor layers 14 and 15. Here, it is assumed that the semiconductor layer 14 is an n-channel TFT and the semiconductor layer 15 is a p-channel TFT.

Next, a gate insulating film 16 covering the semiconductor layers 14 and 15 is formed. The gate insulating film 16 is made of plasma C
Using the VD method or the sputtering method, the thickness is 40 to 150 n
m is formed of an insulating film containing silicon. Needless to say, the gate insulating film may have a single-layer structure or a stacked structure.

Next, as shown in FIG. 4A, a conductive film 17 having a thickness of 100 to 500 nm is formed on the gate insulating film 16. Ta, W, Ti, Mo, C
It may be formed of an element selected from u, Cr, and Nd, an alloy material or a compound material containing the element as a main component, or a semiconductor film typified by a crystalline silicon film. Further, an AgPdCu alloy may be used. In addition, an oxide conductive film transparent to visible light (typically, ITO
Film).

Next, a mask (not shown) made of a resist is formed by photolithography, and an etching process for forming electrodes and wirings is performed to form conductive layers 18 and 19.

Next, using the conductive layers 18 and 19 as a mask, the gate insulating film 16 is selectively removed to form the insulating layer 2.
0 and 21 are formed. (FIG. 4 (B))

Then, a first doping process is performed,
An impurity element is added to the semiconductor layer. (Fig. 4B)
Ping treatment is done by ion doping method or ion implantation method.
Just do it. The condition of the ion doping method is that the dose amount is 1 ×
10¹³~ 5 × 10^Fifteen/ Cm ^TwoAnd the accelerating voltage is 5 to 10
0 kV, the temperature of the substrate during the doping process becomes low
Low current density or dose to add
Perform Further, as an impurity element imparting n-type, 15
Group elements, typically phosphorus (P) or arsenic (A
s) is used. The first doping process comprises the steps of:
19 is a mask for the impurity element, and is self-aligned.
Impurity regions 22 to 25 are formed, and impurity regions 22 to 2 are formed.
5 phosphorus concentration 1 × 10¹⁸~ 1 × 10^{twenty one}/ Cm^Threebecome
To be added. In this embodiment, the active layer of the TFT serves as an active layer.
Since part of the semiconductor layer is exposed,
It has the advantage of being easy to add.

Subsequently, by the second doping process, p
Impurity regions 29 and 30 to which an impurity element imparting a conductivity type opposite to the one conductivity type is added are formed in a semiconductor layer serving as an active layer of the channel type TFT. Also in the second doping process, it is desirable to add the low current density or the dose separately in such a manner that the temperature of the substrate during the doping process becomes low. Using the conductive layer 19 as a mask for the impurity element, an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. (FIG. 4C) In the second doping process, the semiconductor layer forming the n-channel TFT is covered with a mask 28 made of resist. Although phosphorus is added to the impurity regions 29 and 30 by the first doping process, the concentration of the impurity element imparting p-type is set to 1 × 10 ^{19 to} 5 × 10 ²¹ / cm ^3.
By performing the doping process so as to function as described above, no problem occurs because the p-channel TFT functions as a source region and a drain region. In the present embodiment, since a part of the semiconductor layer serving as the active layer of the p-channel TFT is exposed, there is an advantage that an impurity element can be easily added.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, as shown in FIG. 4D, the recovery of the crystal of the semiconductor layer and the activation of the impurity element are performed by heat treatment. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method,
400 to 700 ° C., typically 500 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.
What is necessary is just to carry out at -550 degreeC. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In the heat treatment, the first doping process and the second doping process are performed at a low temperature, so that the activation is performed well, and the functions as the source region and the drain region can be sufficiently performed. .

It should be noted that the present invention relates to the TF described in the embodiment.
Not only the method of manufacturing T, but also bottom gate and other TFT
It can also be applied to the structure of

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0039]

[Embodiment 1] An embodiment of the present invention will be described with reference to the sectional view of FIG.

In FIG. 4A, a glass substrate such as a non-alkali glass such as a synthetic quartz glass substrate, barium borosilicate glass, or aluminoborosilicate glass may be used as the substrate 10. For example, Corning 705
Nine glass, 1737 glass, or the like can be preferably used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used. In this example, a 1737 glass substrate was used.

A base insulating film 11 is formed on the substrate 10 by a known means (LPCVD, plasma CVD, etc.) using a silicon nitride film, a silicon oxynitride film, a silicon oxide film or the like. In this embodiment, a 50-nm-thick silicon oxynitride film (composition ratio: Si = 32%, O = 27%, N = 24%, H = 17)
%).

Next, a semiconductor film is formed to a thickness of 10 to 200 nm (preferably 30 to 100 nm) by a known means such as a plasma CVD method or a sputtering method. Examples of the semiconductor film 12 include an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In this embodiment,
An amorphous silicon film having a thickness of 55 nm was formed by a plasma CVD method. Then, a known crystallization treatment (laser crystallization, thermal crystallization, thermal crystallization using a catalyst such as nickel, or a combination thereof) is performed. As the thermal crystallization method, thermal annealing using a furnace annealing furnace, laser annealing method, or rapid thermal annealing method (RTA method) can be applied. In this embodiment, an aqueous solution of nickel acetate having a concentration of 10 ppm by weight is applied to the amorphous silicon film, and the temperature is 550 ° C.
For 4 hours in a nitrogen atmosphere to form a crystalline silicon film.

Subsequently, the semiconductor layers 14 and 15 are formed by patterning the crystallized semiconductor film into a desired shape. Here, it is assumed that the semiconductor layer 14 is an n-channel TFT and the semiconductor layer 15 is a p-channel TFT.

Next, a gate insulating film 16 covering the semiconductor layers 14 and 15 is formed. The gate insulating film 16 is made of plasma C
Using the VD method or the sputtering method, the thickness is 40 to 150 n
m is formed of an insulating film containing silicon. In this embodiment,
A silicon oxynitride film having a thickness of 110 nm (composition ratio: Si = 32%, O = 59%, N = 7%, H
= 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 4A, a conductive film 17 having a thickness of 100 to 500 nm is formed on the gate insulating film 16. In this example, a conductive film made of a TaN film having a thickness of 30 nm was formed. The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. As the conductive film, Ta, W, Ti,
It may be formed of an element selected from Mo, Cu, Cr, and Nd, an alloy material or a compound material containing the element as a main component, or a semiconductor film typified by a crystalline silicon film. Further, an AgPdCu alloy may be used.
Further, an oxide conductive film (typically, an ITO film) transparent to visible light may be used.

Next, a mask (not shown) made of a resist is formed by photolithography, and an etching process for forming electrodes and wirings is performed to form conductive layers 18 and 19.

Next, using the conductive layers 18 and 19 as a mask, the gate insulating film 16 is selectively removed to form the insulating layer 2.
0 and 21 are formed. (FIG. 4 (B))

Then, a first doping process is performed,
An impurity element is added to the semiconductor layer. (Fig. 4B)
Ping treatment is done by ion doping method or ion implantation method.
Just do it. The condition of the ion doping method is that the dose amount is 1 ×
10¹³~ 5 × 10^Fifteen/ Cm^TwoAnd the accelerating voltage is 5 to 10
0 kV, the temperature of the substrate during the doping process becomes low
Low current density or dose to add
Perform Further, as an impurity element imparting n-type, 15
Group elements, typically phosphorus (P) or arsenic (A
s), but phosphorus (P) was used here. First
In the doping process, the conductive layers 18 and 19 are
And the impurity regions 22 to 25 are self-aligned.
Is formed. In this embodiment, the first doping process
The acceleration voltage is 5 kV and the current density is 1 μA / cm^Two,
adding phosphorus (P) as an impurity element imparting n-type;
The impurity concentration of the impurity regions 22 to 25 is 1 × 10¹⁸~ 1 × 1
0 ^{twenty one}/ Cm^ThreeI tried to be. At this time, the temperature at the time of addition
The temperature was about 150 ° C. In this embodiment, the activity of the TFT is described.
Because part of the semiconductor layer that becomes the conductive layer is exposed, impurities
It has the advantage of being easy to add elements.

Subsequently, by the second doping process, p
Impurity regions 29 and 30 to which an impurity element imparting a conductivity type opposite to the one conductivity type is added are formed in a semiconductor layer serving as an active layer of the channel type TFT. Also in the second doping process, it is desirable to add the low current density or the dose separately in such a manner that the temperature of the substrate during the doping process becomes low. Using the conductive layer 19 as a mask for the impurity element, an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity regions 29 and 30 are formed by an ion doping method using diborane (B ₂ H ₆ ). (FIG. 4C) In the second doping process, the semiconductor layer forming the n-channel TFT is covered with a mask 28 made of resist. Although phosphorus is added to the impurity regions 29 and 30 by the first doping process, the doping process is performed so that the concentration of the impurity element imparting p-type becomes 1 × 10 ^{19 to} 5 × 10 ²¹ / cm ^3. By doing so, there is no problem because it functions as the source and drain regions of the p-channel TFT. In this embodiment, a p-channel TFT
Since a part of the semiconductor layer serving as the active layer is exposed, there is an advantage that an impurity element can be easily added.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, as shown in FIG. 4E, the crystal of the semiconductor layer is recovered and the impurity element is activated by heat treatment. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method,
400 to 700 ° C., typically 500 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.
To 550 ° C., and in this embodiment, at 550 ° C., 4 ° C.
Heat treatment was performed by heat treatment for a long time. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In the above heat treatment, the first doping process and the second doping process are performed at a low temperature, so that the activation is favorably performed and the functions as the source region and the drain region can be sufficiently performed. .

[Embodiment 2] In this embodiment, a configuration different from that of Embodiment 1 will be described with reference to the sectional view of FIG.

According to the first embodiment, the process is performed up to the etching process shown in FIG.

Then, a first doping process is performed,
An impurity element is added to the semiconductor layer. (FIG. 4B) The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 ×
10 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 5 to 10
At 0 kV, the doping is performed by dividing the low current density or the dose amount so that the temperature of the substrate during the doping process becomes low. Further, as an impurity element imparting n-type, 15
Group elements, typically phosphorus (P) or arsenic (A
s), but phosphorus (P) was used here. In the first doping process, the conductive layers 18 and 19 serve as a mask for the impurity element, and the impurity regions 22 to 25 are self-aligned.
Is formed. In this embodiment, as the first doping process, the acceleration voltage is 5 kV, the current density is 5 μA / cm ² ,
Phosphorus (P) is added as an impurity element imparting n-type in six divided portions, and the phosphorus concentration of the impurity regions 22 to 25 is 1 ×.
It was adjusted to 10 ¹⁸ to 1 × 10 ²¹ / cm ³ . At this time, the temperature at the time of addition was about 100 ° C. In this embodiment, since a part of the semiconductor layer serving as the active layer of the TFT is exposed, there is an advantage that an impurity element can be easily added.

Subsequently, by the second doping process, p
Impurity regions 29 and 30 to which an impurity element imparting a conductivity type opposite to the one conductivity type is added are formed in a semiconductor layer serving as an active layer of the channel type TFT. Also in the second doping process, it is desirable to add the low current density or the dose separately in such a manner that the temperature of the substrate during the doping process becomes low. Using the conductive layer 19 as a mask for the impurity element, an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity regions 29 and 30 are formed by an ion doping method using diborane (B ₂ H ₆ ). (FIG. 4C) In the second doping process, the semiconductor layer forming the n-channel TFT is covered with a mask 28 made of resist. Although phosphorus is added to the impurity regions 29 and 30 by the first doping process, the doping process is performed so that the concentration of the impurity element imparting p-type becomes 1 × 10 ^{19 to} 5 × 10 ²¹ / cm ^3. By doing so, there is no problem because it functions as the source and drain regions of the p-channel TFT. In this embodiment, a p-channel TFT
Since a part of the semiconductor layer serving as the active layer is exposed, there is an advantage that an impurity element can be easily added.

Through the above steps, an impurity region is formed in each semiconductor layer.

Next, as shown in FIG. 4D, the recovery of the crystal of the semiconductor layer and the activation of the impurity element are performed by heat treatment. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method,
400 to 700 ° C., typically 500 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.
To 550 ° C., and in this embodiment, at 550 ° C., 4 ° C.
Heat treatment was performed by heat treatment for a long time. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In the above heat treatment, the first doping process and the second doping process are performed at a low temperature, so that the activation is favorably performed and the functions as the source region and the drain region can be sufficiently performed. .

[Embodiment 3] In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS.

First, in this embodiment, Corning # 70
A substrate 300 made of glass such as barium borosilicate glass represented by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that as the substrate 300, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a base film 301 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate 300. Although a two-layer structure is used as the base film 301 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 301, SiH ₄ , N 2
The silicon oxynitride film 301a formed by using H ₃ and N ₂ O as a reaction gas is formed to a thickness of 10 to 200 nm (preferably 50 to 10 nm).
0 nm). In this embodiment, a 50 nm-thick silicon oxynitride film 301a (composition ratio: Si = 32%, O = 27%,
N = 24%, H = 17%). Next, as a second layer of the base film 301, a plasma CVD
A silicon oxynitride film 301b formed by using iH ₄ and N ₂ O as a reaction gas has a thickness of 50 to 200 nm (preferably 100 nm).
(About 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 401b (composition ratio Si =
32%, O = 59%, N = 7%, H = 2%).

Next, a semiconductor film 302 is formed on the base film. As the semiconductor film 302, a semiconductor film having an amorphous structure is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Although there is no limitation on the material of the semiconductor film, it is preferable to use silicon or a silicon germanium (SiGe) alloy. Then, a known crystallization treatment (laser crystallization, thermal crystallization, thermal crystallization using a catalyst such as nickel, or a combination thereof) is performed. As thermal crystallization, thermal annealing using a furnace annealing furnace, laser annealing, or rapid thermal annealing (RT
Method A) can be applied. In this example, an aqueous solution of nickel acetate having a concentration of 10 ppm in terms of weight was applied to the amorphous silicon film, and heated at 550 ° C. for 4 hours in a nitrogen atmosphere to form a crystalline silicon film. The crystallized semiconductor film is patterned into a desired shape to form semiconductor layers 402 to 40.
6 is formed. In this embodiment, after a 55 nm amorphous silicon film is formed by using the plasma CVD method, a solution containing nickel is held on the amorphous silicon film. After dehydrogenation (500 ° C., 1 hour) of this amorphous silicon film, heat treatment (550 ° C., 4 hours) was performed to form a crystalline silicon film. Then, the crystalline silicon film is patterned by a photolithography method so that the semiconductor layer 40 is formed.
2 to 406 were formed.

When a laser crystallization method is also used for crystallization of a semiconductor film, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, a YVO ₄ laser, or the like can be used. When using these lasers,
It is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner, but when an excimer laser is used, the pulse oscillation frequency is 300 Hz.
And a laser energy density of 100 to 400 mJ / cm ²
(Typically 200 to 300 mJ / cm ² ). Also, YA
When a G laser is used, its second harmonic is used to set a pulse oscillation frequency of 1 to 300 Hz and a laser energy density of 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ).
J / cm ² ). And a width of 100 to 1000 μm,
For example, a laser beam condensed linearly at 400 μm may be irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time may be set to 50 to 98%.

After forming the semiconductor layers 402 to 406, T
A small amount of an impurity element (boron or phosphorus) may be added to control the threshold value of FT.

Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) is formed by a plasma CVD method.
And O ₂ , a reaction pressure of 40 Pa and a substrate temperature of 300 to
400 ° C., high frequency (13.56 MHz) power density 0.
It can be formed by discharging at 5 to 0.8 W / cm ² .
The silicon oxide film thus manufactured is thereafter
Good characteristics as a gate insulating film can be obtained by thermal annealing at up to 500 ° C.

Next, as shown in FIG. 5B, a first conductive film 408 having a thickness of 20 to 100 nm and a second conductive film 40 having a thickness of 100 to 400 nm are formed on the gate insulating film 407.
9 are laminated. In this embodiment, a 30 nm-thick T
a first conductive film 408 made of an aN film and a film thickness of 370 nm
A second conductive film 409 made of a W film was laminated. T
The aN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, thermal CV using tungsten hexafluoride (WF ₆ )
It can also be formed by Method D. In any case, it is necessary to lower the resistance in order to use it as a gate electrode,
It is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity of 99.9999%) target, and further taking into consideration that impurities from the gas phase are not mixed during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 408
Is TaN and the second conductive film 409 is W, but there is no particular limitation, and any of Ta, W, Ti, Mo, Al, Cu,
It may be formed of an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component.
Alternatively, a semiconductor film typified by a crystalline silicon film to which an impurity element such as phosphorus is added may be used. AgPdCu
An alloy may be used. A first conductive film formed of a tantalum (Ta) film, a second conductive film formed of a W film, a first conductive film formed of a titanium nitride (TiN) film, and a second conductive film formed of a titanium nitride (TiN) film; Are combined with a W film, the first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. Alternatively, a combination of the second conductive film and the Cu film may be used.

Next, masks 410 to 415 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed.
The first etching process is performed under the first and second etching conditions. In this embodiment, as the first etching condition, an ICP (Inductively Coupled Plasma) etching method is used, and C is used as an etching gas.
Using F ₄ , Cl ₂ and O ₂ , each gas flow ratio was 2
At 5/25/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.
The W film is etched under the first etching conditions to make the end of the first conductive layer tapered.

Then, a mask 410 made of resist is formed.
The second etching condition was changed without removing 415, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30/30 (sccm), and the pressure was 1 Pa to form a coil-type electrode. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the resist mask appropriate,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, the first-shaped conductive layers 417 to 422 (the first conductive layers 417 a to 422 a and the second conductive layers 417 b to 422) formed of the first conductive layer and the second conductive layer by the first etching process.
2b) is formed. 416 is a gate insulating film,
The region not covered by the conductive layers 417 to 422 having the
A region that is etched and thinned by about 50 nm is formed.

Then, the resist mask is removed.
The first doping process without adding an n-type semiconductor layer.
An impurity element to be added is added. (Fig. 6 (A)) Dopi
Is performed by ion doping or ion implantation.
Good. The condition of the ion doping method is that the dose amount is 1 × 1.
0¹³~ 5 × 10^Fifteen/ Cm^TwoAnd the acceleration voltage is 60 to 10
The operation is performed at 0 kV. In this embodiment, the dose amount is 1.5 ×
10^Fifteen/ Cm^TwoAnd the acceleration voltage was set to 80 kV.
Was. Element belonging to Group 15 as an impurity element imparting n-type
Using arsenic, typically phosphorus (P) or arsenic (As)
However, phosphorus (P) was used here. In this case, the conductive layer 4
17 to 421 are masses for the impurity element imparting n-type.
And the first high-concentration impurity region 306 is self-aligned.
To 310 are formed. First high concentration impurity region 306
1x10 for ~ 310²⁰~ 1 × 10 ^{twenty one}/ Cm^ThreeConcentration range
An impurity element imparting n-type is added in the box.

Next, a second etching process is performed without removing the resist mask. Here, the W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as} an etching gas. At this time, second conductive layers 428b to 433b are formed by a second etching process. on the other hand,
The first conductive layers 417a to 422a are hardly etched to form second shape conductive layers 428 to 433.

Next, the resist mask is removed.
Instead, as shown in FIG.
Perform In this case, the doping is performed more than in the first doping process.
Lowering the noise amount, and using a high accelerating voltage of 70 to 120 kV, n
An impurity element for imparting a mold is introduced. Also doping
Lower the current density so that the substrate temperature during processing is low.
Alternatively, the addition is performed by dividing the dose. In this embodiment,
Dose amount 1.5 × 10 ¹⁴/ Cm^TwoAnd the accelerating voltage is 90
kV and the current density is 1 μA / cm^TwoIt was done as.
The second doping process is performed in the second shape conductive layers 428-4.
The second conductive layers 428b to 428b to 43
The impurity element is also introduced into the semiconductor layer below 3b.
And newly added to the second high-concentration impurity regions 423a to 427a.
And low concentration impurity regions 423b to 427b are formed.
You.

Next, after removing the mask made of resist, masks 434a and 434a made of resist are newly added.
34b is formed, and a third etching process is performed as shown in FIG. SF ₆ and Cl ₂ were used as etching gases, and the gas flow ratio was 50/10 (scc
m) and a pressure of 1.3 Pa and 500
An RF (13.56 MHz) power of W is applied to generate plasma, and an etching process is performed for about 30 seconds. 10 W RF (13.56 MH) on the substrate side (data stage)
z) Turn on the power and apply a substantially non-self bias voltage. Thus, the p-channel type TFT and the TFT (pixel T
The TaN film (FT) is etched to form third shape conductive layers 435 to 438.

Next, after removing the resist mask, the gate insulating film 416 is selectively removed using the second shape conductive layers 428 and 430 and the second shape conductive layers 435 to 438 as masks. Insulating layers 439-44
4 is formed. (FIG. 7 (A))

Next, a new mask 4 made of resist is used.
45a to 445c are formed and a third doping process is performed. By the third doping treatment, the impurity region 4 in which the impurity element imparting the conductivity type opposite to the one conductivity type is added to the semiconductor layer serving as the active layer of the p-channel TFT.
46 and 447 are formed. Second conductive layers 435a, 43
8a is used as a mask for the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. In addition, it is desirable that the doping is performed by dividing the low current density or the dose so that the temperature of the substrate during the doping process becomes low. In this embodiment, the impurity region 4
46 and 447 are formed by an ion doping method using diborane (B ₂ H ₆ ). (FIG. 7B) In the third doping process, the semiconductor layers forming the n-channel TFT are covered with masks 445a to 445c made of resist. Phosphorus is added at different concentrations to the impurity regions 446 and 447 by the first doping process and the second doping process, and the concentration of the impurity element imparting p-type is set to 2 × in each of the regions. 10
^By performing the doping treatment so as to have a concentration of ^{20 to} 2 × 10 ²¹ / cm ³ , no problem occurs because the p-channel TFT functions as a source region and a drain region. In this embodiment, since a part of the semiconductor layer serving as the active layer of the p-channel TFT is exposed, there is an advantage that an impurity element (boron) can be easily added.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, a mask 445a made of resist is used.
To 445c are removed to form a first interlayer insulating film 461. As the first interlayer insulating film 461, plasma C
Using a VD method or a sputtering method, a thickness of 100 to 200
The insulating film containing silicon is formed as nm. In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. Of course, the first interlayer insulating film 461
Is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 7C, heat treatment is performed to recover the crystallinity of the semiconductor layers and activate the impurity elements added to the respective semiconductor layers.
This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As a thermal annealing method, an oxygen concentration of 1 p
The heat treatment may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere of pm or less, preferably 0.1 ppm or less. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA)
Law) can be applied.

Further, heat treatment may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) to protect the wiring and the like as in this embodiment, heating is performed. Preferably, a treatment is performed.

Further, a heat treatment is carried out at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

In the case where a laser annealing method is used as the heat treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, a second interlayer insulating film 462 made of an inorganic insulating material or an organic insulating material is formed on the first interlayer insulating film 461. In this embodiment, the film thickness is 1.6 μm
Was formed, but the viscosity was 10 to 1000
cp, preferably 40 to 200 cp, and those having irregularities on the surface were used.

In the present embodiment, in order to prevent specular reflection, the second interlayer insulating film having the unevenness formed on the surface is formed to form the unevenness on the surface of the pixel electrode. In addition, a projection may be formed in a region below the pixel electrode in order to obtain light scattering by providing unevenness on the surface of the pixel electrode. In that case, the projection can be formed using the same photomask as that for forming the TFT, so that the projection can be formed without increasing the number of steps. Note that the protrusions may be appropriately provided on the substrate in the pixel portion region other than the wiring and the TFT portion. Thus, irregularities are formed on the surface of the pixel electrode along irregularities formed on the surface of the insulating film covering the convex portions.

Further, a film whose surface is flattened may be used as the second interlayer insulating film 462. In that case, after forming the pixel electrode, the surface is made uneven by adding a process such as a known sand blasting method or an etching method to prevent specular reflection and increase whiteness by scattering reflected light. Is preferred.

In the drive circuit 506, wirings 463 to 467 electrically connected to the respective impurity regions, respectively.
To form Note that these wirings are made of a 50 nm thick T
A laminated film of an i film and a 500 nm-thick alloy film (an alloy film of Al and Ti) is formed by patterning.

In the pixel portion 507, a pixel electrode 470, a gate wiring 469, and a connection electrode 468 are formed. (FIG. 8) The source electrode (4
43b and 449), an electrical connection is formed with the pixel TFT. The gate wiring 469 is a pixel TFT
And the gate electrode is electrically connected. The pixel electrode 470 is electrically connected to the drain region 442 of the pixel TFT, and is also electrically connected to the semiconductor layer 458 which functions as one electrode forming a storage capacitor. In addition, as the pixel electrode 470, a material having excellent reflectivity, such as a film containing Al or Ag as a main component or a stacked film thereof, is preferably used.

As described above, the n-channel TFT 50
1 and a CMOS circuit comprising a p-channel TFT 502;
And driving circuit 506 having n-channel TFT 503
And a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 can be formed over the same substrate. Thus, an active matrix substrate is completed.

The n-channel TFT 50 of the drive circuit 506
1 includes a channel formation region 423c, a low-concentration impurity region 423b (a GOLD region) overlapping with a first conductive layer 428a which forms part of a gate electrode, and a high-concentration impurity region 423a functioning as a source or drain region. ing. A p-channel TFT 5 connected to the n-channel TFT 501 via an electrode 466 to form a CMOS circuit
02 has a channel formation region 446d, impurity regions 446b and 446c formed outside the gate electrode, and a high-concentration impurity region 446a functioning as a source region or a drain region. Also, an n-channel TFT 50
3 includes a channel formation region 425c, a low-concentration impurity region 425b (GOLD region) overlapping with the first conductive layer 430a which forms part of the gate electrode, and a high-concentration impurity region 425a functioning as a source or drain region. are doing.

The pixel TFT 504 in the pixel portion includes a channel forming region 426c, a low concentration impurity region 426b (LDD region) formed outside the gate electrode, and a high concentration impurity region 426a functioning as a source or drain region.
have. The semiconductor layers 447a and 447b functioning as one electrode of the storage capacitor 505 are each doped with an impurity element imparting p-type. The storage capacitor 505 includes an electrode (438) using the insulating film 444 as a dielectric.
a and 438b), and the semiconductor layers 447a to 447c.
And formed.

In the pixel structure of this embodiment, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

FIG. 9 is a top view of the pixel portion of the active matrix substrate manufactured in this embodiment. FIG.
8 are denoted by the same reference numerals. FIG.
A chain line AA ′ in FIG. 9 corresponds to a cross-sectional view taken along a line AA ′ in FIG. Further, a chain line BB ′ in FIG. 8 corresponds to a cross-sectional view taken along a chain line BB ′ in FIG.

[Embodiment 4] In this embodiment, a process of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 3 will be described below. FIG. 10 is used for the description.

First, in accordance with the third embodiment, after obtaining the active matrix substrate in the state shown in FIG. 12, an alignment film 567 is formed on at least the pixel electrode 470 on the active matrix substrate shown in FIG. Note that in this embodiment, before forming the alignment film 567, a columnar spacer 572 for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 569 is prepared. Next, the coloring layers 570 and 571 and the planarizing film 573 are formed over the counter substrate 569. The red coloring layer 570 and the blue coloring layer 572 are overlapped to form a light shielding portion. Alternatively, the light-blocking portion may be formed by partially overlapping the red coloring layer and the green coloring layer.

In this embodiment, the substrate shown in the third embodiment is used. Therefore, FIG. 9 shows a top view of the pixel portion of the third embodiment.
Then, at least a gap between the gate wiring 469 and the pixel electrode 470, a gap between the gate wiring 469 and the connection electrode 468,
It is necessary to shield the gap between the connection electrode 468 and the pixel electrode 470 from light. In this embodiment, the colored layers are arranged such that the light-shielding portion formed of the colored layers is overlapped at the positions where the light is to be shielded, and the opposing substrates are bonded to each other.

As described above, the number of steps can be reduced by shielding the gap between each pixel with the light-shielding portion composed of the colored layers without forming a light-shielding layer such as a black mask.

Next, a counter electrode 576 made of a transparent conductive film was formed on at least the pixel portion on the flattening film 573, an alignment film 574 was formed on the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealing material 568.
Paste in. A filler is mixed in the sealant 568, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 575 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. Thus, the reflection type liquid crystal display device shown in FIG. 10 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, using a known technique, F
PC was pasted.

The liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.

This embodiment can be freely combined with Embodiments 1 to 5.

[Embodiment 5] In this embodiment, FIG. 16 shows an example of a liquid crystal display device in which a gate wiring serving also as a light shielding film is provided below an n-channel TFT used for a pixel portion. FIG.
FIG. 16A is an enlarged top view of one of the pixels in the pixel portion. In FIG. 16A2, a portion cut along a dotted line EE ′ corresponds to a cross-sectional structure of the pixel portion in FIG. Equivalent to.

In FIG. 16, reference numeral 801 denotes a substrate; 802, a gate wiring; 803a and 803b, insulating films covering the gate wiring; 808, a gate insulating film; 810, a gate electrode;
Reference numeral 11 denotes a capacitance wiring. Note that the gate wiring 802 also functions as a light shielding layer for protecting the active layer from light. The active layer includes regions 812 to 815, of which 812 are low-concentration impurity regions serving as LDD regions,
Reference numeral 813 denotes a high-concentration impurity region serving as a source or drain region to which phosphorus is added at a high concentration;
Is a channel formation region. The low concentration impurity region 8
Reference numeral 12 is doped by self-alignment and does not overlap with the gate electrode 910. When forming at least a high-concentration impurity region among these impurity regions, the present invention is applied. That is, when the impurity element is added, by performing processing so that the temperature of the substrate becomes low, the impurity element can be efficiently activated by heat treatment after the doping treatment.

In FIG. 16, 816 is a passivation film, 817 is an interlayer insulating film made of an organic resin material, 818 is an electrode for connecting a pixel electrode to a high concentration impurity region, 819 is a source wiring, and 820 is acrylic. An interlayer insulating film; 821, a light shielding layer; 822, an interlayer insulating film;
Reference numerals 3 and 824 denote pixel electrodes made of a transparent conductive film.

[Embodiment 6] In this embodiment, an example in which an EL (Electro Luminescence) display device is manufactured as a light emitting device using the present invention will be described. EL is a light-emitting device using, as a light source, a layer containing an organic compound (EL element) from which luminescence generated by application of an electric field is obtained. EL in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state. FIG. 11 is a sectional view of the light emitting device of the present invention.

In FIG. 11, the switching TFT 603 provided on the substrate 700 is an n-channel TFT shown in FIG.
It is formed using FT503. Therefore, for the description of the structure, the description of the n-channel TFT 503 may be referred to.

Although the present embodiment has a double gate structure in which two channel forming regions are formed, a single gate structure in which one channel forming region is formed or a triple gate structure in which three channel forming regions are formed. good.

The drive circuit provided on the substrate 700 is shown in FIG.
It is formed using one CMOS circuit. Therefore, the description of the structure is made of the n-channel TFT 501 and the p-channel TFT
Reference may be made to the description of 502. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The wirings 701 and 703 function as a source wiring of a CMOS circuit, and the wiring 702 functions as a drain wiring.
The wiring 704 is connected to the source wiring 708 and the switching T
The wiring 705 functions as a wiring for electrically connecting the source region of the FT to the source region.
It functions as a wiring for electrically connecting the drain region of the FT.

Note that the current control TFT 604 corresponds to p
It is formed using a channel type TFT 502. Therefore,
For the description of the structure, the description of the p-channel TFT 502 can be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

A wiring 706 is a source wiring (corresponding to a current supply line) of the current control TFT, and an electrode 707 is electrically connected to the pixel electrode 710 by being superposed on the pixel electrode 710 of the current control TFT. is there.

Reference numeral 710 denotes a pixel electrode (anode of an EL element) made of a transparent conductive film. As a transparent conductive film,
A compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used. The pixel electrode 710 has a flat interlayer insulating film 7 before forming the wiring.
11 is formed. In this embodiment, it is very important to flatten the step due to the TFT using the flattening film 711 made of resin. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG. Bank 712 is 10
The insulating film or the organic resin film containing silicon having a thickness of 0 to 400 nm may be formed by patterning.

Since the bank 712 is an insulating film,
Attention must be paid to electrostatic breakdown of the element during film formation.
In this embodiment, the resistivity is reduced by adding carbon particles or metal particles to the insulating film used as the material of the bank 712 to suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of the carbon particles and metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

On the pixel electrode 710, an EL layer 713 is formed. Although only one pixel is shown in FIG. 11, in this embodiment, EL layers corresponding to R (red), G (green), and B (blue) are separately formed. In this embodiment, a low-molecular organic EL material is formed by an evaporation method.
Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a light emitting layer is formed on the copper phthalocyanine film.
It has a laminated structure in which a 0 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

However, the above example is an example of the organic EL material that can be used for the EL layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, a low molecular organic EL material is
Although an example in which the layer is used as a layer has been described, a polymer organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the EL layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (an alloy film of magnesium and silver)
May be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

When the cathode 714 is formed, the EL
The element 715 is completed. Note that the EL element 71 here
Reference numeral 5 denotes a diode formed by the pixel electrode (anode) 710, the EL layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the EL element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used in a single layer or in a stacked layer.

At this time, a film having good coverage is preferably used as a passivation film, and a carbon film, particularly, a D film is preferably used.
It is effective to use an LC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or lower, it can be easily formed above the EL layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen, and the EL layer 713
Can be suppressed. Therefore, the problem that the EL layer 713 is oxidized during the subsequent sealing step can be prevented.

Further, a sealing material 717 is provided on the passivation film 716, and a cover material 718 is attached. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, a cover material 718 having a carbon film (preferably a diamond-like carbon film) formed on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) is used.

Thus, a light emitting device having a structure as shown in FIG. 11 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 without opening to the atmosphere using a multi-chamber (or in-line) film forming apparatus. . Further, by further developing, it is also possible to continuously perform processing up to the step of bonding the cover material 718 without releasing to the atmosphere.

In this manner, the n-channel TFTs 601 and 602 are placed on the insulator 501 whose main body is a plastic substrate.
A switching TFT (n-channel TFT) 603 and a current control TFT (n-channel TFT) 604 are formed. The number of masks required in the manufacturing process up to this point is
Less than a typical active matrix light emitting device.

That is, the manufacturing process of the TFT is greatly simplified, and an improvement in yield and a reduction in manufacturing cost can be realized.

Further, as described with reference to FIG.
By providing an impurity region overlapping the gate electrode with an insulating film interposed therebetween, n is resistant to deterioration caused by the hot carrier effect.
A channel type TFT can be formed. for that reason,
A highly reliable light-emitting device can be realized.

In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other components such as a signal dividing circuit, a D / A converter, an operational amplifier, a γ correction circuit, and the like can be used. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, the EL light emitting device of this embodiment after performing a sealing (or enclosing) step for protecting the EL element will be described with reference to FIG. Note that the reference numerals used in FIG.

FIG. 12A is a top view showing a state in which the process up to sealing of the EL element has been performed, and FIG. 12B is a cross-sectional view of FIG. 12A taken along the line AA ′. 80 shown by dotted line
Reference numeral 1 denotes a source side driving circuit, 806 denotes a pixel portion, and 807 denotes a gate side driving circuit. Reference numeral 901 denotes a cover material;
Denotes a first sealant, 903 denotes a second sealant, and a sealant 907 is provided inside the first sealant 902.

Reference numeral 904 denotes wiring for transmitting signals input to the source-side driving circuit 801 and the gate-side driving circuit 807, and a video signal or a clock signal from an FPC (flexible print circuit) 905 serving as an external input terminal. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached. The light emitting device in this specification includes not only the light emitting device body but also an FPC
Alternatively, this also includes a state where the PWB is attached.

Next, a sectional structure will be described with reference to FIG. A pixel portion 806 and a gate driver circuit 807 are formed above the substrate 700.
Is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 710 electrically connected to its drain. The gate side drive circuit 807 is an n-channel type TF
It is formed using a CMOS circuit (see FIG. 14) in which T601 and p-channel TFT 602 are combined.

The pixel electrode 710 functions as an anode of the EL element. Further, banks 712 are provided at both ends of the pixel electrode 710.
Are formed, and an EL layer 713 and a cathode 714 of an EL element are formed on the pixel electrode 710.

The cathode 714 also functions as a common wiring for all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, all elements included in the pixel portion 806 and the gate driver circuit 807 are covered with the cathode 714 and the passivation film 567.

The cover member 901 is attached by the first seal member 902. Note that a spacer made of a resin film may be provided to secure an interval between the cover member 901 and the EL element. The inside of the first sealant 902 is filled with a sealant 907. Note that an epoxy resin is preferably used for the first sealant 902 and the sealant 907. Further, it is desirable that the first sealant 902 be a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a moisture absorbing effect or a substance having an antioxidant effect may be contained in the sealing material 907.

[0136] The sealing material 907 provided so as to cover the EL element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (FRP) is used as the material of the plastic substrate 901a constituting the cover member 901.
iberglass-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester or acrylic can be used.

Further, the cover material 90 is formed using the sealing material 907.
After bonding, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. Second sealing material 90
For 3, the same material as the first sealant 902 can be used.

With the above structure, the EL element is sealed with the sealing material 90.
By encapsulating the EL element in the EL element, the EL element can be completely shut off from the outside, and it is possible to prevent a substance such as moisture or oxygen, which promotes the deterioration of the EL layer from being oxidized, from entering from the outside. Therefore, a highly reliable light emitting device can be obtained.

This embodiment can be freely combined with Embodiments 1 to 5.

[Embodiment 7] By applying the present invention, various electro-optical devices (active matrix liquid crystal display device, active matrix light emitting device, active matrix EC display device) can be manufactured. That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in the display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector, a head-mounted display (goggle type display), a car navigation, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.). ). FIG. 13 shows an example of these.
It is shown in FIG. 14 and FIG.

FIG. 13A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 13B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102.

FIG. 13C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 13D shows a goggle type display, which comprises a main body 2301, a display section 2302, and an arm section 230.
3 and so on. The present invention can be applied to the display portion 2302.

FIG. 13E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 13F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502.

FIG. 14A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other driving circuits.

FIG. 14B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to a liquid crystal display device 2808 forming a part of the LCD 702 and other driving circuits.

FIG. 14C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 14A and 14B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 14D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 14C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 14D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 14, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and a light emitting device are not shown.

FIG. 15A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904.

FIG. 15B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003.

FIG. 15C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 6.

[0157]

By adopting the configuration of the present invention, the following basic significance can be obtained. (A) This is a simple method adapted to a conventional TFT manufacturing process. (B) The process time can be reduced. (C) The addition amount of the impurity element can be reduced. (D) Recovery of crystal defects by addition of an impurity element is facilitated. (F) This method is a method that, while satisfying the above advantages, can improve the activation efficiency of impurities and produce a TFT having excellent electrical characteristics.

[Brief description of the drawings]

FIG. 1 is a diagram showing a relationship between current density and temperature when ions are added.

FIG. 2A is a diagram showing a relationship between current density after addition of ions and sheet resistance. (B) is a diagram showing the relationship between current density and sheet resistance after heat treatment.

FIG. 3A is a diagram showing a relationship between a current density after addition of ions and a Raman spectrum. FIG. 4B is a diagram illustrating a relationship between a current density after heat treatment and a Raman spectrum.

FIG. 4 is a diagram illustrating a technique disclosed in the present invention for improving activation efficiency.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 9 is a top view illustrating a configuration of a pixel TFT.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 11 is a cross-sectional structural view of a driving circuit and a pixel portion of a light-emitting device.

FIG. 12A is a top view of a light-emitting device. FIG. 2B is a cross-sectional structural view of a driving circuit and a pixel portion of a light-emitting device.

FIG. 13 illustrates an example of a semiconductor device.

FIG. 14 illustrates an example of a semiconductor device.

FIG. 15 illustrates an example of a semiconductor device.

16A and 16B are a cross-sectional view and a top view illustrating an example of a configuration of a pixel TFT.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) HJ12 HJ13 HJ23 HL02 HL03 HL04 HL06 HM15 NN03 NN04 NN22 NN34 NN35 NN40 NN72 NN78 PP01 PP02 PP03 PP10 PP29 PP34 QQ11 QQ24 QQ25 QQ28

Claims (8)

[Claims] A step of adding an impurity element to a semiconductor film formed on a substrate to form an impurity region; and a step of activating the impurity element by heat treatment.
The temperature of the substrate when adding the impurity element is 20
A method for manufacturing a semiconductor device, which is at 0 ° C. or lower. 2. A step of etching a semiconductor film formed on a substrate into a desired shape to form a semiconductor layer; a step of adding an impurity element to the semiconductor layer to form an impurity region; Activating the impurity element by the method described above, wherein the temperature of the substrate at the time of adding the impurity element is 200 ° C. or lower. 3. A method for forming an impurity region by adding an impurity element at least twice into a semiconductor film formed on a substrate, and activating the impurity element by heat treatment. And a temperature of the substrate at which the impurity element is added is 200 ° C. or lower. 4. A semiconductor film formed on a substrate, comprising: a step of adding an impurity element at a low current density to a semiconductor film to form an impurity region; and a step of activating the impurity element by heat treatment. A method for manufacturing a semiconductor device. 5. The method according to claim 1, wherein
The method for manufacturing a semiconductor device, wherein the impurity element is an impurity element imparting n-type, an impurity element imparting p-type, or an impurity element imparting n-type and an impurity element imparting p-type. . 6. The method for manufacturing a semiconductor device according to claim 4, wherein the low current density is a current density at which the temperature of the substrate is 200 ° C. or lower and the impurity element is added. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device or a light emitting device. 8. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a digital camera, a projector, a goggle type display, a personal computer, a DVD player, an electronic book, or portable information. A method for manufacturing a semiconductor device, which is a terminal.