JP2002064107A - Method of manufacturing semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To overcome the conventional problem such that, when a TFT having an LDD structure or GOLD structure is to be formed, the manufacturing process becomes complicated and the number of steps increases. SOLUTION: After an electrode is formed by laminating first and second conductive layers 18b and 17c having different widths upon another and a first conductive layer 18c is formed by selectively etching the conductor layer 18b, a lightly doped region 25a which lies below the first conductive layer 18c and another lightly doped area 25b which does not lie below the layer 18c are formed by performing low-concentration doping by using an impurity element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a thin film transistor (TFT) has been constructed using a semiconductor thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface, and a large-area integrated circuit formed by the TFT has been developed. The development of a semiconductor device having the same is progressing. Active matrix liquid crystal display devices, EL display devices, and contact image sensors are known as typical examples. In particular, a TFT using a crystalline silicon film (typically, a polysilicon film) as an active layer (hereinafter referred to as a polysilicon TFT) has a high field-effect mobility, so that various functional circuits can be formed. It is.

For example, an active matrix type liquid crystal display device controls a pixel circuit for displaying an image for each functional block, and a pixel circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit based on a CMOS circuit. Is formed on one substrate.

In a pixel circuit of an active matrix type liquid crystal display device, TFTs (pixel TFTs) are arranged for tens to millions of pixels, and each of the pixel TFTs is provided with a pixel electrode. A counter electrode is provided on the counter substrate side sandwiching the liquid crystal, and forms a kind of capacitor using the liquid crystal as a dielectric. Then, the voltage applied to each pixel is controlled by the switching function of the TFT, the liquid crystal is driven by controlling the charge to the capacitor, and the amount of transmitted light is controlled to display an image.

The pixel TFT is formed of an n-channel type TFT, and is a device that applies a voltage to a liquid crystal as a switching element to drive the liquid crystal. Since the liquid crystal is driven by alternating current, a method called frame inversion drive is often used. In this method, in order to suppress power consumption, it is important for the characteristics required for the pixel TFT to sufficiently reduce an off-current value (a drain current flowing when the TFT is turned off).

As a structure of a TFT for reducing an off-current value, a lightly doped drain (LDD) is used.
n) Structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration. This region is referred to as an LDD region. Calling. As means for preventing deterioration of the on-current value due to hot carriers, L
The so-called G in which the DD region is arranged so as to overlap the gate electrode
An OLD (Gate-drain Overlapped LDD) structure is known. With such a structure, it is known that a high electric field near the drain is relieved, hot carrier injection is prevented, and deterioration is effectively prevented.

Although the GOLD structure has a high effect of preventing the deterioration of the ON current value, it has a problem that the OFF current value becomes larger than that of the ordinary LDD structure. Therefore, it was not a preferable structure to be applied to the pixel TFT. Conversely, the ordinary LDD structure has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain to prevent deterioration due to hot carrier injection. As described above, in a semiconductor device having a plurality of integrated circuits, such as an active matrix type liquid crystal display device, such a problem is caused particularly by an increase in characteristics of a crystalline silicon TFT, and also in an active matrix type liquid crystal display device. It has become apparent as the required performance increases.

[0009]

Conventionally, when a TFT having an LDD structure or a TFT having a GOLD structure is to be formed, there has been a problem that the manufacturing steps are complicated and the number of steps is increased. . It is clear that an increase in the number of steps not only causes an increase in manufacturing cost but also causes a reduction in manufacturing yield.

The present invention is a technique for solving such a problem. In an electro-optical device and a semiconductor device represented by an active matrix type liquid crystal display device manufactured using a TFT, the operation of the semiconductor device is described. It is an object of the present invention to improve characteristics and reliability, reduce power consumption, reduce the number of steps, and realize a reduction in manufacturing cost and an improvement in yield.

[0011]

In order to reduce the manufacturing cost and the yield, it is conceivable to reduce the number of steps as one means. Specifically, the number of photomasks required for manufacturing a TFT is reduced. A photomask is used in a photolithography technique to form a resist pattern used as a mask on a substrate in an etching step. Therefore, the use of one photomask means that in addition to the steps such as film formation and etching in the preceding and subsequent steps, resist stripping, washing and drying steps are added, and in the photolithography step, This means that complicated processes such as resist coating, pre-baking, exposure, development, and post-baking are performed.

The present invention is characterized in that the number of photomasks is reduced as compared with the conventional one, and a TFT is manufactured by the following manufacturing process. Note that an example of the manufacturing method of the present invention is shown in FIGS.

The structure of the invention disclosed in this specification includes a first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a step of forming a semiconductor layer on the insulating film. ,
A third step of forming a first electrode formed by laminating a first conductive layer having a first width (W1) and a second conductive layer, and using the first electrode as a mask, A fourth step of forming a high-concentration impurity region by adding an impurity element to the layer; and etching the second conductive layer of the first electrode to form a first layer having the first width (W1). A fifth step of forming a second electrode composed of a stack of a conductive layer having a second width and a second conductive layer having a second width (W2); and forming the first conductive layer in the second electrode. Etch,
A third conductive layer having a third width (W3) and a second conductive layer having the second width (W2);
A sixth step of forming an electrode, and using the second conductive layer as a mask, passing the first conductive layer or the insulating film and adding an impurity element to the semiconductor layer to form a low-concentration impurity region. And a seventh step of forming the semiconductor device.

Another example of the manufacturing method of the present invention is shown in FIGS. According to the structure of the present invention, a first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first width (W1) on the insulating film A third step of forming a first electrode composed of a stack of a first conductive layer having a first conductive layer and a second conductive layer;
Etching the second conductive layer on the first electrode to form a first conductive layer having the first width (W1);
A fourth step of forming a second electrode formed by stacking a second conductive layer having a second width (W2), and adding an impurity element to the semiconductor layer using the second electrode as a mask. A fifth step of forming a high concentration impurity region by etching, and etching the first conductive layer in the second electrode to form a third impurity region.
A sixth step of forming a third electrode formed by laminating a first conductive layer having a width (W3) and a second conductive layer having a second width (W2); Forming a low-concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film using the conductive layer as a mask. Is the way.

In each of the above-described manufacturing methods, the second
Is smaller than the first width (W1). Further, in the above manufacturing method, the third width (W3) is smaller than the first width (W1) and wider than the second width (W2).

In each of the above-described manufacturing methods, the third
Forming a first conductive film and a second conductive film on the insulating film, and then performing a first etching process on the second conductive film to form the second conductive layer And the first
Performing a second etching process on the conductive film to form the first conductive layer, and laminating the first conductive layer having the first width (W1) and the second conductive layer The first consisting of
Is formed.

Another example of the manufacturing method of the present invention is shown in FIGS. The structure of the present invention includes a first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first step of forming a first layer on the insulating film.
A third step of laminating the conductive film and the second conductive film,
The second conductive film is etched to have a first width (X1)
A fourth step of forming a second conductive layer having a first width (X1), and using the second conductive layer having the first width (X1) as a mask.
A fifth step of adding an impurity element to the semiconductor layer through the first conductive film or the insulating film to form a high-concentration impurity region; and etching the first conductive film to A sixth step of forming a first electrode formed by laminating a first conductive layer having a width (X2) of 2 and a second conductive layer having a third width (X3); Etching the second conductive layer in the first electrode, the first conductive layer having the second width (X2), and the fourth width (X4)
A seventh step of forming a second electrode formed of a laminate with a second conductive layer having
An eighth step of etching the conductive layer to form a third electrode formed by laminating a first conductive layer having a fifth width and a second conductive layer having the fourth width; Forming a low-concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film using the second conductive layer having the fourth width (X4) as a mask; And a ninth step of fabricating the semiconductor device.

Further, in the above manufacturing method, the second width (X2) is smaller than the first width (X1). The fifth width (X5) is smaller than the second width (X2) and the fourth width (X4).
It is characterized by being wider.

Another example of the manufacturing method of the present invention is shown in FIGS. The structure of the present invention includes a first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first step of forming a first layer on the insulating film.
A third step of laminating the conductive film and the second conductive film,
The second conductive film is etched to have a first width (X1)
A fourth step of forming a second conductive layer having a first width (X1), and using the second conductive layer having the first width (X1) as a mask.
A fifth step of adding an impurity element to the semiconductor layer through the first conductive film or the insulating film to form a high-concentration impurity region, and etching the second conductive layer to form the second conductive layer. A sixth step of forming a second conductive layer having a width (Y2) of 2; etching the first conductive film to form a first conductive layer having a third width (Y3); A seventh step of forming an electrode composed of a laminate with a second conductive layer having a second width (Y2); and forming the electrode using the second conductive layer having the second width (Y2) as a mask. An eighth step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer by passing the semiconductor layer through the first conductive layer or the insulating film.

Further, in the above-mentioned manufacturing method, the second width (Y2) is smaller than the first width (X1). Further, the third width (Y3) is smaller than the first width (X1), and the second width (Y2).
It is characterized by being wider.

Another example of the manufacturing method of the present invention is shown in FIGS. The structure of the present invention includes a first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first conductive film and a second conductive film on the insulating film. A third step of laminating and forming a conductive film, and etching the second conductive film to form a first width (X
A fourth step of forming a second conductive layer having 1), and passing the first conductive film or the insulating film using the second conductive layer having the first width (X1) as a mask. A fifth step of forming a high-concentration impurity region by adding an impurity element to the semiconductor layer by using the first conductive film and the second conductive layer.
Forming an electrode composed of a stack of a first conductive layer having a second width (Z2) and a second conductive layer having a third width (Z3) Using a second conductive layer having the third width (Z3) as a mask, adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film, and forming a low-concentration impurity region. And a seventh step of forming a semiconductor device.

Further, in the above-mentioned manufacturing method, the third width (Z3) is smaller than the first width (X1). Further, in the above manufacturing method, the second width (Z2) is smaller than the first width (X1), and
The width is wider than the third width (Z3).

In each of the above manufacturing methods, the impurity element is an impurity element that imparts n-type or p-type to a semiconductor.

[0024]

(Embodiment 1) Embodiment 1 of the present invention will be described below with reference to FIGS. 1 and 2. FIG.

First, a base insulating film 11 is formed on a substrate 10. The substrate 10 may be a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature may be used.

As the base insulating film 11, a base insulating film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film or a silicon oxynitride film is formed. Here, an example is shown in which a two-layer structure (11a, 11b) is used as the base insulating film 11, but a single-layer film of the insulating film or a structure in which two or more insulating films are stacked may be used. Note that the base insulating film 11
Need not be formed.

Next, the semiconductor layer 12 is formed on the base insulating film 11.
To form The semiconductor layer 12 is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, or the like), and then performing a known crystallization treatment (laser crystallization method, thermal crystallization, or the like). , Or a thermal crystallization method using a catalyst such as nickel) is used to pattern the crystalline semiconductor film into a desired shape using a first photomask. The semiconductor layer 12 is formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon or silicon germanium (SiG
e) It is good to form with an alloy etc.

Next, an insulating film 13 covering the semiconductor layer 12 is formed.

The insulating film 13 is formed by a plasma CVD method or a sputtering method to have a thickness of 40 to 150 nm and have a single-layer or laminated structure of an insulating film containing silicon. In addition,
This insulating film 13 becomes a gate insulating film.

Next, a film thickness of 20 to 100
A first conductive film 14 having a thickness of 100 nm and a second conductive film 15 having a thickness of 100 to 400 nm are stacked. (FIG. 1A) Here, a first conductive film 14 made of a TaN film and a second conductive film 15 made of a W film were formed by sputtering using a sputtering method. Note that, here, the first conductive film 14 is TaN, and the second conductive film 15 is W. However, the present invention is not particularly limited, and any element selected from Ta, W, Ti, Mo, Al, and Cu; Alternatively, it may be formed of an alloy material or a compound material containing the above element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used.

Next, a resist mask 16a is formed using a second photomask, and a first etching step is performed using an ICP etching apparatus. By the first etching step, the second conductive film 15 is etched,
As shown in FIG. 1B, a second conductive layer 17a having a tapered portion (tapered portion) at an end portion
Get.

Here, the angle of the tapered portion (taper angle)
Is defined as the angle between the substrate surface (horizontal plane) and the inclined portion of the tapered portion. The taper angle of the second conductive layer 17a can be set to 5 by appropriately selecting etching conditions.
It can be in the range of up to 45 °.

Next, second etching is performed using the resist mask 16a as it is using an ICP etching apparatus. In the second etching step, the first conductive film 14 is etched to form the first conductive film 14 as shown in FIG.
Is formed. The first conductive layer 18a has a first width (W1). As shown in FIG. 1, when the cross-sectional shape is a trapezoid, “width” is defined as indicating the length of the lower side of the trapezoid. At the time of this second etching, the resist mask, the second conductive layer, and the insulating film are also slightly etched, and the resist mask 16
b, a second conductive layer 17b and an insulating film 19a are formed.

In this case, two etchings (a first etching step and a second etching step) are performed in order to suppress the thickness of the insulating film 13 from being reduced. However, as shown in FIG. There is no particular limitation as long as an electrode structure (a laminate of the second conductive layer 17b and the first conductive layer 18a) can be formed, and the etching may be performed in a single etching step.

Next, a first doping step is performed while the resist mask 16b is left as it is. In this first doping step, through doping is performed via the insulating film 19a to form the high-concentration impurity regions 20 and 21. (Fig. 1 (D))

Next, using the resist mask 16b,
A third etching step is performed using an ICP etching apparatus. In the third etching step, the second conductive layer 17b is etched to form a second conductive layer 17b as shown in FIG.
Of the conductive layer 17c is formed. The second conductive layer 17c has a second width (W2). At the time of the third etching, the resist mask, the first conductive layer, and the insulating film are also slightly etched, and the resist mask 16
c, a first conductive layer 18b and an insulating film 19b are formed.

Next, an RIE etching apparatus or an ICP
A fourth etching step is performed using an etching device.
By this fourth etching step, the first conductive layer 18 is formed.
Part of the tapered portion b is removed. Here, the first width (W
The first conductive layer 18b having 1) has a third width (W).
The first conductive layer 18c having 3) was obtained. (Figure 2
(B))

In the present embodiment, the first conductive layer 18
c and the second conductive layer 17c laminated thereon serve as a gate electrode. In the fourth etching, the insulating film 1
9b is also etched to form an insulating film 19c.
Here, an example is shown in which a part of the insulating film is removed to expose the high-concentration impurity regions, but there is no particular limitation.

Next, a second doping step is performed while the resist mask 16c is left as it is. In this second doping step, through doping is performed via the tapered portion of the first conductive layer 18b and the insulating film 19b to form low-concentration impurity regions 24 and 25. (Figure 2
(C)) In the second doping step, the high concentration impurity region is also doped,
2, 23 are formed.

Thereafter, the resist mask 16c is removed,
The impurity element added to the semiconductor layer is activated. Next, after forming the interlayer insulating film 27, a contact hole reaching the high-concentration impurity region is formed using a third mask, and the electrodes 28 and 29 are formed using a fourth mask.

In this way, with four photomasks, FIG.
A TFT having the structure shown in FIG. 3D can be formed.

The TF formed according to the present embodiment is
The feature of T is that the channel formation region 26 and the drain region 23
Region 25a (GOLD region) overlapping with gate electrode 18c in low-concentration impurity region 25 provided between
And a region 25b not overlapping with the gate electrode (LDD region)
It is a point which has. The peripheral portion of the insulating film 19c, that is, the region 25b that does not overlap with the gate electrode and the regions above the high-concentration impurity regions 22 and 23 are tapered.

When the plasma doping method is used in the second doping step, the impurity concentration in the LDD region 25b is higher than that in the GOLD region 25a because the second conductive layer 18c is somewhat blocked.

(Embodiment 2) Embodiment 2 of the present invention will be described below with reference to FIGS.

This embodiment is similar to the first embodiment.
And the second etching step (FIG. 1C) is the same, and the same reference numeral is used. FIG. 3 (A) shows FIG.
FIG. 3B corresponds to FIG. 1B, and FIG. 3C corresponds to FIG. 1C.

First, according to the first embodiment, FIG.
The state of (C) is obtained. (FIG. 3 (C))

Next, using the resist mask 16b,
A third etching step is performed using an ICP etching apparatus. In the third etching step, the second conductive layer 17b is etched to form a second conductive layer 17b as shown in FIG.
Of the conductive layer 17c is formed. The second conductive layer 17c has a second width (W2). At the time of the third etching, the resist mask, the first conductive layer, and the insulating film are also slightly etched, and the resist mask 16
c, a first conductive layer 18b and an insulating film 19b are formed.
(FIG. 3 (D))

Next, a first doping step is performed while the resist mask 16c is left as it is. In this first doping step, through doping is performed via the insulating film 19b to form the high concentration impurity regions 20 and 21. (FIG. 4 (A))

Next, while the resist mask 16c is left as it is, an RIE etching apparatus or an ICP
A fourth etching step is performed using an etching device.
By this fourth etching step, the first conductive layer 18 is formed.
Part of the tapered portion b is removed. Here, the first width (W
The first conductive layer 18b having 1) has a third width (W).
The first conductive layer 18c having 3) was obtained. (FIG. 4
(B))

In the present embodiment, the first conductive layer 18
c and the second conductive layer 17c laminated thereon serve as a gate electrode. In the fourth etching, the insulating film 1
9b is also etched to form an insulating film 19c.
Here, an example in which a part of the insulating film is removed to expose the high-concentration impurity regions is shown; however, the present invention is not particularly limited. The high-concentration impurity regions may be covered with a thin insulating film.

Next, a second doping step is performed while the resist mask 16c is left as it is. In this second doping step, through doping is performed via the tapered portion of the first conductive layer 18b and the insulating film 19b to form low-concentration impurity regions 24 and 25. (FIG. 4
(C) During the second doping, the high-concentration impurity regions 20 and 21 are also doped, so that the high-concentration impurity regions 22 and 23 are formed.

Here, the second doping step is performed to form a low concentration impurity region. However, in the first doping step, the thickness of the tapered portion of the first conductive layer 18b and the insulating film Depending on the film thickness of 19b and the doping conditions, it is also possible to form a low-concentration impurity region simultaneously with a high-concentration impurity region. In that case, the second doping step becomes unnecessary.

Thereafter, the resist mask 16c is removed,
The impurity element added to the semiconductor layer is activated. Next, after an interlayer insulating film 27 is formed, a contact hole reaching the high-concentration impurity region is formed using a third mask, a conductive film is formed, and then the electrode 2 is formed using a fourth mask.
8 and 29 are formed.

In this manner, four photomasks are used to obtain FIG.
A TFT having the structure shown in FIG. 3D can be formed.

Further, the TF formed according to the present embodiment is
The feature of T is that the channel formation region 26 and the drain region 23
Region 25a (GOLD region) overlapping with gate electrode 18c in low-concentration impurity region 25 provided between
And a region 25b not overlapping with the gate electrode (LDD region)
It is a point which has. The peripheral portion of the insulating film 19c, that is, the region 25b that does not overlap with the gate electrode and the regions above the high-concentration impurity regions 20 and 21 are tapered.

In the second doping step, since the first conductive layer 18c is somewhat blocked, the LDD
The impurity concentration of the region becomes higher than the impurity concentration of the GOLD region.

(Embodiment 3) Embodiment 3 of the present invention will be described below with reference to FIGS.

This embodiment is similar to the first embodiment.
And the first etching step (FIG. 1B) is the same, and the same reference numerals are used. Further, FIG.
FIG. 5 (B) corresponds to FIG. 1 (B).

First, according to the first embodiment, FIG.
(B) state is obtained. (FIG. 5B) The second conductive layer 17a having the first width (X1) is formed by the first etching step.

Next, a first doping step is performed while the resist mask 16a is left as it is. In the first doping step, through doping is performed through the first conductive film 14 and the insulating film 13 using the second conductive layer 17a as a mask to form the high concentration impurity regions 30 and 31. (FIG. 5 (C))

By performing through doping in this manner, the doping amount implanted in the semiconductor layer can be controlled to a desired value.

Next, using the resist mask 16a as it is, a second etching step is performed using an ICP etching apparatus. By the second etching step, the first
Is etched to form a first conductive layer 34a as shown in FIG. First conductive layer 34a
Has a second width (X2). At the time of this second etching, the resist mask, the second conductive layer, and the insulating film are also slightly etched, so that the resist mask 32a and the second conductive layer 33a having the third width (X3) are respectively formed. An insulating film 35a is formed.

Next, using the resist mask 32a,
A third etching step is performed using an ICP etching apparatus. In the third etching step, the second conductive layer 33a is etched to form the second conductive layer 33a as shown in FIG.
Is formed. The second conductive layer 33b has a fourth width (X4). At the time of the third etching, the resist mask, the first conductive layer, and the insulating film are also slightly etched, and the resist mask 32
b, a first conductive layer 34b and an insulating film 35b are formed.
(FIG. 6 (A))

Next, while the resist mask 32b is left as it is, an RIE etching apparatus or an ICP
A fourth etching step is performed using an etching device.
By this fourth etching step, the first conductive layer 34
Part of the tapered portion b is removed. Here, the first width (X
The first conductive layer 34b having 2) has a fifth width (X
This resulted in a first conductive layer 34c having 5). (FIG. 6
(B))

In the present embodiment, the first conductive layer 34
c and the second conductive layer 33b laminated thereon serve as a gate electrode. In addition, at the time of this fourth etching, the insulating film 3
5b is also etched to form an insulating film 35c.
Here, an example in which a part of the insulating film is removed to expose the high-concentration impurity regions is shown; however, the present invention is not particularly limited. The high-concentration impurity regions may be covered with a thin insulating film.

Next, a second doping step is performed while the resist mask 32b is left as it is. Through-doping is performed by the second doping step via the tapered portion of the first conductive layer 34b and the insulating film 35b to form low-concentration impurity regions 38 and 39. (FIG. 6
(C)) At the time of the second doping, the high concentration impurity regions 30 and 31 are also doped, and the high concentration impurity regions 36 and 37 are formed.

After that, the resist mask 32b is removed,
The impurity element added to the semiconductor layer is activated. Next, after an interlayer insulating film 41 is formed, a contact hole reaching the high-concentration impurity region is formed using a third mask, a conductive film is formed, and then the electrode 4 is formed using a fourth mask.
2, 43 are formed.

In this way, four photomasks are used to obtain FIG.
A TFT having the structure shown in FIG. 3D can be formed.

The TF formed according to the present embodiment is
The feature of T is that the channel formation region 40 and the drain region 37
In the low-concentration impurity region 39 provided between the gate electrode (33b and 34c) and the region 39a (G
OLD region) and a region 39b not overlapping with the gate electrode
(LDD region). Further, the peripheral portion of the insulating film 35c, that is, the region 3 not overlapping with the gate electrode.
9b and the region above the high concentration impurity regions 37 and 36 are tapered.

In the second doping step, since the first conductive layer 34b is somewhat blocked, the LDD
The impurity concentration of the region becomes higher than the impurity concentration of the GOLD region.

(Embodiment 4) Embodiment 4 of the present invention will be described below with reference to FIGS.

The present embodiment is similar to the third embodiment.
And the first doping step (FIG. 5C) is the same, and the description is omitted. Also, here, the description will be made using the same reference numerals as those in FIG. 7A corresponds to FIG. 5A, FIG. 7B corresponds to FIG. 5B, and FIG.
Corresponds to FIG. 5 (C).

First, according to the first embodiment, FIG.
The state of (C) is obtained. (FIG. 7 (C))

Next, using the resist mask 16a,
A second etching step is performed using an ICP etching apparatus. In the second etching step, the second conductive layer 17a is etched to form a second conductive layer 17a as shown in FIG.
Is formed. The second conductive layer 51 has a second width (Y2). At the time of the second etching, the resist mask and the first conductive film are also slightly etched to form the resist mask 50 and the first conductive film 52a, respectively. (FIG. 7D) Note that a part of the first conductive film 52a has already been slightly etched in the first etching step, and thus is further thinned by the second etching step. . Also, the second
Out of the first conductive film 52a which does not overlap with the conductive layer of
Portions not etched during the first etching step have a tapered shape.

Next, a third etching step is performed using an RIE etching apparatus or an ICP etching apparatus while keeping the resist mask 50 as it is. By the third etching step, of the exposed first conductive film 52a, a part thinned by the first etching step and a part of a tapered part are removed. Here, by appropriately adjusting the etching conditions in consideration of the thickness of the first conductive film, the thickness of the insulating film, and the like, the first film having a tapered shape and having the third width (Y3) is obtained. Of the conductive layer 52b is formed. (FIG. 8A)

In the present embodiment, the first conductive layer 52
b and the second conductive layer 51 laminated thereon serve as a gate electrode. During the third etching, the insulating film 13
Is also etched to form an insulating film 57.

Next, a second doping step is performed while the resist mask 50 is left as it is. In this second doping step, through doping is performed through the tapered portion of the first conductive film 52a and the insulating film 13 to form low-concentration impurity regions 53 and 54. (FIG. 8 (B))
During the second doping, the high-concentration impurity regions 3
0 and 31 are also doped, and the high-concentration impurity regions 55,
56 are formed.

By performing through doping in this manner, the doping amount implanted in the semiconductor layer can be controlled to a desired value.

After that, the resist mask 50 is removed, and the impurity element added to the semiconductor layer is activated. Next, after forming an interlayer insulating film 59, a contact hole reaching the high-concentration impurity region is formed using a third mask, a conductive film is formed, and then the electrode 6 is formed using a fourth mask.
0 and 61 are formed.

In this way, the four photomasks can be used as shown in FIG.
A TFT having the structure shown in FIG. 3C can be formed.

The TF formed according to the present embodiment is
The feature of T is that the channel formation region 58 and the drain region 56
In the low-concentration impurity region 54 provided between the gate electrode (51 and 52b) and the region 54a (GO
LD region) and a region 54b (L
DD area).

Further, during the second doping step, since the first conductive layer 52b is somewhat blocked,
The impurity concentration of the region becomes higher than the impurity concentration of the GOLD region.

(Embodiment 5) Embodiment 5 of the present invention will be described below with reference to FIGS.

This embodiment is similar to the third embodiment.
And the first doping step (FIG. 5C) is the same, and the description is omitted. Also, here, the description will be made using the same reference numerals as those in FIG. 9A corresponds to FIG. 5A, FIG. 9B corresponds to FIG. 5B, and FIG.
Corresponds to FIG. 5 (C).

First, according to the first embodiment, FIG.
The state of (C) is obtained. (FIG. 9 (C))

Next, using the resist mask 16a,
A second etching step is performed using an ICP etching apparatus.

In the fourth embodiment, an example in which the first conductive film is left on the entire surface has been described. However, in the present embodiment, the first conductive film 17a which is not covered with the second conductive layer 17a during the second etching step is used. Is removed.

By the second etching step, the second
The conductive layer 17a and the first conductive film 14 are etched to form the second conductive layer 71 and the first conductive film 72 as shown in FIG. The first conductive film 72 has a second width (Z
2), and the second conductive layer 71 has a third width (Z3). At the time of the second etching, the resist mask and the insulating film 13 are also slightly etched to form the resist mask 70 and the insulating film 73, respectively.
(FIG. 9 (D))

In this embodiment, the first conductive layer 72
And the second conductive layer 71 laminated thereon becomes a gate electrode.

Next, a second doping step is performed while the resist mask 70 is left as it is. In this second doping step, through doping is performed through the tapered portion of the first conductive film 72 and the insulating film 73 to form low-concentration impurity regions 73 and 74. (FIG. 10A)
During the second doping, the high-concentration impurity regions 3
0, 31 are also doped, and the high-concentration impurity regions 75,
76 is formed.

By performing through doping in this manner, the doping amount implanted in the semiconductor layer can be controlled to a desired value.

After that, the resist mask 70 is removed, and the impurity element added to the semiconductor layer is activated. Next, after forming an interlayer insulating film 79, a contact hole reaching the high-concentration impurity region is formed using a third mask, a conductive film is formed, and then the electrode 8 is formed using a fourth mask.
0 and 81 are formed.

In this way, four photomasks can be used as shown in FIG.
A TFT having the structure shown in FIG.

The TF formed according to the present embodiment is
The feature of T is that the channel formation region 78 and the drain region 76
In the low-concentration impurity region 74 provided between the gate electrode (71 and 72) and the region 74a (GOL).
D region) and a region 74b that does not overlap with the gate electrode (LD region)
D region).

In the second doping step, the impurity concentration in the LDD region is higher than the impurity concentration in the GOLD region, because the impurity concentration is somewhat blocked by the first conductive layer 72.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0097]

[Embodiment 1] Here, a method for simultaneously manufacturing a pixel portion and a TFT (n-channel TFT and p-channel TFT) of a driving circuit provided around the pixel portion on the same substrate is described in detail. This will be described with reference to FIGS.

First, in this embodiment, Corning # 70
A substrate 100 made of glass such as barium borosilicate glass represented by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that the substrate 100 is not limited as long as it is a light-transmitting substrate, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a silicon oxide film is formed on the substrate 100,
A base film 101 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. Although a two-layer structure is used as the base film 101 in this embodiment, a single-layer film of the insulating film or a structure in which two or more insulating films are stacked may be used. For the first layer of the base film 101, a plasma CVD
iH _4, NH _3, a and N ₂ O silicon oxynitride film 101a is formed as the reaction gas 10 to 200 nm (preferably 50 to 100 nm) is formed. In this embodiment, the film thickness 5
0 nm silicon oxynitride film 101a (composition ratio Si = 3
2%, O = 27%, N = 24%, H = 17%). Next, as the second layer of the base film 101, a silicon oxynitride film 101 b formed using SiH ₄ and N ₂ O as a reaction gas by plasma CVD is used to form a 50-200 layer.
nm (preferably 100 to 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 101b (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%).

Next, the semiconductor layers 102 to 10 are formed on the underlying film.
5 is formed. The semiconductor layers 102 to 105 are formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCV
D method or plasma CVD method)
A crystalline semiconductor film obtained by performing a known crystallization treatment (such as a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalyst such as nickel) is patterned and formed into a desired shape. . The thickness of the semiconductor layers 102 to 105 is 2
It is formed with a thickness of 5 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon or silicon germanium (Si _x Ge).
_1-X (0 <X <1, typically X = 0.0001 to 0.
05)) It is good to form with an alloy etc. When silicon germanium is formed, it may be formed by a plasma CVD method using a mixed gas of silane and germanium, germanium may be ion-implanted into a silicon film, or sputtered using a target made of silicon germanium. It may be formed by a method. In this embodiment, a 55-nm-thick amorphous silicon film is formed by a plasma CVD method, and then a solution containing nickel is held on the amorphous silicon film.
Dehydrogenation of this amorphous silicon film (500 ° C, 1 hour)
After that, thermal crystallization (550 ° C., 4 hours) was performed, and further, a laser annealing treatment for improving crystallization was performed to form a crystalline silicon film. Then, semiconductor layers 102 to 105 were formed by patterning the crystalline silicon film using a photolithography method.

After the formation of the semiconductor layers 102 to 105, a small amount of impurity element (boron or phosphorus) may be doped (also called channel doping) in order to control the threshold value of the TFT.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 40.
(Typically ^{200~300mJ / cm 2) 0mJ / cm} 2 to. When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 1 to 10 kHz, and the laser energy density is set to 300 to 600 mJ / cm ² (typically 35 to
0 to 500 mJ / cm ² ). And width 100-1
A laser beam condensed linearly at 000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is 80 to 98%.
What should be done.

Next, a gate insulating film 106 covering the semiconductor layers 102 to 105 is formed. It is preferable that the surface of the semiconductor layer be cleaned before forming the gate insulating film. To remove contaminant impurities (typically C, Na, etc.) on the surface of the coating, clean the surface of the coating with a fluorine-containing acidic solution after cleaning with pure water containing ozone. It can be done by: As a means for etching very thinly, a method of spinning a substrate using a spin device and scattering an acidic solution containing fluorine brought into contact with the surface of the coating film is effective. As the acidic solution containing fluorine, use hydrofluoric acid, diluted hydrofluoric acid, ammonium fluoride, buffered hydrofluoric acid (a mixed solution of hydrofluoric acid and ammonium fluoride), or a mixed solution of hydrofluoric acid and aqueous hydrogen peroxide Can be. After the cleaning, the gate insulating film 107 is continuously formed to a thickness of 40 using a plasma CVD method or a sputtering method.
The insulating film containing silicon is formed to have a thickness of 150 nm, preferably 50 nm to 100 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2) with a thickness of 110 nm by a plasma CVD method.
%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used,
TEOS (Tetraethyl Orthosilica) by plasma CVD
te) and O ₂ , a reaction pressure of 40 Pa, and a substrate temperature of 30
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² at 0 to 400 ° C. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, as shown in FIG. 11A, a first conductive film 107 having a thickness of 20 to 100 nm and a second conductive film 1 having a thickness of 100 to 400 nm are formed on the gate insulating film 106.
08 are laminated. Further, it is preferable that the gate insulating film, the first conductive film, and the second conductive film be formed successively without exposure to the air in order to prevent contamination. In the case where the film is not continuously formed, the contamination at the film interface can be prevented by using a film forming apparatus with a cleaning machine. The cleaning method may be the same as that performed before forming the gate insulating film. In this embodiment, a first conductive film 107 made of a TaN film having a thickness of 30 nm and a second conductive film 108 made of a W film having a thickness of 370 nm are formed continuously. The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set it to 0 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains.
When there are many impurity elements such as oxygen in the film, crystallization is hindered and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity of 99.9999%) target, and further taking into consideration that impurities from the gas phase are not mixed during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 107 is used.
Is TaN, and the second conductive film 108 is W. However, the present invention is not particularly limited, and any of Ta, W, Ti, Mo, Al, Cu,
It may be formed of an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, A
A gPdCu alloy may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, and the first conductive film is formed of a titanium nitride (TiN) film. As a W film, the first
The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of a tantalum nitride (TaN) film. May be combined.

Next, masks 109 to 112 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, the first etching condition is I
Using a CP (Inductively Coupled Plasma) etching method, using CF ₄ , Cl _2, and O _{2 as} etching gases, and using a gas flow ratio of 25/2.
At 5/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to form the first film.
Of the conductive layer is tapered. The etching rate for W under the first etching condition is 200.39 n.
m / min, etching rate for TaN is 80.3
At 2 nm / min, the selectivity ratio of W to TaN is about 2.5. Further, the taper angle of W is about 26 ° under the first etching condition. Note that the etching under the first etching condition here corresponds to the first etching step (FIG. 1B) described in Embodiment 1.

Thereafter, the masks 109-
The second etching condition was changed without removing 112, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30/30 (sccm), and the pressure was 1 Pa to form a coil-type electrode. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%. Note that the etching under the second etching condition here corresponds to the second etching step (FIG. 1C) described in Embodiment 1.

In the first etching process, by making the shape of the mask made of resist suitable,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 degrees. Thus, the first shape conductive layers 113 to 116 (the first conductive layers 113 a to 116 a and the second conductive layer 113 b) including the first conductive layer and the second conductive layer are formed by the first etching process.
To 116b). Here, the width of the first conductive layer in the channel length direction is equal to the width of W shown in the first embodiment.
Equivalent to 1. Note that “width” refers to the width in a cross section of the conductive layer cut in the channel length direction. When the cross-sectional shape in the channel length direction is trapezoidal as shown in FIG. Shall refer to the length of 11
Reference numeral 7 denotes a gate insulating film, and the first shape conductive layers 113 to
The region not covered with 116 is etched by about 20 to 50 nm to form a thinned region.

Then, a first doping process is performed without removing the resist mask to add an impurity element imparting n-type to the semiconductor layer. (FIG. 11B) The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10
^{13 to} 5 × 10 ¹⁵ atoms / cm ² and an acceleration voltage of 60 to 10
The operation is performed at 0 keV. In this embodiment, the dose amount is 1.5 ×
The test was performed at 10 ¹⁵ atoms / cm ² and an acceleration voltage of 80 keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 113 to 116 serve as a mask for the impurity element imparting n-type, and are self-aligned with the high concentration impurity regions 118 to 1.
21 are formed. An impurity element imparting n-type is added to the high concentration impurity regions 118 to 121 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . The first here
The doping process corresponds to the first doping step (FIG. 1D) described in Embodiment 1.

Next, a second etching process is performed without removing the resist mask. (FIG. 11C) Here, CF ₄ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are 25/25/10 (scc).
m) and 500 W of R on the coil-type electrode at a pressure of 1 Pa
F (13.56 MHz) power was applied to generate plasma to perform etching. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. The etching rate for W in the second etching process is 124.62 nm / min, and Ta is
The etching rate for N is 20.67 nm / min, and the selectivity ratio of W to TaN is 6.05. Therefore, the W film is selectively etched. The taper angle of W became 70 ° by the second etching. By this second etching process, the second conductive layers 122b to 122b-1
25b is formed. On the other hand, the first conductive layers 113a to 113a
6a is hardly etched and the first conductive layer 12
2a to 125a are formed. Note that the second etching treatment here corresponds to the third etching step (FIG. 2A) described in Embodiment 1. The width of the second conductive layer in the channel length direction here corresponds to W2 described in Embodiment 1.

Next, a third etching process is performed without removing the resist mask. In the third etching treatment, the tapered portion of the first conductive layer is partially etched to reduce a region overlapping with the semiconductor layer. In the third etching process, CH gas is used as an etching gas.
This is performed using a reactive ion etching method (RIE method) using F ₃ . In this embodiment, the chamber pressure is 6.7P
a, RF power 800 W, CHF ₃ gas flow rate 35 sccm
A third etching process was performed. By the third etching, first conductive layers 138 to 142 are formed. (FIG. 11D) The third etching treatment here is as follows.
The fourth etching step described in Embodiment 1 (FIG.
(B)). Further, the width of the first conductive layer in the channel length direction here corresponds to W3 described in Embodiment 1.

At the time of the third etching process, the insulating film 1
17 is also etched to form the high-concentration impurity regions 130-1.
33 are exposed, and the insulating films 143a to 143d, 14
4 are formed. In this embodiment, the etching conditions in which a part of the high-concentration impurity regions 130 to 133 are exposed are used. However, if the thickness of the insulating film and the etching conditions are changed,
A thin insulating film may be left in the high-concentration impurity region.

The electrode formed by the first conductive layer 138 and the second conductive layer 122b serves as a gate electrode of an n-channel TFT of a driving circuit formed in a later step, and the first conductive layer The electrode formed by the transistor 139 and the second conductive layer 123b serves as a gate electrode of a p-channel TFT of a driver circuit formed in a later step. Similarly, the first conductive layer 1
The electrode formed by the first conductive layer 141 and the second conductive layer 12b becomes a gate electrode of an n-channel TFT of a pixel portion formed in a later step.
5b becomes one electrode of the storage capacitor of the pixel portion formed in a later step.

Next, a second doping process is performed to
The state of 12 (A) is obtained. Doping is performed on the second conductive layer 1
22b-125b used as a mask for impurity elements
Impurity in the semiconductor layer below the tapered portion of the first conductive layer.
The plasma doping method or the
Doping is performed using an on-injection method. In this embodiment,
P (phosphorus) was used as a pure element, and the dose amount was 3.5 × 1.
0¹²atoms / cm^Two, Plasma doping at accelerating voltage 90 keV
Ping was done. Thus, the low concentration overlapping the first conductive layer
Impurity regions 126 to 129 are formed in a self-aligned manner.
Phosphorus added to these low-concentration impurity regions 126 to 129
The concentration of (P) is 1 × 10¹⁷~ 1 × 10 ¹⁸atoms / cm^Threeso
is there. Note that a semiconductor overlapping with the tapered portion of the first conductive layer
In the layer, inside from the end of the tapered portion of the first conductive layer
, The impurity concentration decreases. Also, Takano
Impurity elements are also added to impurity regions 118-121.
As a result, high concentration impurity regions 130 to 133 are formed. What
Here, the second doping process is performed in the first embodiment.
This corresponds to the described second doping step (FIG. 2C).
You.

By the second doping step, the first
Impurity regions that do not overlap with the conductive layers 138 to 142 (LD
D regions) 134a to 137a are formed. Note that the impurity regions (GOLD regions) 134b to 137b remain overlapped with the first conductive layers 138 to 142.

Next, after removing the resist mask, new masks 145 and 146 are formed and a third doping process is performed. Due to this third doping process, the semiconductor layer serving as the active layer of the p-channel TFT has a conductivity type (p-type) opposite to the one conductivity type (n-type).
Region 14 to which an impurity element for imparting (type) is added
7 to 152 are formed. (FIG. 12B) Using the first conductive layers 139 and 142 as a mask for an impurity element, an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity region 14
7 to 152 are formed by an ion doping method using diborane (B ₂ H ₆ ). During the third doping process, the semiconductor layers forming the n-channel TFT are covered with resist masks 145 and 146. Phosphorus is added at different concentrations to the impurity regions 145 and 146 by the first doping process and the second doping process, and the concentration of the impurity element imparting p-type is 2 × in each of the regions. 10 ^{20 to} 2 × 10 ²¹
By performing the doping process so as to be atoms / cm ³ , no problem occurs because the doping process functions as the source region and the drain region of the p-channel TFT. In the present embodiment, the p-channel type T
Since a part of the semiconductor layer serving as the active layer of the FT was exposed,
There is an advantage that an impurity element (boron) can be easily added.

Through the above steps, a desired impurity region is formed in each semiconductor layer.

Next, a mask 145 made of resist is used.
146 is removed to form a first interlayer insulating film (a) 153a. The first interlayer insulating film (a) 153a is formed of an insulating film containing silicon with a thickness of 50 to 100 nm by using a plasma CVD method or a sputtering method. In this embodiment, the film thickness is 50 n by the plasma CVD method.
m of silicon oxynitride film was formed. Needless to say, the first interlayer insulating film (a) 153a is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, a step of activating the impurity element added to each semiconductor layer is performed. (FIG. 12
(C) This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, an oxygen concentration of 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to 55 ° C.
The activation may be performed at 0 ° C., and in this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the above-mentioned activation treatment, nickel used as a catalyst at the time of crystallization contains impurity regions (130, 132, 147, 147) containing a high concentration of phosphorus.
The nickel concentration in the semiconductor layer which is gettered 150) and mainly becomes a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

The activation treatment may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

As another activation treatment, a laser annealing method, for example, irradiation with a laser beam such as an excimer laser or a YAG laser can be performed.

Next, a first interlayer insulating film (b) 153b
To form The first interlayer insulating film (b) 153b is formed of an insulating film containing silicon with a thickness of 50 to 200 nm by using a plasma CVD method or a sputtering method. In this embodiment, a film thickness of 10
A 0-nm-thick silicon nitride film was formed. Needless to say, the first interlayer insulating film (b) 153b is not limited to the silicon nitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Next, 300 to 55 in an inert atmosphere.
A heat treatment is performed at 0 ° C. for 1 to 12 hours to hydrogenate the semiconductor layer. This hydrogenation is desirably at a temperature (400 to 500 ° C.) lower than the heat treatment temperature in the activation treatment. (FIG. 12D) In this example, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation,
300-550 in an atmosphere containing 3-100% hydrogen
Hydrogenation by heat treatment at 1 ° C. for 1 to 12 hours or plasma hydrogenation (using hydrogen excited by plasma) may be performed.

The masks 145, 1 made of resist
After removing 46, thermal activation (typically at 500 to 550 ° C. in a nitrogen atmosphere) is performed to form a first interlayer insulating film (typically, having a thickness of 100 to 20) made of an insulating film containing silicon.
After forming a 0-nm-thick silicon nitride film), hydrogenation (at 300 to 500 ° C. in a nitrogen atmosphere) may be performed.

Next, a first interlayer insulating film (b) 153b
A second interlayer insulating film 154 made of an organic insulating material is formed thereon. In this embodiment, an acrylic resin film having a thickness of 1.6 μm was formed.

Next, a transparent conductive film is formed with a thickness of 80 to 120 nm on the second interlayer insulating film 154, and the pixel electrode 162 is formed by patterning. The transparent conductive film is made of an indium zinc oxide alloy (In ₂ O ₃ —Zn
O) and zinc oxide (ZnO) are also suitable materials, and gallium (G) is used to further increase the transmittance and conductivity of visible light.
Zinc oxide (ZnO: Ga) to which a) is added can be suitably used.

[0129] Although an example in which a transparent conductive film is used as a pixel electrode is described here, a reflective display device can be manufactured by forming a pixel electrode using a conductive material having reflectivity. Can be.

Next, each of the impurity regions 130, 132, 1
Patterning for forming contact holes reaching 47 and 150 is performed.

Then, in the drive circuit 205, electrodes 155 to 161 electrically connected to the impurity regions 130 or 147 are formed. These electrodes are composed of a 50 nm thick Ti film and a 500 nm thick Ti film.
Is formed by patterning a laminated film of an alloy film (an alloy film of Al and Ti).

In the pixel portion 206, the connection electrode 160 in contact with the impurity region 132 or the source electrode 1
59, and the connection electrode 16 in contact with the impurity region 150 is formed.
Form one. Note that the connection electrode 160 is connected to the pixel electrode 16.
2 forms an electrical connection with the drain region of the pixel TFT, and further forms an electrical connection with the semiconductor layer (impurity region 150) functioning as one electrode forming a storage capacitor. Is done. (FIG. 13)

As described above, the n-channel TFT 20
Drive circuit 20 having 1 and p-channel type TFT 202
5 and a pixel portion 206 having a pixel TFT 203 and a storage capacitor 204 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

N-channel TFT 20 of drive circuit 205
Reference numeral 1 denotes a low-concentration impurity region 13 overlapping the channel formation region 163 and the first conductive layer 138 forming a part of the gate electrode.
4b (GOLD region), a low concentration impurity region 134a (LDD region) formed outside the gate electrode, and a high concentration impurity region 1 functioning as a source region or a drain region.
30. The p-channel type TFT 202 includes a channel forming region 164 and a first part forming a part of a gate electrode.
Impurity region 149 overlapping with the conductive layer 139, an impurity region 148 formed outside the gate electrode, and an impurity region 147 functioning as a source or drain region.

In the pixel TFT 203 of the pixel portion 206, a channel formation region 165 and a low concentration impurity region 136b (GOLD) overlapping the first conductive layer 140 forming a gate electrode are provided.
Region), a low-concentration impurity region 136a (LDD region) formed outside the gate electrode, and a high-concentration impurity region 132 functioning as a source or drain region. Each of the semiconductor layers 150 to 152 functioning as one electrode of the storage capacitor 204 is doped with an impurity element imparting p-type. The storage capacitor 204 includes the electrodes 125 and 142 and the semiconductor layers 150 to 152 and 166 using the insulating film 144 as a dielectric.

In addition, according to the steps described in this embodiment, the number of photomasks required for manufacturing the active matrix substrate can be six. As a result, the process is shortened,
This can contribute to reduction in manufacturing cost and improvement in yield.

[Embodiment 2] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below.
FIG. 14 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state shown in FIG. 13, an alignment film 167 is formed on the active matrix substrate shown in FIG. 13 and rubbing is performed. In this embodiment, before forming the alignment film 167, a columnar spacer for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 168 is prepared. The opposite substrate 168 is provided with a color filter in which a coloring layer 174 and a light shielding layer 175 are arranged corresponding to each pixel. Further, a light-blocking layer 177 was provided also in a portion of the driver circuit. A flat interlayer insulating film 176 covering the color filter and the light shielding layer 177 was provided. Next, a counter electrode 169 made of a transparent conductive film was formed in the pixel portion over the flat interlayer insulating film 176, an alignment film 170 was formed over the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealing material 171.
Paste in. A filler is mixed in the sealant 171, and the two substrates are bonded at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 173 is injected between the two substrates, and completely sealed with a sealing agent (not shown). As the liquid crystal material 173, a known liquid crystal material may be used. Thus, the active matrix liquid crystal display device shown in FIG. 14 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a retardation plate, a polarizing plate, and the like were appropriately provided using a known technique. Then, an FPC was attached using a known technique.

The structure of the liquid crystal display panel thus obtained will be described with reference to the top view of FIG. Note that the same reference numerals are used for portions corresponding to those in FIG.

A top view shown in FIG. 15A shows a pixel portion, a driving circuit, an FPC (Flexible Printed Wiring Board: Flexib
le Printed Circuit) external input terminal 20
7. an active matrix substrate on which wirings 208 connecting the external input terminals to the input portions of the respective circuits are formed;
An opposite substrate 168 provided with a color filter and the like is attached to each other with a sealant 171 interposed therebetween.

A light-shielding layer 177a is provided on the counter substrate side so as to overlap with the gate wiring side drive circuit 205a, and a light-shielding layer 177b is formed on the counter substrate side so as to overlap with the source wiring side drive circuit 205b. In the color filter 209 provided on the counter substrate side over the pixel portion 206, a light-shielding layer and colored layers of red (R), green (G), and blue (B) are provided for each pixel. Have been. When actually displaying, a red (R) colored layer, a green (G) colored layer,
A color display is formed by three colors of a blue (B) colored layer.
The arrangement of the colored layers of these colors is arbitrary.

Here, the color filter 209 is provided on the opposite substrate in order to achieve colorization. However, the present invention is not particularly limited. When an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.

Further, a light-shielding layer is provided between adjacent pixels in the color filter to shield a portion other than the display area from light. Here, although the light-blocking layers 177a and 177b are provided also in a region covering the driving circuit, the region covering the driving circuit is covered with a cover when the liquid crystal display device is later incorporated as a display portion of an electronic device. A structure without a light-blocking layer may be employed. When an active matrix substrate is manufactured, a light-blocking layer may be formed on the active matrix substrate.

Further, without providing the above-described light-shielding layer, a colored layer constituting a color filter is appropriately arranged between the opposing substrate and the opposing electrode so as to shield the light by a stacked layer of a plurality of layers, and a portion other than the display region ( The gap between each pixel electrode) and the driving circuit may be shielded from light.

The base film 2 is connected to the external input terminal.
FPC made up of anisotropic conductive resin 2
12 are pasted together. Furthermore, the mechanical strength is enhanced by the reinforcing plate.

FIG. 15B is a sectional view taken along line EE ′ of the external input terminal 207 shown in FIG. Since the outer diameter of the conductive particles 214 is smaller than the pitch of the wiring 215, if the amount of dispersion in the adhesive 212 is made appropriate, the corresponding F can be formed without short-circuiting with the adjacent wiring.
An electrical connection can be formed with the wiring on the PC side.

The liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.

[Embodiment 3] In this embodiment, a method of manufacturing an active matrix substrate different from that of Embodiment 1 will be described with reference to FIG.
This will be described with reference to FIG. In the first embodiment, a transmissive display device is formed. In the present embodiment, a reflective display device is formed.
The feature is that the number of masks is reduced as compared with the first embodiment.

The first embodiment differs from the first embodiment in that the second interlayer insulating film 15
Since the steps up to the step of forming No. 4 are the same, the description is omitted here.

After forming the second interlayer insulating film according to the first embodiment, patterning for forming contact holes reaching each impurity region is performed.

Next, in the drive circuit, similarly to Embodiment 1, electrodes electrically connected to a part of the semiconductor layer (high-concentration impurity region) are formed. Note that these electrodes are formed by patterning a laminated film of a 50-nm-thick Ti film and a 500-nm-thick alloy film (an alloy film of Al and Ti).

In the pixel portion, a pixel electrode 1202 in contact with the high-concentration impurity region 1200 or a source electrode 1203 in contact with the high-concentration impurity region 1201 is formed. Note that the pixel electrode 1202 is electrically connected to the high-concentration impurity region 1200 of the pixel TFT, and is electrically connected to a semiconductor layer (high-concentration impurity region 1204) functioning as one electrode forming a storage capacitor. Is formed. (FIG. 16)

The material of the pixel electrode 1202 is as follows.
It is desirable to use a material having excellent reflectivity, such as a film containing Al or Ag as a main component or a stacked film thereof.

In addition, according to the steps described in this embodiment, the number of photomasks required for manufacturing an active matrix substrate can be reduced to five. As a result, the process is shortened,
This can contribute to reduction in manufacturing cost and improvement in yield.

After the formation of the pixel electrode, a known process such as a sand blast method or an etching method is added to make the surface uneven, thereby preventing specular reflection and scattering the reflected light to increase whiteness. Is preferred. Also,
Before the pixel electrode is formed, the unevenness may be formed on the insulating film, and the pixel electrode may be formed thereon.

[Embodiment 4] In this embodiment, a process for manufacturing a reflection type liquid crystal display device from the active matrix substrate manufactured in Embodiment 3 will be described below. FIG. 17 is used for the description.

First, according to the third embodiment, after an active matrix substrate in the state shown in FIG. 16 is obtained, an alignment film is formed on at least the pixel electrode on the active matrix substrate shown in FIG. 16 and a rubbing process is performed. In this example, before forming the alignment film, a columnar spacer (not shown) for maintaining the substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 1304 is prepared. The opposite substrate is provided with a color filter in which a coloring layer and a light shielding layer are arranged corresponding to each pixel. Next, a flat interlayer insulating film covering the color filter is formed.

Next, a counter electrode made of a transparent conductive film was formed on at least the pixel portion on the flat interlayer insulating film, an alignment film was formed on the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the pixel portion 1301 and the driving circuit 130
The active matrix substrate 1303 on which the substrate 2 is formed and the opposing substrate 1304 are bonded with a sealant 1306.
A filler is mixed in the sealing material 1306.
Two substrates are bonded. Thereafter, a liquid crystal material 1305 is injected between the two substrates, and completely sealed with a sealant. As the liquid crystal material 1305, a known liquid crystal material may be used. Since the present embodiment is a reflection type, the distance between the substrates is about half as compared with the second embodiment. Thus, a reflective liquid crystal display device is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, only the opposing substrate is provided with a retardation plate and a polarizing plate 1.
307 was pasted. Then, using a known technique, FP
C was pasted.

The reflection type liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.

Further, if the liquid crystal display panel alone is used in a dark place, there is a problem in visibility. Therefore,
It is desirable to provide a configuration including a light source, a reflector, and a light guide plate as shown in FIG.

As the light source, one or more LEDs or cold cathode tubes may be used. As shown in FIG. 17, the light source is arranged along the side surface of the light guide plate, and a reflector is provided behind the light source.

When the light emitted from the light source efficiently enters the inside of the light guide plate from the side surface by the reflector, the light is reflected by the special prism processing surface provided on the surface and enters the liquid crystal display panel.

By combining the liquid crystal display panel, the light source and the light guide plate in this manner, the light use efficiency can be improved.

[Embodiment 5] This embodiment shows an example of a manufacturing method different from that of Embodiment 1. This embodiment is different from the first embodiment only in the steps up to the formation of the semiconductor layers 102 to 105, and the subsequent steps are the same as the first embodiment.
Omitted.

First, a substrate is prepared as in the first embodiment.
In the case of manufacturing a transmissive display device, a glass substrate, a quartz substrate, or the like can be used as a substrate. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used. In the case of manufacturing a reflective display device, a reflective substrate in which an insulating film is formed over a surface of a ceramic substrate, a silicon substrate, a metal substrate, or a stainless steel substrate may be used.

Next, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film or a silicon oxynitride film is formed on the substrate. Although a two-layer structure is used as the base film in this embodiment, a single-layer film of the insulating film or a structure in which two or more insulating films are stacked may be used. In this embodiment, the first and second layers of the base film are continuously formed in a first film formation chamber by using a plasma CVD method. As the first layer of the base film, a silicon oxynitride film formed by using a plasma CVD method with SiH ₄ , NH ₃ , and N ₂ O as a reaction gas is 10-2.
A thickness of 00 nm (preferably 50 to 100 nm) is formed. In this embodiment, a 50 nm-thick silicon oxynitride film (composition ratio S
i = 32%, O = 27%, N = 24%, H = 17%). Next, as a second layer of the base film, a silicon oxynitride film to be formed with a thickness of 50 to 200 nm (preferably 100 to 150 nm) by using a plasma CVD method with SiH ₄ and N ₂ O as a reaction gas. To form a laminate. In this embodiment, a 100-nm-thick silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%)
Was formed.

Next, an amorphous semiconductor film is formed on the base film in the second film forming chamber. The amorphous semiconductor film has a thickness of 30 to 60.
It is formed with a thickness of nm. Although there is no limitation on the material of the amorphous semiconductor film, it is preferable to use silicon or a silicon-germanium alloy. In this embodiment, an amorphous silicon film is formed by a plasma CVD method using SiH ₄ gas.

Further, since the base film and the amorphous semiconductor film can be formed by the same film forming method, the base film and the amorphous semiconductor film can be formed continuously.

Next, Ni is added to the amorphous silicon film in the third film forming chamber. Using a plasma CVD method, an electrode containing Ni as a material is attached, argon gas or the like is introduced, plasma is generated, and Ni is added. Of course, an ultra-thin Ni film may be formed using a vapor deposition method or a sputtering method.

Next, a protective film is formed in the fourth film forming chamber. As the protective film, a silicon oxide film, a silicon oxynitride film, or the like is preferably used. It is better not to use a dense film such as a silicon nitride film because dehydrogenation in a later step is difficult to remove hydrogen. In this embodiment, the plasma C
Using the VD method, TEOS (Tetraethyl Orthosilicat
e) and O ₂ are mixed to form a silicon oxide film having a thickness of 100 to 150 nm. The present embodiment is characterized in that the process up to the formation of a silicon oxide film as a protective film is continuously performed without exposing the silicon oxide film to a clean room atmosphere.

The films formed in each of the above film forming chambers are:
Any known forming means such as a plasma CVD method, a thermal CVD method, a reduced pressure CVD method, an evaporation method, a sputtering method, and the like can be used.

Next, dehydrogenation of the amorphous silicon film (5
(At 00 ° C. for 1 hour) and thermal crystallization (at 550 ° C. for 4 hours). Note that the method is not limited to the method of adding a catalyst element such as Ni shown in this embodiment, and thermal crystallization may be performed by a known method.

Then, in order to control the threshold value (Vth) of the n-channel TFT, an impurity element imparting p-type is added. As the impurity element imparting p-type to the semiconductor, an element belonging to Group 13 of the periodic rule such as boron (B), aluminum (Al), and gallium (Ga) is known. In this embodiment, boron (B) is added.

After the addition of boron, the silicon oxide film serving as a protective film is removed using an etching solution such as hydrofluoric acid. Next, continuous processing of cleaning and laser annealing is performed. By adding boron (B), which is an impurity element imparting p-type, to the amorphous semiconductor film and then performing laser annealing, the boron also becomes part of the crystal structure of the crystalline semiconductor film and is crystallized. To do so, it is possible to prevent the destruction of the crystal structure that occurs in the prior art.

Here, by using pure water containing ozone and an acidic solution containing fluorine, an ultra-thin oxide film formed when washing with pure water containing ozone can be obtained. Contaminant impurities adhering to the coating surface can be removed. As a method for producing pure water containing ozone, there are a method of electrolyzing pure water and a method of directly dissolving ozone gas in pure water. The ozone concentration is 6
It is preferable to use it at mg / L or more. It should be noted that optimum conditions for the number of rotations and time of the spin device may be appropriately determined according to the substrate area, the coating material, and the like.

For laser annealing, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The conditions for crystallization by laser annealing may be appropriately selected by the practitioner.

The crystalline semiconductor film thus obtained is patterned into a desired shape to form island-like semiconductor layers 102 to 10.
5 is formed.

The following steps are performed according to the first embodiment, as shown in FIG.
Can be formed.

This embodiment can be freely combined with any one of Embodiments 1 to 4.

[Embodiment 6] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described. FIG. 18 shows E to which the present invention is applied.
It is sectional drawing of an L display device.

In FIG. 18, the switching TFT 603 provided on the substrate 700 is formed using the n-channel TFT 203 shown in FIG. Therefore, for the description of the structure, the description of the n-channel TFT 203 may be referred to.

Although the embodiment has a double gate structure in which two channel formation regions are formed, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. good.

The driving circuit provided on the substrate 700
It is formed using an OS circuit. Therefore, the description of the structure is n
The description of the channel TFT 201 and the p-channel TFT 202 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

Further, wirings 701 and 703 are a source wiring of a CMOS circuit, 702 is a drain wiring, 704 is a source wiring for electrically connecting the source region of the switching TFT, and 705 is a wiring of the drain region of the switching TFT. Functions as a drain wiring to be connected.

It is to be noted that the current control TFT 604 corresponds to p
It is formed using a channel type TFT 202. Therefore,
For the description of the structure, the description of the p-channel TFT 202 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

A wiring 706 is a source wiring of the current control TFT (corresponding to a current supply line), and 707 is an electrode which is electrically connected to the pixel electrode 710 by being superposed on the pixel electrode 710 of the current control TFT. is there.

Reference numeral 710 denotes a pixel electrode (anode of an EL element) made of a transparent conductive film. As a transparent conductive film,
A compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used. The pixel electrode 710 has a flat interlayer insulating film 7 before forming the wiring.
11 is formed. In this embodiment, it is very important to flatten the step due to the TFT by using the flat interlayer insulating film 711 made of resin. EL formed later
Since the layer is very thin, poor light emission may occur due to the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG. Bank 712 is 10
The insulating film or the organic resin film containing silicon having a thickness of 0 to 400 nm may be formed by patterning.

Since the bank 712 is an insulating film,
Attention must be paid to electrostatic breakdown of the element during film formation.
In this embodiment, the resistivity is reduced by adding carbon particles or metal particles to the insulating film used as the material of the bank 712 to suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of the carbon particles and metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

On the pixel electrode 710, an EL layer 713 is formed. Although only one pixel is shown in FIG. 18, EL layers corresponding to R (red), G (green), and B (blue) are separately formed in this embodiment. In this embodiment, a low-molecular organic EL material is formed by an evaporation method.
Specifically, a 20-nm-thick copper phthalocyanine (CuPc) film is provided as a hole-injecting layer, and
It has a stacked structure in which a 0 nm-thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

However, the above example is an example of the organic EL material that can be used for the EL layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, a low molecular organic EL material is
Although an example in which the layer is used as a layer has been described, a polymer organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the EL layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (an alloy film of magnesium and silver)
May be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

When the cathode 714 is formed, EL
The element 715 is completed. Note that the EL element 71 here
Reference numeral 5 denotes a capacitor formed by the pixel electrode (anode) 710, the EL layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the EL element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used in a single layer or in a stacked layer.

At this time, a film having good coverage is preferably used as a passivation film, and a carbon film, particularly, a D film is preferably used.
It is effective to use an LC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or lower, it can be easily formed above the EL layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen, and the EL layer 713
Can be suppressed. Therefore, the problem that the EL layer 713 is oxidized during the subsequent sealing step can be prevented.

Further, a sealing material 717 is provided on the passivation film 716, and a cover material 718 is attached. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, a cover material 718 having a carbon film (preferably a diamond-like carbon film) formed on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) is used.

Thus, an EL display device having a structure as shown in FIG. 18 is completed. After forming the bank 712,
It is effective to perform a process up to the formation of the passivation film 716 continuously without exposing to the atmosphere using a multi-chamber (or in-line) film forming apparatus. Further, by further developing, it is also possible to continuously perform processing up to the step of bonding the cover material 718 without releasing to the atmosphere.

In this manner, the n-channel TFTs 601 and 602 are placed on the insulator 501 whose main body is a plastic substrate.
A switching TFT (n-channel TFT) 603 and a current control TFT (n-channel TFT) 604 are formed. The number of masks required in the manufacturing process up to this point is
The number is smaller than that of a general active matrix type EL display device.

That is, the manufacturing process of the TFT is greatly simplified, and an improvement in yield and a reduction in manufacturing cost can be realized.

Further, as described with reference to FIG.
By providing an impurity region overlapping the gate electrode with an insulating film interposed therebetween, n is resistant to deterioration caused by the hot carrier effect.
A channel type TFT can be formed. for that reason,
A highly reliable EL display device can be realized.

In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other components such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit are provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, an EL light emitting device of this embodiment after performing a sealing (or enclosing) step for protecting the EL element will be described with reference to FIG. It should be noted that the reference numerals used in FIG.

FIG. 19A is a top view showing a state in which the EL element has been sealed, and FIG. 19B is a cross-sectional view of FIG. 19A taken along the line AA ′. 80 shown by dotted line
Reference numeral 1 denotes a source side driving circuit, 806 denotes a pixel portion, and 807 denotes a gate side driving circuit. Reference numeral 901 denotes a cover material;
Denotes a first sealant, 903 denotes a second sealant, and a sealant 907 is provided inside the first sealant 902.

Reference numeral 904 denotes wiring for transmitting signals input to the source-side driving circuit 801 and the gate-side driving circuit 807, and a video signal or a clock signal from an FPC (flexible print circuit) 905 serving as an external input terminal. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached. The EL display device in this specification includes not only the EL display device main body but also a state in which an FPC or a PWB is attached thereto.

Next, the cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate driver circuit 807 are formed above the substrate 700.
Is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 710 electrically connected to its drain. The gate side drive circuit 807 is an n-channel type TF
It is formed using a CMOS circuit combining T601 and p-channel TFT 602.

[0210] The pixel electrode 710 functions as an anode of the EL element. Further, banks 712 are provided at both ends of the pixel electrode 710.
Are formed, and an EL layer 713 and a cathode 714 of an EL element are formed on the pixel electrode 710.

[0211] The cathode 714 also functions as a common wiring for all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, all elements included in the pixel portion 806 and the gate driver circuit 807 are covered with the cathode 714 and the passivation film 567.

A cover member 901 is attached by a first seal member 902. Note that a spacer made of a resin film may be provided to secure an interval between the cover member 901 and the EL element. The inside of the first sealant 902 is filled with a sealant 907. Note that an epoxy resin is preferably used for the first sealant 902 and the sealant 907. Further, it is desirable that the first sealant 902 be a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a moisture absorbing effect or a substance having an antioxidant effect may be contained in the sealing material 907.

[0213] The sealing material 907 provided so as to cover the EL element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (FRP) is used as the material of the plastic substrate 901a constituting the cover member 901.
iberglass-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester or acrylic can be used.

Further, the cover material 90 is formed by using the sealing material 907.
After bonding, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. Second sealing material 90
For 3, the same material as the first sealant 902 can be used.

With the above structure, the EL element is sealed with the sealing material 90.
By encapsulating the EL element in the EL element, the EL element can be completely shut off from the outside, and it is possible to prevent a substance such as moisture or oxygen, which promotes the deterioration of the EL layer from being oxidized, from entering from the outside. Therefore, a highly reliable EL display device can be obtained.

[Embodiment 7] In this embodiment, a method of manufacturing an active matrix substrate different from that of Embodiment 1 will be described with reference to FIGS.
This will be described with reference to FIG.

First, the same state as in FIG. 11A is obtained according to the first embodiment. (FIG. 20A)

Next, a first etching process is performed according to the first embodiment. (FIG. 20 (B)) Here, the first
Corresponds to the second etching step (FIG. 3C) described in the second embodiment.

Next, after performing a second etching process, a first doping process is performed. (FIG. 20C) The second etching process is the same as the second etching process of the first embodiment. Here, the second conductive layers 113b to 113b
116b is etched to become 1001 to 1004. Note that the second etching treatment here corresponds to the third etching step (FIG. 3D) described in Embodiment 2. In addition, the same processing as in the first embodiment is performed for the first doping, and high concentration impurity regions 1005 to 1008 are formed. Note that the first doping process here is the first doping step described in Embodiment 2 (FIG. 4A).
Is equivalent to

Next, a third etching process is performed.
(FIG. 20D) The third etching process is performed in the first embodiment.
The same processing as the third etching processing is performed. Here the second
Of the conductive layers 113a to 116a are
09 to 1012, and the insulating film 117 is simultaneously etched to form insulating films 1013a to 1013c and 1014. Note that the third etching treatment here corresponds to the fourth etching step (FIG. 4B) described in Embodiment 2. Further, the second conductive layer 1009 corresponds to 1 in FIG.
38, 1010 corresponds to 139 in FIG. 11, 1011 corresponds to 140 in FIG. 11, and 1012 corresponds to FIG.
It corresponds to 142 in the middle.

The subsequent steps are the same as the steps after FIG. 12A in the first embodiment, and thus will not be described here.

This embodiment can be freely combined with any one of Embodiments 1 to 6.

[Embodiment 8] In this embodiment, a method of manufacturing an active matrix substrate different from that of Embodiment 1 will be described with reference to FIGS.
This will be described with reference to FIG.

First, the same state as in FIG. 11A is obtained according to the first embodiment. (FIG. 21A)

Next, according to the first embodiment, after performing an etching process under the first etching condition, a first doping process for passing through the insulating film 106 and the first conductive film 107 is performed. (FIG. 21B) Note that the etching treatment under the first etching condition corresponds to the first etching step (FIG. 5B) described in Embodiment 3. Further, the doping process here corresponds to the first doping step (FIG. 5C) described in Embodiment 3. By this first doping process, the high concentration impurity region 130 is formed.
1 to 1304 are formed.

Next, after performing the etching process under the second etching condition according to the first embodiment, the second etching process is performed according to the first embodiment. (FIG. 21C) The etching process under the second etching condition is as follows.
The second etching step described in Embodiment 3 (FIG.
(D)). Further, the second etching treatment here corresponds to the third etching step (FIG. 6A) described in Embodiment 3.

Next, a third etching process is performed.
(FIG. 21D) This third etching process is performed in the first embodiment.
The same processing as the third etching processing is performed.

The subsequent steps are the same as the steps after FIG. 12A of the first embodiment, and thus will not be described here.

This embodiment can be freely combined with any one of Embodiments 1 to 7.

[Embodiment 9] In this embodiment, a method of manufacturing an active matrix substrate different from that of Embodiment 1 will be described with reference to FIG.
This will be described with reference to FIG. In FIG. 22, the same reference numerals are used for portions corresponding to FIG. In the first embodiment, an example is shown in which a part of the insulating film is removed to expose a part of the high-concentration impurity region. However, in the present embodiment, the etching amount of the insulating film during etching is suppressed to reduce the high-concentration impurity region. An example of a process in which a region is covered with a thin insulating film will be described.

First, the same state as in FIG. 21B is obtained according to the eighth embodiment.

Next, after the second conductive layer is etched as shown in Embodiment Mode 4 (FIG. 7D), a third etching step is further performed. Alternatively, in Embodiment 5, an electrode including a stack of a first conductive layer and a second conductive layer is formed by one etching (second etching step) as illustrated in FIG. Is also good.

[0233] In this manner, the etching amount of the insulating film is suppressed, and the insulating film 1400 in contact with the high-concentration impurity region is formed.
Is left about 5 to 50 nm.

The subsequent steps are the same as the steps after FIG. 12A in the first embodiment, and thus will not be described here.

Thus, an active matrix substrate as shown in FIG. 22 can be manufactured.

This embodiment can be freely combined with any one of Embodiments 1 to 8.

[Embodiment 10] TFTs formed by carrying out any one of Embodiments 1 to 9 described above can be used in various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC). Display). That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in the display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector, a head-mounted display (goggle type display), a car navigation, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.). ). FIG. 23 shows an example of them.
FIG. 24 and FIG.

FIG. 23A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 23B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102.

FIG. 23C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 23D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302.

FIG. 23E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 23F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502.

FIG. 24A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other driving circuits.

FIG. 24B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to a liquid crystal display device 2808 forming a part of the LCD 702 and other driving circuits.

FIG. 24C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 24A and 24B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 24D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 24C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 24D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 24, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

FIG. 25A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904.

[0251] FIG. 25B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003.

FIG. 25C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 6.

[0254]

According to the present invention, GOL can be performed with a small number of masks.
A TFT having a D region and an LDD region can be manufactured. Therefore, in the GOLD region overlapping with the gate electrode, the relaxation of the electric field concentration is achieved, which can be prevented by hot carriers, and the LOLD region which does not overlap with the gate electrode.
In the DD region, the off-state current value can be suppressed.

Since the first conductive layer overlapping the GOLD region can be freely adjusted by the etching conditions, the width of the low concentration impurity region (GOLD region) overlapping the gate electrode and the low concentration impurity region not overlapping the gate electrode can be adjusted. (LDD
And the width of the region can be set to a desired value.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a TFT. (Embodiment 1)

FIG. 2 illustrates a manufacturing process of a TFT. (Embodiment 1)

FIG. 3 illustrates a manufacturing process of a TFT. (Embodiment 2)

FIG. 4 is a diagram showing a manufacturing process of a TFT. (Embodiment 2)

FIG. 5 is a diagram showing a manufacturing process of a TFT. (Embodiment 3)

FIG. 6 illustrates a manufacturing process of a TFT. (Embodiment 3)

FIG. 7 illustrates a manufacturing process of a TFT. (Embodiment 4)

FIG. 8 illustrates a manufacturing process of a TFT. (Embodiment 4)

FIG. 9 illustrates a manufacturing process of a TFT. (Embodiment 5)

FIG. 10 illustrates a manufacturing process of a TFT. (Embodiment 5)

FIG. 11 is a diagram showing a manufacturing process of an AM-LCD. (Example 1)

FIG. 12 is a diagram showing a manufacturing process of an AM-LCD. (Example 1)

FIG. 13 is a view showing a manufacturing process of an AM-LCD. (Example 1)

FIG. 14 is a sectional structural view of a transmission type liquid crystal display device.
(Example 1)

FIG. 15 is an external view of a liquid crystal display panel. (Example 2)

FIG. 16 is a sectional structural view of a reflection type liquid crystal display device.
(Example 3)

FIG. 17 is a sectional structural view of a reflective liquid crystal display panel provided with a light source. (Example 4)

FIG. 18 illustrates a structure of an active matrix EL display device.

FIG. 19 illustrates a structure of an active matrix EL display device.

FIG. 20 is a diagram showing a manufacturing process of an AM-LCD. (Example 7)

FIG. 21 is a diagram showing a manufacturing process of an AM-LCD. (Example 8)

FIG. 22 is a diagram showing a manufacturing process of an AM-LCD. (Example 9)

FIG. 23 illustrates an example of an electronic device.

FIG. 24 illustrates an example of an electronic device.

FIG. 25 illustrates an example of an electronic device.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 617L (72) Inventor Toru Takayama 398 Hase, Atsugi-shi, Kanagawa Pref. F-term in the Energy Research Laboratory (Reference) 2H092 JA28 JB56 MA17 MA27 NA26 NA27 NA29 5C094 AA43 AA45 BA03 CA19 DA15 EA04 EA07 FB14 FB15 5F110 AA16 BB02 BB04 CC02 DD01 DD02 DD03 DD05 DD13 DD14 DD15 DD17 EE01 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE02 EE02 EE04 EE02 EE04 EE02 EE04 EE02 EE04 EE02 EE02 EE04 EE02 EE04 EE02 EE02 EE04 EE02 EE02 EE02 EE04 EE02 EE02 EE04 EE02 EE02 FF02 FF04 FF09 FF28 FF30 FF35 FF36 GG01 GG02 GG13 GG25 GG32 GG42 GG43 GG44 GG45 GG47 HJ01 HJ04 HJ12 HJ13 HJ23 HL02 HL03 PP04 HL06 HL07 HL11 HL27 HM02 NN03 PP03 QQ24 QQ25 QQ28 5G435 AA17 CC09 EE34 KK05 KK09 KK10

Claims (16)

[Claims] A first step of forming a semiconductor layer on an insulating surface; a second step of forming an insulating film on the semiconductor layer; and a first step having a first width on the insulating film. Forming a first electrode composed of a laminate of a conductive layer of
A step of forming a high-concentration impurity region by adding an impurity element to the semiconductor layer using the first electrode as a mask; and etching the second conductive layer in the first electrode. A fifth step of forming a second electrode composed of a laminate of the first conductive layer having the first width and the second conductive layer having the second width; The first conductive layer in the electrode is etched to form a third electrode including a stack of a first conductive layer having a third width and a second conductive layer having the second width. A sixth step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer by passing through the first conductive layer or the insulating film using the second conductive layer as a mask; Process and
A method for manufacturing a semiconductor device having: 2. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first step having a first width on the insulating film. Forming a first electrode composed of a laminate of a conductive layer of
And etching the second conductive layer of the first electrode to form a stack of a first conductive layer having the first width and a second conductive layer having a second width. Forming a second electrode, and using the second electrode as a mask.
A fifth step of forming a high-concentration impurity region by adding an impurity element to the semiconductor layer; and etching the first conductive layer of the second electrode to form a first region having a third width.
A sixth step of forming a third electrode composed of a stack of a conductive layer having a second width and a second conductive layer having the second width; and forming the first conductive layer using the second conductive layer as a mask. A seventh step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer through a layer or the insulating film;
A method for manufacturing a semiconductor device having: 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second width is smaller than the first width. 4. The method according to claim 1, wherein the third width is smaller than the first width and the second width is smaller than the first width.
A method for manufacturing a semiconductor device, wherein the width is wider than the width of the semiconductor device. 5. The method according to claim 1, wherein in the third step, after forming a first conductive film and a second conductive film on the insulating film, the second step is performed. Performing a first etching process on the conductive film to form the second conductive layer; performing a second etching process on the first conductive film to form the first conductive layer; The first conductive layer having a width of
A method for manufacturing a semiconductor device, comprising: forming a first electrode; 6. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, a first conductive film and a second conductive film on the insulating film. A third step of laminating and forming a conductive film; a fourth step of etching the second conductive film to form a second conductive layer having a first width; A fifth step of forming a high-concentration impurity region by adding an impurity element to the semiconductor layer by passing through the first conductive film or the insulating film using the second conductive layer as a mask; A sixth step of etching the conductive film to form a first electrode formed by stacking a first conductive layer having the second width and a second conductive layer having a third width; Etching the second conductive layer on the first electrode to form a first conductive layer having the second width; A seventh step of forming a second electrode made of a laminate with a second conductive layer having a width of 4; and etching the first conductive layer of the second electrode to form a fifth width. An eighth step of forming a third electrode formed by laminating a first conductive layer having the fourth width and a second conductive layer having the fourth width; and a second conductive layer having the fourth width. A ninth step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film, using a mask as a mask. 7. The method according to claim 6, wherein the second width is smaller than the first width. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the fifth width is smaller than the second width and wider than the fourth width. 9. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first conductive film and a second conductive film on the insulating film. A third step of laminating and forming a conductive film; a fourth step of etching the second conductive film to form a second conductive layer having a first width; and a fourth step of forming a second conductive layer having a first width. A fifth step of forming a high-concentration impurity region by adding an impurity element to the semiconductor layer by passing through the first conductive film or the insulating film using the second conductive layer as a mask; A sixth step of etching the conductive layer to form a second conductive layer having the second width; and etching the first conductive film to form a first conductive layer having a third width. A seventh step of forming an electrode formed by laminating a second conductive layer having the second width; An eighth step of forming a low-concentration impurity region by adding an impurity element to the semiconductor layer through the first conductive layer or the insulating film using the second conductive layer having a width of as a mask as a mask; A method for manufacturing a semiconductor device having: 10. The method according to claim 9, wherein the second width is smaller than the first width. 11. The method according to claim 9, wherein the third width is smaller than the first width and the second width is smaller than the first width.
A method for manufacturing a semiconductor device, wherein the width is wider than the width of the semiconductor device. 12. A first step of forming a semiconductor layer on an insulating surface, a second step of forming an insulating film on the semiconductor layer, and a first conductive film and a second conductive film on the insulating film. A third step of laminating and forming a conductive film; a fourth step of etching the second conductive film to form a second conductive layer having a first width; and a fourth step of forming a second conductive layer having a first width. A fifth step of forming a high-concentration impurity region by adding an impurity element to the semiconductor layer by passing through the first conductive film or the insulating film using the second conductive layer as a mask; A sixth step of etching the conductive film and the second conductive layer to form an electrode formed by stacking a first conductive layer having a second width and a second conductive layer having a third width; A first conductive layer or the insulating film using a second conductive layer having the third width as a mask; The method for manufacturing a semiconductor device having a seventh step by passing to form a low concentration impurity region by adding an impurity element to the semiconductor layer. 13. The method according to claim 12, wherein the third width is
A method for manufacturing a semiconductor device, wherein the width is smaller than the first width. 14. The method according to claim 12, wherein
The method for manufacturing a semiconductor device, wherein the second width is smaller than the first width and larger than the third width. 15. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity element is an impurity element that imparts n-type or p-type to a semiconductor. 16. A semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera,
Projectors, goggle-type displays, car navigation, personal computers, portable information terminals,
A method for manufacturing a semiconductor device, which is a digital video disk player or an electronic game machine.