JP2020074442A - Semiconductor device - Google Patents

Abstract

To manufacture metal wiring capable of corresponding to enlargement of a substrate.SOLUTION: In the present invention, a conductive film of at least one layer is formed on an insulated surface, a resist pattern is formed on the conductive film and the conductive film having the resist pattern is etched to form metal wiring where taper angle α is controlled in accordance with bias power density, ICP power density, temperature and pressure of a lower electrode, a total flow rate of etching gas, and oxygen or chlorine in the etching gas. The metal wiring formed in the process can reduce dispersions of width and length and can also sufficiently correspond to the enlargement of a substrate.SELECTED DRAWING: None

Description

The present invention relates to a metal wiring formed by using thin film technology and a method for manufacturing the same. Also,
The present invention relates to a metal wiring board and a method for manufacturing the same. In this specification, the metal wiring substrate refers to an insulating substrate such as glass having metal wiring formed by using a thin film technique, or various substrates.

In recent years, a thin film transistor (TFT) is formed using a semiconductor thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface, and development of a semiconductor device having a large area integrated circuit formed by this TFT Is progressing. Active matrix liquid crystal display devices, light emitting devices, and contact image sensors are known as typical examples. In particular, a TFT having a crystalline silicon film (typically a polysilicon film) as an active region (hereinafter referred to as a polysilicon TFT) has a high field-effect mobility, so that various functional circuits can be formed. Is.

For example, in an active matrix type liquid crystal display device, a pixel circuit for performing image display for each functional block, a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like for controlling pixel circuits. The drive circuit is formed on a single substrate.

In the pixel circuit of the active matrix type liquid crystal display device, each pixel of tens to millions has a T
FTs (pixel TFTs) are arranged, and each of the pixel TFTs is provided with a pixel electrode. A counter electrode is provided on the counter substrate side with the liquid crystal sandwiched therebetween, forming a kind of capacitor using the liquid crystal as a dielectric. The voltage applied to each pixel is controlled by the switching function of the TFT, and the charge to this capacitor is controlled to drive the liquid crystal, and the amount of transmitted light is controlled to display an image.

The pixel TFT is generally composed of an n-channel TFT, and serves as a switching element for applying a voltage to liquid crystal to drive it. Since the liquid crystal is driven by alternating current, a method called frame inversion drive is often used. In this method, in order to keep the power consumption low, the pixel TF
For the characteristics required for T, it is important that the off current value (drain current flowing when the TFT is in the off operation) be sufficiently low.

As a structure of a TFT for reducing the off current value, a low concentration drain (LDD: Lightly
Doped Drain) structure is known. In this structure, a region where an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region which is formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. Also, as a means for preventing the deterioration of the on-current value due to hot carriers, a so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is arranged to overlap a gate electrode via a gate insulating film is known. .. It is known that such a structure alleviates a high electric field near the drain, prevents hot carrier injection, and is effective in preventing a deterioration phenomenon.

An example for forming a GOLD structure will be described with reference to the drawings. A base insulating film is formed on a substrate, a semiconductor film is formed on the base insulating film, and an insulating film is formed on the semiconductor film.
A conductive film is formed on the insulating film. Although the base insulating film has a stacked-layer structure in FIG. 1A, it may have a single-layer structure or may not be formed. Further, although the conductive film has a single layer structure, it may have a laminated structure of two or more layers. Subsequently, a resist is formed and etching is performed so that the end portion of the conductive film has a tapered shape. (FIG. 1 (B)) As this etching method, a dry etching method using high density plasma is desirable. An etching apparatus using microwaves or inductively coupled plasma (ICP) is suitable for obtaining a high-density plasma. Then, a low-concentration impurity region overlapping with the gate electrode and a high-concentration impurity region functioning as a source region or a drain region are formed in the semiconductor film by the first doping treatment and the second doping treatment. By the above processing, G
An OLD structure can be realized.

The etching conditions in the ICP etching apparatus are bias power density, ICP power density, pressure, total flow rate of etching gas, and temperature of lower electrode. Further, when oxygen is added to the etching gas, the etching is promoted. Therefore, the oxygen addition rate in the etching gas is also one of the conditions.

However, the selection ratio between the resist and the conductive film may change depending on the etching conditions, and the width of the conductive film may vary within the substrate surface. When the conductive film is used as a gate electrode, the conductive film serves as a mask when an impurity element is introduced, and thus the width of the conductive film varies depending on the length of the channel formation region and the length of the conductive film and the LDD region. This causes variation in the length of the overlapping area. When a TFT is manufactured using such a semiconductor film, it becomes a cause of variations in electrical characteristics and further becomes a factor of deteriorating operating characteristics of the semiconductor device. Further, when the conductive film is used as a wiring, the variation in the width of the conductive film causes the variation in the wiring resistance,
It lowers the electrical characteristics of the TFT. As described above, the variation in the width and the length of the conductive film becomes an increasingly serious problem as the size of the substrate increases, and it is extremely difficult to suppress the variation in the width and the length of the conductive film to improve the uniformity. Is important to.

The present invention is a technique for solving such a problem, and an object thereof is to provide a metal wiring and a method for manufacturing the same, and a metal wiring board and a method for manufacturing the same, which can cope with an increase in the size of a substrate.

The structure of the invention relating to the metal wiring disclosed in this specification is a conductive layer formed of a tungsten film, a metal compound film containing a tungsten compound as a main component, or a metal alloy film containing a tungsten alloy as a main component. And the taper angle α at the end of the conductive layer is 5 °.
It is characterized by being in the range of up to 85 °.

In the above structure, the metal alloy film is formed of Ta, Ti, Mo, Cr, Nb, Si, Sc,
It is characterized in that it is an alloy film of one element or a plurality of elements selected from Nd and tungsten.

Further, in the above structure, the metal compound film is a nitride film of tungsten.

Another structure of the invention relating to metal wiring is an aluminum film, or a metal compound film containing an aluminum compound as a main component, or a conductive layer formed of a metal alloy film containing an aluminum alloy as a main component, The taper angle α at the end of the conductive layer is 5 ° to 85
It is characterized by being in the range of °.

In the above structure, the metal alloy film is formed of Ta, Ti, Mo, Cr, Nb, Si, Sc,
It is characterized by being an alloy film of one element or a plurality of elements selected from Nd and aluminum.

Further, in the above structure, the metal compound film is a nitride film of aluminum.

Further, in each of the above structures, a conductive silicon film (for example, a phosphorus-doped silicon film, a boron-doped silicon film, or the like) may be provided in the lowermost layer in order to improve adhesion.

Further, the structure of the invention relating to the metal wiring board disclosed in the present specification is a metal wiring board having an insulating substrate and a metal wiring, wherein the metal wiring is a tungsten film or a metal compound containing a tungsten compound as a main component. A film or a conductive layer formed of a metal alloy film containing a tungsten alloy as a main component, wherein the taper angle α at the end of the conductive layer is 5 ° to
It is characterized by being in the range of 85 °.

Another aspect of the invention relating to a metal wiring board is an insulating board and a metal wiring board having a metal wiring, wherein the metal wiring is an aluminum film, or a metal compound film containing an aluminum compound as a main component, or A conductive layer formed of a metal alloy film containing aluminum alloy as a main component, characterized in that a taper angle α at an end portion of the conductive layer is in a range of 5 ° to 85 °.

In addition, a structure of the invention relating to a method for manufacturing a metal wiring disclosed in this specification is that a conductive film having at least one layer is formed over an insulating surface, a resist pattern is formed over the conductive film, and the conductive film has the resist pattern. Etching is performed and the taper angle α is changed according to the bias power density.
Is characterized by forming a controlled metal wiring.

Another structure of the invention relating to a method for manufacturing a metal wiring is to form at least one conductive film on an insulating surface, form a resist pattern on the conductive film, and perform etching on the conductive film having the resist pattern. , The metal wiring whose taper angle α is controlled according to the ICP power density is formed.

Another structure of the invention relating to a method for manufacturing a metal wiring is to form at least one conductive film on an insulating surface, form a resist pattern on the conductive film, and perform etching on the conductive film having the resist pattern. It is characterized in that a metal wiring whose taper angle α is controlled according to the temperature of the lower electrode is formed.

In the above-mentioned configuration relating to the method for producing the metal wiring, the temperature of the lower electrode is 85 to 120 ° C.
It is characterized by

Another structure of the invention relating to a method for manufacturing a metal wiring is to form at least one conductive film on an insulating surface, form a resist pattern on the conductive film, and perform etching on the conductive film having the resist pattern. It is characterized in that a metal wiring whose taper angle α is controlled according to pressure is formed.

In the above-mentioned configuration relating to the method for producing the metal wiring, the pressure is set to 2.0 to 13 Pa.

Another structure of the invention relating to a method for manufacturing a metal wiring is to form at least one conductive film on an insulating surface, form a resist pattern on the conductive film, and perform etching on the conductive film having the resist pattern. It is characterized in that a metal wiring whose taper angle α is controlled according to the flow rate of the reaction gas is formed.

In addition, in the configuration related to the method for manufacturing the metal wiring, the total flow rate of the reaction gas is 2.6.
It is characterized in that it is set to 1 × 10 ^{3 to} 10.87 × 10 ³ sccm / m ³ .

Another structure of the invention relating to a method for manufacturing a metal wiring is to form at least one conductive film on an insulating surface, form a resist pattern on the conductive film, and perform etching on the conductive film having the resist pattern. It is characterized in that a metal wiring whose taper angle α is controlled according to the proportion of oxygen in the reaction gas is formed.

In the above-mentioned configuration relating to the method for producing the metal wiring, the proportion of oxygen in the reaction gas is 1
It is characterized by being set to 7 to 50%.

Another structure of the invention relating to a method for manufacturing a metal wiring is to form at least one conductive film on an insulating surface, form a resist pattern on the conductive film, and perform etching on the conductive film having the resist pattern. The metal wiring is characterized in that the taper angle α is controlled according to the proportion of chlorine in the reaction gas.

In each structure relating to the method for manufacturing the metal wiring, the metal thin film is a thin film selected from a tungsten film, a metal compound film containing a tungsten compound as a main component, a metal alloy film containing a tungsten alloy as a main component, and an aluminum film. A thin film selected from a metal compound film containing an aluminum compound as a main component and a metal alloy film containing an aluminum alloy as a main component.

In addition, the structure of the invention relating to the method for manufacturing a metal wiring substrate disclosed in the present specification includes an insulating substrate,
In a method for manufacturing a metal wiring substrate having a metal wiring, at least one conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, the conductive film having the resist pattern is etched, and a bias is applied. It is characterized in that a metal wiring whose taper angle α is controlled according to the power density is formed.

Further, the structure of another invention relating to the method for producing a metal wiring substrate is an insulating substrate, and in the method for producing a metal wiring substrate having metal wiring, at least one conductive film is formed on an insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring whose taper angle α is controlled according to the ICP power density.

Further, the structure of another invention relating to the method for producing a metal wiring substrate is an insulating substrate, and in the method for producing a metal wiring substrate having metal wiring, at least one conductive film is formed on an insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring whose taper angle α is controlled according to the temperature of the lower electrode.

In the structure relating to the method for producing a metal wiring board, the temperature of the lower electrode is 85 to 12
The feature is that the temperature is 0 ° C.

Further, the structure of another invention relating to the method for producing a metal wiring substrate is an insulating substrate, and in the method for producing a metal wiring substrate having metal wiring, at least one conductive film is formed on an insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring whose taper angle α is controlled according to pressure.

In the structure relating to the method for manufacturing a metal wiring board, the pressure is 2.0 to 13 Pa.

Further, the structure of another invention relating to the method for producing a metal wiring substrate is an insulating substrate, and in the method for producing a metal wiring substrate having metal wiring, at least one conductive film is formed on an insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring having a taper angle α controlled according to the total flow rate of the reaction gas.

In the structure relating to the method for manufacturing a metal wiring board, the total flow rate of the reaction gas is 2.61.
It is characterized in that it is set to × 10 ^{3 to} 10.87 × 10 ³ sccm / m ³ .

Further, the structure of another invention relating to the method for producing a metal wiring substrate is an insulating substrate, and in the method for producing a metal wiring substrate having metal wiring, at least one conductive film is formed on an insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring whose taper angle α is controlled according to the ratio of oxygen in the reaction gas.

In the structure relating to the method for producing a metal wiring board, the proportion of oxygen in the reaction gas is set to 17 to 50%.

Further, the structure of another invention relating to the method for producing a metal wiring substrate is an insulating substrate, and in the method for producing a metal wiring substrate having metal wiring, at least one conductive film is formed on an insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring whose taper angle α is controlled according to the proportion of chlorine in the reaction gas.

Further, in each of the configurations related to the method for manufacturing the metal wiring board, the metal thin film is a thin film selected from a tungsten film, a metal compound film containing a tungsten compound as a main component, a metal alloy film containing a tungsten alloy as a main component, and aluminum. A thin film selected from a film, a metal compound film containing an aluminum compound as a main component, and a metal alloy film containing an aluminum alloy as a main component.

By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) It is a simple method adapted to the conventional wiring or wiring board manufacturing process.
(B) By changing the bias power density, the ICP power density, the temperature of the lower electrode or the proportion of chlorine in the etching gas, it becomes possible to form a wiring having a desired taper angle.
(C) By setting the pressure, the total flow rate of the etching gas, the proportion of oxygen in the etching gas, and the temperature of the lower electrode to predetermined values, it is possible to reduce variations within the surface of the substrate.
(D) In addition to satisfying the above advantages, it is possible to sufficiently cope with a metal wiring or a metal wiring board even if the board becomes large.

(A) A diagram showing the relationship between W and the resist etching rate with respect to the bias power density. FIG. 6B is a diagram showing a relationship between W and resist selection ratio with respect to bias power density. FIG. 3A is a diagram showing the relationship between W and resist etching rate with respect to ICP power density. (B) A diagram showing the relationship between W and resist selection ratio with respect to ICP power density. FIG. 5A is a diagram showing the relationship between W and resist etching rate with respect to pressure. FIG. 3B is a diagram showing a relationship between W and resist selection ratio with respect to pressure. FIG. 3A is a diagram showing a relationship between W and a resist etching rate with respect to an oxygen addition rate in an etching gas. FIG. 7B is a diagram showing a relationship between W and a resist selection ratio with respect to an oxygen addition rate in an etching gas. (A) A diagram showing the relationship between W and the resist etching rate with respect to the total flow rate of etching gas. FIG. 6B is a diagram showing the relationship between W and the resist selection ratio with respect to the total flow rate of etching gas. (A) A diagram showing the relationship between W and the resist etching rate with respect to the temperature of the lower electrode. FIG. 6B is a diagram showing the relationship between W and the resist selectivity with respect to the temperature of the lower electrode. The figure which shows the example of an ICP etching apparatus. The figure which shows the example of the concept of this invention. FIG. 9A is a diagram showing the relationship between the taper angle and the resist / W selection ratio when the bias power density is used as a parameter. (B) A graph showing the relationship between the taper angle and the resist / W selection ratio when the ICP power density is used as a parameter. (A) A graph showing the relationship between the taper angle and the resist / W selection ratio when pressure is used as a parameter. (B) A graph showing the relationship between the taper angle and the resist / W selection ratio when the oxygen addition rate in the etching gas is used as a parameter. FIG. 4A is a diagram showing the relationship between the resist / W selectivity and the taper angle when the total flow rate of etching gas is used as a parameter. FIG. 9B is a diagram showing the relationship between the taper angle and the resist / W selection ratio when the temperature of the lower electrode is used as a parameter. (A) A diagram showing the relationship between the etching rate of Al-Si and the resist with respect to the bias power density. FIG. 7B is a diagram showing the relationship between the bias power density and the selection ratio of Al—Si and resist. (A) A diagram showing the relationship between the etching rate of Al-Si and the resist with respect to the ICP power density. (B) A diagram showing the relationship between the Al / Si and resist selectivity with respect to the ICP power density. FIG. 5A is a diagram showing the relationship between the chlorine addition rate in an etching gas and the etching rates of Al—Si and a resist. FIG. 6B is a diagram showing the relationship between the Al—Si and resist selection ratios with respect to the chlorine addition rate in the etching gas. The figure which shows the example of the shape of the wiring produced by applying this invention. The figure which shows the example of the wiring produced by applying this invention. The figure which shows the example of the wiring produced by applying this invention. The figure which shows the example of the wiring produced by applying this invention. 7A to 7C are cross-sectional views illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. 7A to 7C are cross-sectional views illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. 7A to 7C are cross-sectional views illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. The top view which shows the structure of a pixel TFT. 6A to 6C are cross-sectional views illustrating a manufacturing process of an active matrix liquid crystal display device. FIG. 3 is a cross-sectional structural diagram of a driver circuit and a pixel portion of a light emitting device. (A) A top view of a light emitting device. FIG. 6B is a cross-sectional structure diagram of a driver circuit and a pixel portion of the light emitting device. FIG. 10 illustrates an example of a semiconductor device. FIG. 10 illustrates an example of a semiconductor device. FIG. 10 illustrates an example of a semiconductor device.

[Embodiment 1]
The present invention uses an ICP etching apparatus that uses high density plasma. ICP
The etcher uses 10 ¹¹ by inductively coupling RF power into the plasma at low pressure.
A plasma density of at least 1 piece / cm ³ is achieved and processing with a high selectivity and a high etching rate is performed.

First, the plasma generation mechanism of the ICP dry etching apparatus will be described in detail with reference to FIG.

FIG. 7A shows a simplified structural diagram of the etching chamber. Quartz plate 31 on top of chamber
The antenna coil 32 is arranged on the upper side and is connected to the RF power source 34 via the matching box 33. In addition, a matching box 36 is also attached to the lower electrodes 35 on the substrate side which are arranged to face each other.
The RF power source 37 is connected via.

When an RF current is applied to the antenna coil 32 above the substrate, an RF current J flows in the antenna coil 32 in the θ direction, and a magnetic field B is generated in the Z direction.

In accordance with Faraday's law of electromagnetic induction, an induced electric field E is generated in the θ direction.

Electrons are accelerated in the θ direction by the induced electric field E and collide with gas molecules to generate plasma.
Since the direction of the induced electric field is in the θ direction, the probability that charged particles collide with the etching chamber wall or the substrate and lose the charge is low. Therefore, high-density plasma can be generated even at a low pressure of about 1 Pa. Further, since there is almost no magnetic field B in the downstream, the high density plasma region spreads like a sheet.

Controlling the plasma density and the self-bias voltage independently by adjusting the RF power applied to each of the antenna coil 32 (where ICP power is applied) and the lower electrode 35 (where bias power is applied) on the substrate side. Is possible. It is also possible to change the frequency of the RF power applied according to the material of the object to be processed.

In order to obtain high-density plasma with the ICP etching device, R flowing in the antenna coil 32 is used.
It is necessary to flow the F current J with low loss, and in order to increase the area, the inductance of the antenna coil 32 must be reduced. For that purpose, an ICP etching device for a multi-spiral coil 38 in which an antenna is divided has been developed, and its structural diagram is shown in FIG. 7 (B). Here, the parts other than the quartz plate (the structure of the chamber, the structure of the lower electrode, etc.) are the same, and are therefore omitted. When the etching apparatus using the ICP to which the multi-spiral coil 38 is applied is used, the heat resistant conductive material can be satisfactorily etched.

The inventors of the present invention used the multi-spiral coil type ICP etching device (E645, manufactured by Matsushita Electric Industrial Co., Ltd.) to adjust the etching conditions, and conducted the experiments described below.

First, as a sample, a conductive film made of a W film having a thickness of 500 nm was formed on a glass substrate by a sputtering method. Then, a resist is formed and a bias power density which is an etching condition,
The W film was etched under various conditions such as ICP power density, pressure, oxygen addition rate in etching, total flow rate of etching gas, and temperature of lower electrode. Table 1 shows how to swing each condition. Further, in the case of evaluating a certain condition by shaking the condition, the values shown in Table 2 were used for other conditions. In Table 1 and Table 2, the unit of the bias power density and the ICP power density is [W / cm ² ], but in actuality, the power [
W]. The bias power and the ICP power described in Table 1 and Table 2 are the area on which the bias power is applied 12.5 cm × 12.5 cm and the area on which the ICP power is applied 12.
The value is divided by 5 cm × 12.5 cm × π. The volume of the chamber is 18.
Since it is 4 × 10 ⁻³ m ³ , the total flow rate of the etching gas is shown as a value divided by the volume of the chamber.

1 to 6 show the results obtained under various conditions. Each drawing (A) shows the etching rate of W and the resist, and each drawing (B) shows the selection ratio of W with respect to the resist. The number of measurement points in each of the substrate surfaces is 16, and the variation in the substrate surface is indicated by an error bar. FIG. 1 shows the result of changing the bias power density condition, FIG. 2 shows the result of changing the ICP power density condition, FIG. 3 shows the result of changing the pressure condition, and FIG. 4 shows the oxygen addition rate. 5 shows the result of changing the conditions, FIG. 5 shows the result of changing the condition of the total gas flow rate, and FIG. 6 shows the result of changing the temperature condition of the lower electrode.

First, the variation in the plane of the substrate will be considered. From FIG. 1A, when the bias power density is 0.256 to 0.512 W / cm ² , the variation is minimum, and when it is 0.96 W / cm ² or more, the variation is large. Further, as shown in FIG. 2 (A), the ICP power density shows no particular tendency depending on the condition. 3 (A) to 6 (A)
Therefore, the higher the pressure, the oxygen addition rate, the total gas flow rate, and the temperature of the lower electrode, the smaller the variation.

Next, the selection ratio of W with respect to the resist will be considered. From FIG. 1B to FIG. 6B, the selection ratio of W with respect to the resist is as shown in FIG.
There are large changes in the power density and the temperature of the lower electrode.
That is, it is understood that the conditions that affect the W selection ratio with respect to the resist are the bias power density, the ICP power density, and the temperature of the lower electrode.

From the above experiment, it was found that the bias power density, the ICP power density and the temperature of the lower electrode had a great influence on the selection ratio of the W film to the resist. Also, pressure, oxygen addition rate,
It was found that if the total gas flow rate and the temperature of the lower electrode are set high, the variation in the substrate surface is reduced.

Further, the following experiment was conducted in order to examine the correlation between the resist / W selectivity and the taper angle. This will be described with reference to FIG. Note that in this specification, the taper angle is as shown in FIG.
As shown in, the angle α between the tapered portion (inclined portion) of the cross-sectional shape of the conductive layer 15b and the surface of the base film 17b is meant. Further, the taper angle is tan α = using the width Z of the taper portion and the film thickness X.
It can be defined as X / Z.

First, a 50-nm-thick silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) as the insulating film 11 on the glass substrate 10 by the plasma CVD method (composition ratio S
i = 32%, O = 59%, N = 7%, H = 2%).
A TaN film having a film thickness of 50 nm was formed as the first conductive film 11 on the insulating film 11, and a W film having a film thickness of 370 nm was formed as the second conductive film 13 on the first conductive film 12 by a sputtering method.
Then, a resist was formed, and the W film was etched under various conditions such as the bias power density, the ICP power density, the pressure, the oxygen addition rate in etching, the total flow rate of the etching gas, and the temperature of the lower electrode, which are etching conditions. .. Table 1 shows how to swing each condition. Further, in the case of evaluating a certain condition by shaking the condition, the values shown in Table 2 were used for other conditions. Then, as an etching condition of the TaN film, CF ₄ and Cl ₂ are used as etching gas, and the flow rate ratio of each gas is set to 30:30 (sccm) and 1 Pa.
The RF (13.56 MHz) electric power of 0.71 W / cm ² was applied to the coil type electrode at the pressure of 1 to generate plasma to perform etching. RF of 0.128 W / cm ^{2 on} the substrate side (sample stage)
(13.56MHz) power was applied and a substantially negative self-bias voltage was applied.

After etching the first conductive film and the second conductive film in this manner, the cross-sectional shape thereof is observed by SEM at 50,000 times to obtain the taper angle and determine the resist / W selection ratio. I investigated the relationship. The results are shown in FIGS. FIG. 9A shows the relationship between the resist / W selection ratio and the taper angle when the bias power density is changed, and FIG. 9B shows the resist / W selection ratio and the taper when the ICP power density is changed. FIG. 10A shows the relationship between the resist / W selectivity and the taper angle when the pressure is changed, and FIG. 10B shows the relationship when the oxygen addition rate in the etching gas is changed. The relationship between the resist / W selectivity and the taper angle is shown. FIG. 11A shows the relationship between the resist / W selectivity and the taper angle when the total flow rate of the etching gas is changed, and FIG. 11B shows the lower part. The relationship between the resist / W selectivity and the taper angle when the electrode temperature is changed is shown. From FIGS. 9 to 11, it can be seen that the conditions that greatly affect the taper angle are the bias power density, the ICP power density, and the temperature of the lower electrode.

Therefore, the present invention forms a wiring having a desired taper angle by controlling the bias power density, the ICP power density, and the temperature of the lower electrode when the W film is etched using the ICP etching apparatus, Further, it is possible to perform highly uniform etching even on a large area substrate. Furthermore, if the pressure, the oxygen addition rate, the total gas flow rate, and the temperature of the lower electrode are set high, it is possible to reduce the variation in the shape of the wiring within the substrate surface. In particular,
Since the gate electrode made of the W film formed by using the present invention has less variation in shape in the plane of the substrate, when the impurity element is introduced using the gate electrode as a mask, the width and length of the impurity region are increased. It is possible to reduce the occurrence of variations in That is, it is possible to reduce the variation in the width and length of the channel formation region, and it is possible to reduce the variation in the electrical characteristics of the TFT manufactured using such a semiconductor film.
Further, it is possible to improve the operating characteristics and reliability of the semiconductor device.

The present invention can be applied not only to the W film but also to various films containing W as a main component such as a Mo-W film, a WSi film, and a TiW film.

[Embodiment 2]
The inventors of the present invention use the multi-spiral coil type ICP etching apparatus (E645 manufactured by Matsushita Electric Industrial Co., Ltd.) described in Embodiment 1 to set etching conditions for a conductive film different from that of the embodiment, and to describe below. Experiments were also conducted.

First, as a sample, a 500 nm-thick Al-Si (
2 wt%) film was formed. Then, a resist was formed, and the Ai-Si film was etched under the conditions of the bias power density, the ICP power density, and the Cl ₂ addition rate in the etching conditions. Table 3 shows how to shake each condition. Further, in the case of evaluating a certain condition by shaking the condition, the values shown in Table 4 were used for the other conditions. In Tables 1 and 2, the bias power density and IC
Although the unit of P power density is [W / cm ² ], it is actually multiplied by power [W]. The bias power and the ICP power shown in Table 1 and Table 2 are the area to which the bias power is applied 12.5 cm × 12.5 cm and the area to which the ICP power is applied 12.5 cm × 12.5 cm, respectively.
The value divided by × π is shown. Further, since the volume of the chamber is 18.4 × 10 ⁻³ m ³ , the total flow rate of the etching gas is shown as a value divided by the volume of the chamber.

12 to 14 show the results obtained by changing each condition. Each drawing (A) shows the etching rate of Al-Si and the resist, and each drawing (B) shows the selection ratio of Al-Si to the resist. The number of measurement points in each of the substrate surfaces is 16, and the variation in the substrate surface is indicated by an error bar. 12 shows the result of changing the bias power density condition, FIG. 13 shows the result of changing the ICP power density condition, and FIG. 14 shows the result of changing the Cl ₂ addition rate condition.

Consider the selection ratio of Al-Si to the resist. 12 (B) to 14 (B)
Therefore, the selection ratio of Al-Si with respect to the resist largely changes as the conditions change. That is, it is understood that the conditions that affect the Al-Si selection ratio with respect to the resist are the bias power density, the ICP power density, and the Cl ₂ addition rate.

Therefore, the present invention forms a wiring having a desired taper angle by controlling the bias power density, the ICP power density and the Cl ₂ addition rate when the Al-Si film is etched using the ICP etching apparatus. It is possible to do. In particular, A formed using the present invention
Since the gate electrode made of the l-Si film can have a desired taper angle, when an impurity element is introduced using the gate electrode as a mask, an impurity region having a desired width or length is formed. It is possible. That is, it becomes possible to form a channel formation region having a desired width and length, and it is possible to reduce variations in the electrical characteristics of a TFT manufactured using such a semiconductor film. Further, it is possible to improve the operating characteristics and reliability of the semiconductor device.

The present invention is not limited to the W film, but may be an Al-Ti film, an Al-Sc film, an Al-Nd film, or another Al film.
Can be applied to various films containing as a main component.

Examples of the present invention will be described below, but needless to say, the present invention is not limited to these examples.

In this embodiment, an example in which a metal wiring having a taper portion is formed by controlling parameters relating to etching is shown.

First, a 50-nm-thick silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) as the insulating film 11 on the glass substrate 10 by the plasma CVD method (composition ratio S
i = 32%, O = 59%, N = 7%, H = 2%).
A TaN film having a film thickness of 50 nm was formed as the first conductive film 11 on the insulating film 11, and a W film having a film thickness of 370 nm was formed as the second conductive film 13 on the first conductive film 12 by a sputtering method.
Then, a resist is formed and a bias power density of 0.96 W / cm ² , which is an etching condition, I
CP power density of 0.71 W / cm ² , pressure of 1.0 Pa, lower electrode temperature of 70 ° C., CF ₄ and Cl ₂ and O ₂ were used as etching gases, and the flow rate ratio of each gas was 25:25:10 ( scc
m) (The oxygen addition rate in the etching gas is 17%, which is 1.36 × 1 in terms of volume.
The etching of the W film was performed as follows: 0 ³ : 1.36 × 10 ³ : 0.54 × 10 ³ (sccm / m ³ )). Then, as an etching condition for the TaN film, CF ₄ and Cl ₂ are used as an etching gas.
And the respective gas flow rate ratios of 30:30 (sccm) (converted into a volume of 1.63 × 10 ³ sccm / m ³ respectively), a pressure of 1 Pa was applied to the coil-type electrode of 500 W RF (1
3.56 MHz) power (0.71 W / cm ² in terms of power density) was applied to generate plasma for etching. 20 W of RF (13.56 MHz) power (0.128 W / cm ² in terms of power density) was also applied to the substrate side (sample stage), and a substantially negative self-bias voltage was applied.

FIG. 15 shows the results of observing the cross-sectional shape with a SEM at a magnification of 50,000 after the first conductive film and the second conductive film were etched in this manner. The taper angle at this time was 20 °.

In this embodiment, the present invention is applied to an insulated gate field effect transistor (MOSFET or IG).
An example of a case where a CMOS circuit is configured by applying it to a FET) will be described with reference to FIGS.

First, a single crystal silicon substrate 301 is prepared, an impurity element is implanted, and a P-type well 302,
An N-type well 303 is formed. The single crystal silicon substrate may be P-type or N-type. Such a structure is a so-called twin tub structure, and the well concentration is 1 × 10 ¹⁸ / cm ³ or less (typically 1 × 10 ^{16 to} 5 × 10 ¹⁷ / cm ³ ).

Next, after performing selective oxidation by a known LOCOS method or the like to form a field oxide film 304, an oxide film (later gate insulating film) 3 having a thickness of 30 nm is formed on the silicon surface by a thermal oxidation process.
Form 05. (Fig. 16 (A))

Next, the first gate electrode 306 and the second gate electrode 307 are formed. In this embodiment, a conductive silicon film is used as a material for forming the gate electrode, but Ta,
An element selected from W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the above element as a main component can be used.

After the formation of the first gate electrode 306 and the second gate electrode 307, a region (right side in the drawing) to be a p-channel MOSFET is covered with a resist mask 308 so that the single crystal silicon substrate 301 is n-type. The impurity element to be added is introduced. (FIG. 16B) As a method for introducing the impurity element, any one of a laser doping method, a plasma doping method, an ion implantation method, and an ion shower doping method is used, and the concentration is 5 × 10 ¹⁸ to 1 × 10 5.
^It is introduced so that it becomes ¹⁹ / cm ³ . In this example, As was used as the impurity element for imparting n-type conductivity.
To use. Part of the impurity regions 310 and 311 thus formed (the end portion on the side in contact with the channel formation region) will later function as an LDD region of the n-channel MOSFET.

Next, the region to be the n-channel MOSFET is covered with the resist mask 312.
Then, an impurity element imparting p-type conductivity is introduced into the single crystal silicon substrate 301. (FIG. 16C) In this embodiment, B (boron) is used as the impurity element imparting n-type.
In this manner, the impurity regions 314 and 315 which later function as LDD regions of the p-channel MOSFET are formed.

After the state of FIG. 16C is obtained, a silicon oxide film (not shown) is next deposited and etched back to form sidewalls 316 and 317. (Fig. 17 (A)
)

Next, a region to be a p-channel MOSFET is covered again with a resist mask 318, and an impurity element imparting n-type is introduced at a concentration of 1 × 10 ²⁰ / cm ³ . Thus the source region 31
9, the drain region 320 is formed, and the LDD region 321 is formed under the sidewall 316. (Fig. 17 (B))

Similarly, a region to be an n-channel MOSFET is covered with a resist mask 322, and an impurity element imparting p-type is introduced at a concentration of 1 × 10 ²⁰ / cm ³ . Thus, the drain region 32
3, the source region 324 is formed, and the LDD region 325 is formed under the sidewall 317. (FIG. 17C) Further, one or more elements selected from rare gas elements are introduced while being covered with the resist mask 322. In this way, the second gate electrode 30
A large amount of the impurity element is introduced into the first gate electrode 306. Thereby, the second
The compressive stress of the gate electrode 307 of the p-channel type M
The compressive stress received by the channel forming region in the OSFET is also stronger than the stress received by the channel forming region in the n-channel MOSFET.

After the state of FIG. 17C is obtained, first heat treatment is performed to activate the introduced impurity element.

Then, a titanium film is formed and second heat treatment is performed to form a titanium silicide layer 326 on the surfaces of the source region, the drain region, and the gate electrode. Of course, it is also possible to form a metal silicide using another metal film. After forming the silicide layer, the titanium film is removed.

Next, an interlayer insulating film 327 is formed, contact holes are opened, and source electrodes 328 and 32 are formed.
9. Form the drain electrode 330. Of course, it is also effective to perform hydrogenation after forming the electrodes. In this embodiment, a W film is formed and the source electrodes 328 and 329 are formed using an ICP etching device.
The drain electrode 330 is formed. By forming in this way, variation in width and length of the metal wiring can be reduced.

Through the steps described above, a CMOS circuit as shown in FIG. 18 can be obtained. By applying the present invention, the variation in the shape of the metal wiring is reduced, and by having the tapered portion at the end of the metal wiring, the coverage is improved. Furthermore, the operating characteristics of the semiconductor device can be significantly improved.

  Note that this embodiment can be combined with the first embodiment.

In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. In this specification, a substrate in which a pixel portion including a CMOS circuit and a driver circuit, a pixel TFT, and a storage capacitor is formed over one substrate is referred to as an active matrix substrate for convenience.

First, in this embodiment, a substrate 400 made of glass such as barium borosilicate glass typified by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. Note that as the substrate 400, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

Then, a base film 401 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 400. Although a two-layer structure is used as the base film 401 in this embodiment,
A single layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 401, a silicon oxynitride film 401a formed using SiH ₄ , NH ₃ , and N ₂ O as reaction gases is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm) by using a plasma CVD method. To do. In this embodiment, a silicon oxynitride film 401a having a film thickness of 50 nm (composition ratio Si = 32%, O =
27%, N = 24%, H = 17%). Then, as the second layer of the base film 401, a silicon oxynitride film 401b formed by using a plasma CVD method using SiH ₄ and N ₂ O as a reaction gas is deposited to a thickness of 50 to 200 nm (preferably 100 to 150 nm). Laminated to a thickness. In this embodiment, a silicon oxynitride film 401b having a film thickness of 100 nm (composition ratio Si = 32%, O =
59%, N = 7%, H = 2%).

Next, semiconductor layers 402 to 406 are formed over the base film. The semiconductor layers 402 to 406 are formed to have a thickness of 25 to 80 n by a known method (sputtering method, LPCVD method, plasma CVD method, or the like).
A semiconductor film is formed with a thickness of m (preferably 30 to 60 nm), and a known crystallization method (laser crystallization method, thermal crystallization method using RTA or furnace annealing, metal element that promotes crystallization) is formed. (For example, a thermal crystallization method using). Then, the obtained crystalline semiconductor film is patterned into a desired shape to form semiconductor layers 402 to 406. Examples of the semiconductor film include an amorphous semiconductor film, a microcrystalline semiconductor film, and a crystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In this embodiment, plasma C
A 55 nm amorphous silicon film is formed by the VD method. Then, a solution containing nickel is held on the amorphous silicon film, and the amorphous silicon film is dehydrogenated (at 500 ° C. for 1 hour).
Thermal crystallization (550 ° C., 4 hours) is performed to form a crystalline silicon film. Then, the semiconductor layers 402 to 406 are formed by a patterning process using a photolithography method.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti is used. : A sapphire laser or the like can be used. In the case of using these lasers, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly focused by an optical system and is applied to a semiconductor film. The crystallization conditions are appropriately selected by the practitioner, but when an excimer laser is used, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 700 mJ / cm ² (typically 200 to 300 mJ / cm ² ).
In the case of using a YAG laser of pulse oscillation type is a pulse oscillation frequency 1~300Hz using the second harmonic wave, the laser energy density 300~1000mJ / cm ² (typically 350~800mJ / cm ²⁾ Is good. And a width of 100 to 1000 μm, for example 400
It is also possible to irradiate a laser beam that is linearly condensed with μm over the entire surface of the substrate and set the overlapping ratio (overlap ratio) of the linear beams at this time to 50 to 98%.

However, in this embodiment, since the amorphous silicon film is crystallized using the metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 nm is formed on the crystalline silicon film, and a heat treatment (RTA method, thermal annealing using a furnace annealing furnace or the like) is performed to form the amorphous silicon film in the amorphous silicon film. The metal element is diffused, and the amorphous silicon film is removed by etching after heat treatment. By doing so, the content of the metal element in the crystalline silicon film can be reduced or removed.

Further, after forming the semiconductor layers 402 to 406, a slight amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

Next, a gate insulating film 407 which covers the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) having a thickness of 110 nm is formed by the plasma CVD method. Of course, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho
Silica) and O ₂ are mixed, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm ² to discharge.
The silicon oxide film produced in this manner can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Next, a first conductive film 408 with a thickness of 20 to 100 nm and a second conductive film 409 with a thickness of 100 to 400 nm are stacked over the gate insulating film 407. In this embodiment, the film thickness is 30n
A first conductive film 408 made of a TaN film of m and a second conductive film 409 made of a W film having a thickness of 370 nm are stacked. The TaN film is formed by a sputtering method, and is sputtered in an atmosphere containing nitrogen using a Ta target. The W film is formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less.

Although the first conductive film 408 is TaN and the second conductive film 409 is W in this embodiment, the second conductive film is W or an alloy material or a compound material containing W as a main component, or
If the first conductive film is made of Al or an alloy material or a compound material containing Al as a main component, and the selection ratio between the first conductive film and the second conductive film is high at the time of etching, It is not particularly limited. For example, it may be formed of an element selected from Ta, Ti, Mo, Cu, Cr, and Nd, or an alloy material or a compound material containing the above element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also,
AgPdCu alloy may be used.

Next, masks 410 to 415 made of resist are formed using a photolithography method, and first etching treatment for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. (FIG. 19 (B)) In this example, as the first etching condition, an ICP (Inductively Coupled Plasma) etching method was used, and CF ₄ , Cl _2, and O ₂ were used as etching gases, Each gas flow ratio is 2
At 5:25:10 (sccm), a pressure of 1 Pa was applied to the coil-shaped electrode of RF of 500 W (13.56
MHz) Power is supplied to generate plasma for etching. RF (13.56 MHz) power of 150 W is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. The W film is etched under the first etching condition so that the end portion of the first conductive layer is tapered.

Thereafter, the masks 410 to 415 made of resist are not removed, and the second etching condition is changed to CF ₄ and Cl _{2 as} etching gas, and the respective gas flow ratios are set to 30:30 (
sccm), 500 W of RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching was performed for about 30 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.
Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. In order to etch without leaving a residue on the gate insulating film, 10
It is advisable to increase the etching time at a rate of about 20%.

In the first etching process, the shape of the mask made of resist is made suitable, and the ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Becomes The angle of this tapered portion is 15 to 45 °. Thus, the first shape conductive layer 41 including the first conductive layer and the second conductive layer is formed by the first etching process.
7 to 422 (first conductive layers 417a to 422a and second conductive layers 417b to 422b) are formed. Reference numeral 416 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 417 to 422 is etched by about 20 to 50 nm to form a thinned region.

Next, a second etching process is performed without removing the resist mask.
(FIG. 19C) Here, CF ₄ , Cl _2, and O ₂ are used as an etching gas, and the W film is selectively etched. At this time, the second conductive layers 428b to 428b are formed by the second etching treatment.
3b is formed. On the other hand, the first conductive layers 417a to 422a are hardly etched and the second shape conductive layers 428 to 433 are formed.

The conductive layers 428 to 433 formed in this manner have reduced variation in shape in the plane of the substrate.

Then, the first doping process is performed without removing the mask made of resist, and an impurity element imparting n-type conductivity is added to the semiconductor layer at a low concentration. The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10 ^{13 to} 5 ×.
The acceleration voltage is set to 10 ¹⁴ / cm ² and the acceleration voltage is set to 40 to 80 keV. In this embodiment, the dose amount is 1.
The acceleration voltage is set to 5 × 10 ¹³ / cm ² and the acceleration voltage is set to 60 keV. As the impurity element imparting n-type, an element belonging to Group 15 is used, typically phosphorus (P) or arsenic (As), but phosphorus (P) is used here. In this case, the conductive layers 428 to 433 serve as masks for the impurity element imparting n-type, and the impurity regions 423 to 427 are formed in a self-aligned manner. An impurity element imparting n-type conductivity is added to the impurity regions 423 to 427 in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ .

After removing the resist masks, new resist masks 434a to 434a-4
34c is formed, and the second doping process is performed at an acceleration voltage higher than that of the first doping process. The conditions of the ion doping method are a dose of 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² and an acceleration voltage of 6
It is performed as 0 to 120 keV. In the doping process, the second conductive layers 428b to 432b are used as masks for the impurity element, and doping is performed so that the semiconductor layer below the tapered portion of the first conductive layer is added with the impurity element. Then, the accelerating voltage is lowered from the second doping process and the third doping process is performed to obtain the state of FIG. The condition of the ion doping method is that the dose amount is 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ² and the acceleration voltage is 50 to 100 keV. By the second doping treatment and the third doping treatment, the low-concentration impurity regions 436, 442, and 448 overlapping with the first conductive layer are n-doped in a concentration range of 1 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ^3.
A high-concentration impurity region 435, 438, 441, 444 added with an impurity element imparting a mold
447 is doped with an impurity element imparting n-type in a concentration range of 1 × 10 ^{19 to} 5 × 10 ²¹ / cm ³ .

Of course, it is also possible to form the low-concentration impurity region and the high-concentration impurity region by performing the second doping process and the third doping process once by setting an appropriate acceleration voltage.

Next, after removing the resist mask, a new resist mask 450 is formed.
a to 450c are formed and a fourth doping process is performed. By the fourth doping process, impurity regions 453 to 456, 459, and 460 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to a semiconductor layer which is an active layer of a p-channel TFT are formed. To do. The second conductive layers 428a to 432a are used as masks for the impurity element, the impurity element imparting p-type conductivity is added, and the impurity region is formed in a self-aligned manner. In this embodiment, the impurity region 453 is used.
˜456, 459 and 460 are formed by an ion doping method using diborane (B ₂ H ₆ ). (
20B. At the time of the fourth doping process, the semiconductor layer forming the n-channel TFT is covered with masks 450a to 450c made of resist. Although phosphorus is added to the impurity regions 438 and 439 at different concentrations by the first to third doping processes, the concentration of the impurity element imparting p-type conductivity is set to 1 × 10 ¹⁹ to
A p-channel TFT is formed by performing a doping process to obtain 5 × 10 ²¹ atoms / cm ^3.
There is no problem because it functions as a source region and a drain region.

Through the above steps, the impurity regions are formed in the respective semiconductor layers. Since the variation in the shape of the conductive film within the substrate surface is reduced, the variation in the length and width of the low concentration impurity region and the channel formation region is also reduced.

Next, the masks 450a to 450c made of resist are removed to remove the first interlayer insulating film 46.
1 is formed. The first interlayer insulating film 461 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method. Of course, the first interlayer insulating film 461 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Next, as illustrated in FIG. 20C, heat treatment is performed to recover the crystallinity of the semiconductor layers and activate the impurity elements added to the respective semiconductor layers. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to
It may be performed at 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours.
In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (R
TA method) can be applied.

In addition, heat treatment may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, it is activated after forming an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) to protect the wiring and the like as in this embodiment. It is preferable to carry out a chemical treatment.

When heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) is performed, hydrogenation can be performed. This step is a step of terminating the dangling bond of the semiconductor layer with hydrogen contained in the first interlayer insulating film 461. The semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. As other means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or 1 to 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen is used.
You may perform heat processing for 12 hours.

When the laser annealing method is used as the activation treatment, after performing the above hydrogenation,
Irradiation with a laser beam such as an excimer laser or a YAG laser is desirable.

Then, a second interlayer insulating film 462 made of an inorganic insulating film material or an organic insulating material is formed over the first interlayer insulating film 461. In this embodiment, an acrylic resin film having a film thickness of 1.6 μm is formed, but an acrylic resin film having a viscosity of 10 to 1000 cp, preferably 40 to 200 cp is used, and an uneven surface is used.

In this example, in order to prevent specular reflection, the second interlayer insulating film having unevenness formed on the surface was formed to form unevenness on the surface of the pixel electrode. In addition, in order to make the surface of the pixel electrode uneven so as to achieve light scattering, a convex portion may be formed in a region below the pixel electrode. In that case, since the projection can be formed using the same photomask as that for forming the TFT, the projection can be formed without increasing the number of steps. Note that this convex portion may be appropriately provided on the substrate in the pixel portion region other than the wiring and the TFT portion. Thus, the unevenness is formed on the surface of the pixel electrode along the unevenness formed on the surface of the insulating film covering the convex portion.

Alternatively, a film having a flat surface may be used as the second interlayer insulating film 462. In that case, after forming the pixel electrode, a step such as a publicly known sandblast method or etching method is added to make the surface uneven so as to prevent specular reflection and scatter reflected light to increase whiteness. Is preferred.

Then, in the drive circuit 506, the wiring 46 electrically connected to each impurity region.
4 to 468 are formed. Note that these wirings have a Ti film with a film thickness of 50 nm and a film thickness of 500 n.
A laminated film of an alloy film of m (alloy film of Al and Ti) is patterned and formed. Of course, the structure is not limited to the two-layer structure, and may be a single-layer structure or a laminated structure of three or more layers. The material of the wiring is not limited to Al and Ti.
For example, the wiring may be formed by forming Al or Cu on the TaN film and then patterning the laminated film on which the Ti film is formed. (Figure 21)

In the pixel portion 507, the pixel electrode 470, the gate wiring 469, the connection electrode 468.
To form. By this connection electrode 468, the source wiring (a stack of 443a and 443b) is electrically connected to the pixel TFT. The gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. In addition, the pixel electrode 470 is electrically connected to the drain region 442 of the pixel TFT, and further electrically connected to the semiconductor layer 458 which functions as one electrode which forms a storage capacitor. Further, as the pixel electrode 471, it is desirable to use a material having excellent reflectivity such as a film containing Al or Ag as a main component, or a laminated film thereof.

As described above, the CM including the n-channel TFT 501 and the p-channel TFT 502
A driver circuit 506 including an OS circuit and an n-channel TFT 503, and a pixel TFT 504.
The pixel portion 507 having the storage capacitor 505 can be formed over the same substrate. Thus, the active matrix substrate is completed.

The n-channel TFT 501 of the driver circuit 506 includes a channel formation region 437 and a low-concentration impurity region 436 (GOLD region) which overlaps with the first conductive layer 428a forming part of the gate electrode.
A high-concentration impurity region 452 which functions as a source region or a drain region, and an impurity region 451 in which an impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity are introduced. This n-channel TFT 501 is connected to the electrode 466 to form a CMOS circuit p
The channel TFT 502 has a channel formation region 440, a high-concentration impurity region 454 which functions as a source region or a drain region, and an impurity region 453 into which an impurity element imparting n-type and an impurity element imparting p-type are introduced. ing. In addition, the n-channel type TFT5
Reference numeral 03 denotes a channel formation region 443, a low-concentration impurity region 442 (GOLD region) overlapping with the first conductive layer 430a forming part of the gate electrode, a high-concentration impurity region 456 functioning as a source region or a drain region, and n. It has an impurity region 455 into which an impurity element imparting a type and an impurity element imparting a p-type are introduced.

The pixel TFT 504 in the pixel portion is provided with a channel formation region 446, a low concentration impurity region 445 (LDD region) formed outside the gate electrode, a high concentration impurity region 458 functioning as a source region or a drain region, and an n-type. It has an impurity region 457 into which an impurity element and an impurity element imparting p-type conductivity are introduced. An impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity are added to the semiconductor layer functioning as one electrode of the storage capacitor 505. The storage capacitor 505 uses the insulating film 416 as a dielectric to form the electrodes (432a and 432a).
32b) and a semiconductor layer.

In the pixel structure of the present embodiment, the end portion of the pixel electrode is arranged and formed so as to overlap the source wiring so that the gap between the pixel electrodes is shielded from light without using the black matrix.

22 is a top view of the pixel portion of the active matrix substrate manufactured in this embodiment. The same reference numerals are used for the portions corresponding to FIGS. A chain line A- in FIG.
A'corresponds to the cross-sectional view taken along the chain line AA 'in FIG. Further, the chain line BB ′ in FIG. 21 corresponds to the cross-sectional view taken along the chain line BB ′ in FIG.

  Note that this embodiment can be combined with the first embodiment.

In this example, a process of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Example 3 will be described below. FIG. 23 is used for the description.

First, according to Example 3, after obtaining the active matrix substrate in the state of FIG. 21, an alignment film 567 is formed on at least the pixel electrode 470 on the active matrix substrate of FIG. 21, and rubbing treatment is performed. In this embodiment, before forming the alignment film 567, an organic resin film such as an acrylic resin film is patterned to maintain the space between the substrates.
72 was formed at the desired location. Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, the counter substrate 569 is prepared. Then, the colored layers 570 and 57 are formed over the counter substrate 569.
1. A flattening film 573 is formed. By overlapping the red colored layer 570 and the blue colored layer 571,
A light shielding part is formed. In addition, the light-shielding portion may be formed by partially overlapping the red colored layer and the green colored layer.

In this embodiment, the substrate shown in the third embodiment is used. Therefore, in FIG. 22, which is a top view of the pixel portion of Example 3, at least the gap between the gate wiring 469 and the pixel electrode 470, the gap between the gate wiring 469 and the connection electrode 468, and the gap between the connection electrode 468 and the pixel electrode 470 are shown. You need to block light. In this example, the colored layers were arranged so that the light-shielding portions formed by stacking the colored layers overlap each other at the positions where they should be shielded, and the counter substrates were bonded together.

In this way, the number of steps can be reduced by forming a light-shielding layer such as a black mask without forming a light-shielding layer so that the gaps between the pixels are shielded by a light-shielding portion formed by stacking colored layers.

Next, a counter electrode 576 made of a transparent conductive film was formed on the planarization film 573 at least in the pixel portion, an alignment film 574 was formed over the entire surface of the counter substrate, and a rubbing treatment was performed.

Then, the active matrix substrate in which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 568. A filler is mixed in the sealing material 568, and the two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 575 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material 575. Thus, the reflection type liquid crystal display device shown in FIG. 23 is completed. Then, if necessary, the active matrix substrate or the counter substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, the FPC was attached using a known technique.

In the liquid crystal display panel manufactured as described above, variation in shape of the conductive layer is reduced, and variation in width and length of the channel formation region and the low-concentration impurity region is also reduced, which is favorable. It is possible to show operating characteristics. Then, such a liquid crystal display panel can be used as a display unit of various electronic devices.

Note that this embodiment can be freely combined with any one of Embodiments 1 to 3.

In this example, an example of manufacturing a light emitting device using the present invention will be described. In this specification, a light emitting device is a generic term for a display panel in which a light emitting element formed on a substrate is enclosed between the substrate and a cover material, and a display module in which an IC is mounted on the display panel. is there. Note that the light-emitting element has a luminescence (Electro Luminesc) generated by applying an electric field.
ence) is obtained, a layer (light emitting layer) containing an organic compound, an anode layer, and a cathode layer. Also,
Luminescence in organic compounds is the emission of light when returning from the singlet excited state to the ground state (
Fluorescence) and light emission (phosphorescence) when returning from the triplet excited state to the ground state, and either or both of them are included.

In this specification, all layers formed between the anode and the cathode in the light emitting element are defined as the organic light emitting layer. The organic light emitting layer specifically includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, a light emitting device has a structure in which an anode layer, a light emitting layer, and a cathode layer are sequentially stacked. In addition to this structure, an anode layer, a hole injection layer, a light emitting layer, a cathode layer, and an anode layer are provided. It may have a structure in which a hole injecting layer, a light emitting layer, an electron transporting layer, a cathode layer and the like are laminated in this order.

FIG. 24 is a cross-sectional view of the light emitting device of this example. In FIG. 24, the switching TFT 603 provided on the substrate 700 is formed using the n-channel TFT 503 of FIG. Therefore, the description of the n-channel TFT 503 may be referred to for the description of the structure.

Although the double gate structure in which two channel forming regions are formed is used in this embodiment, a single gate structure in which one channel forming region is formed or a triple gate structure in which three channel forming regions are formed may be used.

The driver circuit provided over the substrate 700 is formed using the CMOS circuit in FIG. Therefore, for the description of the structure, the description of the n-channel TFT 501 and the p-channel TFT 502 may be referred to. Although a single gate structure is used in this embodiment, a double gate structure or a triple gate structure may be used.

The wirings 701 and 703 function as a source wiring of the CMOS circuit and the wiring 702 functions as a drain wiring. The wiring 704 functions as a wiring that electrically connects the source wiring 708 and the source region of the switching TFT, and the wiring 705 is a drain wiring 709 and a switching T.
It functions as a wiring that electrically connects the drain region of the FT.

The current control TFT 604 is formed using the p-channel TFT 502 of FIG. Therefore, the description of the structure may be referred to the description of the p-channel TFT 502. Although a single gate structure is used in this embodiment, a double gate structure or a triple gate structure may be used.

The wiring 706 is a source wiring of the current control TFT (corresponding to a current supply line), and
Reference numeral 07 is an electrode that is electrically connected to the pixel electrode 710 by being superimposed on the pixel electrode 710 of the current control TFT.

710 is a pixel electrode (anode of a light emitting element) formed of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 710 is formed on the flat interlayer insulating film 711 before forming the wiring. In this embodiment, the flattening film 7 made of resin is used.
It is very important to use 11 to flatten the step due to the TFT. Since the light emitting layer that is formed later is very thin, the light emitting failure may occur due to the existence of the step. Therefore, it is desirable to flatten the light emitting layer before forming the pixel electrode so that the light emitting layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG.
The bank 712 may be formed by patterning an insulating film containing 100 to 400 nm of silicon or an organic resin film.

Since the bank 712 is an insulating film, it is necessary to pay attention to electrostatic breakdown of the element during film formation. In this embodiment, carbon particles or metal particles are added to the insulating film that is the material of the bank 712 to lower the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of carbon particles or metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

A light emitting layer 713 is formed on the pixel electrode 710. Although only one pixel is shown in FIG. 24, the light emitting layers corresponding to the colors of R (red), G (green), and B (blue) are separately formed in this embodiment. Further, in this embodiment, the low molecular weight organic light emitting material is formed by the vapor deposition method.
Specifically, a 20-nm-thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70-nm-thick tris-8-quinolinolato aluminum complex (Alq ₃
) The film has a laminated structure.
The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1 to Alq ₃ .

However, the above example is an example of an organic light emitting material that can be used as a light emitting layer, and it is not necessary to limit to this. The light emitting layer (charge transporting layer or charge injecting layer) may be freely combined to form a light emitting layer (a layer for emitting light and for moving carriers therefor). For example, in this embodiment, an example in which a low molecular weight organic light emitting material is used as the light emitting layer is shown, but a medium molecular weight organic light emitting material or a high molecular weight organic light emitting material may be used. In the present specification,
An organic light-emitting material having no sublimation property and having a number of molecules of 20 or less or a length of chained molecules of 10 μm or less is referred to as a medium-molecular organic light-emitting material. Further, as an example of using a polymer organic light emitting material, a 20 nm polythiophene (PEDOT) film is provided as a hole injection layer by a spin coating method, and a paraphenylene vinylene (PPV) film having a thickness of about 100 nm is provided thereon as a light emitting layer. It may be a laminated structure. By using a PPV π-conjugated polymer, the emission wavelength can be selected from red to blue. Further, it is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used as these organic light emitting materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the light emitting layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (
An alloy film of magnesium and silver) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

The light emitting element 715 is completed when the cathode 714 is formed. Note that the light-emitting element 715 here refers to a diode formed of the pixel electrode (anode) 710, the light-emitting layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating films are used as a single layer or a stacked layer in which they are combined.

At this time, it is preferable to use a film having good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range of room temperature to 100 ° C. or lower, it can be easily formed over the light-emitting layer 713 having low heat resistance. Further, the DLC film has a high oxygen blocking effect and can suppress oxidation of the light emitting layer 713. Therefore, it is possible to prevent the problem that the light emitting layer 713 is oxidized during the subsequent sealing step.

Further, a sealing material 717 is provided on the passivation film 716 and a cover material 718 is attached. An ultraviolet curable resin may be used as the sealing material 717, and it is effective to provide a substance having a moisture absorption effect or a substance having an antioxidant effect inside. In this embodiment, the cover material 718 is a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) having carbon films (preferably diamond-like carbon films) formed on both sides.

Thus, the light emitting device having the structure as shown in FIG. 24 is completed. Note that it is effective to continuously perform the steps from the formation of the bank 712 to the formation of the passivation film 716 using a multi-chamber system (or in-line system) film formation apparatus without exposing to the atmosphere. .. Further, it is also possible to further develop and continuously process up to the step of attaching the cover material 718 without exposing to the atmosphere.

Thus, on the substrate 700, n-channel type TFTs 601, 602, switching TFTs (
An n-channel TFT 603 and a current control TFT (n-channel TFT) 604 are formed.

Further, as described with reference to FIG. 24, by providing the gate electrode with the impurity region overlapping with the insulating film interposed therebetween, an n-channel TFT which is resistant to deterioration due to the hot carrier effect can be formed. Therefore, a highly reliable light emitting device can be realized.

Although only the configurations of the pixel portion and the driving circuit are shown in the present embodiment, according to the manufacturing process of the present embodiment, other logic circuits such as a signal dividing circuit, a D / A converter, an operational amplifier and a γ correction circuit are also shown. Can be formed on the same insulator, and further a memory and a microprocessor can be formed.

Further, the light emitting device of this embodiment after the sealing (or encapsulation) step for protecting the light emitting element is performed will be described with reference to FIG. In addition, the reference numerals used in FIG. 24 are cited as needed.

25A is a top view showing a state where the light-emitting element is sealed, and FIG. 25B is FIG.
It is sectional drawing which cut | disconnected 5 (A) by CC '. Reference numeral 801 indicated by a dotted line is a source side driver circuit, 806 is a pixel portion, and 807 is a gate side driver circuit. 901 is a cover material, and 902
Is a first sealing material, 903 is a second sealing material, and a sealing material 907 is provided inside the first sealing material 902.

Reference numeral 904 denotes a wiring for transmitting a signal input to the source side driver circuit 801 and the gate side driver circuit 807, which receives a video signal or a clock signal from an FPC (flexible printed circuit) 905 which serves as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to this FPC. The light emitting device in this specification includes not only the light emitting device body but also the FPC or P
The state in which the WB is attached is also included.

Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate side driver circuit 807 are formed above the substrate 700, and the pixel portion 806 includes the current control TFT 60.
4 and a pixel electrode 710 electrically connected to its drain. Further, the gate side drive circuit 807 includes an n-channel TFT 601 and a p-channel TFT 6
It is formed by using a CMOS circuit (see FIG. 20) in which 02 and 02 are combined.

The pixel electrode 710 functions as an anode of the light emitting element. Banks 712 are formed on both ends of the pixel electrode 710, and the light emitting layer 713 and the cathode 714 of the light emitting element are formed on the pixel electrode 710.
Is formed.

The cathode 714 also functions as a wiring common to all pixels, and is connected to the FPC 9 via the connection wiring 904.
05 is electrically connected. Further, all the elements included in the pixel portion 806 and the gate side driver circuit 807 are covered with the cathode 714 and the passivation film 567.

Further, the cover material 901 is attached by the first sealing material 902. A spacer made of a resin film may be provided in order to secure a space between the cover material 901 and the light emitting element.
A sealing material 907 is filled inside the first sealing material 902. An epoxy resin is preferably used as the first sealing material 902 and the sealing material 907. Further, it is desirable that the first sealing material 902 is a material that does not allow moisture and oxygen to permeate as much as possible. further,
A substance having a moisture absorption effect or a substance having an antioxidant effect may be contained inside the sealing material 907.

The sealing material 907 provided so as to cover the light emitting element also functions as an adhesive for bonding the cover material 901. Further, in this embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (Polyvinyl Fluoride), Mylar, polyester or acrylic can be used as the material of the plastic substrate 901a constituting the cover material 901.

Further, after the cover material 901 is bonded using the sealing material 907, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. The second sealing material 903 is the first sealing material 90.
The same material as 2 can be used.

By encapsulating the light emitting element in the sealing material 907 with the above structure, the light emitting element can be completely shielded from the outside, and a substance such as moisture or oxygen which promotes deterioration due to oxidation of the light emitting layer enters from the outside. Can be prevented. Therefore, a highly reliable light emitting device can be obtained.

In the light-emitting device manufactured as described above, variation in shape of the conductive layer is reduced, variation in width and length of the channel formation region and the low-concentration impurity region is also reduced, and favorable operation is achieved. It becomes possible to show characteristics. And such a light emitting device can be used as a display part of various electronic devices.

Note that this embodiment can be freely combined with any one of Embodiments 1 to 3.

Various electro-optical devices to which the present invention is applied (active matrix type liquid crystal display device, active matrix type light emitting device, active matrix type EC display device)
Can be produced. That is, the present invention can be applied to various electronic devices in which those electro-optical devices are incorporated in the display section.

Such electronic devices include video cameras, digital cameras, projectors, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples thereof are shown in FIGS. 26, 27 and 28.

FIG. 26A shows a personal computer, which includes a main body 3001, an image input unit 3002,
A display portion 3003, a keyboard 3004, and the like are included. The present invention can be applied to the display portion 3003.

FIG. 26B illustrates a video camera, which includes a main body 3101, a display portion 3102, a voice input portion 31.
03, operation switch 3104, battery 3105, image receiving unit 3106 and the like. The present invention can be applied to the display portion 3102.

FIG. 26C illustrates a mobile computer (mobile computer), which has a main body 3201.
A camera unit 3202, an image receiving unit 3203, operation switches 3204, a display unit 3205, and the like. The present invention can be applied to the display portion 3205.

FIG. 26D shows a goggle type display, which includes a main body 3301, a display portion 3302, an arm portion 3303, and the like. The present invention can be applied to the display portion 3302.

FIG. 26E shows a player which uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, which includes a main body 3401, a display portion 3402, a speaker portion 3403, a recording medium 3404.
Including an operation switch 3405 and the like. This player uses a DVD (Di
It is possible to play music, watch movies, play games, and use the Internet by using a digital versatile disc), a CD, or the like.
The present invention can be applied to the display portion 3402.

FIG. 26F illustrates a digital camera, which includes a main body 3501, a display portion 3502, and an eyepiece portion 350.
3, an operation switch 3504, an image receiving unit (not shown), and the like. The present invention can be applied to the display portion 3502.

FIG. 27A shows a front type projector, which includes a projection device 3601 and a screen 36.
Including 02 etc. The present invention can be applied to the liquid crystal display device 3808 which constitutes a part of the projection device 3601 and other drive circuits.

FIG. 27B shows a rear type projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. The present invention can be applied to the liquid crystal display device 3808 which constitutes a part of the projection device 3702 and other drive circuits.

Note that FIG. 27C shows a projection device 3601 in FIGS. 27A and 27B.
It is a figure which showed an example of the structure of 3702. The projection devices 3601 and 3702 are the light source optical system 3
801, mirrors 3802, 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a retardation plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited and may be, for example, a single-plate type. In addition, the practitioner appropriately uses an optical lens, a film having a polarizing function, or a film having a polarization function in the optical path indicated by an arrow in FIG.
An optical system such as a film for adjusting the phase difference or an IR film may be provided.

27D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 27C. In this embodiment, the light source optical system 3801 includes a reflector 3811 and a light source 38.
12, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. The light source optical system shown in FIG. 27D is an example and is not particularly limited.
For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 27, the case where a transmissive electro-optical device is used is shown, and application examples in a reflective electro-optical device and a light emitting device are not shown.

FIG. 28A illustrates a mobile phone including a main body 3901, a voice output portion 3902, and a voice input portion 39.
03, display unit 3904, operation switch 3905, antenna 3906 and the like. The present invention can be applied to the display portion 3904.

FIG. 28B illustrates a portable book (electronic book) including a main body 4001 and display portions 4002 and 400.
3, a storage medium 4004, an operation switch 4005, an antenna 4006 and the like. The present invention can be applied to the display portions 4002 and 4003.

FIG. 28C illustrates a display, which includes a main body 4101, a support base 4102, a display portion 4103.
Including etc. The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when it has a large screen and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. Further, the electronic devices of the present embodiment are the first embodiment, the second embodiment, and the first to fourth embodiments.
Alternatively, it can be realized by using a configuration including any combination of the first to third embodiments and the fifth embodiment.

Claims (1)

A gate electrode,
A semiconductor layer including a source region, a drain region and a channel forming region,
A gate insulating film having a region between the gate electrode and the channel formation region,
A gate wiring electrically connected to the gate electrode,
A source wiring electrically connected to the source region or the drain region through a wiring,
The gate wiring intersects with the source wiring,
The source wiring is in the same layer as the gate electrode,
The semiconductor device is characterized in that the gate electrode has a tapered shape at an end.

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