JP6087970B2 - Display device, display module, and electronic device - Google Patents

Description

The present invention relates to a metal wiring formed using thin film technology and a method for manufacturing the same. Also,
The present invention relates to a metal wiring board and a manufacturing method thereof. Note that in this specification, the metal wiring substrate refers to an insulating substrate such as glass or various substrates having metal wiring formed using thin film technology.

In recent years, a thin film transistor (TFT) is formed using a semiconductor thin film (thickness of about several to several hundred nm) formed on a substrate having an insulating surface, and a semiconductor device having a large-area integrated circuit formed using this TFT is developed. Is progressing. Active matrix liquid crystal display devices, light emitting devices, and contact image sensors are known as representative examples. In particular, TFTs having a crystalline silicon film (typically polysilicon film) as an active region (hereinafter referred to as polysilicon TFT) have high field-effect mobility, so that various functional circuits can be formed. It is.

For example, in an active matrix liquid crystal display device, a pixel circuit for displaying an image for each functional block, a pixel circuit such as a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, and a sampling circuit are controlled. A drive circuit is formed on a single substrate.

A pixel circuit of an active matrix type liquid crystal display device has several tens to millions of pixels for each pixel.
FT (pixel TFT) is arranged, and each of the pixel TFTs is provided with a pixel electrode. A counter electrode is provided on the counter substrate side with the liquid crystal interposed therebetween, and a kind of capacitor using the liquid crystal as a dielectric is formed. Then, the voltage applied to each pixel is controlled by the switching function of the TFT, and the liquid crystal is driven by controlling the charge to this capacitor, and the transmitted light quantity is controlled to display an image.

The pixel TFT is generally composed of an n-channel TFT, and is driven by applying a voltage to the liquid crystal as a switching element. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often employed. In this method, the pixel TF is used to reduce power consumption.
As for the characteristics required for T, it is important to sufficiently reduce the off-current value (drain current that flows when the TFT is turned off).

As a TFT structure for reducing the off-current value, a low concentration drain (LDD: Lightly
Doped Drain) structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. A so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film is known as means for preventing deterioration of an on-current value due to hot carriers. . With such a structure, it is known that a high electric field in the vicinity of the drain is relaxed, hot carrier injection is prevented, and the deterioration phenomenon is effective.

An example for forming the GOLD structure will be described with reference to the drawings. Forming a base insulating film on the substrate, forming a semiconductor film on the base insulating film, forming an insulating film on the semiconductor film;
A conductive film is formed on the insulating film. Note that in FIG. 1A, the base insulating film has a stacked structure, but may have a single-layer structure or may not be formed. Moreover, although the said electrically conductive film is made into the single layer structure, it is good also as a laminated structure of two or more layers. Subsequently, a resist is formed, and etching is performed to make the end portion of the conductive film into a tapered shape. (FIG. 1B) As this etching method, a dry etching method using high-density plasma is desirable. An etching apparatus using microwaves or inductively coupled plasma (ICP) is suitable for obtaining high-density plasma. Then, a low concentration impurity region overlapping with the gate electrode and a high concentration impurity region functioning as a source region or a drain region are formed in the semiconductor film by the first doping process and the second doping process. By the above processing, G
An OLD structure can be realized.

Etching conditions in the ICP etching apparatus are bias power density, ICP power density, pressure, total flow rate of etching gas, and temperature of the lower electrode. In addition, when oxygen is added to the etching gas, etching is promoted, so the oxygen addition rate in the etching gas is also one of the conditions.

However, the selection ratio between the resist and the conductive film varies depending on the etching conditions, and the width of the conductive film may vary within the substrate surface. In the case where the conductive film is used as a gate electrode, the conductive film serves as a mask when an impurity element is introduced; therefore, variations in the width of the conductive film are caused by the length of the channel formation region and the conductive film and the LDD region. This causes variation in the length of overlapping regions. When a TFT is manufactured using such a semiconductor film, it causes a variation in electrical characteristics, and further causes a decrease in operating characteristics of the semiconductor device. Further, when the conductive film is used as a wiring, the variation in the width of the conductive film causes a variation in wiring resistance,
The electrical characteristics of the TFT are degraded. As described above, variations in the width and length of the conductive film are becoming a more serious problem as the substrate becomes larger, and it is extremely difficult to improve uniformity by suppressing variations in the width and length of the conductive film. Is important to.

The present invention is a technique for solving such problems, and it is an object of the present invention to provide a metal wiring and a manufacturing method thereof that can cope with an increase in the size of a substrate, and a metal wiring substrate and a manufacturing method thereof.

The structure of the invention related to the metal wiring disclosed in this specification is a conductive layer formed of a tungsten film, a metal compound film mainly containing a tungsten compound, or a metal alloy film mainly containing a tungsten alloy. The taper angle α at the end of the conductive layer is 5 °
It is characterized by being in a range of ˜85 °.

In the above configuration, the metal alloy film includes Ta, Ti, Mo, Cr, Nb, Si, Sc,
It is an alloy film of one kind of element selected from Nd or a plurality of kinds of elements and tungsten.

In the above structure, the metal compound film is a tungsten nitride film.

In another aspect of the invention relating to the metal wiring, an aluminum film, a metal compound film containing an aluminum compound as a main component, or a conductive layer formed of a metal alloy film containing an aluminum alloy as a main component, The taper angle α at the end of the conductive layer is 5 ° to 85
It is characterized by a range of °.

In the above configuration, the metal alloy film includes Ta, Ti, Mo, Cr, Nb, Si, Sc,
It is an alloy film of one element selected from Nd or a plurality of elements and aluminum.

In the above structure, the metal compound film is an aluminum nitride film.

In each of the above structures, a conductive silicon film (for example, a phosphorus-doped silicon film, a boron-doped silicon film, or the like) may be provided in the lowermost layer in order to improve adhesion.

Further, the configuration of the invention related to the metal wiring board disclosed in this specification is a metal wiring board having an insulating substrate and a metal wiring, wherein the metal wiring is a tungsten film or a metal compound containing a tungsten compound as a main component. A conductive layer formed of a film or a metal alloy film containing a tungsten alloy as a main component, and the taper angle α at the end of the conductive layer is 5 ° to
It is characterized by a range of 85 °.

In another aspect of the invention related to the metal wiring board, the metal wiring board having an insulating substrate and a metal wiring, the metal wiring is an aluminum film, or a metal compound film mainly containing an aluminum compound, or A conductive layer formed of a metal alloy film containing an aluminum alloy as a main component, wherein the taper angle α at the end of the conductive layer is in the range of 5 ° to 85 °.

In addition, in the structure of the invention relating to the method for manufacturing a metal wiring disclosed in this specification, at least one conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is formed. Etching the taper angle α according to the bias power density
Is characterized in that a controlled metal wiring is formed.

In another aspect of the invention relating to a method for manufacturing a metal wiring, at least one conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched. A metal wiring having a taper angle α controlled according to the ICP power density is formed.

In another aspect of the invention relating to a method for manufacturing a metal wiring, at least one conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched. A metal wiring having a taper angle α controlled according to the temperature of the lower electrode is formed.

In the configuration relating to the metal wiring manufacturing method, the temperature of the lower electrode is 85 to 120 ° C.
It is characterized by that.

In another aspect of the invention relating to a method for manufacturing a metal wiring, at least one conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched. A metal wiring having a taper angle α controlled according to pressure is formed.

In the configuration related to the metal wiring manufacturing method, the pressure is 2.0 to 13 Pa.

In another aspect of the invention relating to a method for manufacturing a metal wiring, at least one conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched. A metal wiring having a taper angle α controlled according to the flow rate of the reaction gas is formed.

Further, in the configuration related to the metal wiring manufacturing method, the total flow rate of the reaction gas is 2.6.
It is characterized by being 1 × 10 ^{3 to} 10.87 × 10 ³ sccm / m ³ .

In another aspect of the invention relating to a method for manufacturing a metal wiring, at least one conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched. The metal wiring is characterized in that the taper angle α is controlled in accordance with the proportion of oxygen in the reaction gas.

In the configuration relating to the method for manufacturing the metal wiring, the proportion of oxygen in the reaction gas is 1
It is characterized by 7 to 50%.

In another aspect of the invention relating to a method for manufacturing a metal wiring, at least one conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched. The metal wiring is characterized in that the taper angle α is controlled in accordance with the ratio of chlorine in the reaction gas.

Further, in each configuration relating to the method for manufacturing a metal wiring, the metal thin film is a thin film selected from a tungsten film, a metal compound film containing a tungsten compound as a main component, and a metal alloy film containing a tungsten alloy as a main component, and an aluminum film. And a thin film selected from a metal compound film mainly composed of an aluminum compound and a metal alloy film mainly composed of an aluminum alloy.

Further, the configuration of the invention relating to the method for manufacturing a metal wiring board disclosed in this specification includes an insulating substrate,
In a manufacturing method of a metal wiring substrate having a metal wiring, at least one conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and etching is performed on the conductive film having the resist pattern. A metal wiring having a taper angle α controlled according to the power density is formed.

Further, another configuration of the invention relating to a method for manufacturing a metal wiring board is the method for manufacturing a metal wiring board having an insulating substrate and a metal wiring, wherein at least one conductive film is formed on the insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring having a taper angle α controlled in accordance with the ICP power density.

Further, another configuration of the invention relating to a method for manufacturing a metal wiring board is the method for manufacturing a metal wiring board having an insulating substrate and a metal wiring, wherein at least one conductive film is formed on the insulating surface,
A resist pattern is formed on the conductive film, the conductive film having the resist pattern is etched, and a metal wiring having a taper angle α controlled according to the temperature of the lower electrode is formed.

In the configuration related to the method for manufacturing the metal wiring board, the temperature of the lower electrode is 85 to 12%.
It is characterized by being 0 ° C.

Further, another configuration of the invention relating to a method for manufacturing a metal wiring board is the method for manufacturing a metal wiring board having an insulating substrate and a metal wiring, wherein at least one conductive film is formed on the insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring having a taper angle α controlled according to pressure.

In the configuration related to the method for manufacturing the metal wiring board, the pressure is 2.0 to 13 Pa.

Further, another configuration of the invention relating to a method for manufacturing a metal wiring board is the method for manufacturing a metal wiring board having an insulating substrate and a metal wiring, wherein at least one conductive film is formed on the insulating surface,
A resist pattern is formed on the conductive film, the conductive film having the resist pattern is etched, and a metal wiring having a taper angle α controlled according to the total flow rate of the reaction gas is formed.

In the configuration relating to the method for manufacturing the metal wiring board, the total flow rate of the reaction gas is 2.61.
It is characterized by being set to × 10 ^{3 to} 10.87 × 10 ³ sccm / m ³ .

Further, another configuration of the invention relating to a method for manufacturing a metal wiring board is the method for manufacturing a metal wiring board having an insulating substrate and a metal wiring, wherein at least one conductive film is formed on the insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring in which the taper angle α is controlled in accordance with the proportion of oxygen in the reaction gas.

In the configuration related to the method for manufacturing the metal wiring board, the ratio of oxygen in the reaction gas is 17 to 50%.

Further, another configuration of the invention relating to a method for manufacturing a metal wiring board is the method for manufacturing a metal wiring board having an insulating substrate and a metal wiring, wherein at least one conductive film is formed on the insulating surface,
A resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring in which the taper angle α is controlled according to the ratio of chlorine in the reaction gas.

Further, in each configuration relating to the method for manufacturing the metal wiring substrate, the metal thin film is a thin film selected from a tungsten film, a metal compound film mainly containing a tungsten compound, and a metal alloy film mainly containing a tungsten alloy, aluminum It is a thin film selected from a film, a metal compound film containing an aluminum compound as a main component, and a metal alloy film containing an aluminum alloy as a main component.

By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) It is a simple method adapted to a conventional process for manufacturing a wiring or a wiring board.
(B) By changing the bias power density, the ICP power density, the temperature of the lower electrode, or the ratio of chlorine in the etching gas, it is possible to form a wiring having a desired taper angle.
(C) By setting the pressure, the total flow rate of the etching gas, the ratio of oxygen in the etching gas, and the temperature of the lower electrode to predetermined values, it is possible to reduce variations in the substrate surface.
(D) After satisfying the above advantages, the metal wiring or metal wiring board can sufficiently cope with the increase in size of the board.

(A) The figure which shows the relationship between W and the etching rate of a resist with respect to bias power density. (B) The figure which shows the relationship between W and the selection ratio of a resist with respect to a bias power density. (A) The figure which shows the relationship between W and the etching rate of a resist with respect to ICP power density. (B) The figure which shows the relationship between W with respect to ICP power density, and the selection ratio of a resist. (A) The figure which shows the relationship between W with respect to a pressure, and the etching rate of a resist. (B) The figure which shows the relationship between W with respect to a pressure, and the selection ratio of a resist. (A) The figure which shows the relationship between W with respect to the oxygen addition rate in etching gas, and the etching rate of a resist. (B) The figure which shows the relationship between the selection ratio of W with respect to the oxygen addition rate in etching gas. (A) The figure which shows the relationship between W with respect to the total flow rate of etching gas, and the etching rate of a resist. (B) The figure which shows the relationship between W and the selectivity of a resist with respect to the total flow rate of etching gas. (A) The figure which shows the relationship between W and the etching rate of a resist with respect to the temperature of a lower electrode. (B) The figure which shows the relationship between W and the resist selection ratio with respect to the temperature of a lower electrode. The figure which shows the example of an ICP etching apparatus. The figure which shows the example of the concept of this invention. (A) The figure which shows the relationship of the taper angle with respect to the selection ratio of resist / W when a bias power density is used as a parameter. (B) The figure which shows the relationship of the taper angle with respect to the selection ratio of resist / W when ICP power density is used as a parameter. (A) The figure which shows the relationship of the taper angle with respect to the selection ratio of resist / W when pressure is used as a parameter. (B) The figure which shows the relationship of the taper angle with respect to the selection ratio of resist / W when the oxygen addition rate in etching gas is made into a parameter. (A) The figure which shows the relationship of the taper angle with respect to the selection ratio of resist / W when the total flow rate of etching gas is used as a parameter. (B) The figure which shows the relationship of the taper angle with respect to the selection ratio of resist / W when the temperature of a lower electrode is made into a parameter. (A) The figure which shows the relationship between the etching rate of Al-Si and a resist with respect to a bias power density. (B) The figure which shows the relationship of the selection ratio of Al-Si and a resist with respect to bias power density. (A) The figure which shows the relationship between the etching rate of Al-Si and a resist with respect to ICP power density. (B) The figure which shows the relationship of the selectivity of Al-Si and a resist with respect to ICP power density. (A) The figure which shows the relationship between the etching rate of Al-Si and a resist with respect to the chlorine addition rate in etching gas. (B) The figure which shows the relationship of the selectivity of Al-Si and a resist with respect to the chlorine addition rate in etching gas. FIG. 6 is a diagram showing an example of the shape of a wiring manufactured by applying the present invention. FIG. 6 shows an example of a wiring manufactured by applying the present invention. FIG. 6 shows an example of a wiring manufactured by applying the present invention. FIG. 6 shows an example of a wiring manufactured by applying the present invention. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. FIG. 6 is a top view illustrating a configuration of a pixel TFT. Sectional drawing which shows the manufacturing process of an active-matrix liquid crystal display device. FIG. 6 is a cross-sectional structure diagram of a driver circuit and a pixel portion of a light emitting device. FIG. 4A is a top view of a light-emitting device. FIG. 5B is a cross-sectional structure diagram of a driver circuit and a pixel portion of a light-emitting device. FIG. 11 illustrates an example of a semiconductor device. FIG. 11 illustrates an example of a semiconductor device. FIG. 11 illustrates an example of a semiconductor device.

[Embodiment 1]
In the present invention, an ICP etching apparatus using high-density plasma is used. ICP
The etching apparatus inductively couples RF power into the plasma at a low pressure to provide 10 ¹¹
A plasma density of not less than ³ / cm ³ is achieved, and processing with a high selectivity and a high etching rate is performed.

First, the ICP dry etching apparatus plasma generation mechanism will be described in detail with reference to FIG.

FIG. 7A shows a simplified structural diagram of the etching chamber. Quartz plate 31 at the top of the chamber
An antenna coil 32 is disposed above and connected to an RF power source 34 via a matching box 33. The matching box 36 is also applied to the lower electrode 35 on the substrate side that is arranged opposite to the substrate.
An RF power source 37 is connected via

When an RF current is applied to the antenna coil 32 above the substrate, the RF current J flows through the antenna coil 32 in the θ direction, and a magnetic field B is generated in the Z direction.

In accordance with Faraday's law of electromagnetic induction, an induced electric field E is generated in the θ direction.

Electrons are accelerated in the θ direction by this induced electric field E, collide with gas molecules, and plasma is generated.
Since the direction of the induced electric field is the θ direction, the probability that the charged particles collide with the etching chamber wall or the substrate and lose the charge is reduced. Therefore, high-density plasma can be generated even at a low pressure of about 1 Pa. Further, since there is almost no magnetic field B downstream, a high-density plasma region spreading in a sheet shape is obtained.

The plasma density and the self-bias voltage are independently controlled by adjusting the RF power applied to each of the antenna coil 32 (ICP power is applied) and the lower electrode 35 on the substrate side (bias power is applied). Is possible. In addition, it is possible to vary the frequency of the RF power to be applied according to the material of the object to be processed.

In order to obtain high-density plasma with an ICP etching apparatus, R flowing through the antenna coil 32
It is necessary to flow the F current J with low loss, and in order to increase the area, the inductance of the antenna coil 32 must be reduced. For this purpose, an ICP etching apparatus for a multi-spiral coil 38 having an antenna divided therein has been developed, and its structural diagram is shown in FIG. Note that portions other than the quartz plate (chamber structure, lower electrode structure, etc.) are the same, and are omitted here. When an etching apparatus using ICP to which such a multi-spiral coil 38 is applied is used, the heat-resistant conductive material can be satisfactorily etched.

The present inventors performed the experiment described below by changing the etching conditions using this multi-spiral coil ICP etching apparatus (Matsushita Electric Industrial Co., Ltd .: E645).

First, a conductive film made of a W film having a thickness of 500 nm was formed on a glass substrate as a sample by sputtering. Then, a resist is formed, and the bias power density which is an etching condition
Etching of the W film was performed under various conditions for ICP power density, pressure, oxygen addition rate in etching, the total flow rate of etching gas, and the temperature of the lower electrode. Table 1 shows how to set each condition. Further, in the case where the evaluation is performed under certain conditions, the values shown in Table 2 are used for the other conditions. In Tables 1 and 2, the unit of the bias power density and the ICP power density is [W / cm ² ].
W]. The bias power and the ICP power described in Table 1 and Table 2 are respectively an area on which the bias power is applied 12.5 cm × 12.5 cm and an area on which the ICP power is applied.
The value divided by 5 cm × 12.5 cm × π is shown. The chamber volume is 18.
Since it is 4 × 10 ⁻³ m ³ , the total flow rate of the etching gas is indicated by a value divided by the volume of the chamber.

The results obtained by varying each condition are shown in FIGS. Each figure (A) shows the etching rate of W and the resist, and each figure (B) shows the selectivity ratio of W to the resist. In each case, the number of measurement points is 16 in the substrate surface, and the variation in the substrate surface is indicated by error bars. FIG. 1 shows the result of changing the bias power density condition, FIG. 2 shows the result of changing the ICP power density condition, FIG. 3 shows the result of changing the pressure condition, and FIG. 4 shows the oxygen addition rate. FIG. 5 shows the result of changing the total gas flow rate, and FIG. 6 shows the result of changing the temperature condition of the lower electrode.

First, the variation in the substrate plane will be considered. As shown in FIG. 1A, the variation is minimum when the bias power density is 0.256 to 0.512 W / cm ² , and increases when the bias power density is 0.96 W / cm ² or more. Further, from FIG. 2A, there is no particular tendency in the ICP power density due to conditions. 3 (A) to 6 (A)
Thus, the higher the pressure, the oxygen addition rate, the total gas flow rate, and the temperature of the lower electrode, the smaller the variation.

Next, the selection ratio of W to resist will be considered. From FIG. 1B to FIG. 6B, the selection ratio of W to the resist is the bias power density, ICP as the conditions change.
There is a large change in the power density and the temperature of the lower electrode.
That is, it can be seen that the conditions affecting the W selection ratio with respect to the resist are the bias power density, the ICP power density, and the temperature of the lower electrode.

From the above experiments, it was found that the bias power density, ICP power density, and the temperature of the lower electrode have a great influence on the selectivity of the W film to the resist. Also, pressure, oxygen addition rate,
It was found that if the total gas flow rate and the temperature of the lower electrode were set high, the variation in the substrate surface was reduced.

In order to investigate the correlation between the resist / W selection ratio and the taper angle, the following experiment was conducted. This will be described with reference to FIG. Note that in this specification, the taper angle refers to FIG.
As shown, the angle α formed by the taper portion (inclined portion) of the cross-sectional shape of the conductive layer 15b and the surface of the base film 17b. The taper angle is determined by using the width Z of the taper portion and the film thickness X, and tan α =
It can be defined as X / Z.

First, a 50 nm-thick silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) is formed on the glass substrate 10 as an insulating film 11 by plasma CVD.
i = 32%, O = 59%, N = 7%, H = 2%).
A TaN film having a thickness of 50 nm was formed as the first conductive film 11 on the insulating film 11, and a W film having a thickness of 370 nm was formed as the second conductive film 13 on the first conductive film 12 by sputtering.
Then, a resist was formed, and etching of the W film was performed by varying the etching power conditions such as bias power density, ICP power density, pressure, oxygen addition rate in etching, the total flow rate of etching gas, and the temperature of the lower electrode. . Table 1 shows how to set each condition. Further, in the case where the evaluation is performed under certain conditions, the values shown in Table 2 are used for the other conditions. Subsequently, as etching conditions for the TaN film, CF ₄ and Cl ₂ are used as etching gases, the respective gas flow ratios are set to 30:30 (sccm), and 1 Pa.
Etching was performed by generating plasma by applying 0.71 W / cm ² RF (13.56 MHz) power to the coil-shaped electrode at a pressure of 1 mm. RF of 0.128 W / cm ² also on the substrate side (sample stage)
(13.56 MHz) Power was applied and a substantially negative self-bias voltage was applied.

After etching the first conductive film and the second conductive film in this way, the cross-sectional shape is observed with a SEM at 50,000 times, the taper angle is obtained, and the resist / W selection ratio is compared with the resist / W selection ratio. I investigated the relationship. The results are shown in FIGS. FIG. 9A shows the relationship between the resist / W selection ratio and the taper angle when the bias power density is changed, and FIG. 9B shows the resist / W selection ratio and the taper when the ICP power density is changed. 10A shows the relationship between the resist / W selection ratio and the taper angle when the pressure is changed, and FIG. 10B shows the relationship between the oxygen addition rate in the etching gas. FIG. 11A shows the relationship between the resist / W selection ratio and the taper angle. FIG. 11A shows the relationship between the resist / W selection ratio and the taper angle when the total flow rate of the etching gas is changed. FIG. The relationship between the resist / W selection ratio and the taper angle when the electrode temperature is changed is shown. 9 to 11, it can be seen that the conditions that greatly affect the taper angle are the bias power density, the ICP power density, and the temperature of the lower electrode.

Therefore, the present invention forms a wiring having a desired taper angle by controlling the bias power density, the ICP power density, and the temperature of the lower electrode when etching the W film using the ICP etching apparatus, In addition, etching with high uniformity can be performed even on a large-area substrate. Furthermore, if the pressure, the oxygen addition rate, the total gas flow rate, and the temperature of the lower electrode are set high, it is possible to reduce variations in the shape of the wiring in the substrate surface. In particular,
Since the variation in shape of the gate electrode made of the W film formed using the present invention in the substrate surface is reduced, when the impurity element is introduced using the gate electrode as a mask, the width and length of the impurity region It is possible to reduce the occurrence of variations. That is, variation in the width and length of the channel formation region can be reduced, and variation in electrical characteristics of a TFT manufactured using such a semiconductor film can be reduced.
Furthermore, it is possible to improve the operating characteristics and reliability of the semiconductor device.

Note that the present invention can be applied not only to the W film but also to various films mainly composed of W such as a Mo—W film, a WSi film, and a TiW film.

[Embodiment 2]
The inventors used the multi-spiral coil ICP etching apparatus (Made by Matsushita Electric Industrial Co., Ltd .: E645) described in Embodiment 1 to change the etching conditions for the conductive film different from that in the embodiment, and will be described below. Experiments were also conducted.

First, on a glass substrate as a sample, Al—Si (with a thickness of 500 nm) is formed by sputtering.
A conductive film made of a 2 wt% film was formed. Then, a resist was formed, and the Ai-Si film was etched under various conditions with respect to etching conditions such as bias power density, ICP power density, and Cl ₂ addition rate in etching. Table 3 shows how to set each condition. In the case where the evaluation is performed under certain conditions, the values shown in Table 4 are used for the other conditions. In Tables 1 and 2, bias power density and IC
The unit of P power density is [W / cm ² ], but in actuality, power [W] is applied. The bias power and ICP power described in Table 1 and Table 2 are respectively the area where the bias power is applied 12.5 cm × 12.5 cm and the area where the ICP power is applied 12.5 cm × 12.5 cm
The value divided by xπ is shown. Further, since the volume of the chamber is 18.4 × 10 ⁻³ m ³ , the total flow rate of the etching gas is shown as a value divided by the volume of the chamber.

The results obtained by varying each condition are shown in FIGS. Each figure (A) shows the etching rate of Al—Si and the resist, and each figure (B) shows the selectivity of Al—Si to the resist. In each case, the number of measurement points is 16 in the substrate surface, and the variation in the substrate surface is indicated by error bars. 12 shows the result of changing the bias power density condition, FIG. 13 shows the result of changing the ICP power density condition, and FIG. 14 shows the result of changing the Cl ₂ addition rate condition.

Consider the selection ratio of Al—Si to resist. 12 (B) to 14 (B)
Thus, the Al—Si selection ratio with respect to the resist greatly changes as the conditions change. That is, it can be seen that the conditions affecting the Al—Si selection ratio with respect to the resist are bias power density, ICP power density, and Cl ₂ addition rate.

Accordingly, the present invention forms a wiring having a desired taper angle by controlling the bias power density, ICP power density, and Cl ₂ addition rate when etching an Al—Si film using an ICP etching apparatus. It is possible to do. In particular, A formed using the present invention
Since the gate electrode made of an l-Si film can have a desired taper angle, when an impurity element is introduced using the gate electrode as a mask, an impurity region having a desired width and length is formed. Make it possible. That is, a channel formation region having a desired width and length can be formed, and variations in electrical characteristics of TFTs manufactured using such a semiconductor film can be reduced. Furthermore, it is possible to improve the operating characteristics and reliability of the semiconductor device.

In the present invention, not only the W film but also Al—Ti film, Al—Sc film, Al—Nd film, etc.
It can be applied to various films containing as a main component.

Examples of the present invention will be described below, but it is needless to say that the present invention is not limited to these examples.

In this embodiment, an example in which a metal wiring having a tapered portion is formed by controlling parameters relating to etching will be described.

First, a 50 nm-thick silicon oxynitride film (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) is formed on the glass substrate 10 as an insulating film 11 by plasma CVD.
i = 32%, O = 59%, N = 7%, H = 2%).
A TaN film having a thickness of 50 nm was formed as the first conductive film 11 on the insulating film 11, and a W film having a thickness of 370 nm was formed as the second conductive film 13 on the first conductive film 12 by sputtering.
Then, a resist is formed, and a bias power density of 0.96 W / cm ² which is an etching condition, I
CP power density of 0.71 W / cm ² , pressure of 1.0 Pa, lower electrode temperature of 70 ° C., CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the respective gas flow ratios are 25:25:10 ( scc
m) (Oxygen addition rate in the etching gas is 17%, converted to volume 1.36 × 1
The W film was etched at 0 ³ : 1.36 × 10 ³ : 0.54 × 10 ³ (sccm / m ³ )). Subsequently, as etching conditions for the TaN film, CF ₄ and Cl ₂ are used as etching gases.
Each gas flow rate ratio is 30:30 (sccm) (1.63 × 10 ³ sccm / m ³ in terms of volume), and 500 W RF (1
3.56 MHz) power (0.71 W / cm ² in terms of power density) was input to generate plasma and perform etching. 20 W RF (13.56 MHz) power (0.128 W / cm ² in terms of power density) was also applied to the substrate side (sample stage), and a substantially negative self-bias voltage was applied.

FIG. 15 shows the result of observing the cross-sectional shape of the first conductive film and the second conductive film at 50,000 times with an SEM after etching the first conductive film and the second conductive film. The taper angle at this time was 20 °.

In this embodiment, the present invention is applied to an insulated gate field effect transistor (MOSFET or IG).
An example in which a CMOS circuit is configured by applying to a FET) will be described with reference to FIGS.

First, a single crystal silicon substrate 301 is prepared, an impurity element is implanted, and a P-type well 302,
An N-type well 303 is formed. The single crystal silicon substrate may be P-type or N-type. Such a structure is a so-called twin tab structure, and the well concentration is 1 × 10 ¹⁸ / cm ³ or less (typically 1 × 10 ^{16 to} 5 × 10 ¹⁷ / cm ³ ).

Next, after selective oxidation is performed by a known LOCOS method or the like to form a field oxide film 304, a 30 nm thick oxide film (later gate insulating film) 3 is formed on the silicon surface by a thermal oxidation process.
05 is formed. (FIG. 16 (A))

Next, a first gate electrode 306 and a second gate electrode 307 are formed. In this embodiment, a conductive silicon film is used as a material constituting the gate electrode, but Ta,
An element selected from W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component can be used.

After the formation of the first gate electrode 306 and the second gate electrode 307, a region to be a p-channel MOSFET (on the right side in the drawing) is covered with a resist mask 308, and an n-type is formed with respect to the single crystal silicon substrate 301. Impurity elements to be introduced are introduced. (FIG. 16 (B)) As a method for introducing the impurity element, any one of a laser doping method, a plasma doping method, an ion implantation method, and an ion shower doping method is used, and the concentration is 5 × 10 ¹⁸ to 1 × 10.
It introduce | transduces so that it may become ¹⁹ / cm < ³ >. In this embodiment, As an impurity element imparting n-type conductivity is As.
Is used. Part of the impurity regions 310 and 311 formed in this way (ends on the side in contact with the channel formation region) later functions as an LDD region of the n-channel MOSFET.

Next, a region to be an n-channel MOSFET is covered with a resist mask 312.
Then, an impurity element imparting p-type conductivity is introduced into the single crystal silicon substrate 301. (FIG. 16C) In this embodiment, B (boron) is used as an impurity element imparting n-type conductivity.
In this manner, impurity regions 314 and 315 that later function as LDD regions of the p-channel MOSFET are formed.

When the state of FIG. 16C is obtained, a silicon oxide film (not shown) is next deposited and etched back to form sidewalls 316 and 317. (FIG. 17 (A)
)

Next, a region to be a p-channel MOSFET is again covered with a resist mask 318, and an impurity element imparting n-type conductivity is introduced at a concentration of 1 × 10 ²⁰ / cm ³ . Thus, the source region 31
9, a drain region 320 is formed, and an LDD region 321 is formed under the sidewall 316. (Fig. 17 (B))

Similarly, a region to be an n-channel MOSFET is covered with a resist mask 322, and an impurity element imparting p-type conductivity is introduced at a concentration of 1 × 10 ²⁰ / cm ³ . Thus, the drain region 32
3. A source region 324 is formed, and an LDD region 325 is formed under the sidewall 317. (FIG. 17C) Further, one or more elements selected from rare gas elements are introduced while being covered with the resist mask 322. In this way, the second gate electrode 30
7, a larger amount of impurity element is introduced than the first gate electrode 306. As a result, the second
The compressive stress of the gate electrode 307 is stronger than that of the first gate electrode 306, and the p-channel type M
The compressive stress received by the channel formation region in the OSFET is also stronger than the stress received by the channel formation region in the n-channel MOSFET.

When the state of FIG. 17C is obtained, a first heat treatment is performed to activate the introduced impurity element.

Subsequently, a titanium film is formed and second heat treatment is performed to form a titanium silicide layer 326 on the surfaces of the source region, the drain region, and the gate electrode. Of course, a metal silicide using another metal film can also be formed. After the silicide layer is formed, the titanium film is removed.

Next, an interlayer insulating film 327 is formed, contact holes are opened, and source electrodes 328 and 32 are formed.
9. A drain electrode 330 is formed. Of course, it is also effective to perform hydrogenation after electrode formation. In this embodiment, a W film is formed and the source electrodes 328 and 329 are formed using an ICP etching apparatus.
The drain electrode 330 is formed. By forming in this way, variations in the width and length of the metal wiring are reduced.

Through the steps as described above, a CMOS circuit as shown in FIG. 18 can be obtained. By applying the present invention, variation in the shape of the metal wiring is reduced, and by providing the tapered portion at the end of the metal wiring, the coverage is improved. Furthermore, the operating characteristics of the semiconductor device can be greatly improved.

  Note that this embodiment can be combined with the first embodiment.

In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. In this specification, a substrate in which a pixel portion having a CMOS circuit, a driver circuit, a pixel TFT, and a storage capacitor is formed over the same substrate is referred to as an active matrix substrate for convenience.

First, in this embodiment, a substrate 400 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. Note that the substrate 400 may be a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

Next, a base film 401 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 400. In this embodiment, a two-layer structure is used as the base film 401.
A single layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 401, a silicon oxynitride film 401a formed using SiH ₄ , NH ₃ , and N ₂ O as a reactive gas is formed by using a plasma CVD method to a thickness of 10 to 200 nm (preferably 50 to 100 nm). To do. In this embodiment, a silicon oxynitride film 401a having a film thickness of 50 nm (composition ratio Si = 32%, O =
27%, N = 24%, H = 17%). Next, as a second layer of the base film 401, a silicon oxynitride film 401b formed by using a plasma CVD method and using SiH ₄ and N ₂ O as a reaction gas has a thickness of 50 to 200 nm (preferably 100 to 150 nm). Stacked to a thickness. In this embodiment, a silicon oxynitride film 401b with a film thickness of 100 nm (composition ratio Si = 32%, O =
59%, N = 7%, H = 2%).

Next, semiconductor layers 402 to 406 are formed over the base film. The semiconductor layers 402 to 406 are formed to 25 to 80 n by a known means (sputtering method, LPCVD method, plasma CVD method or the like).
m (preferably 30 to 60 nm) of a semiconductor film, and a known crystallization method (laser crystallization method, thermal crystallization method using RTA or furnace annealing furnace, metal element for promoting crystallization) For example, a thermal crystallization method using Then, the obtained crystalline semiconductor film is patterned into a desired shape to form semiconductor layers 402 to 406. Examples of the semiconductor film include an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, and the like, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In this embodiment, plasma C
A 55 nm amorphous silicon film is formed using the VD method. Then, after holding the solution containing nickel on the amorphous silicon film and dehydrogenating the amorphous silicon film (500 ° C., 1 hour),
Thermal crystallization (550 ° C., 4 hours) is performed to form a crystalline silicon film. Then, the semiconductor layers 402 to 406 are formed by a patterning process using a photolithography method.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, Ti : A sapphire laser or the like can be used. In the case of using these lasers, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 700 mJ / cm ² (typically 200 to 300 mJ / cm ^2). ).
In the case of using a YAG laser of pulse oscillation type is a pulse oscillation frequency 1~300Hz using the second harmonic wave, the laser energy density 300~1000mJ / cm ² (typically 350~800mJ / cm ²⁾ And good. And a width of 100 to 1000 μm, for example 400
The laser beam condensed linearly at μm may be irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time may be 50 to 98%.

However, in this embodiment, since the amorphous silicon film is crystallized using a metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 nm is formed on the crystalline silicon film, and heat treatment (RTA method, thermal annealing using a furnace annealing furnace, etc.) is performed, and the amorphous silicon film Metal elements are diffused, and the amorphous silicon film is removed by etching after the heat treatment. By doing so, the content of the metal element in the crystalline silicon film can be reduced or removed.

Further, after forming the semiconductor layers 402 to 406, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by plasma CVD or sputtering. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho
It can be formed by mixing silicate) and O ₂ , setting the reaction pressure to 40 Pa, the substrate temperature to 300 to 400 ° C., and discharging at a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² .
The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

Next, a first conductive film 408 with a thickness of 20 to 100 nm and a second conductive film 409 with a thickness of 100 to 400 nm are stacked over the gate insulating film 407. In this embodiment, the film thickness is 30n.
A first conductive film 408 made of m TaN film and a second conductive film 409 made of a 370 nm thick W film are stacked. The TaN film is formed by sputtering, and is sputtered in a nitrogen-containing atmosphere using a Ta target. The W film is formed by sputtering using a W target. In addition, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less.

Note that in this example, the first conductive film 408 is TaN and the second conductive film 409 is W, but the second conductive film is an alloy material or compound material containing W or W as a main component, or
If the first conductive film is formed of Al or an alloy material or compound material containing Al as a main component and the first conductive film and the second conductive film have a high selection ratio during etching, There is no particular limitation. For example, an element selected from Ta, Ti, Mo, Cu, Cr, and Nd, or an alloy material or a compound material containing the element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also,
An AgPdCu alloy may be used.

Next, resist masks 410 to 415 are formed by photolithography, and a first etching process is performed to form electrodes and wirings. The first etching process is performed under the first and second etching conditions. (FIG. 19B) In this example, ICP (Inductively Coupled Plasma) etching is used as the first etching condition, and CF ₄ , Cl _2, and O ₂ are used as etching gases. Each gas flow ratio is 2
5:25:10 (sccm), 500 W RF (13.56) applied to the coil-type electrode at a pressure of 1 Pa.
MHz) Power is applied to generate plasma and perform etching. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered.

Thereafter, the resist masks 410 to 415 are not removed and the second etching conditions are changed, CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30:30 (
The plasma was generated by applying 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa, and etching was performed for about 30 seconds. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.
Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. In order to perform etching without leaving a residue on the gate insulating film, 10
It is preferable to increase the etching time at a rate of about ˜20%.

In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layer 41 composed of the first conductive layer and the second conductive layer by the first etching process.
7 to 422 (first conductive layers 417a to 422a and second conductive layers 417b to 422b) are formed. Reference numeral 416 denotes a gate insulating film, and a region not covered with the first shape conductive layers 417 to 422 is etched and thinned by about 20 to 50 nm.

Next, a second etching process is performed without removing the resist mask.
Here, CF ₄ , Cl _2, and O ₂ are used as etching gases, and the W film is selectively etched. At this time, the second conductive layers 428b to 43 are formed by the second etching process.
3b is formed. On the other hand, the first conductive layers 417a to 422a are hardly etched, and the second shape conductive layers 428 to 433 are formed.

In the conductive layers 428 to 433 thus formed, variation in shape within the substrate surface is reduced.

Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer at a low concentration. The doping process may be performed by ion doping or ion implantation. The condition of the ion doping method is that the dose is 1 × 10 ^{13 to} 5 ×.
10 ¹⁴ / cm ² and acceleration voltage is 40 to 80 keV. In this embodiment, the dose is set to 1.
5 × 10 ¹³ / cm ² and the acceleration voltage is 60 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 428 to 433 serve as a mask for the impurity element imparting n-type, and the impurity regions 423 to 427 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the impurity regions 423 to 427 in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ .

After the resist mask is removed, new resist masks 434a to 434a-4 are formed.
34c is formed, and the second doping process is performed at an acceleration voltage higher than that of the first doping process. The condition of the ion doping method is that the dose is 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² and the acceleration voltage is 6
0 to 120 keV is performed. In the doping treatment, the second conductive layers 428b to 432b are used as masks against the impurity element, and doping is performed so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer. Subsequently, the third doping process is performed by lowering the acceleration voltage than the second doping process to obtain the state of FIG. The conditions of the ion doping method are a dose amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ² and an acceleration voltage of 50 to 100 keV. By the second doping process and the third doping process, the low-concentration impurity regions 436, 442, and 448 overlapping with the first conductive layer have n concentration in the concentration range of 1 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ^3.
An impurity element imparting a mold is added, and high-concentration impurity regions 435, 438, 441, 444 are added.
447 is doped with an impurity element imparting n-type in a concentration range of 1 × 10 ^{19 to} 5 × 10 ²¹ / cm ³ .

Needless to say, by setting the acceleration voltage to be appropriate, the second and third doping processes can be performed in a single doping process to form the low-concentration impurity region and the high-concentration impurity region.

Next, after removing the resist mask, a new resist mask 450 is formed.
a to 450c are formed and a fourth doping process is performed. By this fourth doping process, impurity regions 453 to 456, 459, and 460 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer that becomes the active layer of the p-channel TFT are formed. To do. The second conductive layers 428a to 432a are used as masks against the impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligning manner. In this embodiment, the impurity region 453 is used.
˜456, 459, and 460 are formed by ion doping using diborane (B ₂ H ₆ ). (
In the fourth doping process, the semiconductor layer for forming the n-channel TFT is covered with masks 450a to 450c made of resist. By the first to third doping treatments, phosphorus is added to the impurity regions 438 and 439 at different concentrations, and the concentration of the impurity element imparting p-type in each of the regions is set to 1 × 10 ¹⁹ to
A p-channel TFT is obtained by doping so as to be 5 × 10 ²¹ atoms / cm ^3.
No problem arises because it functions as a source region and a drain region.

Through the above steps, impurity regions are formed in the respective semiconductor layers. Since variations in the shape of the conductive film in the substrate surface are reduced, variations in the length and width of the low-concentration impurity region and the channel formation region are also reduced.

Next, the resist masks 450a to 450c are removed, and the first interlayer insulating film 46 is removed.
1 is formed. The first interlayer insulating film 461 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 461 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 20C, heat treatment is performed to recover the crystallinity of the semiconductor layers and to activate the impurity elements added to the respective semiconductor layers. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, an oxygen concentration is 1 ppm or less, preferably 400 ppm to 700 ° C., typically 500 to 100 ° C. in a nitrogen atmosphere of 0.1 ppm or less.
What is necessary is just to carry out at 550 degreeC, and the activation process was performed by the heat processing for 4 hours at 550 degreeC in the present Example.
In addition to thermal annealing, laser annealing or rapid thermal annealing (R
TA method) can be applied.

Further, heat treatment may be performed before the first interlayer insulating film is formed. However, when the wiring material used is weak against heat, it is activated after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring as in this embodiment. It is preferable to perform the conversion treatment.

Then, hydrogenation can be performed by heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 461. The semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. As other means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or 1 to 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen is possible.
You may heat-process for 12 hours.

In the case of using a laser annealing method as the activation treatment, after performing the hydrogenation,
It is desirable to irradiate a laser beam such as an excimer laser or a YAG laser.

Next, a second interlayer insulating film 462 made of an inorganic insulating film material or an organic insulating material is formed over the first interlayer insulating film 461. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed, but a film having a viscosity of 10 to 1000 cp, preferably 40 to 200 cp, and having a surface with unevenness is used.

In this embodiment, in order to prevent specular reflection, the surface of the pixel electrode is formed with the unevenness by forming the second interlayer insulating film having the unevenness on the surface. In addition, a convex portion may be formed in a region below the pixel electrode in order to make the surface of the pixel electrode uneven to achieve light scattering. In that case, since the convex portion can be formed using the same photomask as that of the TFT, it can be formed without increasing the number of steps. In addition, this convex part should just be suitably provided on the board | substrate of pixel part area | regions other than wiring and a TFT part. Thus, irregularities are formed on the surface of the pixel electrode along the irregularities formed on the surface of the insulating film covering the convex portions.

Alternatively, a film whose surface is planarized may be used as the second interlayer insulating film 462. In that case, after forming the pixel electrode, adding a step such as a known sandblasting method or etching method to make the surface uneven, prevent specular reflection, and increase the whiteness by scattering the reflected light Is preferred.

In the drive circuit 506, the wiring 46 electrically connected to each impurity region.
4 to 468 are formed. These wirings are a Ti film with a film thickness of 50 nm and a film thickness of 500 n.
The laminated film of the m alloy film (alloy film of Al and Ti) is formed by patterning. Of course, not only a two-layer structure but also a single-layer structure or a laminated structure of three or more layers may be used. Further, the wiring material is not limited to Al and Ti.
For example, a wiring may be formed by patterning a laminated film in which Al or Cu is formed on a TaN film and a Ti film is further formed. (Fig. 21)

In the pixel portion 507, the pixel electrode 470, the gate wiring 469, and the connection electrode 468 are used.
Form. With this connection electrode 468, the source wiring (stacked layer of 443a and 443b) is electrically connected to the pixel TFT. In addition, the gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. In addition, the pixel electrode 470 is electrically connected to the drain region 442 of the pixel TFT and further electrically connected to the semiconductor layer 458 functioning as one electrode forming a storage capacitor. Further, as the pixel electrode 471, it is desirable to use a highly reflective material such as a film containing Al or Ag as a main component or a laminated film thereof.

As described above, a CM composed of an n-channel TFT 501 and a p-channel TFT 502.
A driver circuit 506 including an OS circuit and an n-channel TFT 503, and a pixel TFT 504
The pixel portion 507 including the storage capacitor 505 can be formed over the same substrate. Thus, the active matrix substrate is completed.

An n-channel TFT 501 in the driver circuit 506 includes a channel formation region 437 and a low-concentration impurity region 436 (GOLD region) that overlaps with the first conductive layer 428a that forms part of the gate electrode.
, A high-concentration impurity region 452 functioning as a source region or a drain region, and an impurity region 451 into which an impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity are introduced. The n-channel TFT 501 and the electrode 466 are connected to form a CMOS circuit.
The channel TFT 502 includes a channel formation region 440, a high-concentration impurity region 454 functioning as a source region or a drain region, and an impurity region 453 into which an impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity are introduced. ing. In addition, n-channel TFT 5
03 includes a channel formation region 443, a low-concentration impurity region 442 (GOLD region) that overlaps with the first conductive layer 430a that forms part of the gate electrode, a high-concentration impurity region 456 that functions as a source region or a drain region, and n An impurity region 455 into which an impurity element imparting a type and an impurity element imparting a p-type are introduced is provided.

The pixel TFT 504 in the pixel portion is provided with a channel formation region 446, a low concentration impurity region 445 (LDD region) formed outside the gate electrode, a high concentration impurity region 458 functioning as a source region or a drain region, and an n-type. An impurity region 457 into which an impurity element and an impurity element imparting p-type conductivity are introduced is provided. In addition, an impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity are added to the semiconductor layer functioning as one electrode of the storage capacitor 505. The storage capacitor 505 includes an insulating film 416 as a dielectric and electrodes (432a and 4
32b) and a semiconductor layer.

In the pixel structure of this embodiment, the end portions of the pixel electrodes are arranged and formed so as to overlap the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

FIG. 22 shows a top view of a pixel portion of an active matrix substrate manufactured in this embodiment. In addition, the same code | symbol is used for the part corresponding to FIGS. Chain line A- in FIG.
A ′ corresponds to a cross-sectional view taken along the chain line AA ′ in FIG. Further, a chain line BB ′ in FIG. 21 corresponds to a cross-sectional view taken along the chain line BB ′ in FIG.

  Note that this embodiment can be combined with the first embodiment.

In this embodiment, a process for manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 3 will be described below. FIG. 23 is used for the description.

First, after obtaining the active matrix substrate in the state of FIG. 21 according to Embodiment 3, an alignment film 567 is formed on at least the pixel electrode 470 on the active matrix substrate of FIG. In this embodiment, before the alignment film 567 is formed, the columnar spacer 5 for maintaining the distance between the substrates by patterning an organic resin film such as an acrylic resin film.
72 was formed in the desired position. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.

Next, a counter substrate 569 is prepared. Next, the colored layers 570 and 57 are formed over the counter substrate 569.
1. A planarizing film 573 is formed. Overlapping the red colored layer 570 and the blue colored layer 571,
A light shielding part is formed. Further, the light shielding portion may be formed by partially overlapping the red colored layer and the green colored layer.

In this embodiment, the substrate shown in Embodiment 3 is used. Therefore, in FIG. 22 showing a top view of the pixel portion of Example 3, at least the gap between the gate wiring 469 and the pixel electrode 470, the gap between the gate wiring 469 and the connection electrode 468, and the gap between the connection electrode 468 and the pixel electrode 470 are shown. It is necessary to shield the light. In this example, the respective colored layers were arranged so that the light-shielding portions formed by the lamination of the colored layers overlapped at the positions where light shielding should be performed, and the counter substrate was bonded.

As described above, the number of steps can be reduced by shielding the gap between the pixels with the light shielding portion formed by the lamination of the colored layers without forming a light shielding layer such as a black mask.

Next, a counter electrode 576 made of a transparent conductive film was formed over the planarization film 573 in at least the pixel portion, an alignment film 574 was formed over the entire surface of the counter substrate, and a rubbing process was performed.

Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 568. A filler is mixed in the sealing material 568, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. after that,
A liquid crystal material 575 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. In this way, the reflection type liquid crystal display device shown in FIG. 23 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. And FPC was affixed using the well-known technique.

Since the liquid crystal display panel manufactured as described above has reduced variations in the shape of the conductive layer, variations in the width and length of the channel formation region and the low-concentration impurity region are also reduced. It is possible to show operating characteristics. And such a liquid crystal display panel can be used as a display part of various electronic devices.

Note that this embodiment can be freely combined with any one of Embodiments 1 to 3.

In this example, an example in which a light-emitting device is manufactured using the present invention will be described. In this specification, the light emitting device is a general term for a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module in which an IC is mounted on the display panel. is there. Note that the light-emitting element emits luminescence generated by applying an electric field (Electro Luminesc
ence) includes an organic compound-containing layer (light-emitting layer), an anode layer, and a cathode layer. Also,
Luminescence in organic compounds includes luminescence when returning from the singlet excited state to the ground state (
Fluorescence) and light emission (phosphorescence) when returning from the triplet excited state to the ground state, and includes either or both of them.

In the present specification, all layers formed between the anode and the cathode in the light emitting element are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, a light emitting element has a structure in which an anode layer, a light emitting layer, and a cathode layer are sequentially laminated. In addition to this structure, an anode layer, a hole injection layer, a light emitting layer, a cathode layer, and an anode layer , A hole injection layer, a light emitting layer, an electron transport layer, a cathode layer and the like may be laminated in this order.

FIG. 24 is a cross-sectional view of the light emitting device of this example. In FIG. 24, the switching TFT 603 provided over the substrate 700 is formed using the n-channel TFT 503 in FIG. Therefore, the description of the n-channel TFT 503 may be referred to for the description of the structure.

Note that although a double gate structure in which two channel formation regions are formed is used in this embodiment, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed may be used.

A driver circuit provided over the substrate 700 is formed using the CMOS circuit of FIG. Therefore, for the description of the structure, the description of the n-channel TFT 501 and the p-channel TFT 502 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

Further, the wirings 701 and 703 function as source wirings of the CMOS circuit, and the wiring 702 functions as a drain wiring. The wiring 704 functions as a wiring for electrically connecting the source wiring 708 and the source region of the switching TFT, and the wiring 705 is connected to the drain wiring 709 and the switching T.
It functions as a wiring that electrically connects the drain region of the FT.

Note that the current control TFT 604 is formed using the p-channel TFT 502 in FIG. Accordingly, the description of the p-channel TFT 502 may be referred to for the description of the structure. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

A wiring 706 is a source wiring of the current control TFT (corresponding to a current supply line).
Reference numeral 07 denotes an electrode that is electrically connected to the pixel electrode 710 by being superimposed on the pixel electrode 710 of the current control TFT.

Reference numeral 710 denotes a pixel electrode (anode of a light emitting element) made of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 710 is formed on the flat interlayer insulating film 711 before forming the wiring. In this embodiment, the planarizing film 7 made of resin.
It is very important to flatten the step due to the TFT using 11. Since the light emitting layer formed later is very thin, the presence of a step may cause a light emission failure. Therefore, it is desirable to planarize the pixel electrode before forming it so that the light emitting layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG.
The bank 712 may be formed by patterning an insulating film or organic resin film containing silicon of 100 to 400 nm.

Note that since the bank 712 is an insulating film, attention must be paid to electrostatic breakdown of elements during film formation. In this embodiment, carbon particles or metal particles are added to the insulating film that is the material of the bank 712 to reduce the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
0 ¹² [Omega] m (preferably ^{1 × 10 8 ~1 × 10 10} Ωm) may be adjusted the amount of the composed as carbon particles or metal particles.

A light emitting layer 713 is formed on the pixel electrode 710. Although only one pixel is shown in FIG. 24, in this embodiment, light emitting layers corresponding to the respective colors R (red), G (green), and B (blue) are separately formed. In this embodiment, a low molecular weight organic light emitting material is formed by a vapor deposition method.
Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a tris-8-quinolinolato aluminum complex (Alq ₃ ) having a thickness of 70 nm is formed thereon as a light emitting layer.
) A laminated structure provided with a film.
The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1 to Alq ₃ .

However, the above example is an example of an organic light emitting material that can be used as a light emitting layer, and it is not absolutely necessary to limit to this. A light emitting layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a low molecular weight organic light emitting material is used as the light emitting layer is shown, but a medium molecular weight organic light emitting material or a high molecular weight organic light emitting material may be used. In this specification,
An organic light-emitting material that does not have sublimation and has a number of molecules of 20 or less or a chained molecule length of 10 μm or less is defined as a medium molecular organic light-emitting material. As an example of using a polymer organic light emitting material, a 20 nm polythiophene (PEDOT) film is provided by a spin coating method as a hole injection layer, and a paraphenylene vinylene (PPV) film of about 100 nm is provided thereon as a light emitting layer. Alternatively, a laminated structure may be used. If a PPV π-conjugated polymer is used, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. Known materials can be used for these organic light emitting materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the light emitting layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (
An alloy film of magnesium and silver) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or Group 2 of the periodic table or a conductive film added with these elements may be used.

When the cathode 714 is formed, the light emitting element 715 is completed. Note that the light-emitting element 715 here refers to a diode formed by the pixel electrode (anode) 710, the light-emitting layer 713, and the cathode 714.

It is effective to provide a passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a combination thereof.

At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., it can be easily formed over the light-emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen and can suppress oxidation of the light-emitting layer 713. Therefore, the problem that the light emitting layer 713 is oxidized during the subsequent sealing process can be prevented.

Further, a sealing material 717 is provided over the passivation film 716 and a cover material 718 is attached thereto. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside. In this embodiment, the cover material 718 is formed by forming a carbon film (preferably a diamond-like carbon film) on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film).

Thus, a light emitting device having a structure as shown in FIG. 24 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 using a multi-chamber type (or in-line type) film formation apparatus without releasing to the atmosphere. . Further, it is possible to continuously process the process up to the step of bonding the cover material 718 without releasing to the atmosphere.

Thus, the n-channel TFTs 601 and 602, the switching TFT (
An n-channel TFT) 603 and a current control TFT (n-channel TFT) 604 are formed.

Further, as described with reference to FIG. 24, an n-channel TFT which is resistant to deterioration due to the hot carrier effect can be formed by providing an impurity region overlapping with the gate electrode through an insulating film. Therefore, a highly reliable light emitting device can be realized.

Further, in this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other logic circuits such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit are provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, the light-emitting device of this example after performing the sealing (or sealing) process for protecting the light-emitting element will be described with reference to FIG. In addition, the code | symbol used in FIG. 24 is quoted as needed.

FIG. 25A is a top view showing a state in which the light-emitting element is sealed, and FIG.
It is sectional drawing which cut | disconnected 5 (A) by CC '. Reference numeral 801 indicated by a dotted line denotes a source side driver circuit, 806 denotes a pixel portion, and 807 denotes a gate side driver circuit. Reference numeral 901 denotes a cover material and 902.
Is a first sealing material, 903 is a second sealing material, and a sealing material 907 is provided on the inner side surrounded by the first sealing material 902.

Reference numeral 904 denotes a wiring for transmitting signals input to the source side driver circuit 801 and the gate side driver circuit 807, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 905 serving as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light emitting device in this specification includes not only the light emitting device body but also FPC or P
It shall include the state where WB is attached.

Next, a cross-sectional structure is described with reference to FIG. A pixel portion 806 and a gate side driving circuit 807 are formed above the substrate 700, and the pixel portion 806 includes a current control TFT 60.
4 and a pixel electrode 710 electrically connected to its drain. The gate side driving circuit 807 includes an n-channel TFT 601 and a p-channel TFT 6.
And a CMOS circuit (see FIG. 20) combined with 02.

The pixel electrode 710 functions as an anode of the light emitting element. Further, banks 712 are formed at both ends of the pixel electrode 710, and the light emitting layer 713 and the cathode 714 of the light emitting element are formed on the pixel electrode 710.
Is formed.

The cathode 714 also functions as a wiring common to all pixels, and is connected to the FPC 9 via the connection wiring 904.
05 is electrically connected. Further, all elements included in the pixel portion 806 and the gate side driver circuit 807 are covered with a cathode 714 and a passivation film 567.

Further, a cover material 901 is bonded to the first seal material 902. Note that a spacer made of a resin film may be provided in order to secure a space between the cover material 901 and the light emitting element.
A sealing material 907 is filled inside the first sealing material 902. Note that an epoxy-based resin is preferably used as the first sealing material 902 and the sealing material 907. The first sealing material 902 is desirably a material that does not transmit moisture and oxygen as much as possible. further,
The sealing material 907 may contain a substance having a moisture absorption effect or a substance having an antioxidant effect.

The sealing material 907 provided so as to cover the light emitting element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, or acrylic can be used as the material of the plastic substrate 901a constituting the cover material 901.

In addition, after the cover material 901 is bonded using the sealing material 907, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. The second sealing material 903 is the first sealing material 90.
The same material as 2 can be used.

By encapsulating the light emitting element in the sealing material 907 with the above structure, the light emitting element can be completely blocked from the outside, and a substance that promotes deterioration due to oxidation of the light emitting layer such as moisture and oxygen enters from the outside. Can be prevented. Therefore, a highly reliable light emitting device can be obtained.

In the light-emitting device manufactured as described above, variation in the shape of the conductive layer is reduced, so that variation in width and length of the channel formation region and the low-concentration impurity region is also reduced. It becomes possible to show characteristics. And such a light-emitting device can be used as a display part of various electronic devices.

Note that this embodiment can be freely combined with any one of Embodiments 1 to 3.

Applying the present invention, various electro-optical devices (active matrix liquid crystal display devices, active matrix light emitting devices, active matrix EC display devices)
Can be produced. That is, the present invention can be applied to various electronic devices in which these electro-optical devices are incorporated in a display unit.

Such electronic devices include video cameras, digital cameras, projectors, head-mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples thereof are shown in FIG. 26, FIG. 27 and FIG.

FIG. 26A illustrates a personal computer, which includes a main body 3001, an image input unit 3002,
A display portion 3003, a keyboard 3004, and the like are included. The present invention can be applied to the display portion 3003.

FIG. 26B shows a video camera, which includes a main body 3101, a display portion 3102, and an audio input portion 31.
03, an operation switch 3104, a battery 3105, an image receiving unit 3106, and the like. The present invention can be applied to the display portion 3102.

FIG. 26C illustrates a mobile computer (mobile computer).
A camera unit 3202, an image receiving unit 3203, an operation switch 3204, a display unit 3205, and the like. The present invention can be applied to the display portion 3205.

FIG. 26D illustrates a goggle type display including a main body 3301, a display portion 3302, an arm portion 3303, and the like. The present invention can be applied to the display portion 3302.

FIG. 26E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The main body 3401, a display portion 3402, a speaker portion 3403, and a recording medium 3404 are shown.
Operation switch 3405 and the like. This player uses a DVD (Di as a recording medium).
gial Versatile Disc), CD, etc. can be used for music appreciation, movie appreciation, games, and the Internet.
The present invention can be applied to the display portion 3402.

FIG. 26F illustrates a digital camera, which includes a main body 3501, a display portion 3502, and an eyepiece portion 350.
3, an operation switch 3504, an image receiving unit (not shown), and the like. The present invention can be applied to the display portion 3502.

FIG. 27A shows a front type projector, which includes a projection device 3601 and a screen 36.
02 etc. are included. The present invention can be applied to a liquid crystal display device 3808 constituting a part of the projection device 3601 and other driving circuits.

FIG. 27B shows a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. The present invention can be applied to the liquid crystal display device 3808 constituting a part of the projection device 3702 and other driving circuits.

Note that FIG. 27C illustrates a projection device 3601 in FIGS. 27A and 27B.
3 is a diagram showing an example of a structure 3702. FIG. The projection devices 3601 and 3702 are light source optical systems 3.
801, mirrors 3802, 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, in the optical path indicated by an arrow in FIG. 27C, the practitioner appropriately uses an optical lens, a film having a polarization function,
You may provide optical systems, such as a film for adjusting a phase difference, and an IR film.

FIG. 27D shows an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811 and a light source 38.
12, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 27D is an example and is not particularly limited.
For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

However, the projector shown in FIG. 27 shows a case where a transmissive electro-optical device is used, and an application example in a reflective electro-optical device and a light-emitting device is not shown.

FIG. 28A illustrates a mobile phone, which includes a main body 3901, an audio output unit 3902, and an audio input unit 39.
03, a display portion 3904, an operation switch 3905, an antenna 3906, and the like. The present invention can be applied to the display portion 3904.

FIG. 28B illustrates a portable book (electronic book), which includes a main body 4001 and display portions 4002 and 400.
3, a storage medium 4004, an operation switch 4005, an antenna 4006, and the like. The present invention can be applied to the display portions 4002 and 4003.

FIG. 28C illustrates a display, which includes a main body 4101, a support base 4102, and a display portion 4103.
Etc. The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is so wide that the present invention can be applied to electronic devices in various fields. In addition, the electronic apparatus of this example is the first embodiment, the second embodiment, and the first to fourth examples.
Alternatively, the present invention can be realized by using any combination of the first to third embodiments and the fifth embodiment.

Claims (4)

Having a pixel part,
The pixel portion includes first and second semiconductor layers, first to sixth conductive layers, and an insulating layer.
The end portion of the first conductive layer has a tapered shape,
The end portion of the second conductive layer has a tapered shape,
The end portion of the third conductive layer has a tapered shape,
The first semiconductor layer has a channel formation region of a transistor,
The first semiconductor layer has a source region of the transistor;
The first semiconductor layer has a drain region of the transistor;
The first conductive layer is above the first semiconductor layer;
The first conductive layer has a region functioning as a gate electrode of the transistor;
The second conductive layer is above the second semiconductor layer;
The second conductive layer has a region overlapping with the second semiconductor layer,
The insulating layer is above the first conductive layer, above the second conductive layer, and above the third conductive layer;
The fourth conductive layer is above the insulating layer;
The fourth conductive layer has a region overlapping with the third conductive layer,
The fourth conductive layer is electrically connected to the third conductive layer;
The fourth conductive layer is electrically connected to one of the source region or the drain region;
The fifth conductive layer is above the insulating layer;
The fifth conductive layer is electrically connected to the other of the source region or the drain region;
The fifth conductive layer is electrically connected to the second semiconductor layer;
The sixth conductive layer is above the insulating layer;
The sixth conductive layer has a region overlapping with the first conductive layer,
The display device, wherein the sixth conductive layer is electrically connected to the first conductive layer. Having a pixel part,
The pixel portion includes first and second semiconductor layers, first to sixth conductive layers, and an insulating layer.
The end portion of the first conductive layer has a tapered shape,
The end portion of the second conductive layer has a tapered shape,
The end portion of the third conductive layer has a tapered shape,
The first semiconductor layer has a channel formation region of a transistor,
The first semiconductor layer has a source region of the transistor;
The first semiconductor layer has a drain region of the transistor;
The first conductive layer is above the first semiconductor layer;
The first conductive layer has a region functioning as a gate electrode of the transistor;
The second conductive layer is above the second semiconductor layer;
The second conductive layer has a region overlapping with the second semiconductor layer,
The insulating layer is above the first conductive layer, above the second conductive layer, and above the third conductive layer;
The fourth conductive layer is above the insulating layer;
The fourth conductive layer has a region overlapping with the third conductive layer,
The fourth conductive layer has a region in contact with the upper surface of the third conductive layer,
The fourth conductive layer is electrically connected to one of the source region or the drain region;
The fifth conductive layer is above the insulating layer;
The fifth conductive layer is electrically connected to the other of the source region or the drain region;
The fifth conductive layer is electrically connected to the second semiconductor layer;
The sixth conductive layer is above the insulating layer;
The sixth conductive layer has a region overlapping with the first conductive layer,
The display device, wherein the sixth conductive layer is electrically connected to the first conductive layer. A display device according to any one of claims 1 or 2,
FPC,
A display module. The display device according to any one of claims 1 or 2, or the display module according to claim 3,
An operation switch, a battery, an image receiving unit, a speaker unit, and / or an antenna;
Electronic equipment having

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