JP2007049181A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem of ion introduction onto a semiconductor formed with a resist that causes a factor to deteriorate the properties of the semiconductor because a reaction between ions and a component of the resist generates a gas (dissociated gas) resulting in that the component of the dissociated gas is introduced into the semiconductor. <P>SOLUTION: The dissociated gas to be generated from an organic film is treated. Particularly, the dissociated gas is treated before the ion introduction is performed. As a method of performing such a treatment, the ion introduction is performed by dividing ion introduction processing itself into a plurality of times. The dissociated gas is generated in a maximum quantity just after the ion introduction is started. For this reason, it is possible to decrease an introduction of a component of the dissociated gas into the semiconductor or prevent the component of the dissociated gas from being introduced into the semiconductor, when ion introduction processing is divided into a plurality of times and, in each of the thus-divided ion introduction processing after a second and succeeding time thereof, the ion is introduced while removing the dissociated gas from a treatment chamber by performing evacuation. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for introducing ions. Further, the present invention relates to a method for manufacturing a semiconductor device including a step of introducing ions.

  A technique for manufacturing a circuit having a predetermined function by forming an element such as a thin film transistor on the surface of a semiconductor and connecting the elements by wiring is known. In this technique, an ion introduction technique for forming an impurity region having n-type or p-type conductivity in a predetermined region is no longer essential.

  In the ion introduction technology, the material gas is converted into plasma by the trigger electrode to generate multiple ions with different mass numbers, and appropriate energy is given to the ions in the plasma by the extraction electrode system and acceleration electrode system installed in the chamber. However, a method for introducing the semiconductor into a semiconductor is known. Further, after ionizing the material gas, only ions selected by mass separation may be introduced into the semiconductor. The feature of the ion introduction technique is that the impurity element can be implanted into the semiconductor at a predetermined concentration at a predetermined depth by controlling the acceleration voltage and the ion density. Typically, an ion doping apparatus, an ion implantation apparatus, and the like can be given.

  Further, ions may be introduced only in a desired region in the semiconductor. For example, if a resist made of an organic film is partially formed on a semiconductor and ions are introduced using the resist as a mask, ions can be implanted only into a region where the resist is not formed.

  However, when a resist pattern is formed on a semiconductor and ions are introduced, the resist pattern is also irradiated with ions. Therefore, the accelerated ions heat the resist or react with its components to release gas. Here, this gas is called a dissociation gas. Since the resist is generally an organic material, nitrogen, carbon, oxygen, hydrogen, water vapor, and the like are included as components of the dissociation gas. When the dissociated gas is generated, the components of the dissociated gas are injected into the semiconductor together with ions that are diffused into the gas phase and accelerated by the electric field.

FIG. 6 shows a silicon wafer in which boron is introduced into a silicon wafer on which a resist pattern is formed (indicated by a thick line in the drawing) and a silicon wafer on which a resist is not formed (indicated by a thin line in the drawing). The distribution of boron (B), carbon (C), oxygen (O) and nitrogen (N) is shown. As ion introduction conditions, B ₂ H ₆ was used as a material gas, a high frequency power source was 20 W, an acceleration voltage was 65 kV, and a dose amount was 3.3 × 10 ¹⁵ atoms / cm ² . From FIG. 6, it can be seen that carbon (C), oxygen (O), and nitrogen (N) are distributed much more in a silicon wafer on which a resist is formed than on a silicon wafer on which a resist is not formed. In order to improve the physical properties of the semiconductor, it is desirable that these are as little as possible.

  Further, since the resist is partially formed on the semiconductor, the generation of dissociation gas becomes local, and the amount of ions introduced in the semiconductor varies. Furthermore, the generation of dissociation gas changes the pressure in the processing chamber in which ions are introduced, causing arcing, adversely affecting the ion density and acceleration voltage, and deviating from the set ion introduction conditions. Sometimes. These have become increasingly serious problems as the substrate becomes larger, and can be a major factor in reducing the physical properties of semiconductors.

  Thus, as a method for reducing the generation of dissociation gas, there is a method in which baking, ultraviolet (UV) irradiation, or the like is performed before the introduction of ions. By these treatments, the resist can be cured and generation of dissociation gas can be reduced. On the other hand, the resist is only used as a mask for introducing ions only in a desired region and needs to be removed after the introduction of ions. However, the resist cured by baking or UV irradiation may not be removed even after ashing or peeling. Resist is generally an organic film, so if it stays on the semiconductor as a residue, not only the physical properties of the semiconductor, but also the equipment in the process after the introduction of ions is contaminated, so the physical properties of other semiconductors are also reduced. As a result, the operating characteristics of the semiconductor device are adversely affected. Moreover, the coverage of the film formed after the introduction of ions may be reduced, which may cause disconnection or the like. Further, performing baking, UV irradiation or the like increases the number of steps, leading to an increase in time and cost.

  Therefore, the present invention provides a method for reducing or preventing dissociation gas generated from an organic film typified by a resist. It is another object of the present invention to provide a method for reducing or preventing dissociation gas generated when ions are introduced into a desired region using an organic film. It is another object of the present invention to provide a method for manufacturing a semiconductor device manufactured by including ion introduction in a process.

The present invention is characterized in that the dissociation gas generated from the organic film is treated. In particular, the present invention is characterized in that the dissociation gas is processed before the introduction of ions.
As a method for this purpose, ion introduction is performed in a plurality of times.
Most of the dissociation gas is generated immediately after the introduction of ions starts. Therefore, if the introduction of ions is divided into a plurality of times and the ions are introduced while exhausting and removing the dissociation gas from the processing chamber in at least the second and subsequent ion introductions, the components of the dissociation gas are contained in the semiconductor. It is possible to reduce or prevent the introduction. Of course, the exhaust may be performed from the time of the first introduction of ions, or the dissociation gas may be reduced or removed from the processing chamber by exhausting after the completion of each introduction. For ion introduction, an ion implantation apparatus or an ion doping implantation apparatus is used. For example, an apparatus disclosed in US Pat. No. 5,892,235 may be used.

  The present invention can also be applied to a resist cured by baking, UV irradiation, or the like. Even when ions are introduced after baking or UV irradiation, dissociated gas is often generated. Therefore, it is very effective to apply the present invention.

  The structure of the present invention is characterized in that ions are introduced after the dissociation gas from the organic film is processed.

  According to another configuration of the invention relating to the ion introduction method disclosed in this specification, the organic film is used as a mask to introduce the first ion by using the first acceleration voltage or the first current density. The dissociation gas is treated, and the second ions are introduced by the second acceleration voltage or the second current density using the organic film as a mask.

  In the above configuration, it is desirable that the first acceleration voltage is higher than the second acceleration voltage. By doing in this way, generation | occurrence | production of the dissociation gas in introduction | transduction of the said 2nd ion can be reduced or prevented. The first current density is desirably lower than the second current density. By doing in this way, it can reduce or prevent that the component of dissociation gas is introduce | transduced into a semiconductor.

  In the above structure, the first ions and the second ions are preferably generated using the same material gas. If ions are introduced using different material gases in the same apparatus, the pressure in the processing chamber tends to become unstable when the second ions are introduced, and may deviate from the set introduction conditions. Because. However, if a material generated using an inert gas is used as the first ion and a material generated using a material gas is used as the second ion, the first ion and the second ion are different materials. Stable ion introduction can be performed as compared with the case of using a gas.

In addition, as a material gas, a material gas used for imparting n-type (typically PH ₃ or the like), a material gas used for imparting p-type (typically B ₂ H ₆ or the like). Can be used.

  In the above structure, the time for introducing the first ions into the semiconductor in which the resist is formed by the first acceleration voltage is preferably within 6 minutes, and preferably within 2 minutes. The introduction of the first ions is performed in order to prevent or reduce the generation of dissociation gas when the second ions are introduced into the semiconductor by curing the resist to some extent. If the time for introducing the first ions is too long, the dissociation gas component is introduced into the semiconductor to deteriorate the physical properties of the semiconductor, or the resist to be removed after the introduction of ions is hardened more than necessary. This makes it difficult to remove the resist.

  The structure of the invention related to the method for manufacturing a semiconductor device disclosed in this specification is that an impurity region is formed by introducing ions after processing a dissociation gas from an organic film formed over a semiconductor film. It is a feature.

  Another structure of the invention related to the method for manufacturing a semiconductor device disclosed in this specification is that an organic film formed over a semiconductor film is used as a mask to generate the first ions with the first acceleration voltage or the first current density. The dissociation gas from the organic film is processed by introducing, and the impurity region is formed by introducing the second ions with the second acceleration voltage or the second current density using the organic film as a mask. It is characterized by that.

  In the above configuration, it is desirable that the first acceleration voltage is higher than the second acceleration voltage. The first current density is desirably lower than the second current density.

  In the above structure, the first ions and the second ions are preferably generated using the same material gas. However, if a material generated using an inert gas is used as the first ion and a material generated using a material gas is used as the second ion, the first ion and the second ion are different materials. Stable ion introduction can be performed as compared with the case of using a gas.

In addition, as a material gas, a material gas used for imparting n-type (typically PH ₃ or the like), a material gas used for imparting p-type (typically B ₂ H ₆ or the like). Can be used.

  In the above structure, the time for introducing the first ions into the semiconductor in which the resist is formed by the first acceleration voltage is preferably within 6 minutes, and preferably within 2 minutes.

  In the above structure, it is desirable to use a silicon film as the semiconductor. In addition to the amorphous silicon film, a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. As a substrate for forming a semiconductor, a glass substrate, a quartz substrate, a silicon substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a flexible substrate, or the like can be used. Examples of the glass substrate include a substrate made of glass such as barium borosilicate glass or alumino borosilicate glass. The flexible substrate is a film-like substrate made of PET, PES, PEN, acrylic, or the like. If a semiconductor device is manufactured using the flexible substrate, weight reduction is expected. A barrier layer such as an aluminum film (AlON, AlN, AlO, etc.), a carbon film (DLC (diamond-like carbon), etc.), silicon nitride (SiN), etc., is formed on the surface of the flexible substrate or on the front and back surfaces. If it is formed, durability is improved, which is desirable.

  As described above, the present invention makes it possible to reduce or prevent the introduction of a dissociated gas component into a semiconductor by performing ion introduction in a plurality of times. Further, uniform ions can be introduced into the semiconductor without deviating from the set introduction conditions. Further, since the resist is not baked before the introduction of ions, the number of steps is not increased, and the removal of the resist performed after the introduction of ions can be facilitated. These are very effective means in increasing the size of the substrate.

  Further, by applying the present invention, in a semiconductor device typified by an active matrix liquid crystal display device, improvement in operating characteristics and reliability of the semiconductor device can be realized. Furthermore, the manufacturing cost of the semiconductor device can be reduced. Note that a semiconductor device in this specification refers to all devices that can function by utilizing semiconductor characteristics, such as a liquid crystal display device in which a thin film transistor and a liquid crystal are combined, and a light emitting device in which a thin film transistor and a light emitting element are combined. Suppose you are in that category.

By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) Dissociation gas from the organic film can be prevented even if the ion introduction process using the organic film is performed.
(B) The adverse effect of the process due to the dissociated gas from the organic film can be avoided.
(C) In a semiconductor device typified by an active matrix liquid crystal display device, the operating characteristics and reliability of the semiconductor device can be improved while satisfying the above advantages.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG.

FIG. 1A illustrates an example of a semiconductor in which a resist is partially formed. A base insulating film 11 is formed on the substrate 10, a semiconductor film 12 is formed on the base insulating film 11, and a resist 14 is formed on the semiconductor film 12 with an insulating film 13 interposed therebetween.
Of course, the resist 14 may be formed on the semiconductor film 12 without forming the insulating film 13.

Thus, the 1st introduction | transduction by the 1st ion 15 is performed by the 1st acceleration voltage to the semiconductor in which the resist 14 is formed. For this treatment, an ion doping apparatus, an ion implantation apparatus, or the like may be used, and a known material gas (PH ₃ , B ₂ H _6, etc.) may be used as the material gas. Further, an inert gas that does not affect the semiconductor may be used. Furthermore, it is desirable that the first acceleration voltage is higher than the second acceleration voltage that is performed in a later step. The processing time in the first introduction is desirably within 6 minutes (preferably within 2 minutes). By the first introduction, the first ions 15 react with the resist 14 and a dissociation gas 16 is generated.

  Subsequently, it is desirable to exhaust the processing chamber. This is because the dissociated gas 16 generated by the first introduction is removed from the processing chamber (FIG. 1B). In general, introduction of ions supplies material gas into the processing chamber while exhausting the processing chamber. However, exhaust during the introduction of ions is often performed using a few percent of the exhaust capacity. Therefore, in order to remove the dissociated gas generated in the processing chamber as much as possible, it is desirable to exhaust the processing chamber between the introduction of the first ions and the introduction of the second ions. In an apparatus having a high exhaust capability, the process chamber may not be exhausted between the introduction of the first ions and the introduction of the second ions.

  Then, the second introduction is performed by the second ions 18 at the second acceleration voltage (FIG. 1C). Also in this process, an ion doping apparatus, an ion implantation apparatus, or the like is used as in the first introduction by the first ions. It is preferable to use the same material gas as that used in the first introduction. This is because if different material gases are used in the first introduction and the second introduction, the pressure in the processing chamber becomes unstable, which may adversely affect the second introduction. Of course, if an inert gas is used in the first introduction, stable treatment can be performed with almost no problem. In addition, the second acceleration voltage and the processing time may be determined as appropriate by the practitioner as appropriate for, for example, those suitable for manufacturing a semiconductor device.

  In this manner, by introducing ions in a plurality of times, it is possible to reduce or prevent introduction of the dissociated gas component into the semiconductor. Further, uniform ions can be introduced into the semiconductor without deviating from the set introduction conditions. Further, since the resist is not baked before the introduction of ions, the number of steps is not increased and the removal of the resist performed after the introduction of ions can be facilitated. These are very effective means in increasing the size of the substrate.

In this embodiment, the introduction of ions is performed twice, but the number of times is not limited to two if it is a plurality of times.
Further, in the present embodiment, a process such as resist baking is not performed before the introduction of ions, but the present invention can be applied after the process is performed first.
In this embodiment, a method for reducing or preventing dissociation gas from the resist in the introduction of ions is described. However, in order to reduce or prevent dissociation gas from other organic films such as acrylic and polyimide, The invention can also be applied.

[Embodiment 2]
In the present embodiment, a description will be given of a result of examining a change in pressure in a processing chamber when a resist is formed on a substrate and the first introduction and the second introduction of ions are performed. In the present embodiment, an experiment was performed in which the conditions of the first acceleration voltage in the first introduction were varied.

  FIG. 2 shows an example in which a resist 21 is partially formed on the substrate 20. A glass substrate was used as the substrate 20, and a novolac resin was used as the resist.

In this manner, ions were first introduced into the substrate on which the resist 21 was formed. This treatment was performed using an ion doping apparatus for 6 minutes using B ₂ H ₆ as a material gas. The high frequency power source was constant at 5 W, and the acceleration voltage was three conditions of 10, 40, and 90 kV. The change in pressure in the processing chamber at this time is shown in the column “first introduction” in Table 1 and FIG.

  In Table 1 and FIG. 3A, “1st 10 kV 5W” indicates that the first introduction was performed under the conditions of the high frequency power supply 5 W and the acceleration voltage 10 kV, and “1st 40 kV 5 W” represents the first introduction as the high frequency power supply. 5 W and an acceleration voltage of 40 kV are shown. “1st 90 kV 5 W” indicates that the first introduction is performed under the conditions of a high frequency power supply 5 W and an acceleration voltage of 90 kV.

  While ions are introduced, a material gas is supplied into the processing chamber, while the processing chamber is evacuated, so that the pressure in the processing chamber should be a constant value. However, when the dissociated gas 16 is generated, the amount of gas to be exhausted exceeds the capacity of the apparatus for exhausting the processing chamber. Therefore, the pressure in the processing chamber increases, and when the generation of the dissociating gas ends, the pressure in the processing chamber becomes a constant value. It becomes. FIG. 3A shows that the higher the acceleration voltage, the more dissociated gas is generated. Further, since the pressure becomes a constant value as time passes, it can be understood that the dissociated gas is not generated as time passes.

  Subsequently, the processing chamber is evacuated to remove or reduce the dissociated gas 16 from the processing chamber (FIG. 2B).

Then, the second introduction of ions is performed with the second acceleration voltage on each substrate on which the first introduction has been performed (FIG. 2C). Also in this treatment, an ion doping apparatus was used as in the first introduction of ions. The material gas was B ₂ H ₆ as in the first introduction, the acceleration voltage was 30 kV, and the high-frequency power source was 20 W. The change in pressure in the processing chamber at this time (during the second introduction) is shown in the column “Second introduction” in Table 1 and FIG. In Table 1 and FIG. 3B, “1st 10 kV 5W” indicates that the first introduction is performed under the conditions of the high frequency power supply 5 W and the acceleration voltage 10 kV, and then the second introduction is performed. “1st 40 kV 5 W” Indicates that the first introduction is performed under the condition of the high frequency power supply 5 W and the acceleration voltage 40 kV, and then the second introduction is performed. “1st 90 kV 5 W” indicates that the first introduction is performed under the conditions of the high frequency power supply 5 W and the acceleration voltage 90 kV. The second introduction after the above is shown. Referring to FIG. 3B, when the acceleration voltage for the first introduction is set to 10 kV, which is lower than the acceleration voltage for the second introduction, 30 kV, the pressure is increased from the processing time of 10 seconds (0.17 minutes) to 2 minutes. Is greatly changed, and generation of dissociated gas is observed. On the other hand, when the acceleration voltage for the first introduction is set to 40 kV and 90 kV, which are higher than the acceleration voltage 30 kV for the second introduction, the pressure change in the processing chamber is small and the dissociation gas is hardly generated. Recognize. Therefore, it can be seen from FIG. 3B that when the acceleration voltage during the first introduction is higher than the acceleration voltage during the second introduction, there is almost no change in pressure during the second introduction. That is, it is understood that almost no dissociation gas is generated.

  From the above results and explanation, it can be seen that in the present invention, the first acceleration voltage is preferably higher than the second acceleration voltage. Further, when the processing time in the first introduction becomes long, adverse effects such as introduction of the dissociated gas component into the semiconductor occur. Therefore, the processing time is about 2 minutes, preferably within 1 minute. Alternatively, when the acceleration voltage of the first introduction is 90 kV, the pressure in the processing chamber takes a peak value 10 seconds (0.17 minutes) after the first introduction, and after 40 seconds and 1 minute Since they are the same value, they may be within 40 seconds or within 10 seconds. However, depending on the conditions such as acceleration voltage, the time until the pressure takes a peak value and the time taken to take the peak value and become a constant value are different. It is preferable to check the time until a constant value is obtained.

  In this manner, by introducing ions in a plurality of times, it is possible to reduce or prevent introduction of the dissociated gas component into the semiconductor. Further, uniform ions can be introduced into the semiconductor without deviating from the set introduction conditions. Further, since the resist is not baked before the introduction of ions, the number of steps is not increased, and the removal of the resist performed after the introduction of ions can be facilitated.

  In this embodiment, the introduction of ions is performed in two steps, but the gist thereof is performed a plurality of times and is not limited to two times.

[Embodiment 3]
In the present embodiment, a description will be given of a result of examining a change in pressure in a processing chamber when a resist is formed on a substrate and the first introduction and the second introduction of ions are performed. In the present embodiment, the condition of the second acceleration voltage in the second introduction is set.

  FIG. 2 shows an example in which a resist 21 is partially formed on the substrate 20. A glass substrate was used as the substrate 20, and a novolac resin was used as the resist.

In this manner, ions were first introduced into the substrate on which the resist 21 was formed. This treatment was performed for 6 minutes using an ion doping apparatus, using B ₂ H ₆ as a material gas, a high frequency power source of 5 W, and an acceleration voltage of 90 kV. The change in pressure in the processing chamber at this time is shown in the column “First introduction” in Table 2 and FIG.

  In Table 2 and FIG. 4A, “2nd 10 kV 20 W” indicates that the second introduction was performed under the conditions of a high frequency power supply 20 W and an acceleration voltage 10 kV, and “2nd 30 kV 20 W” represents the second introduction as a high frequency power supply. “2nd 50 kV 20 W” indicates that the second introduction is performed under the conditions of the high frequency power source 20 W and the acceleration voltage 50 kV. In either case, the pressure reached a peak value 10 seconds after the first introduction started, and then decreased.

  Subsequently, the processing chamber is evacuated to remove or reduce the dissociated gas 16 (FIG. 2B).

Then, the second introduction of ions is performed with the second acceleration voltage on each substrate on which the first introduction has been performed (FIG. 2C). Also in this treatment, an ion doping apparatus was used as in the first introduction of ions. The material gas used was B ₂ H ₆ which is the same material gas as in the first introduction, the high frequency power source was 20 W, and the acceleration voltage was 3, 30, and 50 kV. The change in pressure in the processing chamber at this time is shown in the column “Second introduction” in Table 2 and FIG. In Table 2 and FIG. 4B, “2nd 10 kV 20 W” indicates that the second introduction is performed under the conditions of the high frequency power supply 20 W and the acceleration voltage 10 kV, and “2nd 30 kV 20 W” indicates the second introduction is the high frequency power supply. “2nd 50 kV 20 W” indicates that the second introduction is performed under the conditions of the high frequency power source 20 W and the acceleration voltage 50 kV. FIG. 4B shows that when the acceleration voltage at the time of the first introduction is higher than the acceleration voltage at the time of the second introduction, the change in pressure in the second introduction is small. That is, it is understood that almost no dissociation gas is generated.

  From the above results and explanation, it can be seen that in the present invention, the acceleration voltage for the first introduction is preferably higher than the acceleration voltage for the second introduction. That is, if the first acceleration voltage is high, the generation of dissociated gas can be reduced or prevented regardless of the second acceleration voltage, so that more uniform ion introduction can be performed. Furthermore, the current density in each introduction is changed by changing the value of the high-frequency power source in the first introduction and the second introduction. That is, since the current density in the first introduction is lower than the current density in the second introduction, the first introduction can be performed without introducing much of the dissociation gas component into the semiconductor film.

  In this manner, by introducing ions in a plurality of times, it is possible to reduce or prevent introduction of the dissociated gas component into the semiconductor. Further, uniform ions can be introduced into the semiconductor without deviating from the set introduction conditions. Further, since the resist is not baked before the introduction of ions, the number of steps is not increased, and the removal of the resist performed after the introduction of ions can be facilitated.

  In this embodiment, the introduction of ions is performed twice, but the number of times is not limited to two if it is a plurality of times.

[Embodiment 4]
In this embodiment, a method of applying the present invention after baking a resist will be described.

FIG. 5 shows a change in pressure in the processing chamber when a resist is partially formed on the substrate and ions are introduced into the baked sample and the non-baked sample.
A novolak resin was used as a resist, and baking was performed in an oven at 200 ° C. for 2 hours. The ion introduction conditions were as follows: an ion doping apparatus was used, B ₂ H ₆ was used as a material gas, a high frequency power source was 5 W, an acceleration voltage was 80 kV, and a dose amount was 1.5 × 10 ¹⁵ atoms / cm ² . .

  FIG. 5 shows that the pressure in the processing chamber changes even when baking is performed. That is, it can be seen that dissociated gas is generated. Therefore, it is preferable to apply the present invention and prevent the dissociation gas component from being introduced into the semiconductor according to the embodiment.

  In this manner, by introducing ions in a plurality of times, it is possible to reduce or prevent introduction of the dissociated gas component into the semiconductor. Further, uniform ions can be introduced into the semiconductor without deviating from the set introduction conditions.

[Embodiment 5]
In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. In this specification, a substrate in which a pixel portion having a CMOS circuit, a driver circuit, a pixel TFT, and a storage capacitor is formed over the same substrate is referred to as an active matrix substrate for convenience.

  First, in this embodiment, a substrate 400 made of glass such as barium borosilicate glass or alumino borosilicate glass is used. Note that the substrate 400 may be a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed. In addition, a plastic substrate having heat resistance that can withstand the processing temperature of the present embodiment may be used, or a flexible substrate may be used.

  Next, a base film 401 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 400 by a known means. In this embodiment, a two-layer structure is used as the base film 401, but a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used.

Next, a semiconductor film is formed over the base film. The semiconductor film is formed with a thickness of 25 to 300 nm (preferably 30 to 200 nm) by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), and a known crystallization method (laser crystallization method). Crystallization method, thermal crystallization method using RTA or furnace annealing furnace, thermal crystallization method using a metal element that promotes crystallization) or a combination of known crystallization methods. Examples of the semiconductor film include an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, and the like, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film or an amorphous silicon carbide film. May be applied. If the laser crystallization method is applied, the laser to be used is preferably a continuous wave or pulsed solid laser, a gas laser, or a metal laser. Examples of the solid-state laser include a continuous wave or pulsed YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandride laser, Ti: sapphire laser, and the gas laser. There are a continuous wave or pulsed excimer laser, an Ar laser, a Kr laser, a CO ₂ laser, and the like, and examples of the metal laser include a helium cadmium laser, a copper vapor laser, and a gold vapor laser.

In this embodiment, a plasma CVD method is used to form a 50 nm amorphous silicon film, and a thermal crystallization method and a laser crystallization method using a metal element that promotes crystallization on the amorphous silicon film. Do. Nickel is used as the metal element and is introduced onto the amorphous silicon film by a solution coating method, and then a heat treatment is performed at 550 ° C. for 5 hours to obtain a first crystalline silicon film. A laser beam emitted from a continuous wave YVO ₄ laser with an output of 10 W is converted into a second harmonic by a non-linear optical element, and then irradiated to the first crystalline silicon film to form a second crystalline silicon film. obtain. Crystallinity is improved by irradiating the first crystalline silicon film with a laser beam to form a second crystalline silicon film. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed by moving the stage relative to the laser light at a speed of about 0.5 to 2000 cm / s to form a crystalline silicon film. In the case of using a pulsed laser, it is desirable that the frequency be 300 Hz and the laser energy density be 100 to 1500 mJ / cm ² (typically 200 to 1000 mJ / cm ² ). At this time, the laser beams may be overlapped by 50 to 98%.

Needless to say, a TFT can be manufactured using the first crystalline silicon film, but the second crystalline silicon film is preferable because the electrical characteristics of the TFT are improved because the crystallinity is improved. For example, when a TFT is manufactured using a first crystalline silicon film, the mobility is about 300 cm ² / Vs. However, when a TFT is manufactured using a second crystalline silicon film, the mobility is 500 to 600 cm. ^It is remarkably improved to about ² / Vs.

  Semiconductor layers 402 to 406 are formed by patterning the crystalline semiconductor film thus obtained using a photolithography method.

  Further, after forming the semiconductor layers 402 to 406, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

  Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 200 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 110 nm by plasma CVD. Of course, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film may be used as a single layer or a laminated structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0. It can be formed by discharging at 5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

Next, a first conductive film 408 with a thickness of 20 to 200 nm and a second conductive film 409 with a thickness of 100 to 500 nm are stacked over the gate insulating film 407. In this embodiment, a first conductive film 408 made of a 30 nm thick TaN film and a second conductive film 409 made of a 370 nm thick W film are stacked. The TaN film is formed by sputtering, and is sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by sputtering using a W target. In addition, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less.

  In the present embodiment, the first conductive film 408 is TaN and the second conductive film 409 is W. However, there is no particular limitation, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the element selected from these, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used.

Next, resist masks 410 to 415 are formed by photolithography, and a first etching process is performed to form electrodes and wirings. The first etching process is performed under the first and second etching conditions (FIG. 7B). In this embodiment, ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, CF ₄ , Cl _2, and O ₂ are used as etching gases, and each gas flow ratio is 25. : 25: 10 (sccm), etching is performed by generating plasma by applying 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered.

Thereafter, the masks 410 to 415 made of resist are changed to the second etching conditions without removing them, CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30:30 (sccm). Etching is performed for about 30 seconds by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa to generate plasma. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.

  In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 417 to 422 (the first conductive layers 417 a to 422 a and the second conductive layers 417 b to 422 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form. Reference numeral 416 denotes a gate insulating film, and a region not covered with the first shape conductive layers 417 to 422 is etched and thinned by about 20 to 50 nm.

Next, a second etching process is performed without removing the resist mask (FIG. 7C). Here, CF ₄ , Cl _2, and O ₂ are used as the etching gas, and the W film is selectively etched. At this time, second conductive layers 428b to 433b are formed by a second etching process. On the other hand, the first conductive layers 417a to 422a are hardly etched, and the second shape conductive layers 428a to 433a are formed.

Then, the resist mask is removed, first ions are introduced, and an impurity element imparting n-type conductivity is introduced into the semiconductor layer at a low concentration. Ion introduction may be performed by ion doping, ion implantation, or the like. The conditions of the ion doping method are a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 40 to 80 kV.
In this embodiment, the dose is set to 1.5 × 10 ¹³ atoms / cm ² and the acceleration voltage is set to 60 kV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 428 to 433 serve as a mask for the impurity element imparting n-type, and the impurity regions 423 to 427 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the impurity regions 423 to 427 in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm ³ .

After removing the resist mask, new resist masks 434a to 434c are formed, and second ions are introduced as a process for reducing or removing the generation of dissociation gas. The ion doping method is preferably performed at an acceleration voltage of 50 to 120 kV and within 6 minutes. The gas used in the introduction of the second ions may be a known material gas or an inert gas. Although the dissociation gas is released from the resist by the introduction of the second ions, the dissociation gas component is hardly introduced into the semiconductor layer because of the short-time treatment. In this embodiment, the acceleration voltage is 70 kV, PH ₃ is used as the material gas, and the process is performed for 2 minutes.

  Then, after the introduction of the second ions is completed, it is desirable to exhaust the processing chamber to remove or reduce the dissociated gas in the processing chamber.

The third ions are introduced while the resist masks 434a to 434c are kept as they are. The conditions of the ion doping method are a dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁷ atoms / cm ² and an acceleration voltage of 40 to 120 kV. The doping process uses the second conductive layers 428b, 430b, and 432b as masks against the impurity elements, the semiconductor layer that does not overlap with the first conductive layers 428b, 430b, and 432b and the semiconductor layer below the tapered portion of the first conductive layer Doping is performed so that an impurity element is added to (FIG. 8B). In this embodiment, the acceleration voltage is 65 kV, PH ₃ is used as the material gas, and the dose is 4 × 10 ¹⁵ atoms / cm ² . By the second doping treatment, an impurity element imparting n-type conductivity in a concentration range of 1 × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm ³ is formed in the low-concentration impurity regions 436b, 442b, and 448b overlapping with the first conductive layer. In addition, an impurity element imparting n-type conductivity is added to the high concentration impurity regions 435b, 441b, 444b, and 447b in a concentration range of 1 × 10 ^{19 to} 5 × 10 ²¹ atoms / cm ³ .

  Needless to say, the third doping process can be performed twice, and the low-concentration impurity region and the high-concentration impurity region can be formed separately in each doping process.

Next, after removing the resist mask, new resist masks 450a to 450d are formed, and fourth ions are introduced as a process for reducing or removing the generation of dissociation gas. The conditions of the ion doping method are preferably set to an acceleration voltage of 50 to 120 kV and within 6 minutes. The gas used in the introduction of the fourth ions may be a known material gas or an inert gas. Although the dissociation gas is released from the resist by the introduction of the fourth ions, the dissociation gas component is hardly introduced into the semiconductor layer because of the short-time treatment. In this embodiment, the acceleration voltage is 90 kV, B ₂ H ₆ is used as the material gas, and the process is performed for 1 minute.

  Then, after the introduction of the fourth ions is completed, it is desirable to exhaust the processing chamber to remove or reduce the dissociated gas in the processing chamber.

The masks 450a to 450d made of resist are left as they are, and fifth ions are introduced. The conditions of the ion doping method are a dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁸ atoms / cm ² and an acceleration voltage of 40 to 120 kV. By the fifth doping treatment, impurity regions 453b and 454b in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer that becomes the active layer of the p-channel TFT are formed. Using the second conductive layer 429a as a mask against the impurity element, an impurity element imparting p-type conductivity is added to form an impurity region in a self-aligning manner. In this embodiment, the impurity regions 453b and 454b are formed by an ion doping method using diborane (B ₂ H ₆ ). At this time, the acceleration voltage is 80 kV (FIG. 8B).
). When the fifth ions are introduced, the semiconductor layer forming the n-channel TFT is covered with masks 450a to 450d made of resist. By introduction of the first to third ions, phosphorus is added to the impurity region 424, but the concentration of the impurity element imparting p-type is 1 × 10 ^{19 to} 5 × 10 ²¹ atoms / cm ^3. In this case, no problem arises because it functions as the source region and drain region of the p-channel TFT.

  Through the above steps, impurity regions are formed in the respective semiconductor layers.

  Next, the resist masks 450 a to 450 d are removed, and a first interlayer insulating film 461 is formed. The first interlayer insulating film 461 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by plasma CVD. Needless to say, the first interlayer insulating film 461 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, laser light irradiation is performed to recover the crystallinity of the semiconductor layers and to activate the impurity elements added to the respective semiconductor layers. The laser used for laser activation is preferably a continuous wave or pulsed solid laser, a gas laser, or a metal laser. At this time, if using a continuous wave laser, the energy density of the laser beam is about 0.01 to 100 MW / cm ² (preferably 0.01~10MW / cm ²⁾ is required, with respect to the laser beam The substrate is relatively moved at a speed of 0.5 to 2000 cm / s. If a pulsed laser is used, it is desirable that the frequency be 300 Hz and the laser energy density be 50 to 1000 mJ / cm ² (typically 50 to 700 mJ / cm ² ). At this time, the laser beams may be overlapped by 50 to 98%. In addition to the laser annealing method, a thermal annealing method, a rapid thermal annealing method (RTA method), or the like can be applied.

  In addition, activation may be performed before the first interlayer insulating film 461 is formed. However, when the wiring material used is weak against heat, it is activated after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. It is preferable to perform the conversion treatment.

  Then, hydrogenation can be performed by heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours). This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 461. The semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. As other means for hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen may be performed. .

  Next, a second interlayer insulating film 462 made of an inorganic insulating film material or an organic insulating material is formed over the first interlayer insulating film 461. In the present embodiment, an acrylic resin film having a thickness of 1.6 μm is formed, but a film having a viscosity of 10 to 1000 cp, preferably 40 to 200 cp, and having a surface with unevenness is used.

  In this embodiment, in order to prevent specular reflection, the surface of the pixel electrode is formed uneven by forming a second interlayer insulating film having an uneven surface. In addition, a convex portion may be formed in a region below the pixel electrode in order to make the surface of the pixel electrode uneven to achieve light scattering. In that case, since the convex portion can be formed using the same photomask as that of the TFT, it can be formed without increasing the number of steps. In addition, this convex part should just be suitably provided on the board | substrate of pixel part area | regions other than wiring and a TFT part. Thus, irregularities are formed on the surface of the pixel electrode along the irregularities formed on the surface of the insulating film covering the convex portions.

  Alternatively, a film whose surface is planarized may be used as the second interlayer insulating film 462. In that case, after forming the pixel electrode, adding a step such as a known sandblasting method or etching method to make the surface uneven, prevent specular reflection, and increase the whiteness by scattering the reflected light Is preferred.

In the driver circuit 506, wirings 463 to 467 that are electrically connected to the impurity regions are formed. Note that these wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm. Of course, not only a two-layer structure but also a single-layer structure or a laminated structure of three or more layers may be used. Further, the wiring material is not limited to Al and Ti.
For example, Al or Cu may be formed on the TaN film, and a wiring may be formed by patterning a laminated film formed with a Ti film (FIG. 9C).

  In the pixel portion 507, a pixel electrode 470, a gate wiring 469, and a connection electrode 468 are formed. With this connection electrode 468, the source wiring (stacked layer of 433a and 433b) is electrically connected to the pixel TFT. In addition, the gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. In addition, the pixel electrode 470 is electrically connected to the drain region of the pixel TFT, and is further electrically connected to the semiconductor layer 406 functioning as one electrode forming a storage capacitor. Further, as the pixel electrode 470, it is desirable to use a highly reflective material such as a film containing Al or Ag as a main component or a laminated film thereof.

  As described above, the CMOS circuit including the n-channel TFT 501 and the p-channel TFT 502, the driver circuit 506 having the n-channel TFT 503, and the pixel portion 507 having the pixel TFT 504 and the storage capacitor 505 are formed over the same substrate. can do. Thus, the active matrix substrate is completed.

  The n-channel TFT 501 of the driver circuit 506 includes a channel formation region 437, a low-concentration impurity region 436b (GOLD region) that overlaps with the first conductive layer 428a that forms part of the gate electrode, and a high concentration functioning as a source region or a drain region. An impurity region 435b is provided. The p-channel TFT 502 which forms a CMOS circuit by connecting the n-channel TFT 501 and the electrode 466 includes a channel formation region 455, a high-concentration impurity region 453b functioning as a source region or a drain region, and an impurity element imparting n-type conductivity And an impurity region 454b into which an impurity element imparting p-type conductivity is introduced. The n-channel TFT 503 includes a channel formation region 443, a low concentration impurity region 442b (GOLD region) overlapping with the first conductive layer 430a which forms part of the gate electrode, and a high concentration impurity which functions as a source region or a drain region. A region 441b is included.

  The pixel TFT 504 in the pixel portion includes a channel formation region 446, a low concentration impurity region 445b (LDD region) formed outside the gate electrode, and a high concentration impurity region 444b functioning as a source region or a drain region. In addition, an impurity element imparting n-type conductivity and an impurity element imparting p-type conductivity are added to the semiconductor layer functioning as one electrode of the storage capacitor 505. The storage capacitor 505 is formed of an electrode (stack of 432a and 432b) and a semiconductor layer using the insulating film 416 as a dielectric.

  In the pixel structure of this embodiment, without using a black matrix, the end portions of the pixel electrodes are arranged and formed so as to overlap the source wiring so that the gaps between the pixel electrodes are shielded from light.

  FIG. 10 is a top view of the pixel portion of the active matrix substrate manufactured in this embodiment. In addition, the same code | symbol is used for the part corresponding to FIGS. A chain line A-A ′ in FIG. 9 corresponds to a cross-sectional view taken along the chain line A-A ′ in FIG. 10. Further, a chain line B-B ′ in FIG. 9 corresponds to a cross-sectional view taken along the chain line B-B ′ in FIG. 10.

  The active matrix substrate fabricated as described above is fabricated with almost no dissociation gas component introduced during the introduction of ions, and the resist can be easily removed after the introduction of ions. The TFT has a TFT manufactured using a semiconductor film having excellent physical properties, and the electrical characteristics of the TFT are sufficient. A semiconductor device with sufficient operating characteristics and reliability can be manufactured using such a TFT.

[Embodiment 6]
In this embodiment, a process of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 5 will be described below with reference to FIGS. Although the present invention is not described in this embodiment mode, it can be said that the present invention is applied because the active matrix substrate manufactured in Embodiment Mode 5 is used.

  First, according to Embodiment 5, after obtaining the active matrix substrate in the state of FIG. 9, an alignment film 567 is formed on at least the pixel electrode 470 on the active matrix substrate of FIG. In this embodiment, before the alignment film 567 is formed, a columnar spacer 572 for holding the substrate interval is formed at a desired position by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.

  Next, a counter substrate 569 is prepared. Next, colored layers 570 and 571 and a planarization film 573 are formed over the counter substrate 569. The red colored layer 570 and the blue colored layer 571 are overlapped to form a light shielding portion. Further, the light shielding portion may be formed by partially overlapping the red colored layer and the green colored layer.

  In this embodiment, the substrate shown in Embodiment 5 is used. Therefore, in FIG. 10 showing a top view of the pixel portion of Embodiment 5, at least the gap between the gate wiring 469 and the pixel electrode 470, the gap between the gate wiring 469 and the connection electrode 468, and the gap between the connection electrode 468 and the pixel electrode 470 are shown. It is necessary to shield the light. In the present embodiment, the respective colored layers are arranged so that the light-shielding portions formed by the lamination of the colored layers overlap at the positions where the light should be shielded, and the counter substrate is bonded.

  As described above, the number of steps can be reduced by shielding the gap between the pixels with the light shielding portion formed by the lamination of the colored layers without forming a light shielding layer such as a black mask.

  Next, a counter electrode 576 made of a transparent conductive film was formed over the planarization film 573 in at least the pixel portion, an alignment film 574 was formed over the entire surface of the counter substrate, and a rubbing process was performed.

  Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 568. A filler is mixed in the sealing material 568, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 575 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. In this way, the reflection type liquid crystal display device shown in FIG. 11 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. And FPC was affixed using the well-known technique.

  The liquid crystal display device fabricated as described above is fabricated with almost no dissociation gas component introduced during the introduction of ions, and the resist can be easily removed after the introduction of ions. It has a TFT manufactured using a semiconductor film having excellent physical properties, and the liquid crystal display device can have sufficient operating characteristics and reliability. And such a liquid crystal display device can be used as a display part of various electronic devices.

[Embodiment 7]
In this embodiment, an example in which a light-emitting device is manufactured using the TFT manufacturing method for manufacturing the active matrix substrate described in Embodiment 5 will be described. Although the present invention is not described in this embodiment mode, it can be said that the present invention is applied because the active matrix substrate manufactured in Embodiment Mode 5 is used. In this specification, the light emitting device is a general term for a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module including a TFT in the display panel. is there. Note that the light-emitting element includes a layer (light-emitting layer) containing an organic compound from which luminescence (Electro Luminescence) generated by applying an electric field is obtained, an anode layer, and a cathode layer. In addition, luminescence in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state, one of these, Or both luminescence is included.

  In the present specification, all layers formed between the anode and the cathode in the light emitting element are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, a light emitting element has a structure in which an anode layer, a light emitting layer, and a cathode layer are sequentially laminated. In addition to this structure, an anode layer, a hole injection layer, a light emitting layer, a cathode layer, and an anode layer , A hole injection layer, a light emitting layer, an electron transport layer, a cathode layer and the like may be laminated in this order.

  FIG. 12 is a cross-sectional view of the light emitting device of this embodiment. In FIG. 12, a switching TFT 603 provided over a substrate 700 is formed using the n-channel TFT 503 in FIG. Therefore, the description of the n-channel TFT 503 may be referred to for the description of the structure.

  In this embodiment, a double gate structure in which two channel formation regions are formed is used, but a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed may be used.

  A driver circuit provided over the substrate 700 is formed using the CMOS circuit of FIG. Therefore, for the description of the structure, the description of the n-channel TFT 501 and the p-channel TFT 502 may be referred to. In the present embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

  Further, the wirings 701 and 703 function as source wirings of the CMOS circuit, and the wiring 702 functions as a drain wiring. The wiring 704 functions as a wiring that electrically connects the source wiring 708 and the source region of the switching TFT, and the wiring 705 functions as a wiring that electrically connects the drain wiring 709 and the drain region of the switching TFT.

  Note that the current control TFT 604 is formed using the p-channel TFT 502 of FIG. Accordingly, the description of the p-channel TFT 502 may be referred to for the description of the structure. In the present embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

  Further, the wiring 706 is a source wiring (corresponding to a current supply line) of the current control TFT, and 707 is an electrode of the current control TFT that is electrically connected to the pixel electrode 711 by being superimposed on the pixel electrode 711.

  Reference numeral 711 denotes a pixel electrode (anode of the light emitting element) made of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 711 is formed on the flat interlayer insulating film 710 before forming the wiring. In the present embodiment, it is very important to flatten the step due to the TFT using the flattening film 710 made of resin. Since the light emitting layer formed later is very thin, the presence of a step may cause a light emission failure. Therefore, it is desirable to planarize the pixel electrode before forming it so that the light emitting layer can be formed as flat as possible.

After the wirings 701 to 707 are formed, a bank 712 is formed as shown in FIG.
The bank 712 may be formed by patterning an insulating film or organic resin film containing silicon of 100 to 400 nm.

Note that since the bank 712 is an insulating film, attention must be paid to electrostatic breakdown of elements during film formation. In this embodiment, carbon particles or metal particles are added to the insulating film that is the material of the bank 712 to lower the resistivity, thereby suppressing the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 10 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).
The amount of carbon particles or metal particles added may be adjusted so that

A light emitting layer 713 is formed on the pixel electrode 711. Although only one pixel is shown in FIG. 12, in the present embodiment, light emitting layers corresponding to each color of R (red), G (green), and B (blue) are separately formed. In this embodiment, the low molecular weight organic light emitting material is formed by the vapor deposition method. Specifically, a laminated structure in which a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer and a tris-8-quinolinolato aluminum complex (Alq ₃ ) film having a thickness of 70 nm is provided thereon as a light emitting layer. It is said. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1 to Alq ₃ .

  However, the above example is an example of an organic light emitting material that can be used as a light emitting layer, and it is not absolutely necessary to limit to this. A light emitting layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in the present embodiment, an example in which a low molecular weight organic light emitting material is used as a light emitting layer is shown, but a medium molecular weight organic light emitting material or a high molecular weight organic light emitting material may be used. Note that in this specification, an organic light-emitting material that does not have sublimation and has 20 or less molecules or a chain molecule length of 10 μm or less is referred to as a medium molecular organic light-emitting material. As an example of using a polymer organic light emitting material, a 20 nm polythiophene (PEDOT) film is provided by a spin coating method as a hole injection layer, and a paraphenylene vinylene (PPV) film of about 100 nm is provided thereon as a light emitting layer. Alternatively, a laminated structure may be used. If a PPV π-conjugated polymer is used, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. Known materials can be used for these organic light emitting materials and inorganic materials.

  Next, a cathode 714 made of a conductive film is provided on the light emitting layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (magnesium and silver alloy film) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or Group 2 of the periodic table or a conductive film added with these elements may be used.

  When the cathode 714 is formed, the light emitting element 715 is completed. Note that the light-emitting element 715 here refers to a diode formed of a pixel electrode (anode) 711, a light-emitting layer 713, and a cathode 714.

  It is effective to provide a passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a combination thereof.

  At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., it can be easily formed over the light-emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen and can suppress oxidation of the light-emitting layer 713. Therefore, the problem that the light emitting layer 713 is oxidized during the subsequent sealing process can be prevented.

  Further, a sealing material 717 is provided over the passivation film 716 and a cover material 718 is attached thereto. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside. In this embodiment, the cover material 718 is formed by forming a carbon film (preferably a DLC film) on both surfaces of a glass substrate, a quartz substrate, a plastic substrate (including a plastic film), or a flexible substrate. In addition to the carbon film, an aluminum film (AlON, AlN, AlO, etc.), SiN, or the like can be used.

  Thus, a light emitting device having a structure as shown in FIG. 12 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 using a multi-chamber type (or in-line type) film formation apparatus without releasing to the atmosphere. . Further, it is possible to continuously process the process up to the step of bonding the cover material 718 without releasing to the atmosphere.

  Thus, an n-channel TFT 601, a p-channel TFT 602, a switching TFT (n-channel TFT) 603 and a current control TFT (p-channel TFT) 604 are formed on the substrate 700.

  Further, as described with reference to FIGS. 12A and 12B, an n-channel TFT which is resistant to deterioration due to the hot carrier effect can be formed by providing an impurity region overlapping with the gate electrode through an insulating film. Therefore, a highly reliable light emitting device can be realized.

  Further, in the present embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of the present embodiment, other logic circuits such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit are provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

  The light-emitting device manufactured as described above is manufactured with almost no dissociation gas component being introduced during the introduction of ions, and the resist can be easily removed after the introduction of ions. A TFT manufactured using a semiconductor film having excellent physical properties is provided, and the operating characteristics and reliability of the light-emitting device can be made sufficient. And such a light-emitting device can be used as a display part of various electronic devices.

[Embodiment 8]
By applying the present invention, various semiconductor devices (active matrix liquid crystal display device, active matrix light emitting device, active matrix EC display device) can be manufactured. That is, the present invention can be applied to various electronic devices in which these electro-optical devices are incorporated in a display unit. Note that although the present invention is not described in this embodiment mode, it can be said that the present invention is applied because it is manufactured by combining Embodiment Modes 1 to 6 or 7.

  Such electronic devices include video cameras, digital cameras, projectors, head-mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples thereof are shown in FIG. 13, FIG. 14 and FIG.

  FIG. 13A illustrates a personal computer, which includes a main body 3001, an image input portion 3002, a display portion 3003, a keyboard 3004, and the like. By applying the semiconductor device manufactured according to the present invention to the display portion 3003, the personal computer of the present invention is completed.

  FIG. 13B illustrates a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, an image receiving portion 3106, and the like. By applying the semiconductor device manufactured according to the present invention to the display portion 3102, the video camera of the present invention is completed.

  FIG. 13C illustrates a mobile computer, which includes a main body 3201, a camera unit 3202, an image receiving unit 3203, an operation switch 3204, a display unit 3205, and the like. By applying the semiconductor device manufactured according to the present invention to the display portion 3205, the mobile computer of the present invention is completed.

FIG. 13D illustrates a goggle type display, which includes a main body 3301, a display portion 3302, an arm portion 3303, and the like. The display portion 3302 uses a flexible substrate as a substrate, and the goggle type display is manufactured by curving the display portion 3302.
It also realizes a lightweight and thin goggle type display. By applying the semiconductor device manufactured according to the present invention to the display portion 3302, the goggle type display of the present invention is completed.

  FIG. 13E shows a player that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, a speaker portion 3403, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. By applying the semiconductor device manufactured according to the present invention to the display portion 3402, the recording medium of the present invention is completed.

  FIG. 13F illustrates a digital camera, which includes a main body 3501, a display portion 3502, an eyepiece portion 3503, an operation switch 3504, an image receiving portion (not shown), and the like. By applying the semiconductor device manufactured according to the present invention to the display portion 3502, the digital camera of the present invention is completed.

  FIG. 14A illustrates a front type projector, which includes a projection device 3601, a screen 3602, and the like. The front type projector of the present invention is completed by applying the semiconductor device manufactured according to the present invention to the liquid crystal display device 3808 constituting a part of the projection device 3601 and other driving circuits.

  FIG. 14B shows a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. By applying the semiconductor device manufactured according to the present invention to the liquid crystal display device 3808 constituting a part of the projection device 3702 and other driving circuits, the rear projector of the present invention is completed.

  Note that FIG. 14C is a diagram illustrating an example of the structure of the projection devices 3601 and 3702 in FIGS. 14A and 14B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although this embodiment showed the example of a three-plate type, it is not specifically limited, For example, a single plate type may be sufficient. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.

  FIG. 14D shows an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 14D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

  However, the projector shown in FIG. 14 shows a case where a transmissive electro-optical device is used, and an application example in a reflective electro-optical device and a light-emitting device is not shown.

  FIG. 15A illustrates a mobile phone, which includes a main body 3901, an audio output portion 3902, an audio input portion 3903, a display portion 3904, operation switches 3905, an antenna 3906, and the like. By applying the semiconductor device manufactured according to the present invention to the display portion 3904, the cellular phone of the present invention is completed.

  FIG. 15B illustrates a portable book (electronic book), which includes a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, an antenna 4006, and the like. By applying the semiconductor device manufactured according to the present invention to the display portions 4002 and 4003, the portable book of the present invention is completed.

  FIG. 15C illustrates a display, which includes a main body 4101, a support base 4102, a display portion 4103, and the like. The display portion 4103 is manufactured using a flexible substrate, and a lightweight and thin display can be realized. In addition, the display portion 4103 can be curved. By applying the semiconductor device manufactured according to the present invention to the display portion 4103, the display of the present invention is completed. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Further, the electronic device of the present embodiment can also be realized by using a configuration that is a combination of the first to sixth or seventh embodiments.

The figure which shows an example of the ion introduction | transduction method of this invention. The figure which shows an example of the ion introduction | transduction method of this invention. The figure which shows the example of the change of the pressure in a process chamber when a 1st acceleration voltage is shaken and the 2nd acceleration voltage is made into the same conditions. The figure which shows the example of the change of the pressure in a process chamber when the 1st acceleration voltage is made into the same conditions and the 2nd acceleration voltage is shaken. The figure which shows the example of the change of the pressure in a process chamber by the presence or absence of resist baking. The figure which shows the example of distribution of the ion in a silicon wafer by the presence or absence of a resist. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. Sectional drawing which shows the manufacturing process of TFT of a pixel TFT and a driver circuit. FIG. 6 is a top view illustrating a configuration of a pixel TFT. Sectional drawing of an active-matrix liquid crystal display device. FIG. 6 is a cross-sectional structure diagram of a driver circuit and a pixel portion of a light emitting device. FIG. 11 illustrates an example of a semiconductor device. FIG. 11 illustrates an example of a semiconductor device. FIG. 11 illustrates an example of a semiconductor device.

Explanation of symbols

10 Substrate 11 Base Insulating Film 12 Semiconductor Layer 13 Insulating Film 14 Resist 15 First Ion 16 Dissociation Gas 17 Impurity Region 18 Second Ion 19 Impurity Region 20 Substrate 21 Resist

Claims (8)

In the step of introducing ions into the processing chamber by ion implantation or ion doping,
Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first organic film as a mask on the first semiconductor layer;
The dissociation gas from the first organic film is treated by introducing the first ions with the first acceleration voltage,
Exhaust after completion of introduction of the first ions to reduce or remove dissociation gas from the first organic film from the processing chamber,
The second organic film containing a first conductivity type impurity element generated using the same material gas as the first ions by a second acceleration voltage lower than the first acceleration voltage using the first organic film as a mask Impurity regions are formed in the second semiconductor layer by introducing ions,
Forming a second organic film as a mask on the second semiconductor layer after removing the first organic film;
Dissociation gas treatment from the second organic film is performed by introducing third ions with a third acceleration voltage,
Exhaust after completion of the introduction of the third ions to reduce or remove dissociation gas from the second organic film from the processing chamber,
Using the second organic film as a mask, a conductivity type opposite to the one conductivity type generated using the same material gas as the third ions by a fourth acceleration voltage lower than the third acceleration voltage. A method for manufacturing a semiconductor device, wherein an impurity region is formed in the first semiconductor layer by introducing a fourth ion containing an impurity element to be added. In the step of introducing ions into the processing chamber by ion implantation or ion doping,
Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first organic film as a mask on the first semiconductor layer;
By introducing the first ions with a first acceleration voltage of 50 kV to 120 kV, the dissociation gas from the first organic film is treated within 6 minutes,
Exhaust after completion of introduction of the first ions to reduce or remove dissociation gas from the first organic film from the processing chamber,
Using the first organic film as a mask, an impurity element of one conductivity type generated by using the same material gas as the first ions by a second acceleration voltage of 40 kV to 120 kV lower than the first acceleration voltage. An impurity region is formed in the second semiconductor layer by introducing a second ion including
Forming a second organic film as a mask on the second semiconductor layer after removing the first organic film;
The dissociation gas treatment from the second organic film is performed within 6 minutes by introducing the third ions with the third acceleration voltage of 50 kV to 120 kV,
Exhaust after completion of the introduction of the third ions to reduce or remove dissociation gas from the second organic film from the processing chamber,
Using the second organic film as a mask, it is opposite to the one conductivity type generated using the same material gas as the third ions by a fourth acceleration voltage of 40 kV to 120 kV lower than the third acceleration voltage. A method for manufacturing a semiconductor device is characterized in that an impurity region is formed in the first semiconductor layer by introducing a fourth ion containing an impurity element imparting the above conductivity type. In the step of introducing ions into the processing chamber by ion implantation or ion doping,
Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a gate insulating film covering the first semiconductor layer and the second semiconductor layer;
Forming a first conductive film and a second conductive film on the gate insulating film;
A mask made of resist is formed over the first conductive film and the second conductive film, which overlap with the first semiconductor layer and the second semiconductor layer, and a first etching process is performed, so that the first conductive layer is formed. Forming a first shape conductive layer comprising a layer and a second conductive layer on each of the first semiconductor layer and the second semiconductor layer;
A second etching process is performed on the first shape conductive layer without removing the resist mask, and a second shape conductive layer is formed.
Removing the resist mask;
Introducing an impurity element imparting n-type into the first semiconductor layer and the second semiconductor layer at a low concentration;
Forming a first organic film covering the first semiconductor layer;
The dissociation gas from the first organic film is treated by introducing the first ions with the first acceleration voltage,
Exhaust after completion of introduction of the first ions to reduce or remove dissociation gas from the first organic film from the processing chamber,
The second organic film containing a first conductivity type impurity element generated using the same material gas as the first ions by a second acceleration voltage lower than the first acceleration voltage using the first organic film as a mask By introducing ions, a high concentration impurity region and a low concentration impurity region overlapping the first conductive layer are formed in the second semiconductor layer,
Forming a second organic film covering the second semiconductor layer after removing the first organic film;
Dissociation gas treatment from the second organic film is performed by introducing third ions with a third acceleration voltage,
Exhaust after completion of the introduction of the third ions to reduce or remove dissociation gas from the second organic film from the processing chamber,
Using the second organic film as a mask, a conductivity type opposite to the one conductivity type generated using the same material gas as the third ions by a fourth acceleration voltage lower than the third acceleration voltage. A method for manufacturing a semiconductor device, wherein an impurity region is formed in the first semiconductor layer by introducing a fourth ion containing an impurity element to be added. In the step of introducing ions into the processing chamber by ion implantation or ion doping,
Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first organic film as a mask on the first semiconductor layer;
The dissociation gas from the first organic film is treated by introducing the first ions using an inert gas with a first acceleration voltage,
Exhaust after completion of the introduction of the first ions to reduce or remove dissociated gas from the first organic film from the processing chamber,
Using the first organic film as a mask, a second ion containing an impurity element of one conductivity type generated using PH ₃ or B ₂ H ₆ with a _second acceleration voltage lower than the first acceleration voltage. By introducing, an impurity region is formed in the second semiconductor layer,
Forming a second organic film as a mask on the second semiconductor layer after removing the first organic film;
Dissociation gas treatment from the second organic film is performed by introducing third ions using an inert gas with a third acceleration voltage,
Exhaust after completion of the introduction of the third ions to reduce or remove dissociation gas from the second organic film from the processing chamber,
Using the second organic film as a mask, a fourth ion containing an impurity element imparting a conductivity type opposite to the one conductivity type is introduced by a fourth acceleration voltage lower than the third acceleration voltage. Thus, an impurity region is formed in the first semiconductor layer. In the step of introducing ions into the processing chamber by ion implantation or ion doping,
Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a first organic film as a mask on the first semiconductor layer;
The dissociation gas treatment from the first organic film is performed within 6 minutes by introducing the first ions using an inert gas with a first acceleration voltage of 50 kV to 120 kV,
Exhaust after completion of the introduction of the first ions to reduce or remove dissociated gas from the first organic film from the processing chamber,
A first conductivity type impurity element generated using PH ₃ or B ₂ H ₆ with a _second acceleration voltage of 40 kV to 120 kV lower than the first acceleration voltage using the first organic film as a mask. 2 to introduce an impurity region in the second semiconductor layer,
Forming a second organic film as a mask on the second semiconductor layer after removing the first organic film;
The dissociation gas treatment from the second organic film is performed within 6 minutes by introducing the third ions using an inert gas with a third acceleration voltage of 50 kV to 120 kV,
Exhaust after completion of the introduction of the third ions to reduce or remove dissociation gas from the second organic film from the processing chamber,
Using the second organic film as a mask, a fourth ion containing an impurity element imparting a conductivity type opposite to the one conductivity type by a fourth acceleration voltage of 40 kV to 120 kV lower than the third acceleration voltage. An impurity region is formed in the first semiconductor layer by introducing the semiconductor device. In the step of introducing ions into the processing chamber by ion implantation or ion doping,
Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a gate insulating film covering the first semiconductor layer and the second semiconductor layer;
Forming a first conductive film and a second conductive film on the gate insulating film;
A mask made of resist is formed over the first conductive film and the second conductive film, which overlap with the first semiconductor layer and the second semiconductor layer, and a first etching process is performed, so that the first conductive layer is formed. Forming a first shape conductive layer comprising a layer and a second conductive layer on each of the first semiconductor layer and the second semiconductor layer;
A second etching process is performed on the first shape conductive layer without removing the resist mask, and a second shape conductive layer is formed.
Removing the resist mask;
Introducing an impurity element imparting n-type into the first semiconductor layer and the second semiconductor layer at a low concentration;
Forming a first organic film covering the first semiconductor layer;
The dissociation gas from the first organic film is treated by introducing the first ions using an inert gas with a first acceleration voltage,
Exhaust after completion of the introduction of the first ions to reduce or remove dissociated gas from the first organic film from the processing chamber,
Using the first organic film as a mask, a second ion containing an impurity element of one conductivity type generated using PH ₃ or B ₂ H ₆ with a _second acceleration voltage lower than the first acceleration voltage. By introducing, a high-concentration impurity region and a low-concentration impurity region overlapping the first conductive layer are formed in the second semiconductor layer,
Forming a second organic film covering the second semiconductor layer after removing the first organic film;
Dissociation gas treatment from the second organic film is performed by introducing third ions using an inert gas with a third acceleration voltage,
Exhaust after completion of the introduction of the third ions to reduce or remove dissociation gas from the second organic film from the processing chamber,
Using the second organic film as a mask, a fourth ion containing an impurity element imparting a conductivity type opposite to the one conductivity type is introduced by a fourth acceleration voltage lower than the third acceleration voltage. Thus, an impurity region is formed in the first semiconductor layer.   7. The method for manufacturing a semiconductor device according to claim 1, wherein the first ion is introduced after the first organic film is baked or UV-irradiated.   8. The method for manufacturing a semiconductor device according to claim 1, wherein the third ions are introduced after the second organic film is baked or UV-irradiated.

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