JP2001274087A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the diameter of the crystal grain of a crystal semiconductor film that is manufactured by a laser crystallization method, and to manufacture a TFT by the crystal semiconductor film for obtaining reliability that is equal to that of a MOS transistor. SOLUTION: To increase the diameter of a crystal grain of the crystal semiconductor film that is manufactured by the laser crystallization method, a heat- insulating barrier is formed between the semiconductor film and a substrate to reduce the outflow speed of heat, and the cooling process of the semiconductor film that is heated by applying a laser beam is moderated. Crystal growth distance is proportional to the product of growth time and speed, thus moderating the cooling speed, lengthening the growth time, and hence increasing the diameter of the crystal grain.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crystalline semiconductor film and a method for manufacturing the same, and more particularly to a technique which can be suitably used for a semiconductor device having a circuit constituted by thin film transistors. For example, the present invention relates to an electro-optical device typified by a liquid crystal display device and an electronic apparatus equipped with such an electro-optical device as a component.

[0002]

2. Description of the Related Art A thin film transistor (hereinafter referred to as a thin film transistor) in which an amorphous semiconductor film is formed on a light-transmitting insulating substrate such as glass, and a crystalline semiconductor film crystallized by a laser annealing method, a thermal annealing method or the like is used as an active layer. Thin Film Transistor:
TFT) has been developed.

[0003] The laser crystallization method, which is known as one of means for obtaining a crystalline semiconductor film, employs a crystal in which a high energy can be applied only to an amorphous semiconductor film without increasing the temperature of the substrate so much. It is known as chemical technology. In particular, an excimer laser capable of obtaining a large output with ultraviolet light is considered suitable for this application. In the laser crystallization method using an excimer laser, a laser beam is condensed by an optical system so as to form a spot or a line on the surface to be irradiated, and the surface to be irradiated is scanned. (Relative to the surface). For example, when irradiating a linear laser beam, it is possible to process the entire illuminated surface by scanning only in a direction perpendicular to the longitudinal direction, and it can be applied to a large substrate. It has become mainstream.

[0004] Laser crystallization is applicable to the crystallization of various semiconductor materials. However, a material typically used for an active layer of a TFT is a crystalline silicon film, and a high field-effect mobility has been realized by using the material. This technology has enabled a monolithic liquid crystal display device in which a pixel TFT of a pixel portion and a TFT of a driving circuit provided around the pixel portion are integrally formed on one glass substrate.

However, a crystalline silicon film produced by a laser annealing method is a collection of a plurality of crystal grains, and the positions and sizes of the crystal grains are formed at random. Crystal grains cannot be formed by designating the position or size thereof, and the size is about several tens to several hundreds nm. At the interface of crystal grains (grain boundaries), the current transport characteristics of carriers are degraded by the influence of recombination centers, trapping centers, and potential levels at the crystal grain boundaries caused by amorphous structures and crystal defects. was there.

As a factor limiting the characteristics of the TFT, there is an influence of a crystal grain boundary existing in a channel forming region. Therefore, a TFT using a crystalline silicon film as an active layer cannot obtain characteristics equivalent to those of a MOS transistor manufactured on a single crystal silicon substrate.

As a method for solving such a problem,
Eliminating the crystal grain boundaries from the channel forming region by enlarging the crystal grains and controlling their positions is considered as an effective means. For example, "" Location Control of Lar
ge Grain Following Excimer-Laser Melting of Si Thi
n-Films ", R. Ishihara and A. Burtsev, Japanese Journ
al of Applied Physics vol.37, No.3B, pp1071-1075,1
988 "discloses a method of three-dimensionally controlling the temperature distribution of a silicon film to achieve crystal position control and a large grain size. According to the method, a refractory metal is formed on a glass substrate, a silicon oxide film having a partially different thickness is formed thereon, and an amorphous silicon film is formed on the surface thereof. Report that the crystal grain size can be increased to several μm by irradiating an excimer laser beam.

[0008]

Increasing the crystal grain, in other words, increasing the crystal growth distance, is considered to be proportional to the product of the growth time and the growth rate. In order to lengthen the growth time, it is necessary to reduce the speed at which the energy obtained from the laser light flows out.

When a crystalline semiconductor film is formed on a substrate such as glass by a laser crystallization method, a silicon oxide film or the like is interposed between the substrate and the substrate. An excimer laser effective for crystallization of a crystalline semiconductor film emits pulses, and its practical oscillation frequency is several tens to several hundreds Hz, whereas its pulse width is several tens of nanoseconds. When laser crystallization is performed after depositing an amorphous semiconductor film on a silicon oxide film, heat energy accumulated by irradiation with pulsed laser light flows out to the substrate side. A silicon oxide film in which Si—O bonds are randomly network-bonded facilitates the outflow of the thermal energy.

The present invention is a technique for solving such a problem, and an object of the present invention is to realize a crystal grain of a crystalline semiconductor film formed by a laser crystallization method with a large grain size. It is an object of the present invention to manufacture a TFT from the crystalline semiconductor film and obtain reliability comparable to that of a MOS transistor.
Further, such a TFT is used as a transmission type liquid crystal display device or an E-type.
It is an object of the present invention to provide a technique applicable to various semiconductor devices such as an L display device.

[0011]

According to the present invention, a heat insulating layer is provided between a semiconductor film and a substrate in order to realize a large crystal grain of a crystalline semiconductor film produced by a laser crystallization method. When formed, the outflow rate of heat is reduced, and the cooling process of the semiconductor film heated by the irradiation of the laser light is moderated. Since the crystal growth distance is proportional to the product of the growth time and the growth rate, the cooling rate is slow and the growth time is long, so that a large grain size can be realized.

The heat insulating layer is composed of an ethyl (C ₂ H ₅ ) group, a propyl (C ₃ H ₈ ) group, a butyl (C ₄ H ₁₀ ) group, and a vinyl (C
It is formed of silicon oxide (organic silicon oxide) containing any of a ₂ H ₂ ) group, a phenyl (C ₆ H ₅ ) group, and a CF ₃ group. Among these, silicon oxide having an organic bond has a low heat propagation speed because the bond between the silicon and the organic substance does not participate in network bonding, and effectively functions as a heat insulating layer. It is also effective to use porous silicon as another form of the heat insulating layer. Porous silicon can be used as a heat insulating layer because of the vacancies that reduce the speed of heat propagation.

As described above, the crystalline semiconductor film manufactured by the laser crystallization method with the heat insulating layer interposed between the semiconductor film and the substrate can be applied to various semiconductor devices. In particular, it is suitable for forming an active layer of a TFT.

Increasing the grain size of the crystal makes it possible to improve various characteristics such as the field-effect mobility of the TFT. Among them, a semiconductor device suitable for the purpose of securing reliability is a semiconductor device in which a first n-channel TFT and a second n-channel TFT are formed on a substrate. The type TFT has a first semiconductor film and a first gate electrode, and is provided outside a first impurity region overlapping with the first gate electrode and doped with an impurity element of one conductivity type; A second impurity region to which an impurity element of one conductivity type is added, which is in contact with the first impurity region, while the second n-channel type TFT includes a second semiconductor film and a second gate electrode. A third impurity region overlapped with the second gate electrode and doped with an impurity element of one conductivity type;
The gate electrode and the second gate electrode are preferably formed of a first conductive film and a second conductive film formed inside the first conductive film.

In the structure of the TFT, the concentration of the impurity element in the first impurity region to which the impurity element of one conductivity type is added is 2 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ . The concentration of the impurity element in the second impurity region to which the impurity element is added is 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ , and the concentration of the impurity element in the third impurity region to which the one conductivity type impurity element is added is The concentration of the impurity element is 5 × 10 ^{17 to} 5 × 10 ¹⁹ / cm ³ ,
In addition, the concentration of the impurity element in the second impurity region to which the impurity element of one conductivity type is added is higher than the concentration of the impurity element in the first impurity region to which the impurity element of one conductivity type is added, Further, it is preferable that the third impurity region to which the one conductivity type impurity element is added satisfy a relationship lower than the concentration of the impurity element.

Further, the above-mentioned TFT is manufactured by a method of forming a first n-channel TFT and a second n-channel TFT on a substrate.
A first step of forming a heat insulating layer on a substrate, a second step of forming a first insulating layer on the heat insulating layer, and a step of forming a first insulating layer on the heat insulating layer. A third step of forming a semiconductor film having an amorphous structure, a fourth step of irradiating the semiconductor film having an amorphous structure with a laser beam to form a semiconductor film having a crystalline structure, A fifth step of forming a first semiconductor film and a second semiconductor film separated into islands from the semiconductor film having the first semiconductor film and a first conductive layer above the first semiconductor film and the second semiconductor film; A sixth step of forming the first conductive layer and the second conductive layer by overlapping the first conductive layer and the second conductive layer; and forming a plurality of first shape conductive layers having a tapered portion at an end by etching the first conductive layer and the second conductive layer. A seventh step of forming a layer, and anisotropically etching the plurality of first-shape conductive layers to form a first conductive layer. An eighth step of the second conductive layer to form a conductive layer of the plurality of second shape provided in the first
A second conductivity type impurity element is added to the
A ninth step of forming a first impurity region overlapping the conductive layer having the shape of the second shape and a second impurity region not overlapping the conductive layer having the second shape; A tenth step of forming a third impurity region overlapping with the second shape conductive layer by adding an element.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] The crystal grain size of a crystalline silicon film obtained by a laser crystallization method is small because the cooling rate of a silicon layer after melting is high, so that the nucleation density becomes large. This is considered to be because sufficient crystal growth from one crystal nucleus was inhibited. Therefore, when changing from the molten state to the solid state, thermal diffusion from the silicon layer to the lower silicon oxide layer and the substrate is suppressed, and the cooling rate of the silicon layer after melting is reduced, so that a crystal having a large grain size can be obtained. Is thought to be possible.

FIG. 1 shows a configuration capable of suppressing thermal diffusion, and is a view for explaining the concept of the laser crystallization method of the present invention. A first insulating film 102, a heat insulating layer 103, a second insulating film 104, and an amorphous semiconductor film 105 are formed over a substrate 101. The first and second insulating films are formed using silicon oxide, nitride, or a mixture thereof. Preferably, a material selected from silicon oxide, silicon nitride, and silicon oxynitride is selected. Heat insulation layer is ethyl (C ₂ H ₅ )
Oxide film containing any one of a group, a propyl (C ₃ H ₈ ) group, a butyl (C ₄ H ₁₀ ) group, a vinyl (C ₂ H ₂ ) group, a phenyl (C ₆ H ₅ ) group, and a CF ₃ group Formed. For example, in a silicon oxide film containing an ethyl group, since the ethyl group bonds only to silicon, it is considered that the network bond density of silicon is reduced and the rate of thermal diffusion is reduced. Alternatively, it may be formed of a porous silicon film. Since the porous silicon film has a large number of holes, the speed of thermal diffusion is reduced.

The material of the amorphous semiconductor film is amorphous silicon, amorphous silicon germanium, amorphous silicon
It is a carbide or the like, and is formed by a vapor phase growth method such as a plasma CVD method or a sputtering method.

In the laser crystallization method, the semiconductor film is heated and melted by optimizing the conditions of the laser beam (or laser beam) to be irradiated, and the density of crystal nuclei generated and the crystal growth from the crystal nuclei Is controlling. Applicable laser light irradiation conditions include laser energy density, number of irradiation pulses, pulse width (irradiation time), repetition frequency (cooling time), substrate heating temperature, and the like. But,
Substrate heating temperatures below 500 ° C. are not actively used because they do not contribute much to increasing the crystal grain size.

FIG. 2 shows how the substrate 110 on which the amorphous semiconductor film 111 is formed is irradiated with linear laser light 113. The linear laser light is usually applied from the surface on which the film is formed, but may be applied from the opposite substrate side. The laser light is condensed linearly by the cylindrical lens 112, and for that purpose, it is necessary to combine a plurality of cylindrical lenses (omitted in FIG. 2). The intensity distribution of the linear laser light to be irradiated is uniform in the longitudinal direction (y direction) and the width direction (x direction).

FIG. 3 is a diagram showing an example of the configuration of a laser irradiation apparatus used in the laser crystallization method. An excimer laser, a YAG laser, or the like is applied to the laser oscillator 301. Excimer lasers using ArF, KrF, XeCl, or the like have a wavelength of 400 nm or less, and can obtain laser light with high energy density. The diode-pumped YAG laser also has a feature that a laser beam having a high energy density can be obtained at a high oscillation frequency, and is suitable for use in a laser crystallization method. However, in this case, the second harmonic (532 nm) to the third harmonic (355 nm)
nm). As a type of YAG laser, YAG laser
An LF laser and a YVO ₄ laser can also be used.

The laser beam emitted from the laser beam generator 301 is expanded in one direction by beam expanders 302 and 303 and reflected by a mirror 304. Then, the light is divided by the cylindrical lens array 305, and the cylindrical lenses 306 and 30 are divided.
7, a linear beam having a line width of 100 to 1000 μm is irradiated so as to form a linear irradiation area 310 on the sample surface. The substrate 308 is held on a stage 309 that can operate in the X, Y, and θ directions. Then, by moving the stage 309 to the irradiation region 310, laser light can be irradiated over the entire surface of the substrate 308. At this time, the substrate 308 may be held in an air atmosphere, or may be held under reduced pressure or in an inert gas atmosphere for crystallization.

Next, an example of an apparatus for handling the substrate 308 in the laser apparatus having the configuration shown in FIG. 3 will be described with reference to FIG. Substrate 413 held on stage 412
Is installed in the processing chamber (A) 418, and is irradiated with linear laser light having the laser oscillator 411 shown in FIG. 3 as an oscillation source. The inside of the reaction chamber can be set in a reduced pressure state or an inert gas atmosphere by an exhaust system or a gas system (not shown), so that the semiconductor film does not contaminate the semiconductor film.
Stage 425 is a heating means capable of heating to ℃.
Are provided. The stage 425 corresponds to the stage 412 shown in FIG.

The stage 425 is connected to the guide rail 42
1 can be moved in the reaction chamber, and the entire surface of the substrate can be irradiated with linear laser light. The laser light enters from a quartz window (not shown) provided on the upper surface of the substrate 426. In FIG. 15, the reaction chamber 4
Reference numeral 18 is connected to a transfer chamber 415 via a gate valve 424. In the transfer chamber 415, a load / unload chamber 417 via a gate valve 422 and a processing chamber (B) 416 for forming a coating via a gate valve 423.
Is connected.

In the load / unload chamber 417, a cassette 419 capable of holding a plurality of substrates is provided.
The substrate is transferred by the transfer means 420 provided in the transfer chamber 415. The substrate 427 ′ represents the substrate being transported. Processing chamber (B) 416 has plasma C
This is for forming a semiconductor film by a VD method, a sputtering method, or the like. The substrate heating means 428 and the glow discharge generating means 429
In addition, a gas supply unit (not shown) is provided.

Although not shown in FIG. 15, the exhaust means and the gas supply means are connected to the transfer chamber 415 and the processing chamber (A).
415, processing room (B) 416, loading / unloading room 4
With the configuration provided in 17, the formation of the semiconductor film and the heat treatment of the semiconductor film using laser light can be continuously performed under reduced pressure or in an inert gas atmosphere.

Since the pulse width of the excimer laser is several nanoseconds to several tens of nanoseconds, for example, 30 nanoseconds, when the pulse oscillation frequency is set to 30 Hz, the semiconductor film is instantaneously heated by the pulse laser light, and is much longer than the heating time. It will be cooled for a long time. Even if a YAG laser having a higher oscillation frequency is used, the relationship does not change. In the cooling process that starts immediately after the end of the laser beam irradiation, heat diffuses into the substrate and into the gas phase, but the former is the dominant factor in the diffusion speed due to the difference in the medium.

The crystallization process will be described with reference to FIG.
The amorphous semiconductor film 105 has a pulsed laser beam 10
It is heated by the irradiation of No. 6 and once in a molten state. Immediately after the laser beam 106 is cut off, the cooling process starts, and the phase changes to a solid phase state.
3 to be suppressed. That is, the cooling rate is relatively slower than when the heat insulating layer 103 is not provided.

It is presumed that crystal nuclei are formed and formed in a cooling process in which a transition from a molten state to a solid state occurs. The nucleation density has a correlation between the temperature in the molten state and the cooling rate,
Empirical knowledge has shown that the nucleation density tends to increase when quenched from a high temperature. Crystal nuclei are generated near the interface between the semiconductor film and the base. In the case of FIG. 1, by optimizing the irradiation conditions of the laser beam and the thickness of the heat insulating layer 103, the temperature in the molten state and the cooling rate thereof can be controlled, and the number of crystal nuclei 107 generated can be reduced. In addition, a crystal having a large grain size can be grown.

In this sense, the thermal conductivity of the heat insulating layer is desirably 1.0 W / m · K or less, preferably 0.3 W / m · K or less. The thermal conductivity of this heat-insulating layer can be measured using a substrate (1.4 W / m · K for a quartz substrate) or silicon oxide (1-2 W / m · K).
Since the temperature is very low as compared with K), thermal diffusion from the semiconductor film to the substrate can be sufficiently suppressed.

By such a mechanism, the crystal grains of the crystalline semiconductor film produced by the laser crystallization method can be made larger. A crystalline semiconductor film formed over a substrate with a heat insulating layer interposed therebetween can be used as an active layer of a TFT.

[Embodiment 2] An example of a method for manufacturing a crystalline semiconductor film by the laser crystallization method of the present invention will be described with reference to FIGS. In FIG. 4A, an alkali-free glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, or the like can be used as the substrate 201. In addition, polycarbonate (PC), polyarylate (PAr), polyethersulfone (PES),
An organic resin film such as polyether terephthalate (PET) can also be used.

Then, a first insulating film 202 made of an insulating film such as a silicon oxide film, a silicon nitride film or a silicon oxynitride film is formed on the surface of the substrate 101 on which the TFT is to be formed, in order to prevent impurity contamination from the substrate 101. I do. For example, a silicon oxynitride film formed from SiH ₄ , NH ₃ , and N ₂ O is formed by plasma CVD to a thickness of 10 to 200 nm (preferably 50 to 100 nm).

Next, the heat insulating layer 203 is made of ethyl (C ₂ H ₅ ).
Oxide film containing any one of a group, a propyl (C ₃ H ₈ ) group, a butyl (C ₄ H ₁₀ ) group, a vinyl (C ₂ H ₂ ) group, a phenyl (C ₆ H ₅ ) group, and a CF ₃ group Formed. Although a manufacturing method depends on an organic material used as a raw material, a gas phase method or a liquid phase method is used. The thickness of the heat insulating layer is 100 nm to 1000
nm (preferably 200 to 500 nm). By optimizing this film thickness, the cooling rate in the laser crystallization step is controlled. If the thickness is less than 100 nm, a sufficient heat insulating effect cannot be obtained. Also,
If the thickness is more than 1000 nm, it is not preferable because cracks (cracks) are formed in the semiconductor film formed thereon. The second insulating layer 204 is similar to the first insulating layer 202,
It is formed with a thickness of 10 to 100 nm.

As shown in FIG. 4B, the second insulating film 2
On the substrate 04, an amorphous semiconductor film 205 is formed with a thickness of 10 to 100 nm. Although an amorphous silicon film is typically used as the amorphous semiconductor film, a compound semiconductor film having an amorphous structure such as an amorphous silicon / germanium film may be used. The method for forming the amorphous semiconductor film is as follows.
A known method such as a plasma CVD method or a sputtering method may be used.

The conditions for the laser crystal are appropriately selected by the practitioner. For example, the pulse oscillation frequency of the excimer laser is set to 50 Hz, and the laser energy density is set to 200.
４００400 mJ / cm ² (typically 250 to 350 mJ / cm ² ). Then, the linear laser light condensed by the optical system is irradiated over the entire surface of the substrate. The superposition rate (overlap rate) of the linear laser light at this time is set to 80 to 99% (preferably 95 to 99%). Thus, FIG.
A crystalline semiconductor film 207 can be obtained as shown in FIG.

[Third Embodiment] In the second embodiment, as the heat insulating layer 203 shown in FIG.
An organic silicon oxide film formed using (Tetraethyl Ortho Silicate: Si (OC ₂ H ₅ ) ₄ ) can be used. One example of the manufacturing method is to mix TEOS and O _2, and to react at a reaction pressure of 20 to 100 Pa and a substrate temperature of 200 to 350 Pa.
° C, high frequency (13.56 MHz) power density 0.1 ~
A glow discharge is formed at 0.5 W / cm ² . Although the optimum manufacturing conditions also depend on the characteristics of the device to be actually used, it is necessary to lower the substrate temperature and power density to leave undecomposed C _x H _y bonds to form an organic-containing silicon oxide film. it can.

In addition, a phenyl group-containing silicon oxide film is made of phenyltrichlorosilane (PhSiCl ₃ ) and water (H
The gas mixture ₂ O) can be obtained by directly formed on a substrate heated to 60 to 100 [° C.. Further, a silicon oxide film containing CF3 _{groups, CF 3 Si (CH 3)} 3 and ozone (O ₃₎
Can be deposited on a substrate heated to 300 to 400 ° C. [Embodiment 4] FIG. 5 shows an example in which an organic-containing silicon oxide film serving as a heat insulating layer 203 in Embodiment 2 is manufactured by a liquid phase method. A container 501 containing a raw material 505 and a reaction tank 502 containing a solution 506 are connected by a nozzle 504. Solution 50
6 is impregnated with the substrate 508. The flow rate is controlled by a mass flow controller 503 using nitrogen as a carrier gas, the raw material is bubbled and the raw material 505 is supplied to a reaction tank 502 containing a solution 506, and the raw material and the solution are reacted to form an organic-containing silicon oxide film on a substrate. Form. The reaction is carried out while stirring with a stirrer in the solution 506. The temperature may be set at room temperature.

The raw material is ethyltriethoxysilane (CH ₃ CH ₂
Si (OC ₂ H ₅ ) ₃ ), n-propyltriethoxysilane (CH ₃ (CH _{3
2) 2 Si (OC 2 H} 5) 3), n- butyl triethoxysilane run (CH ₃ (C
H ₂ ) ₃ Si (OC ₂ H ₅ ) ₃ ), vinyltriethoxysilane (CH ₂ CHSi
An aqueous solution of an organic compound selected from (OC ₂ H ₅ ) ₃ ) is used.

The solution 506 is an aqueous solution prepared by adjusting formic acid (HCOOH) and ammonia (NH4OH) to a predetermined concentration. The mixing ratio is appropriately adjusted. One example is a solution volume of 400 ml, formic acid 1.5 mol / l, ammonia 1.0 m
ol / l. The advantage of such a liquid phase method is that the film can be deposited at a low temperature and a film can be formed without breaking the molecular structure. However, the deposition rate is slow, 4n
m / hour.

[Embodiment 5] The heat insulating layer can be formed of porous silicon in addition to the organic insulating silicon oxide. An example of such a case will be described with reference to FIGS. In FIG. 11A, a silicon substrate is used as the substrate 21.
This silicon substrate is not limited to a semiconductor grade such as CZ silicon or FZ silicon, but is a solar cell grade (SOG grade).
May be used. Further, a silicon film formed on a glass substrate or a quartz substrate can be used instead.

The porous silicon layer can be easily produced by anodizing a silicon substrate. The anodizing solution used is a mixture of hydrofluoric acid (HF) and ethanol at a ratio of 1: 1 and the current density is 1 to 200 mA / cm ² . The porous silicon layer is formed at 1 to 5 μm. Thus, the heat insulating layer 2 composed of the porous silicon layer is formed on the substrate 210.
12 is formed.

Since the surface of the heat insulating layer 212 made of porous silicon has about 10 ¹¹ holes / cm ² , a silicon layer 213 is formed thereon and flattened. Silicon layer 2
13 is manufactured by a CVD method. 900-1040 ° C first
Heat treatment in hydrogen is performed, and then a silicon film of 10 to 200 nm is deposited. Voids disappear by heat treatment in hydrogen,
The surface can be planarized by epitaxially growing the silicon layer. Further, an insulating layer 214 is formed. A silicon oxide film may be deposited by a thermal CVD method or a plasma CVD method, or the insulating layer 214 may be formed by thermally oxidizing the silicon layer 213. The thickness is 10 to 100 nm.

Then, the second embodiment is formed on the insulating layer 214.
Similarly, the amorphous semiconductor film 215 is formed with a thickness of 10 to 100 nm. Then, the amorphous semiconductor film 215 is crystallized by irradiation with laser light 216 (FIG. 11B). Thus, the crystalline semiconductor film 217 can be obtained as shown in FIG.

[0046]

[Example 1] An example of manufacturing a display device from a crystallized semiconductor film manufactured by using the laser crystallization method of the present invention will be described. Here, the pixel TFT and the storage capacitor in the pixel region and the T of the driving circuit provided around the pixel region are used.
A method for simultaneously manufacturing FTs will be described with reference to the drawings.

In FIG. 6A, a substrate 601 is made of a glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass, etc., and polyethylene terephthalate (PET). ), Polyethylene naphthalate (P
EN), a plastic substrate having no optical anisotropy such as polyethersulfone (PES) can be used. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, a first insulating film 602 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a surface of the substrate 101 where a TFT is to be formed, in order to prevent impurity diffusion from the substrate 601. For example, a silicon oxynitride film formed from SiH ₄ , NH ₃ , and N ₂ O with a thickness of 10 to 100 nm by a plasma CVD method is used as the first insulating film 602.

The silicon oxynitride film is formed by using a parallel plate type plasma CVD method. Silicon oxynitride film
10 SCCM for SiH ₄ , 100 SCCM for NH ₃ , ₂₀ S for N ₂ O
It was introduced into the reaction chamber as CCM, the substrate temperature was 325 ° C., the reaction pressure was 40 Pa, the discharge power density was 0.41 W / cm ² , and the discharge frequency was 6
0 MHz.

The heat insulating layer 603 is an organic-containing silicon oxide film having a thickness of 100 nm to 1000 nm (preferably 200 to 500 nm).
m). The organic-containing silicon oxide film may be formed by the method described in Embodiment Mode 2 or 3. Or,
The porous silicon layer described in Embodiment Mode 5 may be used. Then, similarly to the first insulating layer 602, the second insulating layer 604 is formed using a silicon oxide film or a silicon oxynitride film.
It is formed with a thickness of 0 to 100 nm.

Next, 10 to 100 nm (preferably 30 to 100 nm)
Semiconductor film 605 having a thickness of 60 nm and having an amorphous structure
Is formed by a known method such as a plasma CVD method or a sputtering method. Typically, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. Further, the second insulating film 604 and the amorphous silicon film 605 can be formed continuously. For example, after forming a silicon oxynitride film as described above, the reaction gas is changed from SiH ₄ , N ₂ O, H ₂ to Si.
If only H ₄ and H ₂ or only SiH ₄ are used, they can be formed continuously without exposure to the atmosphere. As a result, it is possible to prevent contamination at this interface, and to fabricate the TFT
And variations in threshold voltage can be reduced.

The crystallization step shown in FIG. 6B is performed by a laser crystallization method. A gas laser typified by a pulse oscillation type excimer laser, or a solid laser typified by a YAG laser or a YVO ₄ laser is used. In the case of using these lasers, a method in which laser light emitted from a laser oscillator is condensed into a linear shape, a rectangular shape, or a rectangular shape by an optical system, and the semiconductor film is irradiated with the light is preferably used. Laser irradiation conditions for the amorphous semiconductor film are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 30 Hz, and the laser energy density is set to 100 to 400 mJ / cm2 (typically 200 to 400 mJ / cm2). ~ 3
00mJ / cm2). When a YAG laser is used, its second harmonic is used to generate a pulse oscillation frequency of 1 to 10.
kHz and laser energy density between 300 and 600
mJ / cm2 (typically 350 to 500 mJ / cm2) is good. And a width of 100 to 1000 μm, for example 400 μm
The laser beam condensed linearly is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is set to 80 to 98%.

The crystalline semiconductor film 607 manufactured by the laser crystallization method has a polycrystalline structure in which a plurality of crystal grains are gathered. However, due to the effect of the provision of the heat insulating layer 603, each of the crystal grains has a large grain size.
The first embodiment may be referred to for the mechanism. In any case, in the transitional process of melting and cooling the semiconductor film by the irradiation of the pulse laser beam, the cooling process is made slow by providing the heat insulating layer 603, so that the crystalline silicon film having a large grain size is obtained. Can be obtained.

Then, as shown in FIG. 6C, a resist pattern is formed by a light exposure process, the crystalline semiconductor film 607 is divided into islands by dry etching, and island-like semiconductor films 608 to 611 are formed. . For dry etching, a mixed gas of CF ₄ and O ₂ is used. The gate insulating film 612 is formed using a plasma CVD method or a sputtering method with a thickness of 40 to 200 nm and containing silicon. A silicon oxynitride film formed from a mixed gas of SiH ₄ and N ₂ O by a plasma CVD method is a material suitable for a gate insulating film, and is formed to a thickness of 80 nm to form a gate insulating film. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, plasma CVD
TEOS and O ₂ are mixed by the method, the reaction pressure is 40 Pa, the substrate temperature is 300-400 ° C., and the high frequency (13.56 MHz)
It can be formed by discharging at a power density of 0.5 to 0.8 W / cm2. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, a first conductive film 613 and a second conductive film 614 for forming a gate electrode are formed over the gate insulating film 612. The gate electrode of the TFT described in this embodiment is formed in a two-layer structure, and the first conductive film 613 is formed of a tantalum nitride (hereinafter, referred to as TaN) film of 50 to 10 nm.
The second conductive film 614 is formed with a thickness of 100 to 300 nm using a tungsten (W) film.

The TaN film is an excellent material having high thermal stability, considering that heat treatment will be performed in a later step. W
The film is formed by a sputtering method using W as a target. Thermal CVD using tungsten hexafluoride (WF ₆ )
It can also be formed by a method. In any case, it is necessary to reduce the resistance in order to use it as a gate electrode. W
The resistivity of the film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. A W target having a purity of 99.9999% is used, and a W film is formed with sufficient care so as not to mix impurities from the gas phase during film formation, thereby realizing a resistivity of 9 to 20 μΩcm. can do.

Next, as shown in FIG. 7A, a mask 615 made of a resist is formed and a first etching process is performed. There is no limitation on the etching method, but preferably ICP
(Inductively Coupled Plasma)
An etching device is used. CF ₄ for etching gas
And Cl ₂ at a pressure of 0.5 to ₂ Pa, preferably 1 Pa, and an RF (13.56 MHz) power of 500 W is applied to the coil-type electrode to generate plasma and perform etching. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and the operation is performed in a state where a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film can be etched at the same speed.

In the first etching treatment, the first conductive layer and the second conductive layer are processed so that the end portions have a tapered shape. The angle of the tapered portion is 15 to 45 °. However, in order to perform etching without leaving any residue on the gate insulating film, an over-etching process in which the etching time is increased by about 10 to 20% is preferably performed. W
Since the selectivity of the silicon oxynitride film to the film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. Thus, by the first etching process, the first shape conductive layers 616 to 620 (the first conductive layers 616 a to 616) including the first conductive layer and the second conductive layer are formed.
0a and the second conductive layers 616b to 620b).

Next, a second etching process is performed as shown in FIG. Using an ICP etching apparatus, CF ₄ , Cl _2, and O ₂ are mixed in an etching gas, and RF power (13.56 MHz) of 500 W is supplied to the coil-type electrode at a pressure of 1 Pa to generate plasma. An RF (13.56 MHz) power of 50 W is applied to the substrate side (sample stage) so that the self-bias voltage is lower than that in the first etching process. Under such conditions, the W film is anisotropically etched,
In addition, the TaN film is anisotropically etched at a lower etching rate to form second shape conductive layers 621 to 625 (first conductive layers 621a to 625a and second conductive layers 621b to 621b).
625b). 626 is a gate insulating film,
Regions that are not covered by the second shape conductive layers 621 to 625 are thinned by approximately 40 to 80 nm by the first etching process and the second etching process.

An n-channel TFT and a p-channel TFT
The FT impurity region is formed in a self-aligned manner using the second shape conductive layer. Two types of impurity regions having different concentrations are formed in the n-channel TFT. FIG. 7 (C)
Is formed by adding an impurity element imparting n-type in a first doping process (a condition of a high acceleration voltage and a low dose) to form a first impurity region 62 overlapping with the first conductive layers 621a to 625a.
7 shows a step of forming 7 to 630. In this case, the second impurity region 6 is located outside the first impurity regions 627 to 630.
31 to 634 are formed. The doping method is
This is performed by an ion doping method or an ion implantation method. The impurity element imparting n-type is an element belonging to Group 15 of the periodic table, and typically uses phosphorus (P) or arsenic (As). The concentration of the added impurity element is set to 2 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ in the first impurity region.
In the second impurity region, 1 × 10 ^{17 to} 5 ×
It should be 10 ¹⁸ / cm ³ .

Next, as shown in FIG.
A mask 635 is formed. This mask is a pixel TFT
And n-channel TFT of the sampling circuit in the driving circuit
Is formed in order to determine the source and drain regions.
The second doping process is an n-channel TFT of a driving circuit.
To form a third impurity region 636. Third
Impurity imparting n-type added to impurity region 636
Element concentration is 5 × 10 ¹⁷~ 5 × 10¹⁹/cm^ThreeSo that
I do. Further, a third doping process is performed to add an n-type.
The impurity element to be given is 1 × 10²⁰~ 1 × 10^{twenty one}/cm^ThreeBy concentration
Forming fourth impurity regions 637 to 639 to be added;
You.

As shown in FIG. 8B, the formation of the impurity region for the p-channel TFT is performed by using a resist mask 6.
40 is formed so as to protect a region where an n-channel TFT is formed, and a fifth impurity region 641 to which an impurity element imparting p-type is added by a fourth doping process is formed.
642. The impurity element imparting p-type is an element belonging to Group 13 of the periodic table, and typically boron (B) is used.

As shown in FIG. 8C, a first interlayer insulating film 463 is formed on the gate electrode and the gate insulating film. The first interlayer insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first interlayer insulating film 643 is formed from an inorganic insulating material, and 5 to 3
0 atomic%, preferably 15 to 25 atomic% of hydrogen is preferably contained. The thickness of the first interlayer insulating film 643 is 10
0 to 200 nm. When a silicon oxide film is used, TEOS and O ₂ are mixed by a plasma CVD method,
It is formed by discharging at a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm 2. In the case of using a silicon oxynitride film, a silicon oxynitride film formed from SiH ₄ , N ₂ O, and NH ₃ by a plasma CVD method or a silicon oxynitride film formed from SiH ₄ and N ₂ O is used. Good. The manufacturing conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² . Also,
SiH4, N ₂ O, may be applied hydrogenated silicon oxynitride film formed from H _2. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method.

Thereafter, a step of activating the n-type or p-type impurity element added at each concentration is performed. In this step, heat treatment may be performed using a furnace annealing furnace, or may be performed by a laser annealing method. When heat treatment is performed, the oxygen concentration is 400 to 70 ppm in a nitrogen atmosphere of 1 ppm or less, preferably 0.1 ppm or less.
0 ° C., typically at 400 to 550 ° C.,
In this embodiment, heat treatment is performed at 500 ° C. for one hour. By this heat treatment, hydrogen contained in the first interlayer insulating film 643 is diffused into the semiconductor film, and hydrogenation can be performed at the same time. In the case where a plastic substrate having a low heat-resistant temperature is used as the substrate 601, a laser annealing method is preferably applied.

After the heat treatment, 3 to 100
% At 300-450 ° C in an atmosphere containing 1% hydrogen.
The semiconductor film may be hydrogenated by performing heat treatment for up to 12 hours. In any case, the purpose of hydrogenation is to reduce the density by compensating dangling bonds of 10 ¹⁶ to 10 ¹⁸ / cm ^{3 in} the semiconductor film with hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

The second interlayer insulating film 644 is formed using an organic insulating material and has an average thickness of 1.0 to 2.0 μm. Organic resin materials include polyimide, acrylic, polyamide, polyimide amide, and BCB (benzocyclobutene)
Etc. can be used. For example, in the case of using a polyimide of a type which is thermally polymerized after being applied to a substrate, it is formed by firing at 300 ° C. using a clean oven. Also,
In the case of using acrylic, a two-pack type is used, after mixing the main material and the curing agent, applying the whole surface of the substrate using a spinner, and then performing preheating at 80 ° C. for 60 seconds on a hot plate. It can be formed by firing at 250 ° C. for 60 minutes using a clean oven.

As described above, the surface can be satisfactorily planarized by forming the interlayer insulating film with the organic insulating material. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and is not suitable as a protective film, as in this embodiment, a silicon oxide film formed as the protective insulating film 146,
It is necessary to use in combination with a silicon oxynitride film, a silicon nitride film, or the like.

Thereafter, a resist mask having a predetermined pattern is formed by a light exposure process, and a contact hole reaching a source region or a drain region formed in each semiconductor film is formed. The formation of the contact hole is performed by a dry etching method. In this case, the second interlayer insulating film 644 made of organic resin material using a mixed gas of CF _4, O _2, He as an etching gas to etch, then followed by the etching gas as CF _4, O ₂ first The interlayer insulating film 643 is etched. Further, in order to increase the selectivity with the island-like semiconductor film, the etching gas is CHF.
_By switching to ₃ and etching the gate insulating film, a contact hole can be formed favorably.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a resist mask having a predetermined pattern is formed by a light exposure process, and a source wiring and a drain wiring 645 to 651 are formed by etching. 652 formed at the same time functions as a pixel electrode. Although not shown, in this embodiment, this electrode is
An i film is formed to a thickness of 50 to 150 nm, a contact is formed with the semiconductor film forming the source or drain region of the island-shaped semiconductor film, and aluminum (A) is superimposed on the Ti film.
1) is formed in a thickness of 300 to 400 nm to form a wiring.

When heat treatment (sintering) is performed at 300 to 450 ° C. for 1 to 12 hours in this state, a good ohmic contact can be obtained. If this heat treatment is performed in a hydrogen atmosphere, it can also serve as a hydrogenation treatment (FIG. 8).
(C)).

As described above, the TFT of the driving circuit and the pixel TFT of the pixel region are integrally formed by using six photomasks by using the crystalline semiconductor film formed by the laser crystallization method in which the heat insulating layer is provided on the substrate. The completed substrate can be completed. The driver circuit 660 includes a first p-channel TFT 653, a first n-channel TFT 654, a second
The pixel TFT 658 and the storage capacitor 659 are formed in the n-channel TFT 657 and the pixel region 661. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

First p-channel type TF of drive circuit 660
T653 includes a channel formation region 662 and source or drain regions 663 and 664 each including a fifth impurity region.
Is formed in a single drain structure having However, the source or drain region 663 is formed so as to overlap with the first conductive layer 621a.

The first n-channel TFT 654 includes a channel formation region 665 and a second conductive layer 62 serving as a gate electrode.
There is a third impurity region 666 overlapping with 2a, and a fourth impurity region 667 formed outside the gate electrode.
The third impurity region 666 is an LDD (Lightly Doped Drai).
n) a region, and the fourth impurity region 667 is a region functioning as a source region or a drain region. In particular,
The third impurity region 666 is an LDD region overlapping with the gate electrode (such an LDD region is referred to as Lov), and is also called a GOLD (Gate Overlapped Drain) structure. Thus, deterioration of the TFT due to the hot carrier effect can be prevented, and extremely stable operation can be obtained even when a high voltage of 10 V or more is applied.

The second n-channel TFT 657 includes a channel forming region 668, a first impurity region 669 overlapping with the second conductive layer 623a serving as a gate electrode, and a second impurity region formed outside the gate electrode. 670 and a fourth impurity region 671. First impurity region 66
Reference numeral 9 denotes Lov, which prevents TFT deterioration due to the hot carrier effect. The second impurity region 670 is an LDD region which does not overlap with the gate electrode (such an LDD region is referred to as Loff), and has an effect of reducing off current.

The pixel TFT 658 includes a channel formation region 672, a first impurity region 673, and a second impurity region 6.
74, and a fourth impurity region 675. FIG.
(C) shows the pixel TFT 658 with a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes. Further, a capacitor wiring 625, an insulating film made of the same material as the gate insulating film, and semiconductor films 678 and 679 (n is 679 in 679)
(An impurity element imparting a mold is added) to form a storage capacitor 659.

The first to fourth impurity regions are doped with an impurity element imparting n-type. 2 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ for the first impurity region, 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^{3 for} the second impurity region, 5 × 10 ¹⁸ / cm ³ for the third impurity region ^An impurity element is added at a concentration of ^{17 to} 5 × 10 ¹⁹ / cm ³ and a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ to the fourth impurity region. The fifth impurity region is doped with an impurity element imparting p-type, and is 1.5 to 3 times larger than the fourth impurity region.
The impurity element is added at twice the concentration.

The first and third impurity regions are L
ov, and the length in the channel length direction is 0.5 to 3 μm, preferably 0.5 to 1.5 μm. The difference between the concentrations of the impurity elements to be added in the two impurity regions is that the former is formed at the lowest possible concentration in consideration of the reduction of off-current, while the latter is for improving the current driving capability. This is due to the emphasis on on-current. The second impurity region is Loff and has a length in the channel length direction of 0.5 to 3 μm, preferably 1.0 to 1.5 μm.
Formed.

The first p-channel TFT 653 and the first
The n-channel TFT 654 forms a shift register circuit, a buffer circuit, and the like. Second n-channel TFT
657 is applied to a sampling circuit. As described above, the structure of the TFT can be optimized in accordance with the specifications required by each circuit formed on the active matrix substrate, and the operation performance and reliability can be improved.

FIG. 9 is a top view showing almost one pixel of the pixel portion. The cross section AA ′ shown in the drawing corresponds to the cross-sectional view of the pixel portion shown in FIG. The gate electrode 624 of the pixel TFT 658 intersects the underlying island-shaped semiconductor film 611 via a gate insulating film (not shown). Although not shown, the island-shaped semiconductor film 611 includes a source region,
A drain region and an LDD region are formed. Also, 6
70 is a contact portion between the source wiring 651 and the source region, and 671 is a contact portion between the pixel electrode 652 and the drain region. The storage capacitor 659 is formed in a region where a capacitor wiring 625 overlaps with a semiconductor film extending from a drain region of the pixel TFT 658 and a gate insulating film. The structure shown here is an active matrix substrate in which the pixel electrode 652 is formed using the same material as the source wiring and the drain wiring, that is, the active matrix substrate can be applied to a reflective display device.

Embodiment 2 The active matrix substrate manufactured in Embodiment 1 can be applied to a reflection type display device. On the other hand, in the case of a transmissive liquid crystal display device, a pixel electrode provided for each pixel in the pixel portion may be formed of a transparent electrode. In this embodiment, a method for manufacturing an active matrix substrate corresponding to a transmission type liquid crystal display device will be described with reference to FIGS.

The active matrix substrate is manufactured in the same manner as in the first embodiment. However, before forming a source wiring and a drain wiring, a transparent conductive film is formed over the second interlayer insulating film 644 and a pixel electrode 680 is formed. After that, a source wiring 681 and a drain wiring 682 are formed. The drain wiring 682 overlaps with the pixel electrode 680 to form a contact portion. As an example of the source wiring and the drain wiring, a Ti film is formed with a thickness of 50 to 150 nm, a contact is formed with the semiconductor film forming the source or drain region of the island-shaped semiconductor film, and an Al film is formed on the Ti film. 30
It is formed and provided with a thickness of 0 to 400 nm. With this configuration, the pixel electrode 680 is connected to the T
It comes into contact with only the i film. As a result, it is possible to prevent the reaction between the transparent conductive film material and Al.

The material of the transparent conductive film is indium oxide (I
n ₂ O ₃ ) and indium tin oxide alloy (In ₂ O ₃ —S
nO ₂ ; ITO) or the like can be formed by a sputtering method, a vacuum evaporation method, or the like. The etching of such a material is performed using a hydrochloric acid-based solution. However, in particular, since etching of ITO easily generates residues, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used in order to improve the etching processability. Since the indium oxide zinc oxide alloy has excellent surface smoothness and excellent thermal stability with respect to ITO, it is possible to prevent a corrosion reaction with Al contacting at the end face of the drain wiring 169. Similarly,
Zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to increase the transmittance and conductivity of visible light can be used.

Thus, an active matrix substrate corresponding to a transmission type liquid crystal display device can be completed. In the present embodiment, steps similar to those in the first embodiment have been described. However, such a configuration can be applied to the active matrix substrates described in the second and third embodiments.

[Embodiment 3] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 or Embodiment 2 will be described. As shown in FIG. 10, a spacer composed of a columnar spacer is formed on the active matrix substrate in the state of FIG. 8C. The spacer may be provided by scattering particles of several μm, but here, a method of forming a resin film over the entire surface of the substrate and then patterning the resin film is adopted. Although the material of such a spacer is not limited, for example, JSR
After applying by a spinner using NN700 manufactured by KK, a predetermined pattern is formed by exposure and development. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The shape of the spacer manufactured in this manner can be varied depending on the conditions of the exposure and the development processing. However, it is preferable that the shape of the columnar spacers 701 and 702 is columnar and the top is flat. When the substrates on the side are aligned, mechanical strength as a liquid crystal display device can be secured. The shape is not particularly limited, such as a conical shape or a pyramid shape. However, the height depends on the liquid crystal material used, and is 3 to 8 μm for a nematic liquid crystal, and 1 to 4 μm for a smectic liquid crystal.

The arrangement of the columnar spacers may be determined arbitrarily. Preferably, as shown in FIG. 10, in the pixel region, the columnar spacers 701 are overlapped with the contact portions 671 of the pixel electrodes 652 so as to cover the portions. It is good to form. Since the flatness of the contact portion 671 is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 701 is formed in such a manner that the contact portion 671 is filled with the resin for the spacer so that disclination and the like can be performed. Can be prevented.

After that, an alignment film 703 is formed. A polyimide resin is used for the alignment film. After forming the alignment film, a rubbing treatment is performed so that the liquid crystal molecules are aligned with a certain pretilt angle. The area not rubbed in the rubbing direction from the end of the columnar spacer 701 provided in the pixel area is set to 2 μm or less. In addition, generation of static electricity often becomes a problem in the rubbing process. However, if the columnar spacer 702 is formed on the TFT of the driving circuit, the original role as the spacer and the TF from the static electricity are reduced.
The effect of protecting T can be obtained.

On the opposite substrate 704 on the opposite side, an opposite electrode 705 and an alignment film 706 formed of a transparent conductive film are formed. Then, the active matrix substrate on which the pixel region and the driving circuit are formed and the counter substrate are bonded with a sealant (not shown). Then, a liquid crystal 707 is placed between the two substrates.
And completely sealed with a sealing material (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 10 is completed.

FIG. 12 is a top view of an active matrix substrate on which spacers and a sealant are formed, and is a top view showing the positional relationship between the pixel portion and the drive circuit portion, the spacers, and the sealant. A scanning signal drive circuit 885 and an image signal drive circuit 886 are provided as drive circuits around the pixel region 888. Further, a signal processing circuit 887 such as a CPU or a memory may be added. These drive circuits are connected to an external input / output terminal 882 by a connection wiring 883. In the pixel portion 888, a gate wiring group 889 extending from the scanning signal driving circuit 885 and a source wiring group 890 extending from the image signal driving circuit 886 intersect in a matrix to form a pixel. The pixel TFT 658 and the storage capacitor 65 shown in FIG.
9 are provided.

The columnar spacer 701 provided in the pixel region is
It may be provided for all pixels, or may be provided every few to several tens of pixels arranged in a matrix. That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion is preferably 20 to 100%. Further, the spacer 702 provided in the driver circuit portion may be provided so as to cover the entire surface thereof, or may be provided in a plurality of pieces in accordance with the positions of the source and drain wirings of each TFT as shown in FIG. good. The sealant 879 is formed outside the pixel portion 888 and the scanning signal control circuit 885, the image signal control circuit 886, and other signal processing circuits 887 on the substrate 101 and inside the external input / output terminal 882.

The structure of such an active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. FIG.
3, the active matrix substrate includes a pixel portion 888 and a scan signal driving circuit 88 formed on the substrate 101.
5, an image signal drive circuit 886 and other signal processing circuits 887. The pixel portion 888 includes a pixel TFT 6
58 and a storage capacitor 659 are provided, and a driving circuit provided around the pixel portion is configured based on a CMOS circuit. Scanning signal drive circuit 885 and image signal drive circuit 8
Reference numeral 86 denotes a gate wiring 624 and a source wiring 651, which are connected to the pixel TFT 658, respectively. Also, Flexible Printed Circuit (FPC)
Reference numeral 891 is connected to the external input terminal 882 and used to input an image signal or the like. The connection wiring 883 is connected to each drive circuit. In addition, the opposite substrate 704
Although not shown, a light-shielding film and a transparent electrode are provided.

The liquid crystal display device having such a structure can be formed by using the active matrix substrates shown in the first and second embodiments. A reflective liquid crystal display device can be obtained by using the active matrix substrate described in Embodiment 1, and a transmissive liquid crystal display device can be obtained by using the active matrix substrate described in Embodiment 2.

[Embodiment 4] In this embodiment, a self-luminous display panel (hereinafter, referred to as an EL display device) using an active matrix substrate similar to that of the first embodiment and using an electroluminescence (EL) material is used. ) Will be described. FIG. 16A shows a top view of the EL display panel. In FIG. 16A, reference numeral 10 denotes a substrate, 11 denotes a pixel portion, 12 denotes a source-side drive circuit, 13 denotes a gate-side drive circuit, and each drive circuit has a wiring
Through 4 to 16, the FPC 17 is reached and connected to an external device.

FIG. 16B is a sectional view taken along the line AA ′ in FIG. At this time, the opposing plate 8 is provided at least above the pixel portion, preferably above the driving circuit and the pixel portion.
0 is provided. Opposite plate 80 is made of TFT and EL with sealing material 19.
It is bonded to an active matrix substrate on which a self-light emitting layer using a material is formed. A filler (not shown) is mixed in the sealant 19, and the two substrates are bonded with a substantially uniform interval by the filler. Further, the outside of the seal member 19 and the upper surface and the periphery of the FPC 17 are sealed with a sealant 81. The sealant 81 uses a material such as a silicone resin, an epoxy resin, a phenol resin, and butyl rubber.

As described above, when the active matrix substrate 10 and the counter substrate 80 are bonded together by the sealant 19, a space is formed therebetween. The space is filled with a filler 83. The filler 83 also has the effect of bonding the opposing plate 80. Filler 83 is made of PVC (polyvinyl chloride), epoxy resin, silicone resin, P
VB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In addition, since the self-luminous layer is weak to moisture and easily deteriorates, it is desirable to mix a desiccant such as barium oxide into the filler 83 because a moisture absorbing effect can be maintained. In addition, a passivation film 82 formed of a silicon nitride film, a silicon oxynitride film, or the like is formed over the self-luminous layer to prevent corrosion due to an alkali element or the like contained in the filler 83.

A glass plate, an aluminum plate, a stainless steel plate, FRP (Fiberglass-Reinforced Pl)
astics) plate, PVF (polyvinyl fluoride) film, mylar film (trade name of DuPont), polyester film, acrylic film or acrylic plate. Further, moisture resistance can be enhanced by using a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or mylar films. In this way, the EL element is in a sealed state and is isolated from the outside air.

In FIG. 16B, a TFT for a driving circuit (here, a C-type TFT combining an n-channel TFT and a p-channel TFT) is formed on the substrate 10 and the base film 21.
2 illustrates a MOS circuit. 22) and TFT for pixel portion
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
Among the FTs, an n-channel TFT, in particular, an LDD region having the configuration shown in this embodiment is provided in order to prevent a decrease in on-current due to a hot carrier effect and a decrease in characteristics due to a Vth shift or bias stress.

For example, a p-channel TFT 653 and an n-channel TFT 654 shown in FIG. 8C may be used as the driver circuit TFT 22. Also, the TFT of the pixel part
FIG. 8 shows that if the voltage is 10 V or more,
A first n-channel TFT 654 shown in FIG. 7C or a p-channel TFT having a structure similar to that may be used. The first n-channel TFT 654 has a structure in which an LDD overlapping the gate electrode is provided on the drain side. However, if the driving voltage is 10 V or less, deterioration of the TFT due to the hot carrier effect can be almost ignored.
There is no need to set it.

In order to manufacture an EL display device from the active matrix substrate in the state shown in FIG. 8C, an interlayer insulating film (planarization film) made of a resin material is formed on the source wiring and the drain wiring.
26, and a pixel electrode 27 made of a transparent conductive film electrically connected to the drain of the pixel portion TFT 23 is formed thereon. For the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 27 is formed, an insulating film 28 is formed, and an opening is formed on the pixel electrode 27.

Next, a self-luminous layer 29 is formed. The self-luminous layer 29 may have a laminated structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials. When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

The self-luminous layer is formed using a shadow mask by an evaporation method, an inkjet method, a dispenser method, or the like. In any case, a color display is possible by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the self-luminous layer 29, the cathode 30 is formed thereon. It is desirable to remove moisture and oxygen existing at the interface between the cathode 30 and the self-luminous layer 29 as much as possible. Therefore, it is necessary to devise a method in which the self-luminous layer 29 and the cathode 30 are continuously formed in a vacuum, or the self-luminous layer 29 is formed in an inert atmosphere and the cathode 30 is formed in a vacuum without opening to the atmosphere. . In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 30 is made of Li
A laminated structure of an F (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1 nm-thick LiF (lithium fluoride) film is formed on the self-luminous layer 29 by a vapor deposition method, and a 300 nm-thick aluminum film is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via an anisotropic conductive paste material 32. A resin layer 80 is further formed on the FPC 17 to increase the adhesive strength at this portion.

In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, contact holes need to be formed in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming a contact hole for a pixel electrode) or at the time of etching the insulating film 28 (at the time of forming an opening before forming a self-luminous layer). Further, when the insulating film 28 is etched, the etching may be performed all at once up to the interlayer insulating film 26. In this case, if the interlayer insulating film 26 and the insulating film 28 are made of the same resin material, the shape of the contact hole can be made good.

The wiring 16 is composed of the seal 19 and the substrate 10.
Is electrically connected to the FPC 17 through a gap (but closed with a sealant 81). Although the wiring 16 has been described here, the other wirings 14 and 15 are also electrically connected to the FPC 17 under the sealing material 18 in the same manner.

FIG. 17 shows a more detailed sectional structure of the pixel portion, FIG. 18A shows a top structure thereof, and FIG.
It is shown in (B). In FIG. 17A, a switching TFT 2402 provided over a substrate 2401 has the same structure as the pixel TFT 149 of FIG. The double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off current value can be reduced by forming an LDD provided with an offset region that does not overlap with the gate electrode. . In this embodiment, a double gate structure is used, but a triple gate structure or a multi-gate structure having more gates may be used.

Further, the current controlling TFT 2403 corresponds to FIG.
It is formed using a first n-channel TFT 654 shown in FIG. This TFT structure is a structure in which an LDD that overlaps with a gate electrode is provided only on the drain side, and has a structure in which a parasitic capacitance between gate and drain and a series resistance are reduced to increase current driving capability. From another point of view, being a structure is very important. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, by providing the current control TFT with an LDD region that partially overlaps the gate electrode, deterioration of the TFT is prevented,
Operation stability can be improved. At this time, the drain line 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. A wiring indicated by 38 is a gate line that electrically connects the gate electrodes 39a and 39b of the switching TFT 2402.

In this embodiment, the current control TFT 24
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 18A, the wiring which becomes the gate electrode 37 of the current controlling TFT 2403 has 24 wirings.
In a region indicated by 04, the region overlaps with the drain line 40 of the current control TFT 2403 via an insulating film. At this time, 24
In a region indicated by 04, a capacitor is formed. The capacitor 2404 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 2403. The drain line 40 is a current supply line (power supply line) 2
501, a constant voltage is always applied.

The first passivation film 4 is formed on the switching TFT 2402 and the current control TFT 2403.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since a self-light-emitting layer formed later is very thin, poor light emission may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the self-luminous layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
403 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed. A groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin).
The light emitting layer 44 is formed in the inside. Although only one pixel is shown here, R (red), G (green), B (blue)
The light emitting layers corresponding to the respective colors may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.
There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Gelsen, E. Klug
e, W. Kreuder, and H. Spreitzer, “Polymers for Light
Emitting Diodes ”, Euro Display, Proceedings, 1999,
p.33-37 "and a material described in JP-A-10-92576 may be used.

As a specific light emitting layer, cyanopolyphenylene vinylene is used for a light emitting layer emitting red light, polyphenylene vinylene is used for a light emitting layer emitting green light, and polyphenylene vinylene or polyalkylphenylene is used for a light emitting layer emitting blue light. Good. Thickness is 30-150nm
(Preferably 40 to 100 nm). However, the above example is an example of an organic EL material that can be used as a light emitting layer, and there is no need to limit the invention to this.
The light-emitting layer, the charge transport layer, or the charge injection layer may be freely combined to form a self-light-emitting layer (a layer for emitting light and moving carriers therefor). For example, in this embodiment, an example in which a polymer material is used for the light emitting layer is shown, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
This is a self-luminous layer having a laminated structure provided with a hole injection layer 46 made of (polythiophene) or PAni (polyaniline). An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, the light emitting layer 45
Since the light generated in step (1) is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the self-luminous element 2405 is completed. The EL element 240 referred to here
Reference numeral 5 denotes a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. FIG.
As shown in FIG. 8A, the pixel electrode 43 substantially matches the area of the pixel, so that the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 18, and has a switching TFT having a sufficiently low off-state current value and a current control portion having a high resistance to hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

FIG. 17B shows an example in which the structure of the light emitting layer is inverted. The current controlling TFT 2601 has the same structure as the p-channel TFT 653 in FIG. Embodiment 1 can be referred to for the manufacturing process. In this embodiment,
A transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 2602 is formed. In the case of this embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed as indicated by the arrow. In the case of the structure as in this embodiment, it is preferable that the current control TFT 2601 be formed of a p-channel TFT.

The EL display device described in this embodiment as described above can be used as the display unit of the electronic device of the sixth embodiment.

[Embodiment 5] In this embodiment, FIG. 19 shows an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. 18B is used. In this embodiment, 2701
270 is the source wiring of the switching TFT 2702, 270
3 is a gate wiring of the switching TFT 2702, 27
04 is a current control TFT, 2705 is a capacitor, 27
Reference numerals 06 and 2708 denote current supply lines, and 2707 denotes an EL element.

FIG. 19A shows an example in which the current supply line 2706 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 2706. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 19B shows a current supply line 270.
8 is provided in parallel with the gate wiring 2703. Note that in FIG. 19B, the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other; It can also be provided as follows. In this case, since the power supply line 2708 and the gate wiring 2703 can share an occupied area, the pixel portion can have higher definition.

FIG. 19C shows that a current supply line 2708 is provided in parallel with the gate wiring 2703 and two pixels are connected to the current supply line 2708 in the same manner as in the structure of FIG.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 2708 so as to overlap with one of the gate wirings 2703. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition. FIG.
19A and 19B, a capacitor 270 is used to hold the voltage applied to the gate of the current controlling TFT 2704.
5, but the capacitor 2705 can be omitted.

As the current controlling TFT 2704, FIG.
Since an n-channel TFT as shown in FIG. 1A is used, an LDD region is provided so as to overlap a gate electrode with a gate insulating film interposed therebetween. In this overlapping region, a parasitic capacitance generally called a gate capacitance is formed.
The feature is that it is actively used instead of 5. Since the capacitance of the parasitic capacitance changes in the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.
In the structure shown in FIGS. 19A, 19B, and 19C, the capacitor 2705 can be omitted.

Note that the circuit configuration of the EL display device shown in this embodiment is selected from the TFT configuration shown in Embodiment Mode 1 and shown in FIG.
9 may be formed. In addition, the EL display panel of this embodiment can be used as the display unit of the electronic device of the seventh embodiment.

[Embodiment 6] An active matrix substrate in which a pixel portion and a driving circuit manufactured by carrying out the present invention are integrally formed on the same substrate can be used in various electro-optical devices (active matrix liquid crystal display devices, active matrix (A matrix type EL display device, an active matrix type EC display device). That is, the present invention can be applied to all electronic devices incorporating these electro-optical devices as display media.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a personal computer, a television, a mobile phone, and an electronic book. Examples of these are shown in FIGS.

FIG. 20A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention can be applied to the display device 9004 including the active matrix substrate.

FIG. 20B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention can be applied to the display device 9102 including the active matrix substrate.

FIG. 20C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display device 9205. The present invention can be applied to the display device 9205 including the active matrix substrate.

FIG. 20D shows a goggle type display, which includes a main body 9301, a display device 9302, and an arm 93.
03. The invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 20E shows a portable book, and a main body 95.
01, a display device 9503, a storage medium 9504, operation switches 9505, and an antenna 9506,
Data stored on a mini disk (MD) or DVD,
This is for displaying the data received by the antenna. In the present invention, the display device 9503 can be applied to a direct-view display device.

FIG. 21A shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Di
Gital Versatile Disc), CDs, etc., can be used for music appreciation, movie appreciation, games, and the Internet.
The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 21B shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103.

FIG. 21C shows a personal computer, which includes a main body 9601, an image input section 9602, and a display device 9.
603, a keyboard 9604 and the like.
The present invention can be applied to the display device 9603.

FIG. 22A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 22B shows a rear projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 22C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 22A and 22B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 22D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 22C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 22D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 22, a case in which a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using a configuration including any combination of the first to fifth embodiments.

[0140]

As described above, the field effect mobility of a TFT greatly depends on the number of crystal boundaries in a channel formation region. In order to improve the field effect mobility, the number of crystal grain boundaries may be reduced. The laser crystallization method of the present invention realizes a large crystal grain by controlling a temperature change in a crystal growth process by a heat insulating layer. Therefore, by using such a crystalline semiconductor film, the number of crystal grain boundaries existing in the channel formation region can be reduced stochastically. As a result, the field effect mobility of the TFT can be improved, and the performance of a liquid crystal display device or an EL display device manufactured using the TFT can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the concept of the laser crystallization method of the present invention.

FIG. 2 illustrates a concept of a laser crystallization method using a linear laser beam.

FIG. 3 illustrates a configuration of a laser device.

FIG. 4 is a diagram illustrating a laser crystallization method of the present invention using an organic-containing silicon oxide film as a heat insulating layer.

FIG. 5 illustrates a method for manufacturing an organic-containing silicon oxide film by a liquid phase method.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 9 is a top view illustrating pixels in a pixel region.

FIG. 10 is a cross-sectional view illustrating a structure of a liquid crystal display device.

FIG. 11 is a diagram illustrating a laser crystallization method of the present invention in which a heat insulating layer is formed of porous silicon.

FIG. 12 is a top view illustrating input terminals, wiring, circuit arrangement, spacers, and sealants of a liquid crystal display device.

FIG. 13 is a perspective view illustrating a structure of a liquid crystal display device.

FIG. 14 is a cross-sectional view illustrating a structure of a pixel in a transmissive liquid crystal display device.

FIG. 15 illustrates a configuration of a laser device.

16A and 16B are a top view and a cross-sectional view illustrating a structure of an EL display device.

FIG. 17 is a cross-sectional view of a pixel portion of an EL display device.

18A and 18B are a top view and a circuit diagram of a pixel portion of an EL display device.

FIG. 19 is an example of a circuit diagram of a pixel portion of an EL display device.

FIG. 20 illustrates an example of a semiconductor device.

FIG. 21 illustrates an example of a semiconductor device.

FIG. 22 illustrates an example of a projector.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) GG15 GG25 GG43 GG45 HJ01 HJ12 HJ13 HJ23 HL03 HL04 HL11 HL22 HL23 HL27 HM15 NN03 NN04 NN22 NN23 NN24 NN27 NN35 NN36 NN72 NN78 PP03 PP04 QQ09 QQ11 QQ23 QQ24 QQ25

Claims (17)

[Claims] An insulating layer formed on an insulating surface, a first insulating film formed on the insulating layer, and a semiconductor film having a crystal structure formed on the first insulating film. The heat insulation layer has an ethyl (C ₂ H ₅ ) group, propyl (C ₃ H ₈ )
A semiconductor device comprising a silicon oxide containing any one of a group, a butyl (C ₄ H ₁₀ ) group, a vinyl (C ₂ H ₂ ) group, a phenyl (C ₆ H ₅ ) group, and a CF ₃ group. 2. A semiconductor device comprising: a heat insulating layer formed on a substrate; a first insulating film formed on the heat insulating layer; and a semiconductor film having a crystal structure formed on the first insulating film. The heat insulating layer is made of porous silicon. 3. A first n-channel TFT and a second n-channel TFT on a substrate.
In the semiconductor device in which the n-channel TFT is formed, the first n-channel TFT has a first semiconductor film and a first gate electrode, and overlaps with the first gate electrode to form one conductivity type. A first impurity region to which an impurity element is added, and a second impurity region provided outside the first gate electrode and in contact with the first impurity region and to which an impurity element of one conductivity type is added. The second n-channel TFT has a second semiconductor film and a second gate electrode, and overlaps with the second gate electrode and has a third conductivity type added with an impurity element of one conductivity type. An impurity region, wherein the first gate electrode and the second gate electrode are formed of a first conductive film and a second conductive film formed inside the first conductive film; A first semiconductor film and a second semiconductor film,
A semiconductor device, wherein a heat insulating layer is formed between the semiconductor device and the substrate. 4. The impurity region according to claim 3, wherein the concentration of the impurity element in the second impurity region to which the one conductivity type impurity element is added is equal to that of the first impurity region in which the one conductivity type impurity element is added. A semiconductor device, wherein the concentration of the impurity element is higher than that of the third impurity region to which the one conductivity type impurity element is added. 5. The method according to claim 3, wherein the concentration of the impurity element in the first impurity region to which the impurity element of one conductivity type is added is 2 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ^3. A concentration of the impurity element in the second impurity region to which the impurity element of one conductivity type is added is 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ ;
The concentration of the impurity element in the third impurity region to which the one conductivity type impurity element is added is 5 × 10 ^{17 to} 5 × 10 ¹⁹ / c.
m ³ , and the concentration of the impurity element in the second impurity region to which the one-conductivity-type impurity element is added is the same as that in the first impurity region to which the one-conductivity-type impurity element is added. A semiconductor device which satisfies a relationship higher than the concentration of an element and lower than the concentration of the impurity element in the third impurity region to which the one-conductivity-type impurity element is added. 6. The heat insulating layer according to claim 3, wherein said heat insulating layer is an ethyl (C ₂ H ₅ ) group, a propyl (C ₃ H ₈ ) group, or a butyl (C ₄ H) group.
₁₀ ) group, vinyl (C ₂ H ₂ ) group, phenyl (C ₆ H ₅ ) group,
A semiconductor device comprising silicon oxide containing any one of CF ₃ groups. 7. The semiconductor device according to claim 3, wherein said heat insulating layer is made of porous silicon. 8. The semiconductor device according to claim 3, wherein the first n-channel TFT is provided in a pixel region, and the second n-channel TFT is provided in a driving circuit portion. 9. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a digital still camera, a goggle type display, an electronic book, a DVD player, a television receiver, a personal computer, A semiconductor device, which is one selected from a projector. 10. Ethyl (C ₂ H ₅ ) group, propyl (C ₃ H ₈ ) group, butyl (C ₄ H ₁₀ ) group, vinyl (C ₂
A first step of forming a heat insulating layer made of silicon oxide containing any one of an H ₂ ) group, a phenyl (C ₆ H ₅ ) group, and a CF ₃ group, and forming a first insulating layer on the heat insulating layer A second step of forming a semiconductor film having an amorphous structure on the first insulating layer; and irradiating the semiconductor film having the amorphous structure with laser light to form a crystal structure. And a fourth step of forming a semiconductor film having the following. 11. A first step of forming a heat insulating layer made of porous silicon on a substrate, a second step of forming a first insulating layer on the heat insulating layer, and a step of forming a first insulating layer on the heat insulating layer. Forming a semiconductor film having an amorphous structure, and irradiating the semiconductor film having an amorphous structure with a laser beam to form a semiconductor film having a crystalline structure. A method for manufacturing a semiconductor device, comprising: 12. A method for manufacturing a semiconductor device in which a first n-channel TFT and a second n-channel TFT are formed on a substrate, wherein an ethyl (C ₂ H ₅ ) group, a propyl (C ₃ H ₈ ) group, butyl (C ₄ H ₁₀ ) group, vinyl (C ₂
A first step of forming a heat insulating layer made of silicon oxide containing any one of an H ₂ ) group, a phenyl (C ₆ H ₅ ) group, and a CF ₃ group, and forming a first insulating layer on the heat insulating layer A second step of forming a semiconductor film having an amorphous structure on the first insulating layer; and irradiating the semiconductor film having the amorphous structure with laser light to form a crystal structure. A fourth step of forming a semiconductor film having: a fifth step of forming a first semiconductor film and a second semiconductor film separated into islands from the semiconductor film having the crystal structure; A sixth step of forming a first conductive layer and a second conductive layer overlying the first semiconductor film and the second semiconductor film, and forming the first conductive layer and the second conductive layer A seventh step of forming a plurality of first-shaped conductive layers having a tapered portion at an end by etching; An eighth step of anisotropically etching the first shape conductive layer to form a plurality of second shape conductive layers having a second conductive layer provided inside the first conductive layer; Adding a first conductivity type impurity element to the first semiconductor film to form a first impurity region overlapping the second shape conductive layer and a second impurity region not overlapping the second shape conductive layer; A ninth step of forming an impurity region of the first type; and a step of adding an impurity element of one conductivity type to the second semiconductor film to form a third impurity region overlapping with the conductive layer of the second shape. 10. A method for manufacturing a semiconductor device, comprising: 13. A method for manufacturing a semiconductor device in which a first n-channel TFT and a second n-channel TFT are formed on a substrate, wherein a heat insulating layer made of porous silicon is formed on the substrate. A second step of forming a first insulating layer on the heat insulating layer; a third step of forming a semiconductor film having an amorphous structure on the first insulating layer; A fourth step of irradiating a semiconductor film having a crystalline structure with a laser beam to form a semiconductor film having a crystalline structure, and a first step of separating the semiconductor film having the crystalline structure into islands.
A fifth step of forming a first semiconductor film and a second semiconductor film, and a first step above the first semiconductor film and the second semiconductor film.
A sixth step of laminating the first conductive layer and the second conductive layer, and etching the first conductive layer and the second conductive layer to form a plurality of first layers each having a tapered portion at an end. A seventh step of forming a conductive layer of the first shape; and anisotropically etching the plurality of first shape conductive layers to provide a second conductive layer inside the first conductive layer. An eighth step of forming a plurality of second-shape conductive layers; and a first step of adding an impurity element of one conductivity type to the first semiconductor film to overlap the second-shape conductive layers. A ninth step of forming an impurity region and a second impurity region which does not overlap with the conductive layer of the second shape; and adding an impurity element of one conductivity type to the second semiconductor film, A tenth step of forming a third impurity region overlapping with the conductive layer having the shape of (2). Law. 14. The method according to claim 12, wherein
A concentration of the impurity element in the second impurity region to which the one conductivity type impurity element is added is higher than a concentration of the impurity element in the first impurity region to which the one conductivity type impurity element is added; And forming the third impurity region to which the one-conductivity-type impurity element is added at a lower concentration than the impurity element. 15. The method according to claim 12, wherein
The concentration of the impurity element in the first impurity region to which the one conductivity type impurity element is added is 2 × 10 ¹⁶ to 1 × 10 ¹⁸ / c.
m ³ , the concentration of the impurity element in the second impurity region to which the one conductivity type impurity element is added is 1 × 10 ¹⁷ to
The concentration of the impurity element in the third impurity region to which the impurity element of one conductivity type is added at 5 × 10 ¹⁸ / cm ³ ,
The concentration of the impurity element in the second impurity region to which the impurity element is added at 5 × 10 ^{17 to} 5 × 10 ¹⁹ / cm ³ and the impurity element of the one conductivity type is added, A third impurity region, which is higher than the concentration of the impurity element in the added first impurity region and in which the one-conductivity-type impurity element is added.
A method for forming the impurity region so as to satisfy a relationship lower than the concentration of the impurity element. 16. The method according to claim 12, wherein
The method for manufacturing a semiconductor device, wherein the first n-channel TFT is formed in a pixel region, and the second n-channel TFT is formed in a driver circuit portion. 17. The semiconductor device according to claim 10, wherein the semiconductor device is a mobile phone, a video camera, a digital still camera, a goggle type display,
A method for manufacturing a semiconductor device, which is one selected from an electronic book, a DVD player, a television receiver, a personal computer, and a projector.