JP4986351B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic apparatus in which such an electro-optical device is mounted as a component.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.
[0003]
[Prior art]
Since a thin film transistor (hereinafter referred to as TFT) can be formed on a transparent substrate, application development to an active matrix liquid crystal display (hereinafter referred to as AM-LCD) has been actively promoted. A TFT using a crystalline semiconductor film (typically a crystalline silicon film) has high mobility, so that a high-definition image display can be realized by integrating functional circuits on the same substrate. ing.
[0004]
2. Description of the Related Art In recent years, attention has been focused on a technique for forming a TFT using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface. TFTs are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly urgently developed as switching elements for image display devices.
[0005]
Various applications using such an image display device are expected, but the use for portable devices is attracting attention. Therefore, it has been attempted to form a TFT element on a flexible plastic film.
[0006]
However, since the heat resistance of the plastic film is low, the maximum temperature of the process has to be lowered, and as a result, TFTs having better electrical characteristics cannot be formed than when formed on a glass substrate. Therefore, a high-performance liquid crystal display device using a plastic film has not been realized.
[0007]
The AM-LCD basically includes a pixel portion that displays an image, a gate driver circuit that drives the TFT of each pixel arranged in the pixel portion, and a source driver circuit (or data) that sends an image signal to each TFT. Driver circuit) is formed on the same substrate.
[0008]
In recent years, a system-on-panel in which signal processing circuits such as a signal dividing circuit and a γ correction circuit are provided on the same substrate in addition to the pixel portion and the driver circuit has been proposed.
[0009]
[Problems to be solved by the invention]
The present invention has been made in view of the above problems, and an object thereof is to provide an inexpensive electro-optical device. It is another object of the present invention to provide an electro-optical device that is light and inexpensive by using a thin substrate having flexibility and forming a thin film transistor over the substrate. Furthermore, it is an object to provide an inexpensive electronic device having the display portion.
[0010]
Furthermore, in the present invention, improvements related to the pixel portion are performed. Specifically, it is an object of the present invention to provide an electro-optical device with excellent contrast by forming a storage capacitor that can secure a large capacity without reducing the aperture ratio.
[0011]
[Means for Solving the Problems]
The present invention is characterized in that a substrate having a metal surface is used as an element formation substrate (substrate on which elements such as TFTs are formed), and necessary elements are formed on the substrate having the metal surface to obtain an electro-optical device. It is said. If the substrate having a metal surface is thin, a semiconductor device typified by an electro-optical device that is flexible and lightweight can be obtained.
[0012]
Note that the necessary element refers to a semiconductor element (typically a TFT) used as a pixel switching element in an active matrix electro-optical device.
[0013]
In addition, the storage capacitor in the pixel portion is formed by using the insulating film on the substrate having the metal surface as a dielectric, the substrate having the metal surface, and a drain wiring connected to the semiconductor layer constituting the pixel TFT. Features.
[0014]
The structure of the invention disclosed in this specification is a semiconductor device including a substrate having a metal surface, an insulating film on the substrate having the metal surface, and a pixel portion on the insulating film, The TFT has a wiring connected to the TFT, and the storage capacitor is formed of the substrate having the metal surface, the insulating film, and the wiring.
[0015]
In the above structure, the substrate having a metal surface (referred to as a metal substrate in this specification) is a stainless steel substrate or a substrate having a metal element coated on the substrate surface.
[0016]
In the above structure, the substrate having the metal surface is a heat-resistant metal substrate. Further, the maximum height (R of surface roughness of the substrate having the metal surface) _MAX ) Is 1 μm or less. Moreover, the curvature radius of the convex part which exists in the surface of the board | substrate which has the said metal surface is 1 micrometer or more, It is characterized by the above-mentioned.
[0017]
In the above structure, the stainless steel substrate has a thickness of 10 μm to 30 μm.
[0018]
In the above structure, the insulating film preferably contains silicon, and the film thickness of the insulating film is 50 to 500 nm (preferably 50 to 300 nm).
[0019]
In the above structure, the storage capacitor is formed by a wiring connected to the metal substrate, the insulating film, and a semiconductor layer included in the pixel TFT.
[0020]
In the above structure, the wiring is formed in contact with the insulating film and connected to the pixel electrode.
[0021]
According to another aspect of the invention for realizing the above structure, a first insulating film is formed over a substrate having a metal surface, a semiconductor layer is formed over the first insulating film, and the first insulating film is formed over the semiconductor layer. 2 is formed, a gate electrode is formed on the second insulating film, a third insulating film is formed to cover the semiconductor layer and the gate electrode, and the third insulating film is partially covered And removing a part of the semiconductor layer and a part of the first insulating film, electrically connecting the semiconductor layer and contacting the part of the first insulating film. It is characterized by forming.
[0022]
In the above structure, the wiring is formed to be connected to the semiconductor layer and a part of the first insulating film.
[0023]
In the above structure, the storage capacitor included in the pixel portion is formed of the metal substrate, a part of the first insulating film, and a wiring.
[0024]
In the above structure, the capacity of the storage capacitor can be increased as the first insulating film is thinner. The capacity can also be increased when the area where the first insulating film and the wiring are in contact with each other is large.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a cross-sectional view of a manufacturing process of a pixel TFT and a storage capacitor. Here, a single-gate TFT is manufactured as the pixel TFT. Of course, not only a single gate structure but also a double gate structure or a triple gate structure may be used.
[0026]
First, a metal substrate 11 serving as an element formation substrate is prepared. For example, a stainless steel substrate such as SUS304 or SUS316, a substrate on which a conductive film is formed, or the like can be used as the metal substrate 11. Typically, the conductive film may be a conductive silicon film (for example, a phosphorus-doped silicon film, a boron-doped silicon film, etc.) or a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, a titanium film, etc.) A silicide film obtained by siliciding a metal film or a nitrided nitride film (such as a tantalum nitride film, a tungsten nitride film, or a titanium nitride film) may be used. Moreover, you may laminate | stack combining these freely.
[0027]
Moreover, the roughness of the metal surface irregularities on the metal substrate is 1 μmR. _MAX It is preferable to be flat as follows. Or it is preferable that the surface roughness per 1 mm square of the unevenness | corrugation of the metal surface in a metal substrate will be 1 micrometer. Further, the radius of curvature of the uneven projection is 1 μm or more, preferably 10 μm or more. A known technique for improving the flatness of the metal surface of the metal substrate, for example, a polishing process called CMP (Chemical Mechanical Polishing) may be used.
[0028]
Next, a base insulating film 12 is formed on the metal substrate 11. The base insulating film 12 also functions as a dielectric (first dielectric) of a storage capacitor in the pixel portion. At this time, it is advantageous to use a thin insulating film because a large capacity can be obtained.
[0029]
A semiconductor layer (not shown) serving as an active region of the driver TFT and a semiconductor layer 13 serving as an active region of the pixel TFT are formed on the base insulating film 12.
[0030]
Then, a gate insulating film 14 is formed so as to cover the semiconductor layer. Typically, the thickness of the gate insulating film 14 may be 5 to 150 nm (preferably 10 to 200 nm).
[0031]
Next, a conductive film 15 is formed on the gate insulating film 14. As a material for forming the conductive film 15, a conductive film having heat resistance that can withstand temperatures of 800 to 1150 ° C. (preferably 900 to 1100 ° C.) is used. (Fig. 1 (A))
[0032]
Typically, a conductive silicon film (for example, a phosphorus-doped silicon film or a boron-doped silicon film) or a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, or a titanium film) may be used, and the metal film may be silicided. A silicide film or a nitrided nitride film (such as a tantalum nitride film, a tungsten nitride film, or a titanium nitride film) may be used. Moreover, you may laminate | stack combining these freely.
[0033]
When the metal film is used, it is desirable to have a laminated structure with a silicon film in order to prevent oxidation of the metal film. In terms of preventing oxidation, a structure in which a metal film is covered with an insulating film containing silicon is effective. As the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (also referred to as a silicon nitride oxide film) can be used. Note that a silicon oxynitride film is an insulating film containing oxygen, nitrogen, and silicon at a predetermined ratio.
[0034]
Note that when the conductive film is formed using the above material, an insulating film containing silicon is provided as the uppermost layer during film formation, and the gate wiring pattern may be formed by collectively etching the insulating film containing silicon and the above material. it can. In this case, only the upper surface of the gate wiring is protected by the insulating film containing silicon.
[0035]
Subsequently, patterning is performed to form the gate electrode 16. Note that in this specification, an “electrode” is a part of “wiring” and refers to a portion where electrical connection with another wiring is performed or a portion intersecting with a semiconductor layer. Therefore, for convenience of explanation, “wiring” and “electrode” are properly used, but it is assumed that “electrode” is always included in the term “wiring”.
[0036]
Next, doping is performed to add an impurity element to the semiconductor layer. (FIG. 1B) The doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁵ / Cm ² And an acceleration voltage of 5 to 100 keV. In this case, the conductive layer 16 serves as a mask for the impurity element, and the impurity regions 18 and 19 are formed in a self-aligning manner.
[0037]
Note that before performing the doping treatment, the gate insulating film may be partially etched using the gate electrode as a mask to partially expose the semiconductor layer. By doing so, an impurity element can be easily added to the semiconductor film, and the addition amount can be reduced.
[0038]
Then, the impurity element is activated by heat treatment. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace, a rapid thermal annealing method (RTA method) or a laser annealing method.
[0039]
Next, the first interlayer insulating film 20 is formed of a silicon nitride film, a silicon nitride oxide film, or a silicon oxide film manufactured by a known method (thermal CVD method, plasma CVD method, vapor deposition method, sputtering method, reduced pressure thermal CVD method, etc.). Form. (Figure 1 (C))
[0040]
Next, contact holes reaching the source region and the drain region are formed using a known technique. At the same time, in the pixel portion, the first interlayer insulating film and the gate insulating film are etched in a region surrounded by source wiring and drain wiring formed in a later process and not overlapping with the semiconductor layer of the pixel TFT. The base film is partially exposed. At this time, the area of the region where the base film is exposed can be determined as appropriate. A wider area of the exposed base film is advantageous because a wide wiring can be formed, and a storage capacity formed by the metal substrate, the base film, and the drain wiring can provide a large capacity. Further, when the first interlayer insulating film and the gate insulating film are etched, it is advantageous to simultaneously make the base film thin by etching because a large capacity can be obtained for the storage capacity.
[0041]
Subsequently, a source wiring or a drain wiring is formed to obtain a TFT. However, the drain wiring of the pixel TFT is formed by connecting the drain region and the exposed base film. (Figure 1 (D))
[0042]
Next, hydrogenation is performed using a known technique, and the whole is hydrogenated to complete a TFT. In this embodiment, the hydrogenation treatment was performed using hydrogen plasma that can be performed at a relatively low temperature.
[0043]
Subsequently, a second interlayer insulating film 22 is formed. (FIG. 1E) As the second interlayer insulating film 22, a resin film having a small relative dielectric constant is preferable. As the resin film, a polyimide film, an acrylic film, a polyamide film, a BCB (benzocyclobutene) film, or the like can be used. Further, a planarizing film may be used. Thereafter, etch back is performed to expose part of the drain wiring, and the pixel electrode 24 is formed by connecting to the drain wiring 21 of the pixel TFT. (FIG. 1 (F)) As the pixel electrode 24, a metal film having a high reflectance represented by an aluminum film may be used if a reflective AM-LCD is manufactured.
[0044]
As described above, in FIG. 1, the storage capacitor in the pixel TFT is formed by the substrate having a metal surface, the base film, and the drain wiring of the pixel TFT. It is desirable that the substrate having the metal surface has a constant potential.
[0045]
Since the present invention uses a substrate having a metal surface as a substrate, it cannot be used for a transmission type electro-optical device. However, since the storage capacitor has the maximum area and can be formed using a region surrounded by the gate wiring and the source wiring and not overlapping with the pixel TFT, a storage capacitor having a very large capacity is effectively realized. be able to. Further, when the base insulating film functioning as a dielectric is made thin, the capacity can be further increased.
[0046]
The present invention having the above-described configuration will be described in more detail with the following embodiments.
[0047]
【Example】
[Example 1]
An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a cross-sectional view of a manufacturing process of a pixel TFT and a storage capacitor. Here, a single-gate TFT is manufactured as the pixel TFT. Of course, not only a single gate structure but also a double gate structure or a triple gate structure may be used. Needless to say, the present invention is not limited to this embodiment.
[0048]
First, a metal substrate 11 serving as an element formation substrate is prepared. When a stainless substrate having a thickness of 10 μm to 30 μm is used for the purpose of weight reduction, since the stainless substrate has flexibility, there is a problem in transportation or the like when an apparatus corresponding to a glass substrate or a synthetic quartz substrate is used. Therefore, for example, if a substrate holder is prepared and a stainless steel substrate is fixed to the substrate holder, the shape can be adapted to the apparatus.
[0049]
Moreover, the roughness of the metal surface irregularities on the metal substrate is 1 μmR. _MAX It is preferable that the surface roughness per 1 mm square is 1 μm. Further, the radius of curvature of the uneven projection is 1 μm or more, preferably 10 μm or more. A known technique for improving the flatness of the metal surface of the metal substrate, for example, a polishing process called CMP (Chemical Mechanical Polishing) may be used.
[0050]
Next, a base insulating film 12 is formed on the metal substrate 11. The base insulating film 12 also functions as a storage capacitor dielectric (first dielectric) in the pixel portion. At this time, it is advantageous to use a thin insulating film because a large capacity can be obtained. As the base insulating film, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOxNy), or a laminated film of these can be used in a film thickness range of 50 to 500 nm. A method (thermal CVD method, plasma CVD method, vapor deposition method, sputtering method, reduced pressure thermal CVD method, or the like) is used. In this embodiment, a silicon oxynitride film containing more nitrogen than oxygen is formed with a thickness of 150 nm in the film composition.
[0051]
A semiconductor film is formed on the base insulating film 12 to a thickness of 10 to 200 nm (preferably 30 to 100 nm) by a known means such as a plasma CVD method or a sputtering method. Note that the semiconductor film includes an amorphous semiconductor film, a microcrystalline semiconductor film, and the like, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. As a method for forming a semiconductor film, a known film formation method (thermal CVD method, plasma CVD method, vapor deposition method, sputtering method, low pressure thermal CVD method, etc.) can be used, and a crystallization method is also a known method (solid phase growth). Or a solid phase growth method using a catalytic element). In this embodiment, an amorphous silicon film is formed by a sputtering method that can be formed at a low temperature, and a crystalline silicon film is formed by a laser crystallization method. When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO _Four A laser can be used. Etching was then performed to form a semiconductor layer 13 having a desired shape.
[0052]
Then, the gate insulating film 14 is formed using the plasma CVD method or the sputtering method so as to cover the semiconductor layer. Typically, the thickness of the gate insulating film 14 may be 5 to 150 nm (preferably 10 to 200 nm). In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0053]
Next, a conductive film 15 is formed on the gate insulating film 14. As a material for forming the conductive film 15, a conductive film having heat resistance that can withstand temperatures of 800 to 1150 ° C. (preferably 900 to 1100 ° C.) is used. (Fig. 1 (A))
[0054]
Typically, a conductive silicon film (for example, a phosphorus-doped silicon film or a boron-doped silicon film) or a metal film (for example, a tungsten film, a tantalum film, a molybdenum film, or a titanium film) may be used, and the metal film may be silicided. A silicide film or a nitrided nitride film (such as a tantalum nitride film, a tungsten nitride film, or a titanium nitride film) may be used. Moreover, you may laminate | stack combining these freely.
[0055]
When the metal film is used, it is desirable to have a laminated structure with a silicon film in order to prevent oxidation of the metal film. In terms of preventing oxidation, a structure in which a metal film is covered with an insulating film containing silicon is effective. As the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (also referred to as a silicon nitride oxide film) can be used. Note that a silicon oxynitride film is an insulating film containing oxygen, nitrogen, and silicon at a predetermined ratio.
[0056]
Note that when the conductive film is formed using the above material, an insulating film containing silicon is provided as the uppermost layer during film formation, and the gate wiring pattern may be formed by collectively etching the insulating film containing silicon and the above material. it can. In this case, only the upper surface of the gate wiring is protected by the insulating film containing silicon. In this example, a conductive film made of a TaN film having a thickness of 30 nm was formed. The TaN film was formed by sputtering, and was sputtered in a nitrogen-containing atmosphere using a Ta target.
[0057]
Subsequently, patterning is performed to form the gate electrode 16.
[0058]
Next, doping is performed to add an impurity element to the semiconductor layer. (FIG. 1B) The doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁵ / Cm ² And an acceleration voltage of 5 to 100 keV. In this case, the conductive layer 16 serves as a mask for the impurity element, and the impurity regions 18 and 19 are formed in a self-aligning manner. In this embodiment, phosphorus (P) is added as an impurity element imparting n-type as doping treatment, and the phosphorus concentration in the impurity regions 18 and 19 is 1 × 10 6. ²⁰ ~ 5x10 ^{twenty one} / Cm ^Three I tried to become. Here, since an n-channel TFT is used for the pixel TFT, only the doping process of an impurity element imparting n-type is shown, but a p-channel TFT is also manufactured in the driver circuit. When doping an impurity element imparting p-type conductivity, a semiconductor layer for forming an n-channel TFT is covered with a mask made of resist.
[0059]
Then, the impurity element is activated by heat treatment. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace, a rapid thermal annealing method (RTA method) or a laser annealing method. In this embodiment, the heat treatment was performed at a temperature of 550 degrees for 4 hours.
[0060]
Next, the first interlayer insulating film is formed by a silicon nitride film, a silicon nitride oxide film, or a silicon oxide film manufactured by a known method (thermal CVD method, plasma CVD method, vapor deposition method, sputtering method, reduced pressure thermal CVD method, etc.). Form. (FIG. 1 (C)) In this example, an acrylic resin film having a film thickness of 1.6 μm was formed, but one having a viscosity of 10 to 1000 cp, preferably 40 to 200 cp was used.
[0061]
Next, contact holes reaching the source region and the drain region are formed using a known technique. At the same time, in the pixel portion, the first interlayer insulating film and the gate insulating film are etched in a region surrounded by source wiring and drain wiring formed in a later process and not overlapping with the semiconductor layer of the pixel TFT. The base film is partially exposed. At this time, the area of the region where the base film is exposed can be determined as appropriate. A wider area of the exposed base film is advantageous because a wide wiring can be formed, and a storage capacity formed by the metal substrate, the base film, and the drain wiring can provide a large capacity. Further, when the first interlayer insulating film and the gate insulating film are etched, it is advantageous to simultaneously make the base film thin by etching because a large capacity can be obtained for the storage capacity.
[0062]
Subsequently, a source wiring or a drain wiring is formed to obtain a TFT. However, the drain wiring of the pixel TFT is formed by connecting the drain region and the exposed base film. (Figure 1 (D))
[0063]
Next, hydrogenation is performed using a known technique, and the whole is hydrogenated to complete a TFT. In this embodiment, the hydrogenation treatment was performed using hydrogen plasma that can be performed at a relatively low temperature.
[0064]
Subsequently, a second interlayer insulating film 22 is formed. (FIG. 1E) As the second interlayer insulating film 22, a resin film having a small relative dielectric constant is preferable. As the resin film, a polyimide film, an acrylic film, a polyamide film, a BCB (benzocyclobutene) film, or the like can be used. Further, a planarizing film may be used. Thereafter, when etch back is performed, the second interlayer insulating film 22 is etched to have a shape indicated by 23, and a part of the wiring is exposed. Then, the pixel electrode 24 is formed by connecting to the drain wiring 21 of the pixel TFT. (FIG. 1 (F)) As the pixel electrode 24, a metal film having a high reflectance represented by an aluminum film may be used if a reflective AM-LCD is manufactured.
[0065]
As described above, in FIG. 1, the storage capacitor in the pixel TFT is formed by the substrate having a metal surface, the base film, and the drain wiring of the pixel TFT.
[0066]
Since the present invention uses a substrate having a metal surface as a substrate, it cannot be used for a transmission type electro-optical device. However, since the storage capacitor has the maximum area and can be formed using a region surrounded by the gate wiring and the source wiring and not overlapping with the pixel TFT, a storage capacitor having a very large capacity is effectively realized. be able to. Further, if the base film functioning as a dielectric is made thin, the capacity can be further increased.
[0067]
[Example 2]
In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS.
[0068]
First, in this embodiment, a substrate 300 having a metal surface is used. Note that the substrate 300 may be a stainless steel substrate or a glass substrate in which a conductive film is formed.
[0069]
Moreover, the roughness of the metal surface irregularities on the metal substrate is 1 μmR. _MAX It is preferable to be flat as follows. Or it is preferable that the surface roughness per 1 mm square of the unevenness | corrugation of the metal surface in a metal substrate will be 1 micrometer. Further, the radius of curvature of the uneven projection is 1 μm or more, preferably 10 μm or more. A known technique for improving the flatness of the metal surface of the metal substrate, for example, a polishing process called CMP (Chemical Mechanical Polishing) may be used.
[0070]
Next, a base film 301 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 300. Although a two-layer structure is used as the base film 301 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 301, a plasma CVD method is used, and SiH _Four , NH _Three And N ₂ A silicon oxynitride film 301a formed using O as a reactive gas is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm). In this embodiment, a 50 nm thick silicon oxynitride film 301a (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) was formed. Next, as a second layer of the base film 301, a plasma CVD method is used, and SiH _Four And N ₂ A silicon oxynitride film 301b formed using O as a reaction gas is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). In this embodiment, a silicon oxynitride film 301b (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) having a thickness of 100 nm is formed.
[0071]
Next, after a semiconductor film having an amorphous structure is formed on the base film to a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (such as sputtering, LPCVD, or plasma CVD). Then, a known crystallization treatment (laser crystallization method, thermal crystallization method, thermal crystallization method using a catalyst such as nickel) is performed to obtain a crystalline semiconductor film. (FIG. 2A) There is no limitation on the material of the semiconductor film, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy. In this example, a 55 nm amorphous silicon film was formed by plasma CVD, and then a solution containing nickel was held on the amorphous silicon film. This amorphous silicon film is dehydrogenated (500 ° C., 1 hour), then thermally crystallized (550 ° C., 4 hours), and further subjected to laser annealing to improve crystallization. A crystalline silicon film was formed. Then, semiconductor layers 402 to 405 were formed on the crystalline semiconductor film by patterning using a photolithography method.
[0072]
When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, Ar laser, Kr laser, YAG laser, YVO _Four Laser, YLF laser, YAlO _Three A laser, a glass laser, a ruby laser, an alexandride laser, a Ti: sapphire laser, or the like can be used. Moreover, you may use the harmonic converted by the nonlinear optical element. In the case of using these lasers, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The crystallizing conditions are appropriately selected by the practitioner. However, in the present invention, a metal substrate having a higher thermal conductivity is used than a glass substrate, so that heat energy due to laser beam irradiation is easily escaped. . Therefore, it is preferable to irradiate with higher energy than laser irradiation conditions when a glass substrate or a synthetic quartz substrate is used.
[0073]
For example, when an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 800 mJ / cm. ² (Typically 300-700mJ / cm ² ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 300 Hz, and the laser energy density is 300 to 1000 mJ / cm. ² (Typically 350-800mJ / cm ² ) Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser beam at this time is set to 50 to 98%. Also good. When a continuous wave laser is used, for example, a continuous wave YVO with an output of 10 W is used. _Four Laser light emitted from the laser is converted into a harmonic by a non-linear optical element. Also, YVO in the resonator _Four There is also a method of emitting harmonics by inserting a crystal and a nonlinear optical element. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. The energy density at this time is 0.01 to 100 MW / cm. ² Degree (preferably 0.1-10 MW / cm ² )is required. Then, irradiation is performed by moving the semiconductor film relative to the laser light at a speed of about 0.5 to 2000 cm / s.
[0074]
In addition, after forming the semiconductor layers 402 to 405, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.
[0075]
Next, a gate insulating film 407 covering the semiconductor layers 402 to 405 is formed. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by plasma CVD or sputtering. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0076]
When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.
[0077]
Next, as illustrated in FIG. 2B, a first conductive film 408 with a thickness of 20 to 100 nm and a second conductive film 409 with a thickness of 100 to 400 nm are stacked over the gate insulating film 407. In this embodiment, a first conductive film 408 made of a TaN film with a thickness of 30 nm and a second conductive film 409 made of a W film with a thickness of 370 nm are stacked. The TaN film was formed by sputtering, and was sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by sputtering using a W target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Therefore, in this embodiment, a sputtering method using a target of high purity W (purity 99.9999%) is used, and the W film is formed with sufficient consideration so that impurities are not mixed in from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.
[0078]
In this embodiment, the first conductive film 408 is TaN and the second conductive film 409 is W. However, there is no particular limitation, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the element selected from these, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film doped with an impurity element such as phosphorus may be used. Further, an AgPdCu alloy may be used. In addition, the first conductive film is formed using a tantalum (Ta) film, the second conductive film is formed using a W film, the first conductive film is formed using a titanium nitride (TiN) film, and the second conductive film is formed. The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. The second conductive film may be a combination of Cu films.
[0079]
Next, resist masks 410 to 414 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ The gas flow ratio was 25:25:10 (sccm), and 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. . Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered.
[0080]
Thereafter, the resist masks 410 to 414 are not removed and the second etching condition is changed, and the etching gas is changed to CF. _Four And Cl ₂ The gas flow ratio is 30:30 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and etching for about 30 seconds. Went. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching condition in which is mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0081]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 417 to 421 (first conductive layers 417 a to 421 a and second conductive layers 417 b to 421 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form. Reference numeral 416 denotes a gate insulating film, and a region not covered with the first shape conductive layers 417 to 421 is etched and thinned by about 20 to 50 nm.
[0082]
Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer. (FIG. 3B) The doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁵ / Cm ² The acceleration voltage is set to 60 to 100 keV. In this embodiment, the dose is 1.5 × 10 ¹⁵ / Cm ² The acceleration voltage was 80 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 417 to 421 serve as a mask for the impurity element imparting n-type, and the first high-concentration impurity regions 306 to 309 are formed in a self-aligning manner. The first high-concentration impurity regions 306 to 309 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} / Cm ² An impurity element imparting n-type is added in a concentration range of.
[0083]
Next, a second etching process is performed without removing the resist mask. Here, CF is used as an etching gas. _Four And Cl ₂ And O ₂ Then, the W film is selectively etched. At this time, second conductive layers 428b to 432b are formed by a second etching process. On the other hand, the first conductive layers 417a to 421a are hardly etched, and second shape conductive layers 428 to 432 are formed.
[0084]
Next, a second doping process is performed as shown in FIG. 3C without removing the resist mask. In this case, an impurity element imparting n-type conductivity is introduced at a high acceleration voltage of 70 to 120 keV with a lower dose than in the first doping treatment. In this embodiment, the dose is 1.5 × 10 ¹⁴ / Cm ² Then, the acceleration voltage is set to 90 keV, and a new impurity region is formed in the semiconductor layer inside the first high-concentration impurity regions 306 to 309 formed in FIG. The second doping process uses the second shape conductive layers 428 to 432 as a mask, and an impurity element is also introduced into the semiconductor layer below the second conductive layers 428 b to 432 b to newly add a second high-concentration impurity. Regions 423a to 426a and low concentration impurity regions 423b to 426b are formed.
[0085]
Next, after removing the resist mask, new resist masks 434a and 434b are formed, and a third etching process is performed as shown in FIG. SF for etching gas ₆ And Cl ₂ And a gas flow rate ratio of 50:10 (sccm), 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.3 Pa, plasma is generated, and etching is performed for about 30 seconds. Perform processing. 10 W of RF (13.56 MHz) power is applied to the substrate side (material stage), and a negative self-bias voltage is substantially applied. Thus, the third etching process is performed to etch the TaN film of the p-channel TFT and the TFT (pixel TFT) of the pixel portion, thereby forming third shape conductive layers 435 to 437.
[0086]
Next, after removing the resist mask, the gate insulating film 416 is selectively removed using the second shape conductive layers 428 and 430 and the third shape conductive layers 435 to 437 as masks. 439 to 443 are formed. (Fig. 4 (B))
[0087]
Next, new resist masks 445a to 445c are formed, and a third doping process is performed. By this third doping treatment, an impurity region 446 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer that becomes an active layer of the p-channel TFT is formed. Using the second conductive layer 435a as a mask against the impurity element, an impurity element imparting p-type conductivity is added to form an impurity region in a self-aligning manner. In this embodiment, the impurity region 446 is diborane (B ₂ H ₆ ) Using an ion doping method. (FIG. 4C) In the third doping process, the semiconductor layer forming the n-channel TFT is covered with masks 445a to 445c made of resist. By the first doping process and the second doping process, phosphorus is added to the impurity regions 446 at different concentrations, and the concentration of the impurity element imparting p-type is 2 × 10 2 in any of the regions. ²⁰ ~ 2x10 ^{twenty one} / Cm ^Three By performing the doping treatment so as to become, no problem arises because it functions as the source region and drain region of the p-channel TFT. In this embodiment, since a part of the semiconductor layer serving as an active layer of the p-channel TFT is exposed, there is an advantage that an impurity element (boron) can be easily added.
[0088]
Through the above steps, impurity regions are formed in the respective semiconductor layers.
[0089]
Next, the resist masks 445a to 445c are removed, and a first interlayer insulating film 461 is formed. The first interlayer insulating film 461 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 461 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0090]
Next, as shown in FIG. 5A, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, 550 ° C. for 4 hours. The activation treatment was performed by heat treatment. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0091]
In this embodiment, simultaneously with the activation treatment, the impurity regions 423a, 425a, 426a, and 446a containing nickel having a high concentration of nickel used as a catalyst during crystallization are crystallized. Therefore, the metal element is gettered in the impurity region, and the nickel concentration in the semiconductor layer mainly serving as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0092]
In addition, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak against heat, it is activated after an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring as in this embodiment. It is preferable to perform the conversion process.
[0093]
Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0094]
In the case where a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after the hydrogenation.
[0095]
Next, a second interlayer insulating film 462 made of an inorganic insulating film material or an organic insulating material is formed over the first interlayer insulating film 461. (FIG. 5 (B)) In this example, an acrylic resin film having a film thickness of 1.6 μm was formed, but a film having a viscosity of 10 to 1000 cp, preferably 40 to 200 cp, and having unevenness on the surface. Was used.
[0096]
In this embodiment, in order to prevent specular reflection, the surface of the pixel electrode is formed with the unevenness by forming the second interlayer insulating film having the unevenness on the surface. In addition, a convex portion may be formed in a region below the pixel electrode in order to make the surface of the pixel electrode uneven to achieve light scattering. In that case, since the convex portion can be formed using the same photomask as that of the TFT, the convex portion can be formed without increasing the number of steps. In addition, this convex part should just be suitably provided on the board | substrate of pixel part area | regions other than wiring and a TFT part. Thus, irregularities are formed on the surface of the pixel electrode along the irregularities formed on the surface of the insulating film covering the convex portions.
[0097]
Alternatively, a film whose surface is planarized may be used as the second interlayer insulating film 462. In that case, after forming the pixel electrode, adding a step such as a known sandblasting method or etching method to make the surface uneven, prevent specular reflection, and increase the whiteness by scattering the reflected light Is preferred.
[0098]
In the driver circuit 506, wirings 463 to 467 that are electrically connected to the impurity regions are formed. Note that these wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm.
[0099]
In the pixel portion 507, at the same time when the contact holes reaching the source region and the drain region are formed, a region surrounded by the source wiring and the drain wiring formed in a later process, and the semiconductor layer of the pixel TFT In the non-overlapping region, the first interlayer insulating film, the second interlayer insulating film, and the gate insulating film are etched to partially expose the base film. At this time, the area of the region where the base film is exposed can be determined as appropriate. A wider area of the exposed base film is advantageous because a wide wiring can be formed, and a storage capacity formed by the metal substrate, the base film, and the drain wiring can provide a large capacity. Then, as shown in FIG. 5C, a drain wiring 470, a gate wiring 469, and a connection electrode 468 are formed. With this connection electrode 468, the source wiring (stack of 436a and 436b) is electrically connected to the pixel TFT. In addition, the gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. In addition, the drain wiring 470 is electrically connected to the drain region 426 h of the pixel TFT, and further functions as one electrode that forms the storage capacitor 505. (Fig. 5 (C))
[0100]
Subsequently, a third interlayer insulating film 471 is formed. (FIG. 6A) The third interlayer insulating film 471 is preferably a resin film having a low relative dielectric constant. As the resin film, a polyimide film, an acrylic film, a polyamide film, a BCB (benzocyclobutene) film, or the like can be used. Further, a planarizing film may be used as the third interlayer insulating film.
[0101]
Thereafter, when etch back is performed, the third interlayer insulating film 471 is etched to have a shape indicated by 473, and a part of the wiring is exposed. Then, a pixel electrode 473 is formed by connecting to the drain wiring 470 of the pixel TFT. (FIG. 6B) As the pixel electrode 473, if a reflective AM-LCD is manufactured, a metal film having a high reflectance represented by an aluminum film may be used. For example, as the pixel electrode 473, it is desirable to use a highly reflective material such as a film containing Al or Ag as a main component or a laminated film thereof.
[0102]
As described above, a CMOS circuit including an n-channel TFT 501 and a p-channel TFT 502, a driver circuit 506 having an n-channel TFT 503, and a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 are formed over the same substrate. can do. Thus, the active matrix substrate is completed.
[0103]
The n-channel TFT 501 of the driver circuit 506 includes a channel formation region 423c, a low-concentration impurity region 423b (GOLD region) that overlaps with the first conductive layer 428a which forms part of the gate electrode, and a high function as a source region or a drain region. A concentration impurity region 423a is provided. The p-channel TFT 502 which is connected to the n-channel TFT 501 and the electrode 466 to form a CMOS circuit functions as a channel formation region 446d, impurity regions 446b and 446c formed outside the gate electrode, and a source region or a drain region. A high concentration impurity region 446a is provided. In addition, the n-channel TFT 503 includes a channel formation region 425c, a low-concentration impurity region 425b (GOLD region) that overlaps with the first conductive layer 430a that forms part of the gate electrode, and a high-concentration function as a source region or a drain region. An impurity region 425a is provided.
[0104]
The pixel TFT 504 in the pixel portion includes a channel formation region 426c, a low concentration impurity region 426b (LDD region) formed outside the gate electrode, and a high concentration impurity region 426a functioning as a source region or a drain region. The storage capacitor 505 is formed of the drain wiring 470 and the metal substrate 300 using the base film 301 as a dielectric.
[0105]
In the pixel structure of this embodiment, the end of the pixel electrode overlaps with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.
[0106]
A top view of a pixel portion of an active matrix substrate manufactured in this embodiment is shown in FIG. In addition, the same code | symbol is used for the part corresponding to FIGS. A chain line AA ′ in FIG. 6 corresponds to a cross-sectional view taken along the chain line AA ′ in FIG.
[0107]
Note that this embodiment can be freely combined with Embodiment 1.
[0108]
[Example 3]
In this embodiment, a process for manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 2 will be described below. FIG. 8 is used for the description.
[0109]
First, after obtaining an active matrix substrate in the state of FIG. 6B in accordance with Embodiment 2, an alignment film 567 is formed on at least the pixel electrode 473 on the active matrix substrate of FIG. . In this embodiment, before forming the alignment film 567, an organic resin film such as an acrylic resin film is patterned to form columnar spacers 572 for maintaining a substrate interval at a desired position. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0110]
Next, a counter substrate 569 is prepared. Next, colored layers 570 and 571 and a planarization film 573 are formed over the counter substrate 569. The red colored layer 570 and the blue colored layer 572 are overlapped to form a light shielding portion. Further, the light shielding portion may be formed by partially overlapping the red colored layer and the green colored layer.
[0111]
In this embodiment, the substrate shown in Embodiment 2 is used. Therefore, in FIG. 7 showing a top view of the pixel portion of Example 2, at least the gap between the gate wiring 469 and the pixel electrode 473, the gap between the gate wiring 469 and the connection electrode 468, and the gap between the connection electrode 468 and the pixel electrode 473 are shown. It is necessary to shield the light. In this example, the respective colored layers were arranged so that the light-shielding portions formed by the lamination of the colored layers overlapped at the positions where light shielding should be performed, and the counter substrate was bonded.
[0112]
As described above, the number of steps can be reduced by shielding the gap between the pixels with the light shielding portion formed by the lamination of the colored layers without forming a light shielding layer such as a black mask.
[0113]
Next, a counter electrode 576 made of a transparent conductive film was formed over the planarization film 573 in at least the pixel portion, an alignment film 574 was formed over the entire surface of the counter substrate, and a rubbing process was performed.
[0114]
Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 568. A filler is mixed in the sealing material 568, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 575 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. In this way, the reflection type liquid crystal display device shown in FIG. 8 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. And FPC was affixed using the well-known technique.
[0115]
The liquid crystal display panel manufactured as described above can be used as a display portion of various electronic devices.
[0116]
In addition, this embodiment can be freely combined with Embodiment 1 or 2.
[0117]
[Example 4]
Here, an example in which an EL (Electro Luminescence) display device is manufactured as an example of a light-emitting device using the present invention will be described.
[0118]
In this specification, the light emitting device is a general term for a display panel in which a light emitting element formed on a substrate is sealed between the substrate and a cover material, and a display module in which an IC is mounted on the display panel. is there. Note that the light-emitting element includes a layer containing an organic compound (light-emitting layer) from which luminescence is generated by applying an electric field, an anode layer, and a cathode layer. In addition, luminescence in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state, one of these, Or both luminescence is included.
[0119]
FIG. 9 is a cross-sectional view of the EL display device of the present invention. FIG. 9 shows an example of a light-emitting device having a pixel portion and a driving circuit for driving the pixel portion on the same insulator (but a state before sealing). Note that a CMOS circuit serving as a basic unit is shown in the driver circuit, and one pixel is shown in the pixel portion. This CMOS circuit can be obtained according to the second embodiment.
[0120]
In FIG. 9, reference numeral 600 denotes a metal substrate. On a base insulating film provided on the metal substrate, a driving circuit 617 composed of an n-channel TFT 501 and a p-channel TFT 502, a switching TFT 603 composed of a p-channel TFT, and n A current control TFT 604 composed of a channel type TFT 604 is formed. In this embodiment, all TFTs are formed by top gate type TFTs.
[0121]
In FIG. 9, the description of the n-channel TFT and the p-channel TFT is omitted because it is sufficient to refer to the second embodiment. The switching TFT 603 is a p-channel TFT having a structure (double gate structure) having two channel formation regions between a source region and a drain region. Note that this embodiment is not limited to the double gate structure, and may be a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. The current control TFT 604 is a single-gate n-channel TFT. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.
[0122]
The drain region of the switching TFT 603 is connected to the gate electrode of the current control TFT (not shown), but at the same time, the first interlayer insulating film 607 and the second interlayer insulating film 608 are etched to partially form the base insulating film 601. Expose. At this time, the area of the region where the base insulating film 601 is exposed can be determined as appropriate. However, the wider the area of the exposed base insulating film, the wider wiring can be formed. The storage capacitor 605 formed by the 601 and the drain wiring 614 is advantageous because a large capacity can be obtained. Further, when the first interlayer insulating film 607 and the second interlayer insulating film 608 are etched, if the base insulating film 601 is etched and thinned, it is advantageous because the storage capacitor 605 can obtain a larger capacity. Then, a source wiring and a drain wiring are formed to obtain a TFT. However, in the pixel portion, a drain wiring 614 that connects the drain region and the exposed base insulating film 601 is formed.
[0123]
Subsequently, a third interlayer insulating film 613 is formed. As the third interlayer insulating film 613, for example, a planarizing film made of resin is used. It is very important to flatten the step due to the TFT and the storage capacitor by using the flattening film. Since the EL layer 611 formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0124]
Subsequently, a pixel electrode 609 connected to the drain wiring 615 is provided. The pixel electrode 609 is an electrode that functions as a cathode of the EL element, and is formed using a conductive film containing an element belonging to Group 1 or 2 of the periodic table. In this embodiment, a conductive film made of a compound of lithium and aluminum is used.
[0125]
The EL element 610 includes a pixel electrode (cathode) 609, an EL layer 611, and an anode 612. As the anode 612, a conductive film having a high work function, typically an oxide conductive film, is used. As the oxide conductive film, indium oxide, tin oxide, zinc oxide, or a compound thereof may be used.
[0126]
In this specification, the light emitting layer (EL film) is a general term for a layer in which a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, or an electron blocking layer are combined. Is defined as an EL layer. However, the EL layer includes a case where the EL film is used as a single layer.
[0127]
The light emitting layer is not particularly limited as long as it is an EL material. For example, a thin film made of a light emitting material that emits light by doublet excitation or a thin film made of a light emitting material that emits light by triplet excitation can be used.
[0128]
Although not shown here, it is effective to provide a passivation film so as to completely cover the EL element 610 after the anode 612 is formed. As the passivation film, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a combination thereof.
[0129]
Next, the EL display device after the process up to the sealing (or encapsulation) process for protecting the EL element is described with reference to FIGS. FIG. 10A is a top view illustrating a state where the EL element is sealed, and FIG. 10B is a cross-sectional view taken along CC ′ of FIG. 10A. 701 indicated by a dotted line is a pixel portion, 702 is a source side driver circuit, and 703 is a gate side driver circuit. 704 is a cover material, 705 is a first seal material, and 706 is a second seal material.
[0130]
Reference numeral 707 denotes wiring for transmitting signals input to the source side driver circuit 702 and the gate side driver circuit 703, and receives video signals and clock signals from an FPC (flexible printed circuit) 708 serving as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC.
[0131]
Next, a cross-sectional structure is described with reference to FIG. A pixel portion and a source side driver circuit 709 are formed above the insulator 700 (corresponding to the element formation substrate 600), and the pixel portion includes a current control TFT 710 and a pixel electrode 711 electrically connected to its drain. It is formed by a plurality of pixels. In addition, a storage capacitor is formed by 718 which is part of the drain wiring of the switching TFT, the base insulating film, and the stainless steel substrate 700. The source side driver circuit 709 is formed using a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined.
[0132]
A third interlayer insulating film 712 is formed on both ends of the pixel electrode 711, and an EL layer 713 and an anode 714 of the EL element are formed on the pixel electrode 711. The anode 714 also functions as a wiring common to all pixels, and is electrically connected to the FPC 716 through the connection wiring 715. Further, all elements included in the pixel portion and the source side driver circuit 709 are covered with a passivation film (not shown).
[0133]
Further, a cover material 704 is bonded to the first seal material 705. Note that a spacer may be provided in order to ensure a space between the cover material 704 and the EL element. A gap 717 is formed inside the first sealing material 705. Note that the first sealing material 705 is desirably a material that does not transmit moisture or oxygen. Furthermore, it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside the gap 717.
[0134]
Note that a carbon film (specifically, a diamond-like carbon film) is preferably provided as a protective film on the front and back surfaces of the cover material 704 in a thickness of 2 to 30 nm. Such a carbon film (not shown here) has a role of preventing oxygen and water from entering and mechanically protecting the surface of the cover material 704. Further, a polarizing plate (typically, a circularly polarizing plate) may be attached to the cover material 704.
[0135]
Further, after the cover material 704 is bonded, the second seal material 706 is provided so as to cover the exposed surface of the first seal material 705. The second sealant 706 can be made of the same material as the first sealant 705.
[0136]
By encapsulating the EL element with the structure as described above, the EL element can be completely shut off from the outside, and prevents substances that promote deterioration due to oxidation of the EL layer, such as moisture and oxygen, from entering from the outside. Can do. Therefore, an EL display device with high reliability can be obtained.
[0137]
Note that this embodiment can be freely combined with any one of Embodiments 1 to 3.
[0138]
[Example 5]
In this embodiment, in the EL display device obtained in Embodiment 4, a more detailed top surface structure of the pixel portion is shown in FIG. In addition, the same code | symbol is used for the part corresponding to FIG. A chain line BB ′ in FIG. 9 corresponds to a cross-sectional view taken along the chain line BB ′ in FIG.
[0139]
The source of the switching TFT 603 is connected to the source wiring 815, and the drain is connected to the drain wiring 614. The drain wiring 614 is electrically connected to the gate electrode 807 of the current control TFT 604. The source of the current control TFT 604 is electrically connected to the current supply line 816, and the drain is electrically connected to the drain wiring 615. The drain wiring 615 is electrically connected to a pixel electrode (cathode) 609 indicated by a dotted line.
[0140]
At this time, a storage capacitor is formed in the region indicated by 605. The storage capacitor 605 is formed between the drain wiring 614, a base insulating film (not shown), and a metal substrate (not shown).
[0141]
Note that this embodiment can be freely combined with any one of Embodiments 1 to 3.
[0142]
[Example 6]
The TFT formed by implementing any one of the first to fifth embodiments can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated in the display unit.
[0143]
Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) and the like. . Examples thereof are shown in FIGS. 12 and 13.
[0144]
FIG. 12A illustrates a personal computer, which includes a main body 3001, an image input portion 3002, a display portion 3003, a keyboard 3004, and the like. The present invention can be applied to the display portion 3003.
[0145]
FIG. 12B illustrates a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, an image receiving portion 3106, and the like. The present invention can be applied to the display portion 3102.
[0146]
FIG. 12C illustrates a mobile computer, which includes a main body 3201, a camera unit 3202, an image receiving unit 3203, an operation switch 3204, a display unit 3205, and the like. The present invention can be applied to the display portion 3205.
[0147]
FIG. 12D illustrates a goggle type display, which includes a main body 3301, a display portion 3302, an arm portion 3303, and the like. The present invention can be applied to the display portion 3302.
[0148]
FIG. 12E shows a player that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, a speaker portion 3403, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 3402.
[0149]
FIG. 12F illustrates a digital camera, which includes a main body 3501, a display portion 3502, an eyepiece portion 3503, an operation switch 3504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 3502.
[0150]
FIG. 13A illustrates a mobile phone, which includes a main body 3901, an audio output portion 3902, an audio input portion 3903, a display portion 3904, operation switches 3905, an antenna 3906, and the like. The present invention can be applied to the display portion 3904.
[0151]
FIG. 13B illustrates a portable book (electronic book) which includes a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, an antenna 4006, and the like. The present invention can be applied to the display portions 4002 and 4003.
[0152]
FIG. 13C illustrates a display, which includes a main body 4101, a support base 4102, a display portion 4103, and the like. The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0153]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. In particular, it can also be suitably used for electronic devices that require weight reduction. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-5.
[0154]
【Effect of the invention】
By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) A simple structure suitable for a conventional TFT manufacturing process.
(B) The storage capacitor is formed by a substrate having a metal surface, an insulating film, and wiring. The capacity of the storage capacitor can be appropriately changed by a base insulating film that functions as a dielectric. Specifically, the capacity of the storage capacitor can be changed according to the thickness of the base insulating film and the area of the base insulating film exposed by etching.
(C) A method capable of producing a good semiconductor device while satisfying the above advantages.
If the substrate having the metal surface is thin, a flexible and lightweight semiconductor device can be obtained.
[Brief description of the drawings]
FIGS. 1A and 1B illustrate an example of a method for manufacturing a pixel TFT and a storage capacitor disclosed in the present invention. FIGS.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a driver circuit TFT;
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 7 is a top view illustrating a structure of a pixel portion.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 9 is a cross-sectional structure diagram of a driving circuit and a pixel portion of an EL display device.
FIG. 10A is a top view of an EL display device.
FIG. 5B is a cross-sectional structure diagram of a driver circuit and a pixel portion of an EL display device.
FIG. 11 is a top view of a pixel portion of an EL display device.
FIG 12 illustrates an example of an electronic device.
FIG. 13 illustrates an example of an electronic device.

Claims (7)

A substrate having a conductive surface;
An insulating film formed on the conductive surface;
A pixel TFT formed on the insulating film;
A first interlayer insulating film formed on the pixel TFT;
A contact hole formed in the first interlayer insulating film,
A wiring electrically connected to the semiconductor film serving as an active region of the pixel TFT through the contact hole is formed on the insulating film and the first interlayer insulating film,
A second interlayer insulating film is formed on the wiring,
A pixel electrode electrically connected to the wiring is formed on the second interlayer insulating film,
A semiconductor device, wherein a capacitance is constituted by the conductive surface, the insulating film, and the wiring. A substrate,
A metal film formed on the substrate;
An insulating film formed on the metal film;
A pixel TFT formed on the insulating film;
A first interlayer insulating film formed on the pixel TFT;
A contact hole formed in the first interlayer insulating film,
A wiring electrically connected to the semiconductor film serving as an active region of the pixel TFT through the contact hole is formed on the insulating film and the first interlayer insulating film,
A second interlayer insulating film is formed on the wiring,
A pixel electrode electrically connected to the wiring is formed on the second interlayer insulating film,
A semiconductor device, wherein a capacitor is constituted by the metal film, the insulating film, and the wiring. A substrate,
A conductive semiconductor film formed on the substrate;
An insulating film formed on the conductive semiconductor film;
A pixel TFT formed on the insulating film;
A first interlayer insulating film formed on the pixel TFT;
A contact hole formed in the first interlayer insulating film,
A wiring electrically connected to the semiconductor film serving as an active region of the pixel TFT through the contact hole is formed on the insulating film and the first interlayer insulating film,
A second interlayer insulating film is formed on the wiring,
A pixel electrode electrically connected to the wiring is formed on the second interlayer insulating film,
A semiconductor device, wherein a capacitor is constituted by the conductive semiconductor film, the insulating film, and the wiring. A substrate having a conductive surface;
An insulating film formed on the conductive surface;
A TFT formed on the insulating film;
A first interlayer insulating film formed on the TFT;
A contact hole formed in the first interlayer insulating film,
A wiring electrically connected to the semiconductor film serving as the active region of the TFT through the contact hole is formed on the insulating film and the first interlayer insulating film,
A second interlayer insulating film is formed on the wiring,
An electrode electrically connected to the wiring is formed on the second interlayer insulating film,
A semiconductor device, wherein a capacitance is constituted by the conductive surface, the insulating film, and the wiring. A substrate,
A metal film formed on the substrate;
An insulating film formed on the metal film;
A TFT formed on the insulating film;
A first interlayer insulating film formed on the TFT;
A contact hole formed in the first interlayer insulating film,
A wiring electrically connected to the semiconductor film serving as the active region of the TFT through the contact hole is formed on the insulating film and the first interlayer insulating film,
A second interlayer insulating film is formed on the wiring,
An electrode electrically connected to the wiring is formed on the second interlayer insulating film,
A semiconductor device, wherein a capacitor is constituted by the metal film , the insulating film, and the wiring. In any one of Claims 1 thru | or 5 ,
The semiconductor device is a substrate having flexibility. In any one of Claims 1 thru | or 6 ,
The thickness of the insulating film at the location where the capacitor is formed is smaller than the thickness of the insulating film formed under the semiconductor film that becomes the active region of the pixel TFT. .

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