JPH0225A - Driving device - Google Patents
Driving deviceInfo
- Publication number
- JPH0225A JPH0225A JP1109527A JP10952789A JPH0225A JP H0225 A JPH0225 A JP H0225A JP 1109527 A JP1109527 A JP 1109527A JP 10952789 A JP10952789 A JP 10952789A JP H0225 A JPH0225 A JP H0225A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- capacitor
- counter electrode
- electrode
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 claims abstract description 25
- 239000003990 capacitor Substances 0.000 claims description 30
- 239000010408 film Substances 0.000 claims description 16
- 239000004973 liquid crystal related substance Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 abstract description 23
- 239000004065 semiconductor Substances 0.000 abstract description 21
- 239000000463 material Substances 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 125000006850 spacer group Chemical group 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- DSSYKIVIOFKYAU-XCBNKYQSSA-N (R)-camphor Chemical compound C1C[C@@]2(C)C(=O)C[C@@H]1C2(C)C DSSYKIVIOFKYAU-XCBNKYQSSA-N 0.000 description 1
- -1 CeO2 Chemical class 0.000 description 1
- 241000723346 Cinnamomum camphora Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000004990 Smectic liquid crystal Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 229910001634 calcium fluoride Inorganic materials 0.000 description 1
- 229960000846 camphor Drugs 0.000 description 1
- 229930008380 camphor Natural products 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 230000003098 cholesteric effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000004927 clay Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 229910052809 inorganic oxide Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910001635 magnesium fluoride Inorganic materials 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の分野〕
本発明は表示駆動装置、特に、新規構成の薄膜トランジ
スタ(TPT)アレイを設けた基板を具備した表示駆動
装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display driver, and more particularly to a display driver having a substrate provided with a thin film transistor (TPT) array of a novel configuration.
従来、この種の装置としては特開昭50−17599号
明細書に記載の表示セルが知られている。Conventionally, as this type of device, a display cell described in Japanese Patent Laid-Open No. 17599/1984 is known.
斯かる表示セルの駆動用スイッチング素子に於いては、
第6図に示すように、基板B上にゲート線Gl、G、・
・・、更にこれらの上の全面にわたって絶縁層■、半導
体SCを積層している。又、ゲート線G、、G、に交差
して、半導体SCに接するソース線Sls S2を設け
、ゲート線とソース線の交点付近にはセグメント電極と
なるドレインD1゜D2e D3e D4が設けら
れている。In the switching element for driving such a display cell,
As shown in FIG. 6, gate lines Gl, G, .
. . . Furthermore, an insulating layer (1) and a semiconductor SC are laminated over the entire surface of these layers. In addition, a source line Sls S2 is provided which intersects with the gate lines G, , G, and is in contact with the semiconductor SC, and drains D1, D2, D3, and D4, which serve as segment electrodes, are provided near the intersection of the gate line and the source line. .
上記半導体SCは薄膜状に形成され、TFT (Thi
nF i l m T r a n s i s t
o r ) T代表される様な駆動用スイッチング素
子となっている。The semiconductor SC is formed in the form of a thin film, and TFT (Th
nF i l m T r a n s i s t
o r ) It is a driving switching element as typified by T.
そして、上記駆動用スイッチング素子アレイを有する基
板と、対向電極(例えば全面電極)を設けた対向基板と
の間に液晶層を挾持することにより、第7図の等価回路
が形成される。The equivalent circuit shown in FIG. 7 is formed by sandwiching a liquid crystal layer between the substrate having the drive switching element array and the counter substrate provided with counter electrodes (for example, full-surface electrodes).
ゲート線G 1 # G 11 w ”−には駆動電圧
が、ソース線s、、S2e−”には信号が印加され、且
つこれらに対しては、それぞれ適当な行発生路(R1゜
R2−R,及びP 1 e Plg・−pIl)が接線
され、行−時走査が行われる。A drive voltage is applied to the gate line G 1 #G 11 w ”-, a signal is applied to the source lines s, , S2e-”, and appropriate row generation paths (R1゜R2-R , and P 1 e Plg·-pIl) are tangent and a row-time scan is performed.
又、T11. T、、、 T、、、 T22.−・−は
、上述のようにして構成されるTPTであり、C11s
CL!wC21e CKM e ””は、TPTスイッ
チング素子アレーの各ゲート線とそれ自身のドレインと
の間に形成される蓄積用コンデンサー、LC11m l
ctt t t、c gt IL Cne ”−”はド
レインCD*−D2e D3e n4゜・・・)と
アースされた対向電極(不図示)との間に形成される液
晶層を含むコンデンサーである。Also, T11. T,,, T,,, T22. --- is a TPT configured as described above, and C11s
CL! wC21e CKM e "" is a storage capacitor formed between each gate line of the TPT switching element array and its own drain, LC11m l
ctt t t, c gt IL Cne "-" is a capacitor including a liquid crystal layer formed between a drain CD*-D2e D3e n4°...) and a grounded counter electrode (not shown).
一方、上記と類似の表示セルとしてIEEE Tran
s。On the other hand, as a display cell similar to the above, IEEE Tran
s.
on Electron Devices ED
−20、P、995(1973)に開示されている様な
表示セルもある。on Electron Devices ED
-20, P. 995 (1973).
斯かるセルに係る駆動用スイッチング素子セグメントの
一部の平面図を第3図に示す。A plan view of a portion of a driving switching element segment related to such a cell is shown in FIG.
即ち、複数のゲート線Gl、 G、、・・・がガラス等
の基板上に設けられ、この上に絶縁層(不図示)を介し
て、半導体SCを設ける。該半導体SCの一端にはソー
ス線S11他端には表示用セグメントのドレインD1が
接触して設けられる。該ドレインD1の下面には、半導
体SCが設けられているゲート線G2に対し隣接するゲ
ート線G!に導通した電極Pが対向している。この構成
の等価回路を第4図に示す。この等価回路図に於いて、
(第7図と同様に、)TIは第3図で示°すTFT%L
Clは、ドレインD1とアースされた対向電極(不図示
)との間に形成される液晶層を含むコンデンサー、C1
はTFTのドレインと、該ドレインに対応するゲート線
(G2)に隣接するゲート線(G1)に導通した電極P
との間に形成される蓄積用コンデンサーである。That is, a plurality of gate lines Gl, G, . . . are provided on a substrate made of glass or the like, and a semiconductor SC is provided thereon via an insulating layer (not shown). A source line S11 is provided at one end of the semiconductor SC, and a drain D1 of a display segment is provided at the other end in contact with the source line S11. On the lower surface of the drain D1, a gate line G! adjacent to the gate line G2 provided with the semiconductor SC! Electrodes P that are electrically connected are facing each other. An equivalent circuit of this configuration is shown in FIG. In this equivalent circuit diagram,
(Similar to Figure 7) TI is TFT%L shown in Figure 3.
Cl is a capacitor, C1, including a liquid crystal layer formed between a drain D1 and a grounded counter electrode (not shown).
is an electrode P that is electrically connected to the drain of the TFT and the gate line (G1) adjacent to the gate line (G2) corresponding to the drain.
This is a storage capacitor formed between the
上記の様な回路では、信号が選択されたゲート線に印加
された瞬間に、ソース線の電圧がドレインに加わり表示
がなされる。その立ち上がりの時定数は、半導体のオン
(ON)抵抗と容量(液晶層を、含むコンデンサー及び
蓄積コンデンサーの和)との積で決定される。In a circuit like the one described above, the moment a signal is applied to a selected gate line, the voltage of the source line is applied to the drain and a display is produced. Its rise time constant is determined by the product of the on-resistance of the semiconductor and the capacitance (the sum of the capacitor including the liquid crystal layer and the storage capacitor).
しかしながら、上記いずれの表示セルにも、解決される
べき問題が存在している。例えば、第6図に於いて例示
した駆動用スイッチング素子を備えた表示装置では第7
図の等価回路で示されるように、蓄積用コンデンサー〇
、1の対極はアドレスを行うためのゲート線を対極とす
ることになり、このコンデンサーに所定の電圧を付与す
るには、ゲート信号電圧に対する差分の電圧をPlに供
給しなければならない。更に液晶の容量成分LC1□が
無視できない大きさを持つ時には、C□とLC11の容
量比に応じて補正された信号をP、に与えなければなら
ず、複雑な信号処理を必要とする。又別の問題は、この
ような構成のセルでは、構成の一部を成す半導体が不透
明であうたり、光導電性を有する意味で表示部を透過型
にでき難い点である。However, both of the display cells described above have problems that need to be solved. For example, in the display device equipped with the driving switching element illustrated in FIG.
As shown in the equivalent circuit in the figure, the opposite electrodes of storage capacitors 〇 and 1 are the opposite electrodes of the gate line for addressing, and in order to apply a predetermined voltage to this capacitor, The differential voltage must be supplied to Pl. Furthermore, when the capacitance component LC1□ of the liquid crystal has a size that cannot be ignored, a signal corrected according to the capacitance ratio between C□ and LC11 must be given to P, which requires complicated signal processing. Another problem is that in a cell having such a structure, the semiconductor forming a part of the structure may be opaque, and it is difficult to make the display section a transmissive type in the sense that it has photoconductivity.
一方、第3図に示す駆動用スイッチング素子を備えた表
示装置の構成では、第4図の等価回路に見る通り、G2
がONの時、G1が接地であれば、S1の信号電圧はC
,に蓄積され、G2がOFFになった後、S1に与えた
所定の電圧がLClに印加されることとなり回路から見
た点では問題を生じない。On the other hand, in the configuration of the display device equipped with the driving switching element shown in FIG. 3, as shown in the equivalent circuit of FIG.
is ON, if G1 is grounded, the signal voltage of S1 is C
, and after G2 is turned off, the predetermined voltage applied to S1 will be applied to LCl, causing no problem from the perspective of the circuit.
ところが、このセルは本来透過型構成が可能な構造であ
りなiら、実際に透過型セルとして製造するためには問
題を生ずる。即ち、蓄積用コンデンサー08の対極とし
て、絶縁層(不図示)を介して、ドレインD、の下にP
なる電極を形成しな(ではならない。一般に表示絵素単
位となるDIの面積は、有効表示面積として大きくした
い、同時にこの絵素を高密度化しようとする時、非表示
部となるゲート線G1はできるだけ細(しなければなら
ない。ところが、細線化すれば、抵抗値が上昇するので
、この点では導電性の良い金属膜の使用が必要となる。However, since this cell originally has a structure that allows a transmission type structure, problems arise when actually manufacturing it as a transmission type cell. That is, as a counter electrode of the storage capacitor 08, P is connected below the drain D through an insulating layer (not shown).
In general, when you want to increase the effective display area of DI, which is a display pixel unit, and at the same time increase the density of this pixel, the gate line G1, which is a non-display area, must be formed. The wire must be made as thin as possible. However, if the wire is made thinner, the resistance value will increase, so in this respect it is necessary to use a metal film with good conductivity.
従って、表示絵素つまりドレインD1の対極用電極Pを
透過型として構成する為に透明導電膜を使用すれば、こ
のゲート線金属と透明導電膜と異なる部材を用いること
になる。この構成は微細パターンを形成する時、加工方
法を難しくすると同時に工程が増して好ましくない。こ
の様に第3図の構成は回路的には第1図のものより都合
が良く、又透過型セルが構成できる長所も有するが、製
造上は複雑であり、又加エニ数も多くなる欠点も持つ。Therefore, if a transparent conductive film is used to constitute the display picture element, that is, the counter electrode P of the drain D1, as a transmission type, members different from the gate line metal and the transparent conductive film will be used. This configuration is not preferable because it makes the processing method difficult and increases the number of steps when forming a fine pattern. In this way, the configuration shown in Figure 3 is more convenient than the one shown in Figure 1 in terms of circuitry, and has the advantage of being able to configure a transmission type cell, but it has the disadvantages that it is complicated to manufacture and requires a large number of parts to be added. also have
そこで本発明は上記諸点に鑑みてなされたものであり、
第1の目的は高密度な画素を有する表示装置を、高い信
頼性を保ち、生産しやすい表示用パネルとして与えるこ
とである。又他の目的は簡略な駆動方法によって、安定
した均一な画像特性を示す表示装置を与えることにある
。更に本発明の別の目的は上記二つの目的に適した透過
型表示パネルを与えることである。Therefore, the present invention has been made in view of the above points,
The first objective is to provide a display device having high density pixels as a display panel that maintains high reliability and is easy to produce. Another object of the present invention is to provide a display device that exhibits stable and uniform image characteristics using a simple driving method. Furthermore, another object of the present invention is to provide a transmissive display panel suitable for the above two purposes.
叙上の目的を達成する本発明の表示駆動装置は、a、複
数の行及び列に沿って配列した複数の薄膜トランジスタ
、行に沿って配列した複数の薄膜トランジスタのゲート
を共通に接続したゲート線、列に沿って配列した複数の
薄膜トランジスタのソースを共通に接続したソース線、
並びに薄膜トランジスタ毎のドレインと並列接続した第
1のコンデンサ及び2第のコンデンサを有し、第1のコ
ンデンサが薄膜トランジスタのドレインと接続したセグ
メント電極、該セグメント電極と対向配置した第1の対
向電極及び該セグメント電極と第1の対向電極との間に
配置した液晶層によって形成され、且つ第2のコンデン
サが前記セグメント電極、該セグメント電極の背面に対
向配置し、薄膜トランジスタのゲートと絶縁した第2の
対向電極及び該セグメント電極と第2の対向電極との間
に配置した絶縁膜によりて形成され、該第2のコンデン
サの第2の対向電極を共通に接続するための接続導電部
を有する回路、並びに
す、選択されたゲート線に駆動電圧を印加し、ソース線
に画像情報に応じた信号を印加し、第1の対向電極と第
2の対向電極とを電気的に独立にバイアス電圧を印加す
る手段
を有する駆動装置を特徴としている。A display driving device of the present invention that achieves the above objects includes: a) a plurality of thin film transistors arranged along a plurality of rows and columns; a gate line commonly connecting the gates of the plurality of thin film transistors arranged along the rows; A source line that commonly connects the sources of multiple thin film transistors arranged along a column,
and a segment electrode having a first capacitor and a second capacitor connected in parallel with the drain of each thin film transistor, the first capacitor being connected to the drain of the thin film transistor, a first counter electrode disposed opposite to the segment electrode, and a first counter electrode disposed opposite to the segment electrode. A second capacitor is formed by a liquid crystal layer disposed between a segment electrode and a first counter electrode, and a second capacitor is disposed opposite to the segment electrode, and a second capacitor is disposed opposite to the back surface of the segment electrode and insulated from the gate of the thin film transistor. a circuit formed of an electrode and an insulating film disposed between the segment electrode and a second opposing electrode, and having a connecting conductive part for commonly connecting the second opposing electrodes of the second capacitor; A driving voltage is applied to the selected gate line, a signal according to image information is applied to the source line, and a bias voltage is applied to the first counter electrode and the second counter electrode electrically independently. The invention is characterized by a drive device having means.
以下、本発明を図面によって説明する。 Hereinafter, the present invention will be explained with reference to the drawings.
第5図は本発明に係る駆動用スイッチング素子アレイを
設けた基板の略画的斜視図である。ガラス等からなる基
板B、上に導電膜TC1が全面に形成されている。更に
この上面に絶縁層1.が積層されている。本発明ではこ
のような加工を施した基板上に通常のTFTアレイを構
成してなるものである。FIG. 5 is a schematic perspective view of a substrate provided with a driving switching element array according to the present invention. A conductive film TC1 is formed over the entire surface of a substrate B made of glass or the like. Furthermore, an insulating layer 1 is formed on this upper surface. are layered. In the present invention, a normal TFT array is constructed on a substrate subjected to such processing.
絶縁層■1の上にゲート線Gl* cll!が設けられ
、このゲート構成部では後に重置する半導体下面に延在
するようパターンが形成されている。このゲート線G、
、G、、・・・の上に別途絶縁層■2が全面に形成され
ている。そして、前記ゲート構成部の上に絶縁層12を
介して薄膜半導体sc、、sc2.sc3゜SC4,・
・・が図示の如(形成されている。この半導体sc、、
sc2. sc3. sc4.−・・の一端に接して
、前記ゲート線と直交するソース線s、 # 521−
・・が設けられ、更に前記各半導体の他端に接してドレ
インD1.D、、D3.D4.−・・が設けられる。こ
れ等のドレインD1 + D2 w D3 e D4
−・は何れも蓄積用コンデンサーの一方の電極であると
同時に表示絵素用のセグメント電極を兼ねるものである
。このように構成した駆動用スイッチング素子アレイを
有する基板と、別に、その片面に電極を形成した基板と
で電気光学的変調材料を挾持した構成の表示セルの部分
断面構造を、第1図に示す。なお、第1図に於ける図面
下側の基板の構成は第5図のA−A断面を示したもので
ある。そして、第1図中、下部の基板に関しては第5図
と同一の記号を用いているものは同一の部材であり第5
図の説明−を援用して、ここでは、その説明を省く。図
面上側の基板B2の片面には薄膜電極TC,が形成され
ている。この両基板B、、 B、が所定の間隙を保つよ
うスペーサ(不図示)を介して互いに対向させ電気光学
変調材料LCを挾持させた後周囲を密閉シールして第1
図に図示した表示装置が構成される。このような表示装
置の−絵素分についての等価回路を第2図に示す。A gate line Gl* cll! is placed on the insulating layer ■1. is provided, and a pattern is formed in this gate component so as to extend to the lower surface of the semiconductor that will be superimposed later. This gate line G,
, G, . . . , an additional insulating layer 2 is formed over the entire surface. Then, thin film semiconductors sc, sc2 ., sc2 . sc3゜SC4,・
. . is formed as shown in the figure. This semiconductor sc, .
sc2. sc3. sc4. - a source line s, #521-, in contact with one end of the gate line and perpendicular to the gate line;
... are provided, and a drain D1... is provided in contact with the other end of each of the semiconductors. D,,D3. D4. -... is provided. These drains D1 + D2 w D3 e D4
- and both serve as one electrode of a storage capacitor and also serve as segment electrodes for display picture elements. FIG. 1 shows a partial cross-sectional structure of a display cell having an electro-optic modulating material sandwiched between a substrate having a drive switching element array constructed in this way and a separate substrate having an electrode formed on one side. . Note that the configuration of the substrate on the lower side of the drawing in FIG. 1 is shown in the AA cross section of FIG. 5. In Fig. 1, the same symbols as in Fig. 5 are used for the lower board, and they are the same members.
The explanation of the figure will be omitted here with reference to the explanation of the figure. A thin film electrode TC is formed on one side of the substrate B2 on the upper side of the drawing. These two substrates B, , B are made to face each other with a spacer (not shown) in between so as to maintain a predetermined gap, and after sandwiching the electro-optic modulation material LC, the periphery is hermetically sealed and the first
The display device illustrated in the figure is constructed. An equivalent circuit for one picture element of such a display device is shown in FIG.
第2図に於いてS、、 S、はソース線、GK、G2は
ゲート線で第5図に示すものと同一要素である。In FIG. 2, S, , S are source lines, GK and G2 are gate lines, which are the same elements as shown in FIG. 5.
LC□はドレイン電極り、と対向電極TC,が電気光学
的変調材料LCを挟んで構成される表示絵素である。C
1は蓄積用コンデンサーで、ドレイン電極D1と、本発
明に特有の電極TC1とによって絶縁層■、を介して形
成されたコンデンサーである。LC□ is a display picture element composed of a drain electrode and a counter electrode TC sandwiching an electro-optic modulating material LC. C
Reference numeral 1 denotes a storage capacitor, which is formed by a drain electrode D1 and an electrode TC1 specific to the present invention, with an insulating layer 2 interposed therebetween.
そして、TIはGiのゲート構成部上に絶縁層■2を介
して設けた半導体SC□にオーミックな接続をしてなる
ソース電極S1とドーレインD、が所定のギャップで形
成するMOS形のトランジスタである。TI is a MOS transistor in which a source electrode S1 and a drain D are formed with a predetermined gap and are ohmically connected to a semiconductor SC□ provided on a Gi gate component via an insulating layer 2. be.
叙上の図示例による本発明の特徴はC1が常時対−極を
接地状態で作動でき、先に説明した第4図に示す等価回
路に類似して動作させやすいこ′と。又ゲート線と蓄積
用コンデンサーの対極を一体化しないため同一部材を用
いないで済み、蓄積コンデンサーの対極としてのパター
ニングが不要であると同時に、透過型構成に表示装置を
製作する時、設計に任意性がもたらされる。即ち、ゲー
ト線を細線化する時抵抗値が上昇するのを防ぐ意味で良
導電性の金属部材を使用する場合、TClに対しては透
明導電膜で構成する如き構成が可能となる点である。又
このような構成では半導体SC、。The feature of the present invention according to the above-described illustrated example is that C1 can be operated with its opposite pole always grounded, and is easy to operate in a manner similar to the equivalent circuit shown in FIG. 4 described above. In addition, since the gate line and the counter electrode of the storage capacitor are not integrated, it is not necessary to use the same material, and there is no need to pattern the counter electrode of the storage capacitor. sex is brought about. In other words, if a metal member with good conductivity is used to prevent the resistance value from increasing when the gate line is made thinner, a structure such as a transparent conductive film can be used for TCl. . Also, in such a configuration, the semiconductor SC.
sc、、sc 3.sc 4−・・等の下部だけ金属ゲ
ートが設けられるので、各半導体への下部基板B1側か
ら入射する光によって、半導体sc、、sc2゜5C,
,SC4−・・が光導電的影響を生じるのを防止できる
と言う効果も付加される。sc,,sc 3. Since a metal gate is provided only at the lower part of the semiconductors sc 4-, etc., the semiconductors sc, , sc2°5C,
, SC4-... can be prevented from producing photoconductive effects.
本発明による効果は透過型構成を採用−するときのみに
止まるものではない。即ち反射型の表示装置を構成する
場合には、−ドレインの各絵素とソース線間に生ずる隙
間に対して、各ドレインの反射性金属と同一の部材によ
って導電膜TC,を形成すれば、見掛士光学的に一様な
反射性をもった表示面が構成でき、しかも前述の如き動
作上の効果をも製造しやすい構成で得られる。更に前述
のように下部基板B1の側から入射する光の遮蔽効果も
透過型表示装置の場合以上に強イしできる。The effects of the present invention are not limited to the adoption of a transmission type configuration. That is, when configuring a reflective display device, if a conductive film TC is formed from the same material as the reflective metal of each drain in the gap between each picture element of the drain and the source line, A display surface having optically uniform reflectivity can be constructed, and the operational effects as described above can also be obtained with a construction that is easy to manufacture. Furthermore, as described above, the effect of blocking light incident from the side of the lower substrate B1 can be enhanced more than in the case of a transmissive display device.
これ等透過型構造や反射型構造のいずれにおいても得ら
れる更に別の効果も本発明にはある。即ち、第1図に示
した本発明による構成は上基板B2の全面に導電層TC
,,下基板B1の回路構成層の下側に別の導電層TC1
が形成されており、これを第2図に示すように両者共接
地すれば、このTFTアレイ回路部は外部電界に対して
シールド効果をもたらす点である。このようなシールド
効果はMOS構造のトランジスタの安定動作に対して有
利となる。又、本発明ではこれ等の導電膜TC,。The present invention also has other effects that can be obtained with either the transmission type structure or the reflection type structure. That is, the structure according to the present invention shown in FIG. 1 has a conductive layer TC on the entire surface of the upper substrate B2.
,,Another conductive layer TC1 is provided below the circuit structure layer of the lower substrate B1.
is formed, and if both are grounded as shown in FIG. 2, this TFT array circuit section provides a shielding effect against external electric fields. Such a shielding effect is advantageous for stable operation of a transistor having a MOS structure. Further, in the present invention, these conductive films TC.
Te3は電気的に独立であるから、必要に応じて、一方
のみ又は両方に所定のバイアス電圧を印加することもで
きる。Since Te3 is electrically independent, a predetermined bias voltage can be applied to only one or both, if necessary.
以上述べたように、本発明は表示装置に係る製造技術上
の効果と駆動上の効果を兼ね備えたものである。As described above, the present invention has both manufacturing technology advantages and driving effects related to display devices.
本発明で使用される材料は基板(B*t B2)として
、ガラスが一般的なものであるが、表示装置を反射型に
する場合には、一方を金属、セラミツ。The material used in the present invention is generally glass as the substrate (B*t B2), but when the display device is of a reflective type, one side is made of metal or ceramic.
クス等不透明な材料としても良い。It may also be made of an opaque material such as camphor.
導電性材料、即ちゲート線G、、G、、−・−、ソース
線Sls S!w”・・、ドレインD、、D、、D3
゜D4.−・・対向電極” C2m導電膜TC,には、
透明性を要する時にはIn 203 、 Sn02等の
透明導電性無機酸化物の薄膜不透光性で良い場合は、A
1. Ag、 Pd、 Pt、 Cr、 Ni、
Me、 Si等の金属又は合金による薄膜を用いる。更
に絶縁層としてはSin、 Si02 、 Ti02
、 Zr02 、 AjF 203 。Conductive materials, i.e. gate lines G,,G,, -.-, source lines Sls S! w”..., drain D,,D,,D3
゜D4. -...The counter electrode "C2m conductive film TC,"
When transparency is required, a thin film of transparent conductive inorganic oxide such as In 203 or Sn 02 may be used.
1. Ag, Pd, Pt, Cr, Ni,
A thin film made of metal or alloy such as Me or Si is used. Furthermore, as an insulating layer, Sin, Si02, Ti02
, Zr02, AjF 203.
CeO2等の金属酸化物、MgF2.CaF2等のハロ
ゲン化物、チッ化シリコン等から適宜選ばれる。半導体
SC,,SC2,SC3,SC4,−・・としてはCd
S、CdSe、Se、Teの他のアモルファスシリコン
等が選択使用される。Metal oxides such as CeO2, MgF2. It is appropriately selected from halides such as CaF2, silicon nitride, and the like. The semiconductors SC,,SC2,SC3,SC4,-... are Cd
Amorphous silicon other than S, CdSe, Se, Te, etc. are selectively used.
電気光学的変調材料LCとしては液晶、EC(エレクト
ロクロミー)、EL (エレクトロルミネッセンス)等
が用いられる。液晶は、表示動作モードに応じてネマテ
ィック、コレステリック、スメクテイツクを示す液晶の
単体及び混合物を用いる。As the electro-optic modulation material LC, liquid crystal, EC (electrochromy), EL (electroluminescence), etc. are used. The liquid crystal used may be a single liquid crystal or a mixture of liquid crystals exhibiting nematic, cholesteric, or smectic properties depending on the display operation mode.
これ等の表示動作モードはいわゆるTN、DAP。These display operation modes are so-called TN and DAP.
DSM、RAN、ゲストホスト、相転移等いずれのタイ
プであっても良(、選択したモードと表示効果から、適
当な光学的検知手段(λ/4板、偏光板、反射板、カラ
ーフィルター、レンズ、照明装置)を適宜選択して本発
明装置に付加する。It can be any type such as DSM, RAN, guest host, phase change, etc. (Depending on the selected mode and display effect, use appropriate optical detection means (λ/4 plate, polarizing plate, reflector, color filter, lens). , lighting device) are selected as appropriate and added to the device of the present invention.
本発明で用いるコンデンサは、その対極がゲート線から
絶縁されているため、ゲート線とは独立にバイアス電圧
を設定することができ、キャパシタとなる絶縁膜が第6
図に示す様にコンデンサ対極の導電膜をゲートから絶縁
する時に用いた絶縁膜から延長して形成されているため
、コンデンサ対極となる導電膜が基板上の全面に亘って
形成することができ、このため外部の電圧から薄膜トラ
ンジスタをシールドすることができる。Since the counter electrode of the capacitor used in the present invention is insulated from the gate line, the bias voltage can be set independently of the gate line, and the insulating film that becomes the capacitor is the sixth
As shown in the figure, since the conductive film for the capacitor counter electrode is formed extending from the insulating film used to insulate the capacitor from the gate, the conductive film for the capacitor counter electrode can be formed over the entire surface of the substrate. Therefore, the thin film transistor can be shielded from external voltage.
従って、本発明によれば、例えば液晶駆動の温度補償を
与えるために、コンデンサ対極の導電膜にバイアス電圧
を設定しても、この電圧による薄膜トランジスタの誤動
作を生じることがない。Therefore, according to the present invention, even if a bias voltage is set on the conductive film of the counter electrode of the capacitor, for example, in order to provide temperature compensation for driving the liquid crystal, the thin film transistor does not malfunction due to this voltage.
軟土の本発明による表示装置は駆動性、生産性、信頼性
が良く高密度画素を持つ、小型表示器として、テレビ、
ビデオカメラ用モニタ一等の表示装置に好適に使用する
ことができる。The display device made of soft clay according to the present invention has good drive performance, productivity, and reliability, and has high-density pixels, and can be used as a small display device for televisions,
It can be suitably used for display devices such as video camera monitors.
第1図は、本発明表示装置の構成例の部分断面図であり
、第2図は本発明の駆動装置に於ける−絵素分の等価回
路図である。第3図及び第6F!4は、従来の駆動用ス
イッチング素子アレイの構成例を示す説明図であり、第
4図は第3図の等価回路図であり、第5図は本発明に係
る駆動用スイッチング素子アレイ設置基板の略画的構成
図、第7図は第6図の等価回路図である。
図に於いて、Blp B11は基板、TC,は導電膜、
TC2は薄膜電極、■1.1□は絶縁層、G、、G。
はゲート線、Sl、S2はソース線、SC1,SC2゜
SC3,SC4は半導体、D1e D2e D35 D
4はドレイン、LCは電気光学的変調材料である。FIG. 1 is a partial sectional view of a configuration example of a display device of the present invention, and FIG. 2 is an equivalent circuit diagram of a -picture element in a driving device of the present invention. Figure 3 and 6th floor! 4 is an explanatory diagram showing a configuration example of a conventional driving switching element array, FIG. 4 is an equivalent circuit diagram of FIG. 3, and FIG. 5 is an illustration of a driving switching element array installation board according to the present invention. The schematic configuration diagram, FIG. 7, is an equivalent circuit diagram of FIG. 6. In the figure, Blp B11 is a substrate, TC is a conductive film,
TC2 is a thin film electrode, ■1.1□ is an insulating layer, G, ,G. is a gate line, SL, S2 are source lines, SC1, SC2° SC3, SC4 are semiconductors, D1e D2e D35 D
4 is a drain, and LC is an electro-optic modulation material.
Claims (1)
ジスタ、行に沿って配列した複数の薄膜トランジスタの
ゲートを共通に接続したゲート線、列に沿って配列した
複数の薄膜トランジスタのソースを共通に接続したソー
ス線、並びに薄膜トランジスタ毎のドレインと並列接続
した第1のコンデンサ及び第2のコンデンサを有し、第
1のコンデンサが薄膜トランジスタのドレインと接続し
たセグメント電極、該セグメント電極と対向配置した第
1の対向電極及び該セグメント電極と第1の対向電極と
の間に配置した液晶層によって形成され、且つ第2のコ
ンデンサが前記セグメント電極、該セグメント電極の背
面に対向配置し、薄膜トランジスタのゲートと絶縁した
第2の対向電極及び該セグメント電極と第2の対向電極
との間に配置した絶縁膜によって形成され、該第2のコ
ンデンサの第2の対向電極を共通に接続するための接続
導電部を有する回路、並びに b、選択されたゲート線に駆動電圧を印加し、ソース線
に画像情報に応じた信号を印加し、第1の対向電極と第
2の対向電極とを電気的に独立にバイアス電圧を印加す
る手段 を有する駆動装置。[Claims] a. A plurality of thin film transistors arranged along a plurality of rows and columns, a gate line that commonly connects the gates of the plurality of thin film transistors arranged along the rows, and a plurality of thin film transistors arranged along the columns. a source line to which the sources of the thin film transistors are commonly connected, and a first capacitor and a second capacitor connected in parallel to the drain of each thin film transistor, a segment electrode in which the first capacitor is connected to the drain of the thin film transistor; a liquid crystal layer disposed between the segment electrode and the first counter electrode; Formed by a second counter electrode insulated from the gate of the thin film transistor and an insulating film disposed between the segment electrode and the second counter electrode, and for commonly connecting the second counter electrodes of the second capacitor. and (b) applying a driving voltage to the selected gate line, applying a signal according to image information to the source line, and electrically connecting the first counter electrode and the second counter electrode. A drive device having means for independently applying a bias voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1109527A JPH0225A (en) | 1989-04-28 | 1989-04-28 | Driving device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1109527A JPH0225A (en) | 1989-04-28 | 1989-04-28 | Driving device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14186979A Division JPS5665176A (en) | 1979-09-06 | 1979-10-31 | Display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0225A true JPH0225A (en) | 1990-01-05 |
Family
ID=14512521
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1109527A Pending JPH0225A (en) | 1989-04-28 | 1989-04-28 | Driving device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0225A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0634800A1 (en) * | 1993-07-12 | 1995-01-18 | Philips Electronics Uk Limited | An imaging device |
JP2002189429A (en) * | 2000-09-06 | 2002-07-05 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
WO2005048354A1 (en) * | 2003-11-14 | 2005-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element, method for manufacturing the same, liquid crystal display device, and method for manufacturing the same |
JP2007256914A (en) * | 2006-02-21 | 2007-10-04 | Seiko Epson Corp | Active matrix substrate, electro-optic device and electronic apparatus |
KR100849771B1 (en) * | 2002-05-30 | 2008-07-31 | 샤프 가부시키가이샤 | Substrate for liquid crystal display and liquid crystal display device having the substrate and manufacturing method thereof |
US7598129B2 (en) | 2003-11-14 | 2009-10-06 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device and method for manufacturing the same |
US7977680B2 (en) | 2000-09-06 | 2011-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having thin film transistors on a metal substrate |
KR20160114925A (en) | 2015-03-25 | 2016-10-06 | 홍광의 | dividing 2 step, heating medium of oil, disassembled fermentation , and waste handling equipment which make use of microorganisms organaized ripen of 1 and 2 age. |
-
1989
- 1989-04-28 JP JP1109527A patent/JPH0225A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0634800A1 (en) * | 1993-07-12 | 1995-01-18 | Philips Electronics Uk Limited | An imaging device |
JP2002189429A (en) * | 2000-09-06 | 2002-07-05 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
US7977680B2 (en) | 2000-09-06 | 2011-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having thin film transistors on a metal substrate |
KR100849771B1 (en) * | 2002-05-30 | 2008-07-31 | 샤프 가부시키가이샤 | Substrate for liquid crystal display and liquid crystal display device having the substrate and manufacturing method thereof |
WO2005048354A1 (en) * | 2003-11-14 | 2005-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element, method for manufacturing the same, liquid crystal display device, and method for manufacturing the same |
US7598129B2 (en) | 2003-11-14 | 2009-10-06 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device and method for manufacturing the same |
US8053780B2 (en) | 2003-11-14 | 2011-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element, method for manufacturing the same, liquid crystal display device, and method for manufacturing the same |
US8518728B2 (en) | 2003-11-14 | 2013-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element, method for manufacturing the same, liquid crystal display device, and method for manufacturing the same |
JP2007256914A (en) * | 2006-02-21 | 2007-10-04 | Seiko Epson Corp | Active matrix substrate, electro-optic device and electronic apparatus |
KR20160114925A (en) | 2015-03-25 | 2016-10-06 | 홍광의 | dividing 2 step, heating medium of oil, disassembled fermentation , and waste handling equipment which make use of microorganisms organaized ripen of 1 and 2 age. |
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