JP2001094113A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a thin-film transistor. SOLUTION: A gate electrode is formed of a first electrode 108 having tapered section, and a second electrode 109 having a width narrower than that of the first electrode 108. In a semiconductor layer, phosphorus is doped at low concentration via the first gate electrode 108, and two kinds of n-type impurity regions 124 to 127 are formed at the region between a channel-forming region 121 and n-type impurity regions 122, 123. The n-type impurity regions 124, 125 are overlapped with the gate electrode, but the regions 126, 127 are not overlapped therewith. By forming two kinds of n-type impurity regions, off-current can be reduced, and at the same time, characteristics can be prevented from deteriorating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter referred to as TFT) and a semiconductor device having a circuit composed of the thin film transistor. For example, the present invention relates to a configuration of an electro-optical device typified by a liquid crystal display panel as a semiconductor device and an electronic device equipped with such an electro-optical device as a component. Note that in this specification, a semiconductor device generally means a device that functions by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are also semiconductor devices.

[0002]

2. Description of the Related Art Recently, a TF using a crystalline silicon film has been developed.
An active matrix type liquid crystal display device in which a circuit is configured with T has attracted attention. This is to realize a high-definition image display by controlling the electric field applied to the liquid crystal in a matrix by a plurality of pixels arranged in a matrix.

In such an active matrix type liquid crystal display device, as the resolution becomes higher, such as XGA or SXGA, the number of pixels alone exceeds one million. A driver circuit for driving all of them is very complicated and formed by many TFTs.

The specifications required for an actual liquid crystal display device (also referred to as a liquid crystal panel) are strict, and high reliability is required for both pixels and drivers in order for all pixels to operate normally. In particular, when an abnormality occurs in the driver circuit, a defect called a line defect occurs in which pixels in one column (or one row) are completely annihilated.

[0005] However, T using a crystalline silicon film.
FT is an M which is still used in LSIs etc. in terms of reliability.
It is said to be inferior to OSFETs (transistors formed on a single crystal semiconductor substrate). Unless this weakness is overcome, it is becoming increasingly difficult to form an LSI circuit using TFTs.

As a structure for improving the reliability of a TFT,
GOLD (Gate Overlapped Light-doped Drain) and L
ATID (Large-Tilt-Angle Implanted Drain) and the like are known. The feature of these structures is that the LDD region and the gate electrode overlap. This makes it possible to reduce the impurity concentration in the LDD region, thereby increasing the effect of relaxing the electric field and increasing the hot carrier resistance. Increase.

For example, "M. Hatano, H. Akimoto, and T. Sak
ai, IEDM97 TECHNICAL DIGEST, p523-526, 1997 ”, a TFT having a GOLD structure is realized by using a sidewall formed of silicon.

However, the GOL disclosed in the same paper
The off current (TFT) in the D structure is lower than that in the normal LDD structure.
However, there is a problem that the current flowing when the transistor is in the off state increases, and a countermeasure for that problem is required.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the drawbacks of the GOLD structure TFT, to provide a TFT with reduced off-current and high hot carrier resistance. It is another object of the present invention to realize a highly reliable semiconductor device including a semiconductor circuit in which a circuit is formed using such a TFT.

[0010]

In order to solve the above-mentioned problems, a thin film transistor according to the present invention comprises an n-type or p-type first thin film which functions as a source region or a drain region in a semiconductor layer where a channel is formed. In addition to the impurity regions, impurity regions (second and third regions) having the same conductivity type as the two types of first impurity regions are provided between the channel and the first impurity region.
Impurity region). These second and third impurity regions have lower impurity concentrations that determine the conductivity type than the first impurity region, and function as high-resistance regions.

The second impurity region is a low-concentration impurity region overlapping with the gate electrode via the gate insulating film, and has a function of improving hot carrier resistance. On the other hand, the third impurity region is a low-concentration impurity region that does not overlap with the gate electrode, and has a function of preventing an increase in off-state current.

Note that the gate electrode is an electrode that intersects the semiconductor layer with a gate insulating film interposed therebetween, and is an electrode for applying an electric field to the semiconductor layer to form a depletion layer. In the gate wiring, a portion intersecting the semiconductor layer with the gate insulating film interposed therebetween is a gate electrode.

Further, in the present invention, the thickness of the gate electrode linearly decreases from the central flat portion toward the outside around the gate electrode. Since the impurity imparting the conductivity type is added to the second impurity region through the tapered portion of the gate electrode, the concentration gradient reflects the inclination of the side surface of the gate electrode (change in film thickness). That is, the second
The impurity concentration added to the impurity region increases from the channel formation region toward the first region.

According to the present invention, in another configuration of the gate electrode, a first gate electrode in contact with the gate insulating film;
A second gate electrode formed over the first gate electrode is stacked. In this configuration, the angle formed by the first gate electrode with the side surface or the gate insulating film is a tapered shape whose value is in a range of 3 degrees or more and 60 degrees or less. On the other hand, the width of the second gate electrode in the channel length direction is smaller than that of the first gate electrode.

In the above-described thin film transistor having a stacked gate electrode, the impurity concentration distribution in the second impurity region reflects a change in the film thickness of the first gate electrode, and the impurity concentration varies from the channel formation region to the first gate electrode. 1 will be increased.

The thin-film transistor according to the present invention has two types of low-concentration impurity regions in the semiconductor layer, so that
It has comparable or even higher reliability than FETs.

(Advantages of Thin Film Transistor of the Present Invention) Referring to FIG. 34, advantages of the present invention will be described in comparison with the characteristics of a conventional TFT.

As described above, according to the present invention, two types of low-concentration impurities, that is, a second impurity region (gate overlap type LDD region) and a third impurity region (non-gate overlap type LDD region) are added to the semiconductor layer. It is characterized by forming.

FIG. 34A is a schematic diagram of an n-channel TFT without an LDD region, and FIG. 34B shows its electrical characteristics (gate voltage Vg vs. drain current Id characteristics). 34 (C) and (D) show the case of a normal LDD structure, and FIGS. 34 (E) and (F) show the case of a so-called GOLD structure. Shows the case of the n-channel TFT of the present invention.

[0020] Incidentally, n ⁺ in the drawings indicates the source or drain region, channel represents a channel formation region, n ^- refers to the low concentration impurity region lower in impurity concentration than the n ^+. Id indicates a drain current, and Vg indicates a gate voltage.

As shown in FIGS. 34A and 34B, the LDD
When there is no such current, the off current (drain current when the TFT is in the off state) is high, and the on current (drain current when the TFT is in the on state) and the off current tend to deteriorate.

On the other hand, by forming a non-gate overlap type LDD, the off-state current can be suppressed considerably, and the deterioration of both the on-state current and the off-state current can be suppressed. However, the deterioration of the on-current is not completely suppressed. (FIG. 3
4 (C), (D))

A TFT structure (GOLD structure) having only an overlap type LDD in which an LDD region overlaps with a gate electrode (FIGS. 34E and 34F).
This structure focuses on suppressing the deterioration of the ON current in the conventional LDD structure.

In this case, while the deterioration of the ON current can be sufficiently suppressed, the ordinary non-overlap type LDD
There is a problem that the off-state current is slightly higher than the structure. The paper described in the conventional example employs this structure, and the present invention recognizes the problem that the off-state current is high and seeks a structure to solve the problem.

The structure of the present invention is shown in FIG.
As shown in (H), an LDD region (second impurity region) overlapping with the gate electrode and an LDD region (third impurity region) not overlapping with the gate electrode were formed in the semiconductor layer. By employing this structure, it is possible to reduce the off-current while keeping the effect of suppressing the deterioration of the on-current.

The present applicant has guessed why the off-state current becomes high in the structure shown in FIGS. 34 (E) and (F) as follows. When the n-channel TFT is off, a negative voltage such as minus several tens of volts is applied to the gate electrode. If a positive voltage of plus several tens of volts is applied to the drain region in that state, a very large electric field is formed at the drain-side end of the gate insulating film.

At this time, holes are induced in the LDD region, and a current path is formed by minority carriers connecting the drain region, the LDD region, and the channel forming region.
This current path is expected to cause an increase in off-state current.

The present applicant considers that in order to cut off such a current path halfway, it is necessary to form another resistor, that is, a third impurity region LDD region at a position not overlapping with the gate electrode. Was. The present invention relates to a thin film transistor having such a configuration and a circuit using the thin film transistor.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

[Embodiment 1] In the present embodiment, the present invention
This is applied to FT. The manufacturing process of this embodiment will be described with reference to FIGS.

First, a base film 101 is formed on the entire surface of the substrate 100, and an island-shaped semiconductor layer 102 is formed on the base film 101. An insulating film 103 serving as a gate insulating film is formed over the entire surface of the substrate 100 so as to cover the semiconductor layer 102. (Figure 1
(A))

As the substrate 100, a glass substrate, a quartz substrate,
A crystalline glass substrate, a stainless steel substrate, or a resin substrate such as polyethylene terephthalate (PET) can be used.

The base film 101 is a film for preventing impurities such as sodium ions from diffusing from the substrate into the semiconductor layer 102 and for improving the adhesion of the semiconductor film formed on the substrate 100. As the base film 101, a single-layer or multilayer film of an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used.

The method of forming the base film 101 is not limited to the CVD method or the sputtering method. When a heat-resistant substrate such as a quartz substrate is used, an amorphous silicon film is formed and thermally oxidized. A method for forming a silicon film can also be used.

In addition to the inorganic insulating film described above, a conductive film such as a metal or alloy such as silicide such as tungsten silicide, chromium, titanium, titanium nitride, or aluminum nitride is used as a lower layer of the base film 101. A multilayer film in which an insulating film is stacked as an upper layer can be used as a base film.

The material and crystallinity of the semiconductor layer 102 may be appropriately selected according to the characteristics required for the TFT. It is possible to use amorphous silicon, amorphous silicon germanium, amorphous germanium, or crystalline silicon, crystalline germanium, or crystalline silicon germanium obtained by crystallizing these amorphous semiconductor films by laser irradiation or heat treatment. it can. The thickness of the semiconductor layer 102 may be 10 to 150 nm.

The insulating film 103 is a film constituting a gate insulating film of the TFT, and is a single-layer film or a multilayer film of an inorganic insulating film of silicon oxide, silicon nitride, or silicon nitride oxide. For example, in the case of a stacked film, a two-layer film of a silicon nitride oxide film and a silicon oxide film, a stacked film in which a silicon nitride film is interposed between silicon oxides, and the like are used.

As a means for forming the insulating film 103, a chemical vapor method (CVD) such as a plasma CVD method or an ECRCVD method or a physical vapor method (PVD) such as a sputtering method may be used.

On the insulating film 103, a first conductive film 104 and a second conductive film 1 constituting a gate electrode (gate wiring) are formed.
05 is formed. (FIG. 1 (B))

The first conductive film 104 forms a first gate electrode (first gate wiring) 108 having a tapered portion. Therefore, a material that can easily perform taper etching is desired. For example, chromium (Cr), tantalum (T
A material containing a) as a main component (composition ratio is 50% or more), and n-type silicon containing phosphorus are typically used. Also, titanium (Ti), tungsten (W), molybdenum (M
o) can be used. Further, not only a single-layer film of these materials but also a multilayer film can be used.
A three-layer film sandwiched between films can be used.

The second conductive film 105 is a film constituting the second gate electrode (second gate wiring) 109, and is made of aluminum (Al), copper (Cu), chromium (Cr), tantalum (Ta), titanium It can be formed of a material containing (Ti), tungsten (W), and molybdenum (Mo) as main components (composition ratio is 50% or more), a phosphorus-containing n-type silicon, a material such as silicide, or the like. However, in the patterning of the first conductive film and the second conductive film, it is necessary to select a material having an etching selectivity.

For example, as the first conductive film 104 / second conductive film 105, n-type Si / Ta, n-type Si / Ta-M
o alloy, Ta / Al, Ti / Al, WN / W, TaN /
A combination such as Ta can be selected. Another index for selecting a material is resistivity. It is desired that the second conductive film 105 be a material having as low a resistivity as possible, that is, a material having a lower sheet resistance than at least the first conductive film 104. This is because a contact is made between the second gate wiring and the upper wiring in order to connect the gate wiring to the upper wiring. The thickness of the first conductive film 104 is 10 to 400 nm, and the thickness of the second conductive film is 10 to 40 nm.
0 nm, so that the total thickness is 200 to 500 nm.

Next, a resist mask 106 is formed on the second conductive film 105. The second conductive film 105 is etched using the resist mask 106 to form a second gate electrode 109. For the etching, isotropic wet etching may be used. In the case where an etching selectivity with the first conductive film 104 can be obtained, dry etching can be used. (Fig. 1 (C))

Using the same resist mask 106, the first
The first conductive film 104 is anisotropically etched (so-called tapered etching) to form a first gate electrode (first gate wiring) 108. In addition, a new resist mask can be formed for this etching.

By this etching, as shown in FIG. 3, the taper angle θ between the side surface of the gate electrode 108 and the gate insulating film 103 is set to a value in the range of 3 degrees to 60 degrees. The taper angle θ is preferably in a range of 5 degrees or more and 45 degrees or less, and more preferably in a range of 7 degrees or more and 20 degrees or less. The smaller the angle θ, the smaller the change in the film thickness of the tapered portion of the gate electrode 108, and correspondingly, the change in the n-type or p-type impurity concentration is moderated at the portion intersecting the tapered portion of the semiconductor layer. be able to.

As shown in FIG. 3, the taper angle θ can be defined as tan θ = HG / WG using the width WG and thickness HG of the tapered portion.

The resist mask 106 is removed, and a predetermined conductivity type (n-type or p-type) impurity is added to the semiconductor layer 102 using the gate electrodes 108 and 109 as a mask. As an addition method, an ion implantation method or an ion doping method can be used. The n-type impurity is an impurity serving as a donor, and is a Group 15 element for silicon and germanium, and is typically phosphorus (P) or arsenic (As). p
The type impurity is an impurity serving as an acceptor, and is a Group 13 element for silicon and germanium, and is typically boron (B).

Here, phosphorus is added by an ion doping method to form n ⁻ -type impurity regions 111 and 112. In this addition step, n ⁻ -type second impurity regions 124 and 125 and n ⁻ -type third impurity regions 126 and 1
The concentration distribution of the n-type impurity at 27 is determined. In this specification, the term “n ⁻ type” indicates that the impurity concentration as a donor is lower and the sheet resistance is higher than that of the n ⁺ type. (Figure 2
(A))

Since phosphorus is added to the n ⁻ -type impurity regions 111 and 112 through the tapered portion of the first gate electrode 108, the concentration gradient is as shown in FIG. Reflects the change in film thickness. That is, when attention is paid to a depth at which an arbitrary concentration is obtained in the concentration distribution of phosphorus in the depth direction, the concentration gradient has a profile reflecting the inclination of the tapered portion of the gate electrode.

Further, as described later, the concentration gradient of the n ⁻ -type impurity regions 111 and 112 also depends on the acceleration voltage at the time of doping. In the present invention, phosphorus is used for the first gate electrode 1.
08 to pass through the tapered portion and the insulating film 103.
The acceleration voltage for doping needs to be set as high as 40 to 100 keV. Also, with this acceleration voltage, phosphorus can pass through a portion where the thickness of the tapered portion of the gate electrode 108 is 100 nm or less.

In FIG. 2A, n ⁻ type impurity region 11 is formed.
In FIGS. 1 and 112, the region overlapping with the first gate electrode 108 is indicated by hatching and a white background. This does not indicate that phosphorus is not added to the white background, but is described above. As described above, it is possible to intuitively understand that the phosphorus concentration distribution in this region reflects the thickness of the tapered portion of the first gate electrode 108. This is the same in other drawings of this specification.

Next, a resist mask 120 is formed to cover the gate electrodes 108 and 109. The length of the third impurity region is determined by the mask 120. Via the resist mask 120, phosphorus, which is an n-type impurity, is again added to the semiconductor layer 102 by an ion doping method.
(FIG. 2 (B))

N not covered with the resist mask 120
Phosphorus is selectively added to the ⁻ type impurity regions 111 and 112 to form n ⁺ type first impurity regions 122 and 123. In addition, the region 121 covered with the second gate electrode 109 becomes a channel formation region because phosphorus is not added in the addition step of FIGS. 2A and 2B.

Also, n ⁻ type impurity regions 111 and 112
In FIG. 2B, regions where phosphorus is not added in the addition step of FIG. 2B are low-concentration impurity regions 124 to 127 having higher resistance than the source / drain regions.

A low-concentration impurity region 124 overlapping (overlapping) with the first gate electrode 108;
Reference numeral 125 denotes an n ⁻ -type second impurity region, and low-concentration impurity regions that do not overlap with the first electrode 108 become n ⁻ -type third impurity regions 126 and 127.

Note that the insulating film 103 may be etched using the gate wiring as a mask to partially expose the surface of the semiconductor layer 102 prior to the adding step of FIG. 2B.

As shown in FIG. 4, the second impurity region 12
4 can be classified into four types. FIG. 4 is divided into FIGS.
Were assigned A to D. Although not shown in FIG. 4, the other second impurity region 125 formed symmetrically with the gate electrode 109 interposed therebetween is similar to the region 124.

As shown in FIG. 4A, the concentration of phosphorus in the second impurity region 124A is
8 is inversely proportional to the change in the thickness of the tapered portion.
From the impurity region 126A to the channel forming region 121A. That is, when the concentration of phosphorus in the second impurity region 124A is averaged in the depth direction, the averaged concentration of phosphorus is
A increases from A to the third impurity region 126A.

In this case, in the third impurity region 126A, the phosphorus concentration averaged in the thickness direction becomes substantially uniform in the region 126A. Further, since no phosphorus is added to the semiconductor layer covered with the second gate electrode 109, this region becomes a channel formation region 121A and a channel length is reduced.
LA is the width of the second gate electrode 109 in the channel length direction.

Further, in the phosphorus addition step of FIG.
FIG. 4 shows a case where the acceleration voltage is higher than that in the case of FIG.
As shown in (B), the second impurity region 124B has
Phosphorus is also added to the junction with the channel formation region 121B. Also in this case, the channel formation region 121B is
Is a region covered with the gate electrode 109 of FIG.
LB is the width of the second gate electrode 109 in the channel length direction. Further, even when the acceleration voltage is the same as that in FIG. 4A, the second impurity region 124B can be formed even when the taper angle is small or the thickness of the tapered portion is small.

When the acceleration voltage is further increased, FIG.
As shown in (C), the phosphorus concentration averaged in the film thickness direction in the second impurity region 124C can be made uniform. In this case, the channel length LC is the width of the second gate electrode 109 in the channel length direction.

In the step of adding phosphorus shown in FIG.
When the accelerating voltage is lower than in the case of FIG.
As shown in FIG. 4D, phosphorus can only pass through a portion where the thickness of the tapered portion of the first gate electrode 108 is small, so that the second impurity region 124D is narrower than that in FIG.

In the second impurity region 124D, the phosphorus concentration averaged in the depth direction is the same as in FIG.
From the third impurity region 126D to the channel formation region 121
It gradually decreases toward D. However, in the case of FIG. 4D, unlike FIG. 4A, the junction between the second impurity region 124D and the channel formation region 121D exists below the tapered portion of the first gate electrode 108. For this reason, the channel length LD becomes wider than the width of the second gate electrode 109 in the channel length direction.

It should be noted that even if the acceleration voltage is the same as that of FIG.
Even when the film thickness of 8 is large, the second impurity region 124D of FIG. 4D can be formed.

When the impurity is added by the plasma doping method as described above, the impurity passes through a portion having a thickness of 100 nm or less in the tapered portion of the first gate electrode 108 to form the second impurity region 124. By adjusting the thickness of the first conductive film 104 (the thickness of the portion where the thickness of the first gate electrode 108 is maximum) and the taper angle θ, the channel length, It is possible to control the length of the second impurity region.

Here, the length (in the channel length direction) of the first impurity regions 122 and 123 is 2 to 20 μm (typically 3 to 20 μm).
〜１０10 μm). The concentration of an impurity (in this case, phosphorus) that imparts conductivity to the semiconductor layer is 1 × 10 ¹⁹ to 1 ×.
10 ²¹ atoms / cm ³ (typically 1 × 10 ^{20 to} 5 × 10 ²⁰
atoms / cm ³ ). The first impurity regions 122 and 12
Reference numeral 3 denotes a low-resistance region for electrically connecting the source wiring or the drain wiring to the TFT, and serves as a source region or a drain region.

The length of the second impurity regions 124 and 125 is 0.1 to 1 μm (typically 0.1 to 0.5 μm,
The concentration of phosphorus is preferably 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ (typically 5 × 1 μm).
0 ^{15 to} 5 × 10 ¹⁶ atoms / cm ³ , preferably 1 × 10 ¹⁶ to
2 × 10 ¹⁶ atoms / cm ³ ), and the first gate electrode 10
Since the impurities are added through 8, the concentration of phosphorus is lower than that of the first and third impurity regions.

The length of the third impurity regions 126 and 127 is 0.5 to 2 μm (typically 1 to 1.5 μm), and the concentration of phosphorus is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms /. cm
³ (typically 1 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ , preferably 5 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ ).

The channel formation region 121 is an intrinsic semiconductor layer, and does not contain an impurity (phosphorus) added to the first impurity region, or contains boron in a concentration of 1 × 10 ^{16 to} 5 × 1.
This is a region containing a concentration of 0 ¹⁸ atoms / cm ³ . Boron is an impurity for controlling the threshold voltage and preventing punch-through, and can be replaced with another element as long as it produces the same effect. In that case, the concentration is the same as that of boron.

Note that, between the first impurity regions 122 and 123 and the second impurity regions 124 and 125, a low-concentration impurity region which does not overlap with the gate electrode (the third impurity region 12
6, 127), but two or more impurity regions having different impurity concentrations may be formed in this portion. In the present invention, at least the first impurity region 12
2, 123 and the second impurity regions 124, 125,
More impurity (phosphorus) than the first impurity regions 122 and 123
An impurity region having a low concentration, that is, a first impurity region 122;
It is sufficient that at least one impurity region having a resistance higher than 123 exists. Of course, it is also important that this high-resistance impurity region (third impurity region) does not overlap with the gate electrode.

After forming the first impurity regions 122 and 123, the resist mask 120 is removed. Heat treated,
The phosphorus added to the semiconductor layer 102 is activated. In the activation step, not only heat treatment but also optical annealing using laser or infrared lamp light can be performed.

Next, an interlayer insulating film 1 made of silicon oxide or the like is used.
Form 30. Gate insulating film 103, interlayer insulating film 13
At 0, contact holes reaching the first impurity regions 122 and 123 and the second gate wiring 109 are formed. Then, a source electrode 131, a drain electrode 132, and an extraction electrode of a gate wiring (not shown) are formed.

[Embodiment 2] A manufacturing process of the TFT of this embodiment will be described with reference to FIGS. This embodiment is a modification of the first embodiment, in which the structure of the gate electrode (gate wiring) is modified, and the other main structures are the same as the first embodiment.

In the first embodiment, the gate electrodes have different widths.
Although this embodiment has a structure in which two gate electrodes are stacked, this embodiment omits the upper second electrode and forms the gate electrode only with the first gate electrode having a tapered portion.

First, a base film 141 is formed on the entire surface of the substrate 140, and an island-shaped semiconductor layer 142 is formed on the base film 141. An insulating film 143 serving as a gate insulating film is formed over the entire surface of the substrate 140 so as to cover the semiconductor layer 142. (FIG. 5
(A))

On the gate insulating film 143, a conductive film 144 forming a gate electrode (gate wiring) is formed. It is desired that the conductive film 144 be made of a material that can be easily tapered. For example, chrome (Cr), tantalum (Ta)
Is mainly used, and n-type silicon containing phosphorus is typically used. Also, titanium (Ti), tungsten (W), molybdenum (Mo)
A material containing, for example, a main component can be used. In addition, not only a single-layer film of these materials but also a multilayer film can be used. For example, a three-layer film in which a tantalum film is sandwiched between tantalum nitride (TaN) films can be used. The thickness of the conductive film 144 is 200 to 500 nm. (FIG. 5 (B))

Next, the resist mask 1 is formed on the conductive film 144.
45 is formed. The conductive film 144 is etched using the mask 145 to form a gate electrode (gate wiring) 146. (FIG. 5 (C))

As a result of this etching, as shown in FIG. 3, the taper angle θ between the side surface of the gate electrode 146 and the gate insulating film is set to a value within a range from 3 degrees to 60 degrees. The taper angle θ is preferably 5 degrees or more and 45 degrees or less, and more preferably 7 degrees or more and 20 degrees or less.

With the resist mask 145 present,
A predetermined conductivity type (n-type or p-type) impurity is added to the semiconductor layer 142. Here, phosphorus is added by an ion doping method to form n ⁻ -type impurity regions 148 and 149. In this addition step, n ⁻ -type second impurity regions 154 and 155, and n ⁻ -type third impurity regions 156 and 155
57 are determined. As described later, a region covered with the resist mask 145 becomes a channel formation region 151. (FIG. 6 (A))

Since the second gate electrode does not exist, this adding step requires a mask for preventing phosphorus from being added to the region of the semiconductor layer 142 where the channel is to be formed. Although the resist mask 145 used for etching the conductive film 144 is used as such a mask, it can be newly formed for adding impurities.

Next, the resist mask 145 is removed, and a resist mask 150 is formed to cover the gate electrode 146. Via the resist mask 150, phosphorus, which is an n-type impurity, is again doped into the semiconductor layer 142 by ion doping.
Is added to the third mask by the resist mask 150.
Of the impurity region is determined. Prior to this addition step, the insulating film 14 is formed using the gate wiring 146 as a mask.
3 may be etched to expose the surface of the semiconductor layer 142. (FIG. 6 (B))

As shown in FIG. 6B, n ⁻ -type impurity regions 148 and 14 not covered with resist mask 150 are formed.
Phosphorus 9 is selectively added to form n ⁺ -type first impurity regions 152 and 153.

The region covered with the resist mask 150 is kept of the conductivity type and the resistance value as shown in FIG.
Therefore, the region 151 previously covered with the resist mask 145 becomes a channel formation region. A region overlapping (overlapping) with the gate electrode 146 is an n ⁻ -type second region.
Impurity regions 154 and 155 of the gate electrode 146.
Is not overlapped with the n ⁻ -type third impurity region 15.
6, 157. Second and third impurity regions 154-1
Reference numeral 57 denotes a low-concentration impurity region having a higher resistance than the first impurity regions 152 and 153.

In the present embodiment, the same as in the first embodiment, the second
Impurity regions 154 and 155 can be classified into the four types shown in FIG. The channel formation region 151 and the first
The length and impurity concentration of the third to third impurity regions 152 to 157 in the channel length direction are the same as those in the first embodiment.
However, the channel length is the second gate electrode 1 of the first embodiment.
In this embodiment, it is determined by the resist mask 145 used in the addition step of FIG.

Since the gate electrode of Embodiment 1 has a laminated structure of electrodes having different shapes, even if the thickness of the first gate electrode 108 is reduced, the resistance can be reduced by increasing the thickness of the second gate electrode 109. However, since the gate electrode 146 of this embodiment is a single-layer electrode having a tapered portion, its thickness is larger than that of the first gate electrode 108.

Considering the gate electrode width, the width of the tapered portion
Since the length of the WG (see FIG. 3) is limited, it is most practical that the impurity concentration distribution of the second impurity regions 154 and 155 is of the type shown in FIG.

Note that a low-concentration impurity region (the third impurity region 15) which does not overlap with the gate electrode is provided between the first impurity regions 152 and 153 and the second impurity regions 154 and 155.
6, 157), but two or more impurity regions having different impurity concentrations may be formed in this portion. In the present invention, at least the first impurity region 15
2, 153 and the second impurity regions 154, 155,
More impurity (phosphorus) than the first impurity regions 152 and 153
It is sufficient that at least one impurity region having a low concentration and a high resistance exists.

After forming first impurity regions 152 and 153, resist mask 150 is removed. By heat treatment, phosphorus added to the semiconductor layer 142 is activated. In the activation step, not only heat treatment but also light annealing using laser or infrared lamp light can be performed. However, in order to activate phosphorus in the second impurity regions 154 and 155, heat treatment is necessarily performed because the region overlaps with the gate electrode 146.

Next, an interlayer insulating film 1 made of silicon oxide or the like is used.
58 is formed. Gate insulating film 143, interlayer insulating film 15
8, the first impurity regions 152 and 153, the gate wiring 14
A contact hole reaching 6 is formed. Then, a source electrode 159, a drain electrode 160, and an extraction electrode of a gate wiring 146 (not shown) are formed.

[Embodiment 3] A manufacturing process of a TFT of this embodiment will be described with reference to FIGS. This embodiment is also a modification of the first embodiment, and includes a gate electrode (gate wiring).
This is a modification of the first embodiment, and the other main structures are the same as those of the first embodiment. In FIG. 7, the same reference numerals as those in FIGS. 1 and 2 indicate the same components.

As in the first embodiment, the first gate electrode 168 and the second gate electrode 16
9, the first gate electrode 168 does not have a tapered side surface. In this embodiment, the first gate electrode 168 extends outward from the second gate electrode 169 side surface. The film thickness is almost constant even in the part.

The semiconductor layer is doped with phosphorus in the same manner as in the first embodiment to form a channel forming region 161, n ⁺ -type first impurity regions 162 and 163, and n ⁻ -type second impurity regions 164 and 165. , N ⁻ -type third impurity regions 166, 1
67 are formed.

In this embodiment, the first gate electrode 168
Is constant, the second impurity region 164,
At 165, there is almost no gradient in the impurity concentration.

[Embodiment 4] This embodiment is a modification of the first and second embodiments. In the first and second embodiments, the thickness of the gate electrode at the tapered portion changes substantially linearly. In the present embodiment, the thickness of the tapered portion is changed non-linearly.

FIG. 8 shows a modification of the TFT of the first embodiment. 8, the same reference numerals as those in FIG. 2 indicate the same components. As shown in FIG. 8, the thickness of the tapered portion of the first gate electrode 170 (gate wiring) is changed nonlinearly. In the semiconductor layer, through the same addition of phosphorus as in the first embodiment, the channel formation region 171, the n ⁺ -type first impurity regions 172 and 173, the n ⁻ -type second impurity region 174,
175, n ⁻ -type third impurity regions 176 and 177 are formed.

FIG. 9 shows a modification of the TFT of the second embodiment. In FIG. 9, the same reference numerals as those in FIG. 6 indicate the same components. As shown in FIG. 9, the thickness of the tapered portion of the gate electrode 180 (wiring) changes nonlinearly. In the semiconductor layer, the channel formation region 181 and the n ⁺ -type first impurity regions 182 and 18 are added through the same addition of phosphorus as in the first embodiment.
3, n ⁻ -type second impurity regions 184 and 185 and n ⁻ -type third impurity regions 186 and 187 are formed.

As shown in the cross-sectional views of FIGS. 8 and 9, the gate electrodes 170 and 180 are formed so as to have a very small thickness at a portion where the film thickness is slightly shifted from a fixed portion to an end, so that the Impurities easily pass through the gate electrodes 170 and 180.

The tapered portion shown in FIG.
In order to form the conductive films 70 and 180, the conductive film may be etched by combining anisotropic etching and isotropic etching.

It is needless to say that the structure of the TFT described in the first to fourth embodiments can be applied to all examples of the present invention described below.

[0100]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 In this embodiment, an example in which the present invention is applied to an active matrix type liquid crystal display device will be described.

FIG. 10 is a schematic structural view of the active matrix type liquid crystal panel of this embodiment. A liquid crystal panel has a structure in which liquid crystal is sandwiched between an active matrix substrate and a counter substrate, and a voltage corresponding to video data is applied to the liquid crystal by electrodes formed on the active matrix substrate and the counter substrate. , Can display video on the panel.

In the active matrix substrate 200, a pixel portion 202 using a TFT as a switching element, a gate driver circuit 203 for driving the pixel portion 202, and a source driver circuit 204 are formed on a glass substrate 300. The driver circuits 203 and 204 are connected to the pixel unit 202 by a source wiring and a drain wiring, respectively.

Further, on the glass substrate 300, a signal processing circuit 205 for processing signals input to the driver circuits 203 and 204 is formed.
204, an external terminal for inputting power and a control signal to the signal processing circuit 205 is formed.
06 is connected.

In the counter substrate 210, a transparent conductive film such as an ITO film is formed on the entire surface of the glass substrate. The transparent conductive film is a counter electrode with respect to the pixel electrode of the pixel portion 202. By changing the electric field intensity between the pixel electrode and the counter electrode, the orientation of the liquid crystal material is changed, and a gray scale display can be performed. Further, the counter substrate 210 may have an alignment film if necessary,
A color filter is formed.

FIG. 11A is an equivalent circuit of one pixel of the pixel portion, and FIG. 11B is a top view of the pixel portion 202.
FIG. 11C is a top view of a CMOS circuit included in the driver circuits 203 and 204.

FIG. 12 is a sectional view of an active matrix substrate. FIG. 12A is a cross-sectional view of the pixel portion 202, which corresponds to a cross section taken along a dashed line XX ′ in FIG. FIG. 12B is a cross-sectional view of the CMOS circuit, and FIG.
1 (C) corresponds to the cross section along the chain line YY ′. FIG.
As shown in FIG. 2, the pixel TFT and the thin film transistor of the CMOS circuit are simultaneously formed on the same glass substrate 300.

In the pixel section 202, the gate wiring 350
Are formed for each row, and the source wiring 380 is formed for each column. The pixel TFT 220 is formed near the intersection of the gate line 350 and the source line 380. The source region of the pixel TFT 220 is connected to a source line 380, and the drain region is a liquid crystal cell 240 and a storage capacitor 2.
Two capacitors of 30 are connected.

The liquid crystal cell 240 is a capacitor using a liquid crystal as a dielectric with the pixel electrode 390 and the transparent electrode of the counter substrate 210 as an electrode pair.
220 is electrically connected. The storage capacity 230 is
This capacitor uses a common line 360 and a channel region formed in the semiconductor layer of the pixel TFT 220 as an electrode pair and a gate insulating film as a dielectric.

The manufacturing process of the active matrix substrate of this embodiment will be described with reference to FIGS. FIG.
FIG. 14 is a cross-sectional view illustrating a manufacturing process of the pixel portion.
5 and FIG. 16 are cross-sectional views showing the steps of manufacturing a CMOS circuit.

A glass substrate 300 is prepared. In this embodiment, a 1737 glass substrate manufactured by Cornings is used. In contact with the surface of the glass substrate 300, TEO is formed by plasma CVD.
A 200-nm-thick silicon oxide film is formed as a base film 301 using S gas as a raw material. Then, the base film 301 is
Heat at 0 ° C. for 4 hours.

H _{2 is formed} on the underlying film 301 by PECVD.
An amorphous silicon film having a thickness of 500 nm is formed using SiH ₄ diluted with a gas. Next, the amorphous silicon film is heated at 450 ° C. for one hour to perform a dehydration treatment. Hydrogen atoms in the amorphous silicon film are 5 atomic% or less, preferably 1 atomic% or less.
% Or less. The crystalline (polycrystalline) silicon film 401 is formed by irradiating an excimer laser beam to the amorphous silicon film after the hydrogen removal treatment. The conditions for laser crystallization are as follows: a XeCl excimer laser is used as a laser light source, the laser light is linearly shaped by an optical system, the pulse frequency is 30 Hz, the overlap ratio is 96%, and the laser energy density is 359.
mJ / cm ² . (FIG. 13 (A), FIG. 15 (A))

The method for forming an amorphous silicon film is PECVD.
In addition to the method, an LPCVD method or a sputtering method can be used. As a laser for crystallizing amorphous silicon, a continuous wave laser such as an Ar laser may be used in addition to a pulsed laser such as an excimer laser. Further, instead of laser crystallization, a lamp annealing step using a halogen lamp or a mercury lamp, or a heat treatment step at 600 ° C. or higher can be used.

Next, a photoresist pattern (not shown) is formed by using a photolithography process, and the crystalline silicon film 401 is patterned into an island shape using the photoresist pattern to form semiconductor layers 302, 303, and 304. A silicon nitride oxide film is formed as the gate insulating film 305 so as to cover the semiconductor layers 302, 303, and 304. The film forming method was PECVD, and SiH ₄ and NO ₂ were used as source gases.
Was used. The thickness of the silicon nitride oxide film is 120 nm. (FIG. 13 (B), FIG. 15 (B))

On the gate insulating film 305, n containing phosphorus
A stacked film of a silicon film 402 of a mold type and a molybdenum-tungsten alloy (Mo-W) film 403 is formed by a sputtering method. The thickness of the silicon film 402 is 200 nm, and the thickness of Mo-
The thickness of the W film 403 is 250 nm. Mo-W film 40
The target material of No. 3 had a Mo: W composition ratio of 1: 1. (FIG. 13 (C), FIG. 15 (C))

The resist mask 40 is formed on the Mo-W film 403.
5 is formed. Mo-W using resist mask 405
The film 403 is wet-etched, and the second gate wiring 352 and the second common wiring 36 which are upper wirings of the gate wiring and the common wiring of the pixel TFT and the gate wiring of the CMOS circuit
2. A second gate wiring 372 is formed. (FIG. 13
(D), FIG. 15 (D))

Using the resist mask 405 again, anisotropic etching using a chlorine-based gas is performed, the n-type silicon film 402 is etched, and the first gate wiring 351 is formed.
A second common wiring 361 and a first gate wiring 371 are formed. At this time, the angle (taper angle) θ between the side surface of each of the wirings 351, 361, and 371 and the gate insulating film 305 is set to 20 degrees, and a tapered portion is formed on the side. (Figure 1
3 (E), FIG. 15 (E))

After removing the resist mask 405, phosphorus is added to the semiconductor layers 302 to 304 by ion doping using the wirings 350, 360, and 370 as a mask.
The n ⁻ -type regions 406 to 413 are formed in a self-aligned manner. In this phosphorus addition step, the first electrodes 351, 361, 3
71 (the second electrodes 352, 362, 372)
(The portion outside the side surface of the substrate) and the gate insulating film 305, and the acceleration voltage is increased to 90 KeV to add phosphorus.

[0119] n ^- to determine the phosphorus concentration of the low concentration impurity regions of the mold, and the dose is set to a low concentration, n ^{- -} phosphorus concentration impurity regions 406 to 413 of the types n of the final TFT type impurity regions 406 413, the electrodes 350, 36
0, the concentration of phosphorus in the region not intersecting with 370 is 1 × 1
0 ¹⁸ atoms / cm ³ . Phosphine diluted with hydrogen is used as a doping gas.

Next, a resist mask 415 covering the electrodes 350, 360, and 370 is formed. Resist mask 41
5 extends outside the side surfaces of the first electrodes 351, 361, 371 of the respective electrodes.
The length of the n ⁻ -type low-concentration impurity region that does not overlap with 361 and 371 is determined. Here, no resist mask is formed over the semiconductor layer 304 of the CMOS circuit.

[0121] Using the resist mask 415, phosphorus is added by an ion doping method. In this addition step, phosphine diluted with hydrogen was used as the doping gas. Further, in order to allow phosphorus to pass through the gate insulating film 305, the acceleration voltage is set as high as 80 keV,
N ⁺ -type impurity regions 313 to 31 formed in this step
5,332,333,421,422 phosphorus concentration is 5
The dose was set so as to be × 10 ²⁰ atoms / cm ³ .

In the pixel portion 202, phosphorus is selectively added to the n ⁻ -type impurity regions 406 to 409 of the semiconductor layer 302 to form n ⁺ -type impurity regions 313 to 315. The regions to which phosphorus is not added in the n ⁻ -type impurity regions 406 to 409 function as high-resistance regions, and the n ⁻ -type impurity regions 316 to 319 overlapping with the first gate electrode 351 and the first common electrode are formed. 326, 327 and n ⁻ -type impurity regions 320 to 323, 328 which do not overlap with the first gate electrode 351 and the first common electrode 361. Further, regions 311, 312, and 325 to which phosphorus has not been added in the two phosphorus addition steps are defined as channel formation regions. (FIG. 14A)

[0123] n ^- -type impurity regions 316 to 319 is the concentration of phosphorus the n ^- lower -type impurity regions 320 to 323, and the concentration of phosphorus the n ^- toward -type impurity regions 320 to 323 in the channel forming region 311, 312 It is lower.

In a CMOS circuit, an n-channel type TF
N ⁻ -type impurity regions 410 and 411 of T semiconductor layer 303
Is selectively added also to the n ⁺ -type impurity region 32.
2, 323 are formed. On the other hand, n ⁻ type impurity region 4
In regions 10 and 411, the region to which phosphorus is not added functions as a high-resistance region, and n ⁻ -type impurity regions 334 and 335 overlapping with the first gate electrode 371 do not overlap with the first gate electrode 371. n ^- type impurity region 3
36, 337. The region 331 to which phosphorus has not been added in the two phosphorus addition steps is defined as a channel formation region.

In n ⁻ -type impurity regions 334 and 335, the concentration of phosphorus is lower than n ⁻ -type impurity regions 336 and 337, and the concentration of phosphorus decreases from n ⁻ -type impurity regions 336 and 337 toward channel formation region 331. ing.

The semiconductor layer 30 of the p-channel TFT is
In No. 4, phosphorus is hardly added to a portion where the gate electrode 370 is present, and n ⁺ -type regions 421 and 422 are formed in a portion where the gate electrode 370 is not present. An n ⁻ -type impurity region remains below the gate electrode. (FIG. 16A)

After removing the resist mask 415, a resist mask 416 covering the n-channel TFT is formed. Using the second gate electrode 372 of the p-channel TFT as a mask, the first gate electrode 37 on the semiconductor layer 304 side is used.
1 is thinned by etching, and a third gate electrode 373 is formed.
To form (FIG. 14 (B), FIG. 16 (B))

The side surface of the third gate electrode 373 and the gate insulating film 305 have a taper angle θ of 75 degrees. The taper angle of the third electrode 373 is in the range of 60 degrees or more and 90 degrees or less, and more preferably in the range of 70 degrees or more and 85 degrees or less.

With the resist mask 416 remaining, boron and ion doping are added to the semiconductor layer 304. The gate electrodes 372 and 373 function as masks, and the channel formation region 341, the p ⁺ -type impurity region 34
2, 343 and p ⁺ -type impurity regions 344 and 345 are formed in a self-aligned manner. Note that the resist mask 416 may be removed and a new resist mask may be formed separately. (FIG. 14 (C), FIG. 16 (C))

In the boron addition step, the accelerating voltage is set to 80 k
eV, and the dose is p ⁺ -type impurity regions 342 to 3
The boron concentration was set to be 3 × 10 ²¹ atoms / cm ³ . By using diborane diluted with hydrogen as the doping gas, p ⁺ -type impurity regions 344 and 345
^The boron concentration is the same as that of ⁺ type impurity regions 342 and 343, but the phosphorus concentration is low. p ⁺ type impurity region 3
The concentration distributions of 44 and 345 correspond to changes in the thickness of the tapered portion of the first gate electrode 371, and the channel formation region 341
It is lower toward.

After removing the resist mask 416, 50
Heating at 0 ° C. activates phosphorus and boron added to the semiconductor layer. Prior to the heat treatment, a protective film 306 made of silicon oxide with a thickness of 50 nm is formed in order to prevent oxidation of the gate wiring 350, the common electrode 360, and the gate wiring 370. (FIG. 14 (C), FIG. 16 (C))

Next, as the interlayer insulating film 307, PECV
20 nm thick silicon nitride film by method D, 900 nm thick
Are laminated and formed. Interlayer insulating film 30
7, n ⁺ -type impurity regions 313 to 315 and n ⁺ -type impurity regions 332 and 33
3. A contact hole reaching the p ⁺ -type impurity regions 342 and 343 and the second gate wiring 372 is formed.

On the interlayer insulating film 307, titanium (150 n
m) / aluminum (500 nm) / titanium (100 n
m) is formed by sputtering and patterned to form a source wiring 380, a drain electrode 381, source electrodes 384, 385, and a drain electrode 386.
As described above, the circuit 203 mainly composed of the CMOS circuit
205 and the pixel portion 202 provided with the pixel TFT 220 and the storage capacitor 230 are formed on the same glass substrate 300. (FIG. 14 (E), FIG. 16 (E))

To complete the active matrix substrate, a flattening film 308 is further formed on the entire surface of the substrate 300. Here, acryl is applied by a spin coating method and baked to form an acrylic film having a thickness of 1 μm. Flattening film 3
At 08, contact holes for the source electrodes 384 and 385 of the CMOS circuit are opened. A 200-nm-thick titanium film is formed by sputtering and patterned to form source wirings 387 and 388.

Next, similarly to the first flattening film 308, an acrylic having a thickness of 0.5 μm is applied to the second flattening film 309.
Form as A contact hole for the drain electrode 381 is formed in the planarization films 308 and 309. An ITO film is formed by a sputtering method and patterned to form a pixel electrode 390 connected to the drain electrode 381.
(FIGS. 12A and 12B)

In this embodiment, a low-concentration impurity region functioning as a high-resistance region is not formed with respect to the p-channel TFT. However, since the p-channel TFT originally has no high-resistance region, its reliability is high. There is no problem. On the contrary, when the high-resistance region is not formed, the ON current can be increased, and the characteristics with the n-channel TFT can be balanced, which is convenient.

[Embodiment 2] This embodiment is a modification of the embodiment 1 and is the same as the embodiment 1 except that the order of the steps of adding phosphorus and boron is changed. The manufacturing process of this embodiment will be described with reference to FIGS. 17, the same reference numerals as those in FIGS. 15 and 16 denote the same components.

In Example 1, boron was added after phosphorus was added to the semiconductor layer. In this example, boron was added first.

In this embodiment, a process for manufacturing a CMOS circuit will be described. However, it is needless to say that this embodiment can be applied to a process for manufacturing an active matrix substrate in which a pixel portion and a driver circuit are integrated as in the embodiment. .

According to the steps shown in Embodiment 1, FIG.
(E) is obtained. Next, the resist mask 405 is removed. FIG. 17A shows this state.

Next, a resist mask 451 covering the n-channel TFT is formed. Using the resist mask 451, boron is added to the semiconductor layer 304 by an ion doping method. The gate electrodes 371 and 372 function as masks, and the p ⁺ -type impurity region 5 that functions as a channel formation region 501, a source region, and a drain region in the semiconductor layer 304.
02, 503 are formed in a self-aligned manner.

The acceleration voltage is 80 keV and the dose is p
The boron concentration of the ⁺ type impurity regions 502 and 503 is 3 × 10
^The setting was made to be ²⁰ atoms / cm ³ . Here, the p ⁺ -type impurity regions 502 and 503 are expected to wrap around boron at the time of doping and have a small thickness on the side of the gate electrode 370, so that they slightly overlap with the lower portion. (FIG. 17B)

After removing the resist mask 451, a resist mask 452 covering the p-channel TFT is formed. Then, the semiconductor layer 303 is formed by an ion doping method.
To the n ⁻ -type low-concentration impurity regions 453 and 4.
54 are formed in a self-aligned manner. The acceleration voltage was set to 90 keV, and the dose was set so that the phosphorus concentration of the n ⁻ -type impurity regions 453 and 454 was 1 × 10 ¹⁸ atoms / cm ³ . In addition, phosphine diluted with hydrogen is used as a doping gas. (FIG. 17C)

Next, the resist mask 452 is removed,
New p-channel TFT and n-channel TFT
Is formed to partially cover the resist. In the n-channel TFT, the length of the mask 456 extending outside the side surface of the first gate electrode 371 determines the length of the n ⁻ -type impurity region which does not overlap with the first gate electrode 371.

Using a resist mask 456, phosphorus is added by an ion doping method. Also in this addition step, phosphine diluted with hydrogen was used as the doping gas.

In a CMOS circuit, an n-channel type TF
N ⁻ -type impurity regions 453 and 454 of T semiconductor layer 303
Is selectively added to the n ⁺ -type impurity region 51.
2, 513 are formed. In this step, the accelerating voltage is 80 keV to pass phosphorus through the gate insulating film 305.
And higher. The dose was set such that the concentration of phosphorus in n ⁺ -type impurity regions 512 and 513 was 5 × 10 ²⁰ atoms / cm ³ .

On the other hand, n ⁻ -type impurity regions 453 and 454
, The region to which phosphorus has not been added functions as a high-resistance region, and overlaps with the first gate electrode 371.
^- -type impurity regions 514 and 515, the first gate electrode 3
N ⁻ -type impurity regions 516 and 517 not overlapping with 71
Is defined as A region 511 where phosphorus is not added in the two phosphorus addition steps is defined as a channel formation region. (FIG. 17D)

Also in this embodiment, the n ⁻ -type impurity regions 514 and 515 overlapping the gate electrode 371 have a phosphorus concentration of n.
^The impurity concentration is lower than that of the ⁻ type impurity regions 516 and 517 (and the n ⁺ type impurity regions 512 and 513), and the concentration of phosphorus decreases toward the channel formation region 511.

After removing the resist mask 456, a protective film 306 made of silicon oxide having a thickness of 50 nm is formed, and heat treatment is performed to activate phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384, 385 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 17E)

In this embodiment, the first of the p-channel TFTs
The step of thinning the gate electrode can be omitted.
Note that, before performing the boron addition step of FIG.
A step of forming the third gate electrode 373 by etching the first gate electrode 371 of the channel type TFT using the second gate electrode 372 as a mask can also be added.

[Embodiment 3] In this embodiment, as in Embodiment 2, a manufacturing process in which the order of the steps of adding phosphorus and boron is changed will be described. The manufacturing process of this embodiment will be described with reference to FIGS. In FIG. 18, the same reference numerals as those in FIGS. 15 and 16 denote the same components.

This embodiment also corresponds to a modification of the second embodiment. In the second embodiment, an n-channel TFT is manufactured by adding phosphorus at a low concentration and then adding boron. In the present embodiment, an example in which boron is added at a high concentration first. It is.

According to the steps shown in Embodiment 1, FIG.
(E) is obtained. Next, the resist mask 405 is removed. FIG. 18A shows this state.

Next, a resist mask 600 covering the n-channel TFT is formed. Using the resist mask 600, boron is added to the semiconductor layer 304 by an ion doping method. The gate electrodes 371 and 372 function as a mask, and the semiconductor layer 304 has a p ⁺ -type impurity region 6 functioning as a channel formation region 601, a source region, and a drain region.
02, 603 are formed in a self-aligned manner. The doping acceleration voltage is set to 80 keV, and the dose is set so that the boron concentration of the p ⁺ -type impurity regions 602 and 603 is 2 × 10 ²⁰ atoms / cm ^3.
It was set to be.

A resist mask 605 that partially covers the entire p-channel TFT and the n-channel TFT is formed. Using the resist mask 605, phosphorus is added by an ion doping method. In this addition step, phosphine diluted with hydrogen was used as the doping gas. n
Phosphorus is selectively added to the semiconductor layer 303 of the channel type TFT to form n ⁺ -type impurity regions 606 and 607. Further, in this step, the accelerating voltage is 80 keV in order to pass phosphorus through the gate insulating film 305. And higher.
(FIG. 18 (C))

After removing the resist mask 605, a resist mask 608 covering the p-channel TFT is formed. Then, the semiconductor layer 303 is formed by an ion doping method.
Add phosphorus. The gate electrode 370 functions as a mask, and the channel formation region 611 and the n ⁻ -type impurity region 61
4, 615 and n ⁻ -type impurity regions 616 and 617 are formed in a self-aligned manner.

The n ⁺ -type impurity regions 612 and 613 function as source / drain regions and have a phosphorus concentration of 5 × 10 ^20.
The resistance is reduced so as to be atoms / cm ³ . N ⁻ -type impurity regions 614 to 617 are n ⁺ -type impurity regions 612 and 61
The phosphorus concentration is made lower than 3, and the resistance is increased. N ⁻ -type impurity region 61 not overlapping with first gate electrode 371
The phosphorus concentrations of 6 and 617 are set to 1 × 10 ¹⁸ atoms / cm ³ .
(FIG. 18D)

After removing the resist mask 608, a protective film 306 made of silicon oxide having a thickness of 50 nm is formed.
Heat treatment activates phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384, 385 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 18E)

In this example, in the step of adding phosphorus,
Resist masks 605 and 60 covering p-channel TFT
8 were formed, but these resist masks 605 and / or
And 608 can also be omitted. In this case, p ⁺
Since phosphorus is added to the impurity regions 602 and 603 of the mold, it is necessary to add a large amount of boron in consideration of the concentration of phosphorus to be added.

[Embodiment 4] This embodiment is also a modified example of Embodiment 1, except that the order of the steps of adding phosphorus and boron is changed, and the main configuration is the same as that of Embodiment 1.

The manufacturing process of this embodiment will be described with reference to FIG. 19, the same reference numerals as those in FIGS. 15 and 16 indicate the same components.

According to the steps shown in Embodiment 1, FIG.
(E) is obtained. Next, the resist mask 405 is removed. Then, in the gate wiring 370, a resist mask which covers at least a portion functioning as a gate electrode of the n-channel TFT is formed, and the first gate electrode (wiring) is formed using the second gate electrode (wiring) 372 as an etching mask. ) Etch 371 to form a third gate electrode (wiring).

That is, at least the first gate wiring 37
In 1, a third gate electrode 373 is formed by reducing the width of a portion overlapping with the semiconductor layer 304 of the p-channel TFT. (FIG. 19A)

The semiconductor layer 30 is formed by the ion doping method.
3, 304 Add phosphorus to low concentration. The first to third gate electrodes 371 to 373 function as masks, and n ⁻ -type regions 621 to 624 are formed in a self-aligned manner. (Figure 1
9 (B))

Next, a resist mask 630 covering the n-channel TFT is formed. Using the resist mask 630, boron is added to the semiconductor layer 304 at a high concentration by an ion doping method. First and third gate electrodes 371, 37
3 functions as a mask, and p ⁺ -type impurity regions 632 and 633 functioning as a channel formation region 631, a source region, and a drain region are formed in the semiconductor layer 304 in a self-aligned manner. (FIG. 19C)

Next, the resist mask 630 is removed.
New p-channel TFT and n-channel TFT
Is formed to partially cover the resist. Using the resist mask 640, phosphorus is added at a high concentration by an ion doping method. Phosphorus is selectively added to the n ⁻ -type impurity regions 621 and 622 of the semiconductor layer 303 of the n-channel TFT, so that n ⁺ -type impurity regions 642 and 643 are formed. Further, regions covered with the resist mask 640 are n ⁻ -type impurity regions 644 and 645 overlapping with the channel formation region 641 and the first gate electrode 371.
And n ⁻ -type impurity regions 646 and 647 that do not overlap with the first gate electrode 371. (FIG. 19
(D))

Also in this embodiment, the n ⁻ -type impurity regions 644 and 645 overlapping the gate electrode 371 have a phosphorus concentration of n.
^The impurity concentration is lower than that of the ⁻ type impurity regions 646 and 647 (and n ⁺ type impurity regions 642 and 643), and the concentration of phosphorus decreases toward the channel formation region 641.

After removing the resist mask 640, a protective film 306 made of silicon oxide having a thickness of 50 nm is formed, and heat treatment is performed to activate phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384, 385 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 19E)

In this embodiment, the p-channel type TFT is used.
Although the width of the first gate electrode is reduced, this step can be omitted.

In this example, in the step of adding phosphorus,
Resist masks 630 and 64 covering p-channel TFT
0, but these resist masks 630 and / or
And 640 may be omitted. In this case, p ⁺
Since phosphorus is added to the impurity regions 632 and 633 of the mold, it is necessary to add a large amount of boron in consideration of the concentration of phosphorus to be added.

[Embodiment 5] This embodiment is a modification of the embodiment 1 and is different from the embodiment 1 in that the order of the steps of adding phosphorus and boron is changed. The main configuration is the same as that of the first embodiment.

The manufacturing process of this embodiment will be described with reference to FIG. 20, the same reference numerals as those in FIGS. 15 and 16 indicate the same components.

This embodiment corresponds to a modification of the fourth embodiment, and the third gate electrode 373 is formed by narrowing the first gate electrode of the p-channel TFT as in the fourth embodiment. . (FIG. 20A)

Next, a resist mask 650 that partially covers the entire p-channel TFT and the n-channel TFT is formed. Using a resist mask 650, phosphorus is added at a high concentration by an ion doping method to form an n-type region 651,
652 are formed. (FIG. 20 (B))

Next, a resist mask 660 covering the n-channel TFT is formed. Using the resist mask 660, boron is added to the semiconductor layer 304 at a high concentration by an ion doping method. First and third gate electrodes 371, 37
3 functions as a mask, and p ⁺ -type impurity regions 662 and 663 functioning as a channel formation region 661 and source and drain regions are formed in the semiconductor layer 304 in a self-aligned manner. (FIG. 20 (C))

Next, the resist mask 660 is removed,
A new resist mask 6 covering the entire p-channel TFT
70 is formed. Phosphorus is added at a low concentration by an ion doping method, and the acceleration voltage is set as high as 90 keV so that phosphorus passes through the tapered portion of the first gate electrode 371.

As a result, in the semiconductor layer 303 of the n-channel TFT, the channel formation region 671, the n ⁺ -type impurity regions 672 and 673, and the n ⁻ -type impurity regions 674 and 675 overlapping the first gate electrode 371 are formed. An n ⁻ -type impurity region 676 not overlapping with the first gate electrode 371;
677 are formed in a self-aligned manner. (FIG. 20 (D))

After removing the resist mask 670, a protective film 306 made of silicon oxide having a thickness of 50 nm is formed, and heat treatment is performed to activate phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384, 385 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 20 (E))

In this embodiment, the p-channel type TFT is used.
Although the width of the first gate electrode is reduced, this step can be omitted.

In this example, in the step of adding phosphorus,
Resist masks 650 and 67 covering p-channel TFT
0, but these resist masks 650 and / or
And 670 may be omitted. In this case, p ⁺
Since phosphorus is added to the impurity regions 662 and 663 of the mold, it is necessary to add a large amount of boron in consideration of the concentration of phosphorus to be added.

[Embodiment 6] This embodiment is a modification of the embodiment 1, in which the order of the steps of adding phosphorus and boron is changed, and the other structure is almost the same as that of the embodiment 1.

Hereinafter, the manufacturing process of this embodiment will be described with reference to FIGS. 21, the same reference numerals as those in FIGS. 15 and 16 indicate the same components.

This embodiment corresponds to a modification of the fifth embodiment, and the third gate electrode 373 is formed by narrowing the first gate electrode of the p-channel TFT as in the fifth embodiment. . (FIG. 21A)

Further, similarly to the fifth embodiment, the p-channel type TF
A resist mask 680 that partially covers the entire T and the n-channel TFT is formed. Using a resist mask 680, phosphorus is added at a high concentration by an ion doping method,
The n-type regions 681 and 682 are formed. (FIG. 21 (B))

Next, the resist mask 680 is removed.
A new resist mask 6 covering the entire p-channel TFT
90 are formed. Phosphorus is added at a low concentration by an ion doping method. The acceleration voltage is set as high as 90 keV so that phosphorus passes through the tapered portion of the first gate electrode 371.

As a result, in the semiconductor layer 303 of the n-channel TFT, the channel formation region 691, the n ⁺ -type impurity regions 692 and 693, and the n ⁻ -type impurity regions 694 and 675 overlapping with the first gate electrode 371 are formed. An n ⁻ -type impurity region 696 that does not overlap with the first gate electrode 371;
697 are formed in a self-aligned manner. (FIG. 21 (C))

Next, after forming a resist mask 700 covering the entire n-channel TFT, boron is added to the semiconductor layer 304 at a high concentration by ion doping. The first and third gate electrodes 371 and 373 function as masks,
In the semiconductor layer 304, a p ⁺ -type impurity region 70 functioning as a channel formation region 701, a source region, and a drain region
2, 703 are formed in a self-aligned manner. (FIG. 21
(D))

After removing the resist mask 700, a protective film 306 made of silicon oxide having a thickness of 50 nm is formed, and heat treatment is performed to activate phosphorus and boron added to the semiconductor layer. An interlayer insulating film 307 is formed, a contact hole is opened, and a source electrode 384 and a drain electrode 386 are formed. Thus, a CMOS circuit is manufactured. (FIG. 21E)

In this embodiment, a p-channel type TFT is used.
Although the width of the first gate electrode is reduced, this step can be omitted.

In this example, in the step of adding phosphorus,
Resist masks 680 and 69 covering p-channel TFT
0, but these resist masks 680 and / or
And 690 can also be omitted. In this case, p ⁺
Since phosphorus is added to the impurity regions 702 and 703 of the mold, it is necessary to add a large amount of boron in consideration of the concentration of phosphorus to be added.

As described above, in the second to sixth embodiments, the CMOS
A circuit manufacturing process will be described. Needless to say, the present embodiment can be applied to a manufacturing process of an active matrix substrate in which a pixel portion and a driver circuit are integrated as in the first embodiment.

[Embodiment 7] In this embodiment, an example of a gate electrode having a tapered portion shown in Embodiment 1 and the like and a method of forming the gate electrode will be described.

First, a gate insulating film made of a silicon nitride oxide film was formed, and a metal laminated film was formed thereon by a sputtering method. In this embodiment, a tungsten target having a purity of 6N or more was used. As a sputtering gas, argon (Ar), krypton (Kr), xenon (X
A simple gas such as e) or a mixed gas thereof may be used. In addition, film forming conditions such as sputtering power, gas pressure, and substrate temperature may be appropriately controlled by an operator. The metal laminated film has a tungsten nitride film represented by WNx (where 0 <x <1) as a lower layer and a tungsten film as an upper layer.

The metal laminated film thus obtained contains almost no impurity elements, and particularly has an oxygen content of 30%.
ppm or less, and the electrical resistivity is 20 μΩ ·
cm or less, typically, 6 μm to 15 μΩ · cm. The stress of the film is -5 × 10 ^{9 to} 5 × 1.
It can be set to ⁹ dyn / cm ² .

The silicon oxynitride film is SiOxNy.
And an insulating film containing silicon, oxygen, and nitrogen at a predetermined ratio.

Next, a resist mask pattern (film thickness: 1.5 μm) for obtaining a desired gate wiring pattern is formed.

Next, in this embodiment, an ICP (Induplex) using high-density plasma for patterning the metal laminated film is used.
Etching was performed using a ctively coupled plasma etching apparatus to form a gate electrode having a tapered cross section and a gate electrode.

Here, the plasma generation mechanism of the ICP dry etching apparatus will be described in detail with reference to FIG.

FIG. 22 shows a simplified structural diagram of an etching chamber. An antenna coil 12 is arranged on a quartz plate 11 at the top of the chamber, and R
It is connected to the F power supply 14. Further, an RF power source 17 is also connected to the lower electrode 15 on the substrate side, which is disposed to face the opposite side, via a matching box 16.

When an RF current is applied to the antenna coil 12 above the substrate, the RF current J is applied to the antenna coil 12 by α
And a magnetic field B is generated in the Z direction. The relationship between the current J and the magnetic field B follows the following equation.

Μ ₀ J = rotB (μ ₀ is magnetic susceptibility)

An induction electric field E is generated in the α direction according to Faraday's law of electromagnetic induction represented by the following equation.

-∂B / ∂t = rotE

The electrons are accelerated in the α direction by the induction electric field E and collide with gas molecules to generate plasma. Since the direction of the induced electric field is the α direction, the probability of the charged particles colliding with the etching chamber wall or the substrate and losing the charge is reduced.
Therefore, high-density plasma can be generated even at a low pressure of about 1 Pa. Further, since there is almost no magnetic field B downstream, a high-density plasma region spreading like a sheet is formed.

The plasma density and the self-bias voltage can be independently controlled by adjusting the RF power applied to each of the antenna coil 12 (to which ICP power is applied) and the lower electrode 15 (to which bias power is applied) on the substrate side. It is possible to control. In addition, different frequencies of RF power can be applied depending on the film to be etched.

In order to obtain high-density plasma with an ICP etching apparatus, an RF current J flowing through the antenna coil 12 is required.
Must be flowed with low loss, and in order to increase the area, the inductance of the antenna coil 12 must be reduced. For this purpose, an ICP etching apparatus for a multi-spiral coil 22 in which an antenna is divided as shown in FIG. 23 has been developed. 23 in FIG. 23 is a quartz plate, 23,
26 is a matching box, and 24 and 27 are RF power supplies. At the bottom of the chamber, a lower electrode 25 for holding a substrate 28 is provided via an insulator 29.

In this example, a wiring having a desired taper angle θ was formed by using a multi-spiral coil type ICP etching apparatus among various ICP etching apparatuses.

In this embodiment, in order to obtain a desired taper angle θ, the bias power density of the ICP etching apparatus is adjusted. FIG. 24 is a diagram showing the bias power dependence of the taper angle θ. As shown in FIG. 24, the taper angle θ can be controlled according to the bias power density.

The flow ratio of CF _{4 in} the etching gas (mixed gas of CF ₄ and Cl ₂ ) may be adjusted. FIG. 25 is a diagram showing the dependence of the taper angle θ on the flow ratio of CF ₄ . If the flow ratio of CF ₄ is increased, the selectivity between tungsten and resist is increased, and the taper angle θ of the wiring can be increased.

It is considered that the taper angle θ depends on the selectivity between tungsten and resist. FIG. 26 shows the dependence of the selectivity of tungsten and resist on the taper angle θ.

By appropriately determining the bias power density and the reactant gas flow ratio by using the ICP etching apparatus as described above, the desired taper angle θ = 3 to 60 can be extremely easily obtained.
° (preferably 5 to 45 °, more preferably 7 to 20 °)
The gate electrode and the wiring having the above can be formed.

Although the W film is shown as an example here, generally known heat-resistant conductive materials (Ta, Ti, M
When an ICP etching apparatus is used for (o, Cr, Nb, Si, etc.), the end of the pattern can be easily processed into a tapered shape.

In addition, the edge used for the dry etching is used.
CF as a gas_Four(Carbon tetrafluoride gas) and Cl_TwoMoth
Although a mixed gas with a gas was used, there is no particular limitation, for example,
C_TwoF ₆Or C_FourF₈Reaction gas containing fluorine selected from
And Cl_Two, SiCl_FourOr BCl_ThreeSalt selected from
It is also possible to use a mixed gas with a gas containing nitrogen.

In the subsequent steps, according to the first embodiment, the semiconductor device is completed.

The structure of this embodiment can be applied to the process of manufacturing an electrode having a tapered portion of the embodiment described in this specification.

[Eighth Embodiment] In the first embodiment, a polycrystalline silicon film crystallized by an excimer laser is used for the semiconductor layer. However, this embodiment shows another crystallization method.

The crystallization step of this embodiment is described in JP-A-7-130.
652 discloses a crystallization technique. This crystallization step will be described with reference to FIG.

First, a silicon oxide film 1002 is formed as a base film on a glass substrate 1001. Silicon oxide film 1
An amorphous silicon film 1003 is formed over 002. In this embodiment, the silicon oxide film 1002 and the amorphous silicon film 1
003 was continuously formed by a sputtering method. next,
A nickel acetate solution containing 10 ppm by weight of nickel was applied to form a nickel-containing layer 1004. (FIG. 27A)

[0219] In addition to nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn),
One or more elements selected from elements such as lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold (Au), and silicon (Si) may be used.

Next, after a hydrogenation step at 600 ° C. for 1 hour, a heat treatment is performed at 450 ° C. to 1100 ° C. for 4 to 12 hours (500 ° C. for 4 hours in this embodiment) to obtain the crystalline silicon film 1.
005 was formed. It has been found that the crystalline silicon film 1005 thus obtained has extremely excellent crystallinity. (FIG. 27 (B))

Note that the crystallization step of this embodiment can be applied to the step of forming a semiconductor layer described in this specification.

[Embodiment 9] This embodiment relates to a crystallization step different from that of Embodiment 8, and is disclosed in
An example in the case of crystallization using the technique described in Japanese Patent Publication No. 329 will be described. The technique described in Japanese Patent Application Laid-Open No. 8-78329 enables selective crystallization of a semiconductor film by selectively adding a catalyst element. A case where the same technology is applied to the present invention will be described with reference to FIG.

First, a silicon oxide film 1012 was formed on a glass substrate 1011, and an amorphous silicon film 1013 and a silicon oxide film 1014 were formed continuously on the surface thereof. At this time, the thickness of the silicon oxide film 1014 is 150 n.
m.

Next, an opening 1015 was selectively formed by patterning the silicon oxide film 1014, and then a nickel acetate solution containing 100 ppm by weight of nickel was applied. The formed nickel-containing layer 1016 was in contact with the amorphous silicon film 1013 only at the bottom of the opening 1015. (FIG. 28A)

Next, a heat treatment was performed at 500 to 650 ° C. for 4 to 24 hours (in this embodiment, 14 hours at 550 ° C.) to crystallize the amorphous silicon film. In this crystallization process, the portion in contact with nickel is first crystallized, and crystal growth proceeds in a direction substantially parallel to the substrate. It has been confirmed crystallographically that it proceeds in the <111> axis direction.

The crystalline silicon film 10 thus formed is
Reference numeral 17 is an aggregation of rod-shaped or needle-shaped crystals, and each rod-shaped crystal macroscopically grows in a specific direction, and thus has the advantage of uniform crystallinity.

In the technology described in the above publication, germanium (Ge) and iron (F) are also used in addition to nickel (Ni).
e), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold (Au), silicon (Si) A plurality of elements can be used.

A semiconductor film including a crystal (including a crystalline silicon film and a crystalline silicon germanium film) is formed by using the above-described techniques, and is patterned to form a semiconductor layer formed of a semiconductor film including a crystal. Good. Subsequent steps may follow the first embodiment. Of course, a combination with Embodiments 2 to 7 is also possible.

When a TFT is manufactured using a semiconductor film containing crystals crystallized by using the technique of this embodiment, high field-effect mobility (mobility) can be obtained, but high reliability has been required. . However, the TF of the present invention
The adoption of the T structure makes it possible to manufacture a TFT that makes full use of the technology of this embodiment.

[Embodiment 10] This embodiment relates to Embodiment 8,
An example in which a step of removing nickel used for crystallization of the semiconductor shown in No. 9 using phosphorus after crystallization is performed will be described. In the present embodiment, the technique described in JP-A-10-135468 or 10-135469 was used as the method.

The technique described in the publication is a technique of removing the catalytic element used for crystallization of the amorphous semiconductor film after crystallization by using the gettering action of phosphorus. By using the same technology, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 1
It can be reduced to 0 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ .

The configuration of this embodiment will be described with reference to FIG. Here, an alkali-free glass substrate typified by a Corning 1737 substrate was used. In FIG. 29A, the underlying film 1 is formed using the crystallization technique described in the second embodiment.
022, a state where the crystalline silicon film 1023 is formed. Then, a silicon oxide film 1024 for a mask is formed on the surface of the crystalline silicon film 1023 to a thickness of 150 nm, an opening is provided by patterning, and a region where the crystalline silicon film is exposed is provided. And
By performing the step of adding phosphorus, a region 1025 in which phosphorus was added to the crystalline silicon film was provided.

In this state, 550 to 10
When heat treatment is performed at 20 ° C. for 5 to 24 hours, for example, at 600 ° C. for 12 hours, the region 1025 in which phosphorus is added to the crystalline silicon film functions as a gettering site, and the catalyst remaining in the crystalline silicon film 1023 The element was able to segregate in the region 1025 to which phosphorus was added.

Then, silicon oxide film 1024 for mask is used.
And the region 1025 to which phosphorus is added by etching to remove the crystalline silicon film in which the concentration of the catalyst element used in the crystallization step is reduced to 1 × 10 ¹⁷ atms / cm ³ or less. I got it. This crystalline silicon film could be used as it is as the semiconductor layer of the TFT of the present invention shown in the first embodiment.

[Embodiment 11] This embodiment shows an example in which the techniques described in JP-A-10-135468 or JP-A-10-135469 are combined with Embodiments 8 and 9.

The technology described in the publication is described in Examples 3 and 4.
This is a technique for removing the nickel used for crystallization of the semiconductor shown in the above by using the gettering action of a halogen element (typically chlorine) after crystallization. By using this technique, the nickel concentration in the semiconductor layer can be reduced to 1 × 10 ¹⁷ atoms / cm ³ or less (preferably 1 × 10 ¹⁶ atoms / cm ³ or less).

The structure of this embodiment will be described with reference to FIG. First, a quartz substrate 1031 having high heat resistance is used as a substrate.
Was used. Of course, a silicon substrate or a ceramic substrate may be used. When a quartz substrate is used, there is no contamination from the substrate side even if a silicon oxide film is not provided as a base film.

Next, a crystalline silicon film (not shown) was formed by using the crystallization method of Embodiments 3 and 4, and was patterned to form semiconductor layers 1032 and 1033. Further, a gate insulating film 1034 made of a silicon oxide film was formed to cover the semiconductor layers. (FIG. 30A)

After forming the gate insulating film 1034, heat treatment was performed in an atmosphere containing a halogen element. In this embodiment, the processing atmosphere is an oxidizing atmosphere in which oxygen and hydrogen chloride are mixed, the processing temperature is 950 ° C., and the processing time is 30 minutes. The processing temperature may be selected from 700 to 1150 ° C (typically 900 to 1000 ° C), and the processing time is also 10 minutes to 8 hours (typically 30 minutes to 2 hours).
You can choose between. (FIG. 30 (B))

At this time, nickel becomes volatile nickel chloride and is released into the processing atmosphere, and the nickel concentration in the crystalline silicon film is reduced. Therefore, the concentration of nickel contained in the semiconductor layers 1035 and 1036 shown in FIG. 30B was reduced to 1 × 10 ¹⁷ atoms / cm ³ or less.

A semiconductor layer is formed by using this embodiment having the above-described technique, and the subsequent steps may be performed according to the first and second embodiments. Of course, it has been found that the combination of the crystallization methods of the present embodiment and the embodiment 4 can realize a crystalline silicon film having extremely high crystallinity.

(Knowledge on Crystal Structure of Semiconductor Layer) The semiconductor layer formed in accordance with the above-described manufacturing process has a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) gathered and arranged microscopically. It has a crystal structure. This is T
It was easily confirmed by observation by EM (transmission electron microscopy).

Further, electron diffraction and X-ray (X-ray)
Using diffraction, it was confirmed that the main orientation plane was a {110} plane, although the surface of the semiconductor layer (portion where a channel was formed) contained some deviation in the crystal axis. As a result of the applicant's detailed observation of an electron beam diffraction photograph with a spot diameter of about 1.5 μm, diffraction spots corresponding to the {110} plane clearly appear, but each spot has a distribution on a concentric circle. confirmed.

The applicant has observed, by HR-TEM (high-resolution transmission electron microscopy), a grain boundary formed by the contact of individual rod-shaped crystals, and found that the crystal lattice at the grain boundary has continuity. It was confirmed. This can be easily confirmed because the observed lattice fringes are continuously connected at the crystal grain boundaries.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

Particularly, when the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

As a result of observing the crystalline silicon film obtained by carrying out the present invention in detail by using a TEM, it was found that most (90% or more, typically 95% or more) of the crystal grain boundary was $ 3.
, That is, a {211} twin grain boundary.

In a grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3.

In the crystalline silicon film of this embodiment, the lattice fringes of adjacent crystal grains at the crystal grain boundary are continuous at exactly an angle of about 70.5 °, which means that this crystal grain boundary has
We arrived at the conclusion that it was a 1｝ twin grain boundary.

When θ = 38.9 °, a corresponding grain boundary of Σ9 was obtained, but such other crystal grain boundaries also existed.

Such a corresponding grain boundary is formed only between crystal grains having the same plane orientation. That is, the crystalline silicon film obtained by carrying out the present embodiment can form such a corresponding grain boundary over a wide range only because the plane orientation is approximately {110}.

Such a crystal structure (accurately, the structure of a crystal grain boundary) indicates that two different crystal grains at the crystal grain boundary are joined with extremely high consistency. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, it can be considered that the semiconductor thin film having such a crystal structure has substantially no crystal grain boundary.

It has been confirmed by TEM observation that defects existing in crystal grains have almost disappeared by the heat treatment process at a high temperature of 700 to 1150 ° C.
This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, the spin density of the crystalline silicon film manufactured according to the manufacturing process of this embodiment is at least 3 × 10 ¹⁷ spins / cm ³ or less (preferably 5 × 10 ¹⁵ s).
pins / cm ³ or less). However,
Since this measurement is close to the detection limit of existing measuring equipment,
The actual spin density is expected to be even lower.

As described above, the crystalline silicon film obtained by performing this embodiment has substantially no single crystal silicon film or substantially single crystal silicon film because there is substantially no inside of crystal grains and no crystal grain boundaries. Think of it as a membrane. The present applicant has proposed a crystalline silicon film having such a crystal structure as CGS (Continuou).
s Grain Silicon).

The description relating to CGS is disclosed in Japanese Patent Application Laid-Open No. Hei 10-294280 and Japanese Patent Application No. Hei 10-15231 by the present applicant.
6, Japanese Patent Application No. 10-152308 or Japanese Patent Application No. 10-152308
Reference may be had to the application of US Pat.

(Knowledge Regarding Electrical Characteristics of TFT) The TFT manufactured in this example exhibited electrical characteristics comparable to MOSFETs. The following data is obtained from the TFT prototyped by the present applicant.

The sub-threshold coefficient which is an index of the switching performance (the agility of switching on / off operation) is
60 for both n-channel and p-channel TFTs
~ 100mV / decade (typically 60-85mV / decade).

(2) The field effect mobility (μFE) which is an index of the operation speed of the TFT is 200 to 65 for the n-channel type TFT.
0 cm ² / Vs (typically 300 to 500 cm ² / Vs), 100 to 300 cm ² / Vs for p-channel TFT (typically 150 to ²⁰⁰ cm ² / Vs)
Vs) and big.

(3) The threshold voltage (Vth) as an index of the driving voltage of the TFT is -0.5 to 1.5 for the n-channel TFT.
V, p-channel type TFT is as small as -1.5 to 0.5 V.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

(Knowledge on Circuit Characteristics) Next, the frequency characteristics of a ring oscillator manufactured using the TFT formed by carrying out this embodiment will be described. The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered stage ring shape, and is used to determine a delay time per one stage of the inverter circuit. The configuration of the ring oscillator used in the experiment is as follows. Number of steps: 9 Steps Thickness of gate insulating film of TFT: 30 nm and 50 nm Gate length of TFT: 0.6 μm

As a result of examining the oscillation frequency with this ring oscillator, it was possible to obtain an oscillation frequency of 1.04 GHz as the maximum value. Further, a shift register, which is one of the TEGs of the LSI circuit, was actually manufactured, and the operating frequency was confirmed. As a result, the thickness of the gate insulating film is 30 nm, and the gate length is
An output pulse having an operation frequency of 100 MHz was obtained in a shift register circuit having 0.6 μm, a power supply voltage of 5 V, and 50 stages.

The surprising data of the ring oscillator and the shift register as described above is that the TFT of this embodiment is a MOS transistor.
Performance comparable to or superior to FET (electrical characteristics)
Has been shown.

[Embodiment 12] This embodiment also relates to a technique for gettering the catalyst element used in the crystallization step.

In the tenth embodiment, the gettering region 102 is used to getter the catalytic element in the crystallized silicon.
5 (see FIG. 29). Since the TFT cannot be formed in the gettering region,
Prevents circuit integration. The present embodiment is a gettering method that solves the above-described problem, and is an n-channel type TFT.
The n ⁺ -type impurity regions and, using a p ⁺ -type impurity region of the p-channel type TFT in the gettering region.

In the steps described in the first embodiment, n ⁺ -type impurity regions 313 to 315 and p ⁺ -type impurity regions
In 33, phosphorus exists at a high concentration of 5 × 10 ²⁰ atoms / cm ³ . (See FIGS. 14 and 16.) Therefore, these regions can be used as gettering regions.

For this reason, the semiconductor layers 302 to 30 of the TFT
In the case where the substrate No. 4 is formed of the crystalline silicon shown in the third and fourth embodiments, the step of activating phosphorus and boron may be combined with the heating step for gettering. For example, the activation step (FIG. 14)
(D) and FIG. 16 (D)).
C. (typically 550-600 C.) at a processing temperature of 2-2.
The heat treatment step may be performed for 4 hours (typically, 4 to 12 hours).

In this heat treatment step, the channel forming regions 311, 312, 325, 331, 341 of each TFT are formed.
Is diffused toward the n ⁺ -type impurity region and the p ⁺ -type impurity region by the action of phosphorus, and is captured there.

Therefore, n ⁺ -type impurity regions 313 to 31
5 and the concentration of nickel (catalyst) in p ⁺ -type impurity regions 332 and 333 is 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ³ (typically 1 × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm ³ ) On the other hand, the channel forming regions 311, 312, 325,
The nickel concentration of 331 and 341 is 2 × 10 ¹⁷ atoms / cm ³
Below (typically 1 × 10 ^{14 to} 5 × 10 ¹⁶ atoms / cm ³ )
Can be reduced to

In order to obtain the effect of this embodiment, n⁺Type
Impurity regions 313 to 315 and p ⁺Type impurity region 33
2,333 have a phosphorus or arsenic concentration of at least 1
× 10¹⁹atoms / cm^ThreeOr more (preferably 1 × 10²⁰~ 5x
10^{twenty one}atoms / cm^Three).

[Embodiment 13] The present embodiment is a modification of the CMOS circuit of the embodiment 1. Using FIG. The structure of the TFT of this embodiment will be described. FIG. 31 (A) to (D)
, The same reference numerals indicate the same components. In addition, the manufacturing steps of this embodiment may be the same as those of Embodiments 1 and 2, and the detailed description is omitted.

FIG. 31A shows a modification of the first embodiment, in which the second gate electrode (wiring) is omitted, and the gate electrode (wiring) is formed only by the electrode (wiring) having a tapered portion. It is an example.

A base film 901 made of silicon oxide is formed on the entire surface of the substrate 900. On the base film 901, island-shaped semiconductor layers of an n-channel TFT and a p-channel TFT are formed. A gate insulating film 905 is formed over the entire surface of the substrate 900 so as to cover the island-shaped semiconductor layers. Further, T
A protective film 906 made of silicon nitride and an interlayer insulating film 907 are formed to cover the FT, and a source electrode 941, 942 and a drain electrode 943 are formed on the interlayer insulating film 907.

A gate wiring (gate electrode) 933 is formed across the semiconductor layer with the gate insulating film 905 interposed therebetween. The side surface of the gate wiring 931 is formed in a tapered shape. Here, it was formed of chromium having a thickness of 250 nm. Further, the portion intersecting with the semiconductor layer of the p-channel TFT is reduced in width so that the second gate electrode 933 is formed.
A is formed.

Example 1 was applied to the method of adding phosphorus and boron to the semiconductor layer. In the semiconductor layer of the n-channel TFT, channel formation regions 911A, n ⁺ -type impurity regions 912A and 913A, n ⁻ -type impurity regions 914A and 915A overlapping with the gate electrode 931A, and the gate electrode 9
N ⁻ -type impurity regions 916 A, 9 9 which do not overlap with 31 A
17A are formed.

N ⁻ -type impurity regions 914 A, 915 A, n
^- -type impurity regions 916A, 917a is the concentration of phosphorus n ⁺
It is lower than the type impurity regions 912A and 913A. The junction between n ⁻ -type impurity regions 914A and 915A and channel formation region 911A is formed at gate electrode 931A.
Of the n ⁻ -type impurity region 914
The concentration of A and 915A decreases toward the channel formation region 911A.

On the other hand, in the semiconductor layer of the p-channel type TFT, a channel formation region 921A and ap ⁺ -type impurity region 92
2A, 923A, p ⁺ -type impurity regions 924A, 925A
Are formed. p ⁺ -type impurity regions 922A and 923
The p ⁺ -type impurity regions 924A and 925A have a lower phosphorus concentration and the same boron concentration than A.

FIG. 31B is a modification of the second and third embodiments, in which the second electrode is omitted and the gate electrode is formed only of an electrode having a tapered portion.

In FIG. 31B, the gate electrode 931B is formed in a tapered shape in both the n-channel TFT and the p-channel TFT. Here, it was formed of chromium having a thickness of 250 nm.

Example 2 was applied to the step of adding phosphorus and boron to the semiconductor layer. In the semiconductor layer of the n-channel TFT, channel formation region 911B, n ⁺ -type impurity regions 912B and 913B, n ⁻ -type impurity regions 914B and 915B overlapping with gate electrode 931B, and gate electrode 9
N ⁻ -type impurity regions 916B and 9 not overlapping with 31B
17B are formed.

N ⁻ -type impurity regions 914 B, 915 B, n
^- -type impurity regions 916B, 917b is the concentration of phosphorus n ⁺
It is lower than the type impurity regions 912B and 913B. Further, n ^- -type impurity regions 914B, the junction between 915B and the channel formation region 911B is present under the taper portion of the gate electrode 931, n ^- -type impurity regions 914B,
The concentration of 915B decreases toward the channel formation region 911B.

On the other hand, in the semiconductor layer of the p-channel type TFT, the channel formation region 921B and the p ⁺ -type impurity region 92
2B and 923B are formed in a self-aligned manner using the gate electrode 931B as a mask.

FIG. 31C shows an example in which the taper etching of the first gate electrode is omitted in the first embodiment.

The gate wiring comprises a first gate wiring 931C and a second gate wiring 932C having a smaller width in the channel length direction than the first gate wiring 931C. Note that a portion where the first gate wiring 931C intersects with the semiconductor layer of the p-channel TFT is provided with a third gate electrode 933C having a reduced width using the second gate wiring 932C as a mask.

In the semiconductor layer of the n-channel TFT, a channel formation region 911C, n ⁺ -type impurity regions 912C, 9
@ 13 C, n overlaps with the gate electrode 931C ^- impurity type regions 914C, 915C, not overlapping with the gate electrode 931C n ^- -type impurity regions 916C, 917C are formed.

N ⁻ -type impurity regions 914 C, 915 C, n
^- -type impurity regions 916C, 917C is the concentration of phosphorus n ⁺
It is lower than the type impurity regions 912C and 913C.

On the other hand, in the semiconductor layer of the p-channel TFT, a channel formation region 921C and ap ⁺ -type impurity region 92
2C, 923C, p ⁺ -type impurity regions 924C, 925C
Are formed. p ⁺ -type impurity regions 924C and 925
C has a lower phosphorus concentration than the p ⁺ -type impurity regions 922C and 923C.

FIG. 31D shows an example in which the fourth gate wiring covering the surface of the gate wiring is formed in the first embodiment.

In the CMOS circuit, the step of adding boron is performed according to the steps of the first embodiment. Next, instead of forming the protective film 906 made of silicon nitride, a metal film made of chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), or these elements is used. An alloy as a main component or a conductive material such as silicide is formed and patterned to form a fourth gate wiring 934D. After that, activation may be performed.

With this structure, the second gate wiring 932
D is the first gate wiring 931D (third gate electrode 93
3D) and a fourth gate wiring 934D.

In this case, the semiconductor of the n-channel TFT is
In the body layer, channel formation regions 911D, n⁺Type impurity area
Area 912D, 913D, overlap with gate electrode 931D
N^-Impurity type regions 914D, 915D, gate electrode
N not overlapping with 931D ^-Type impurity region 916D,
917D is formed, but n^-Type impurity region 914
D and 915D intersect the first and fourth gate electrodes.
And n^-Type impurity regions 916D and 917D
It does not intersect with the fourth gate electrode 934D.

The advantage of this structure is that the first gate electrode 93
This is particularly effective when phosphorus is hardly added to the semiconductor layer below 1D. As shown in FIG. 31D, n ⁻
The impurity type regions 914D and 915D are the first gate electrodes 9
Even if the fourth gate electrode 934D does not substantially overlap with the base electrode 31D, the fourth gate electrode 934D can overlap the n ⁻ -type impurity region.
^- it is possible to form the impurity regions.

On the other hand, the channel formation region 921D and the p ⁺ -type impurity region 92
2D, 923D, p ⁺ -type impurity regions 924D, 925D
Are formed. p ⁺ -type impurity regions 924D and 925
D has a lower phosphorus concentration than the p ⁺ -type impurity regions 922D and 923D. In this case, the n ⁻ -type impurity region and the fourth gate electrode 934D overlap. In the case where a problem occurs in off-state current characteristics or withstand voltage, when forming the fourth gate wiring 934D, be careful not to form the fourth gate wiring 934D in a portion that intersects with the semiconductor layer of the p-channel TFT. What should I do?

[Embodiment 14] In the liquid crystal display device described in this specification, various liquid crystals other than the nematic liquid crystal can be used. For example, 1998, SID, "Characteristics
and Driving Scheme of Polymer-Stabilized Monostable
FLCD Exhibiting Fast Response Time and High Contra
st Ratio with Gray-Scale Capability "by H. Furue e
t al., 1997, SID DIGEST, 841, "A Full-Color Thre
sholdless Antiferroelectric LCDExhibiting Wide Vie
wing Angle with Fast Response Time "by T. Yoshida
et al., 1996, J. Mater. Chem. 6 (4), 671-673, "Thr
esholdless antiferroelectricity in liquid crystals
and its application to displays "by S. Inui et a
and the liquid crystal disclosed in U.S. Pat. No. 5,594,569 can be used.

A ferroelectric liquid crystal (FLC) showing an isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 41 shows the electro-optical characteristics of a monostable FLC in which the cholesteric phase-chiral smectic C phase transition is performed while applying a DC voltage and the cone edge is almost aligned with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 41 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 41 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For the fV-shaped switching mode, see Terada et al.
Half-V switching mode FLCD ", 46th
Proceedings of the JSCE Lecture Meeting, March 1999
Moon, p. 1316, and Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol. 3, No. 19, 1992.
See page 0 for details.

As shown in FIG. 41, it can be seen that when such a ferroelectric mixed liquid crystal is used, low-voltage driving and gradation display are possible. A ferroelectric liquid crystal having such electro-optical characteristics can be used in the liquid crystal display device of the present invention.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

Note that low-voltage driving is realized by using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, so that low power consumption is realized.

[Embodiment 15] The TFT according to the present invention is described in Embodiment 1.
The present invention can be applied not only to the liquid crystal display device shown in FIG. That is, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor, or from a signal processing circuit such as a D / A converter to a portable device (cellular phone, PHS, mobile computer).
May be applied to a high-frequency circuit for use.

Further, it is possible to realize a semiconductor device having a three-dimensional structure in which an interlayer insulating film is formed on a conventional MOSFET, and a semiconductor circuit is formed thereon using the TFT of the present invention. As described above, the present invention can be applied to all semiconductor devices using LSIs at present. That is, SIMOX, Smart-Cut (SOITEC
The present invention may be applied to an SOI structure (TFT structure using a single crystal semiconductor thin film) such as a registered trademark of ELECTRONICS CORPORATION and ELTRAN (a registered trademark of Canon Inc.).

The semiconductor circuit of this embodiment is similar to those of the first to third embodiments.
The present invention can be realized by using any combination of the thirteen combinations.

[Embodiment 16] In this embodiment, an example in which an active matrix EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 35A is a top view of an EL display device using the present invention. In FIG. 35A, 4010
Denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, and 4013 denotes a gate side driver circuit. Each of the driver circuits is connected to an FPC 4017 through wirings 4014 to 4016.
And connected to the external device.

At this time, the cover material 600 is formed so as to surround at least the pixel portion, preferably the driving circuit and the pixel portion.
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 35B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
The FT may use a known structure (top gate structure or bottom gate structure).

The present invention is directed to a TFT 4022 for a driving circuit,
It can be used for the TFT 4023 for the pixel portion.

By using the present invention, the TFT 402 for the driving circuit
2. When the pixel portion TFT 4023 is completed, the pixel portion TFT is formed on an interlayer insulating film (flattening film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the FT 4023 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

[0312] In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, a cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 4030 is
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

The cathode 40 in the region indicated by 4031
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Further, the sealing material 7000 and the sealing material 7 are provided inside the substrate 4010 so as to surround the EL element portion.
000 is provided, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0319] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

[Embodiment 17] In this embodiment, an example of manufacturing an EL display device different from that of Embodiment 16 by using the present invention will be described with reference to FIGS. 36 (A) and 36 (B). . 35 (A) and 35 (B) indicate the same parts, and thus description thereof will be omitted.

FIG. 36A is a top view of the EL display device of this embodiment, and FIG. 36B is a cross-sectional view taken along line AA ′ of FIG. 36A.

According to the seventeenth embodiment, up to the passivation film 6003 is formed to cover the surface of the EL element.

[0327] Further, a filler 6004 is provided so as to cover the EL element. This filler 6004 is used as the cover material 6
000 also functions as an adhesive for bonding. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

Further, a spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

[0331] However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

[0332] Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of the sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

[Embodiment 18] Embodiments 16 and 1
The present invention can be used in an active matrix type EL display panel having the configuration as shown in FIG. In Embodiments 17 and 18, light is emitted downward. In this embodiment, an example of a more detailed sectional structure of the pixel portion is shown in FIG. 37, an upper surface structure is shown in FIG. The figure is shown in FIG. FIGS. 37, 38 (A) and 38
In (B), since a common code is used, they may be referred to each other. In this embodiment, an example of upward irradiation is shown. However, it goes without saying that an EL display device can be manufactured by applying the structure of the pixel portion of this embodiment to Embodiments 17 and 18.

In FIG. 37, the switching TFT 3502 provided on the substrate 3501 is the NTF of the present invention.
It is formed using T (see Examples 1 to 13). In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However,
The double gate structure has a structure in which substantially two TFTs are connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. In addition, the PT of the present invention
It may be formed using FT.

The current controlling TFT 3503 is formed using the NTFT of the present invention. At this time, the drain wiring 3035 of the switching TFT 3502 is connected to the wiring 3
036, the gate electrode 3037 of the current controlling TFT
Is electrically connected to From the gate wiring 3039 to the gate electrode 3039a of the switching TFT 3502,
3039b is extended. Note that, although the drawing is complicated, FIG. 38A shows only one layer of the gate wiring 3039 and the gate electrodes 3037, 3039a, and 3039b, but actually has two layers as shown in FIG.

At this time, it is very important that the current control TFT 3503 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current controlling TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

In this embodiment, the current controlling TFT 35 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

As shown in FIG. 38A, the wiring which becomes the gate electrode 3037 of the current controlling TFT 3503 is a region indicated by 3504, and the current controlling TFT 3503
Overlap with the drain wiring 3040 via the insulating film. At this time, a capacitor is formed in a region indicated by 3504. This capacitor 3504 is used as a current controlling TFT 35.
It functions as a capacitor for holding the voltage applied to the gate of the gate 03. Note that the drain wiring 3040 is connected to a current supply line (power supply line) 3601, and a constant voltage is constantly applied.

The first passivation film 3 is formed on the switching TFT 3502 and the current control TFT 3503.
041 is provided, and a planarizing film 3042 made of a resin insulating film is formed thereon. TF using the flattening film 3042
It is very important to flatten the step due to T. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, E
It is desirable to planarize the pixel layer before forming the pixel electrode so that the L layer can be formed as flat as possible.

Reference numeral 3043 denotes a pixel electrode (a cathode of an EL element) made of a highly reflective conductive film, and a current control TF
It is electrically connected to the drain of T3503. As the pixel electrode 3043, a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof is preferably used. Of course, a stacked structure with another conductive film may be employed.

A light emitting layer 3045 is formed in a groove (corresponding to a pixel) formed by banks 3044a and 3044b formed of an insulating film (preferably resin). Although only one pixel is shown here, R
Light emitting layers corresponding to the colors (red), G (green), and B (blue) may be separately formed. A conjugated polymer-based material is used as the organic EL material for the light emitting layer. Typical polymer-based materials include polyparaphenylene vinylene (PPV),
Examples thereof include polyvinyl carbazole (PVK) and polyfluorene.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As a specific light emitting layer, cyanopolyphenylenevinylene is used for a red light emitting layer, polyphenylene vinylene is used for a green light emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of an organic EL material that can be used as a light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, the PED is formed on the light emitting layer 3045.
EL having a laminated structure provided with a hole injection layer 3046 made of OT (polythiophene) or PAni (polyaniline)
And layers. An anode 3047 made of a transparent conductive film is provided over the hole injection layer 3046. In the case of this embodiment, since the light generated in the light emitting layer 3045 is emitted toward the upper surface (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

[0348] When the anode 3047 is formed, the EL element 3505 is completed. Note that the EL element 35 here
05 denotes a pixel electrode (cathode) 3043, a light emitting layer 3045,
Refers to a diode formed by the hole injection layer 3046 and the anode 3047. As shown in FIG.
Since 43 substantially corresponds to the area of the pixel, the entire pixel is EL
Functions as an element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In this embodiment, a second passivation film 3048 is further provided on the anode 3047. As the second passivation film 3048, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 37, and a switching TFT having a sufficiently low off-current value and a current control device which is strong against hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

The structure of this embodiment is similar to that of the first to thirteenth embodiments.
It can be implemented in any combination with the configuration.
In addition, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of Embodiment 22.

[Embodiment 19] In this embodiment, Embodiment 18 will be described.
A structure in which the structure of the EL element 3505 is inverted in the pixel portion shown in FIG. FIG. 39 is used for the description. Note that the point different from the structure of FIG. 37 is only the EL element portion and the current controlling TFT, and the other description is omitted.

In FIG. 39, the current controlling TFT 350
3 is formed using the PTFT of the present invention. For the manufacturing process, Embodiments 1 to 13 may be referred to.

In this embodiment, the pixel electrode (anode) 3050
Is used as a transparent conductive film. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Of course, a conductive film formed of a compound of indium oxide and tin oxide may be used.

Then, the bank 3051a made of an insulating film,
After the formation of 3051b, a light emitting layer 3052 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 3053 made of potassium acetylacetonate (denoted as acacK) and a cathode 3054 made of an aluminum alloy are formed thereon. In this case, the cathode 3
054 also functions as a passivation film. Thus, an EL element 3701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 3052 is radiated outside from the substrate on which the TFT is formed as shown by the arrow.

The structure of this embodiment is similar to those of the first to thirteenth embodiments.
Can be freely combined with the above configuration. In addition, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of Embodiment 22.

[Embodiment 20] In this embodiment, FIG.
FIGS. 40A to 40C illustrate an example in which a pixel having a structure different from that of the circuit diagram illustrated in FIG. In this embodiment, 3801 is a switching TF.
T3802 source wiring, 3803 switching T
FT3802 gate wiring; 3804, TF for current control
T and 3805 are capacitors, 3806 and 3808 are current supply lines, and 3807 is an EL element.

FIG. 40A shows an example in which a current supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 40B shows a current supply line 380.
8 is provided in parallel with the gate wiring 3803. Note that although the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other in FIG. 40B, if the wiring is formed in a different layer,
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

In FIG. 40C, a current supply line 3808 is provided in parallel with the gate wiring 3803 in the same manner as in the structure of FIG. 40B, and two pixels are connected to the current supply line 3808.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of this embodiment is similar to that of the first to first embodiments.
3, 15 to 17 can be freely combined and implemented. In addition, it is effective to use an EL display panel having a pixel structure of this embodiment as a display portion of the electronic device of Embodiment 22.

Example 21 FIG. 3 shown in Example 18
In FIGS. 8A and 38B, a capacitor 350 is used to hold a voltage applied to the gate of the current controlling TFT 3503.
4, but the capacitor 3504 can be omitted. In the case of the nineteenth embodiment, since the NTFT of the present invention as shown in the first to thirteenth embodiments is used as the current controlling TFT 3503, the LDD region provided so as to overlap the gate electrode via the gate insulating film is provided. ing. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

In addition, FIGS. 40 (A) to 40 (A) to
Similarly, in the structure of (C), the capacitor 3805 can be omitted.

The structure of this embodiment is similar to that of the first to first embodiments.
3, 16 to 20 can be freely combined and implemented. In addition, it is effective to use an EL display panel having a pixel structure of this embodiment as a display portion of the electronic device of Embodiment 22. Examples 17 to 22
Among them, NTFT and PTFT are the n-channel type TF of the present application.
It goes without saying that it refers to the same thing as the T and p channel type TFTs.

Embodiment 22 A semiconductor device using a TFT formed by carrying out the present invention can be applied to various semiconductor circuits and display devices typified by electro-optical devices. That is, the present invention can be applied to all electronic devices in which the electro-optical device and the semiconductor circuit are incorporated as components.

[0368] Such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a personal computer, and a portable information terminal (mobile computer, mobile phone). Or an electronic book). Examples of these are shown in FIGS.

FIG. 32A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display device 2.
003 and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.

FIG. 32B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, an operation switch 2104, a battery 2105, and an image receiving portion 21.
06. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

FIG. 32C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 and other signal control circuits.

FIG. 32D shows a goggle type display, which includes a main body 2301, a display device 2302, and an arm 23.
03. The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 32E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display device 2402, and a speaker unit 24.
03, a recording medium 2404, and operation switches 2405. This device uses a DVD (Digt
al Versatile Disc), CDs, etc., to enjoy music, movies, games and the Internet. The present invention can be applied to the display device 2402 and other signal control circuits.

FIG. 32F shows a digital camera, which comprises a main body 2501, a display device 2502, an eyepiece unit 2503, operation switches 2504, and an image receiving unit (not shown). The present invention can be applied to the display device 2502 and other signal control circuits.

FIG. 33A shows a front type projector, which comprises a display device 2601 and a screen 2602. The present invention can be applied to a display device and other signal control circuits.

FIG. 33B shows a rear type projector, which includes a main body 2701, a display device 2702, and a mirror 270.
3. It is composed of a screen 2704. The present invention can be applied to a display device and other signal control circuits.

[0377] FIG. 33C is a diagram showing an example of the structure of the display devices 2601 and 2702 in FIGS. 33A and 33B. Display devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 33D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 33D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

As described above, the semiconductor device of the present invention has an extremely wide range of application, and can be applied to electronic devices in all fields. Further, the semiconductor device of the present embodiment can be realized by using a configuration composed of any combination of Embodiments 1 to 21.

[0380]

According to the present invention, the reliability of the TFT can be improved, and in particular, the reliability of the n-channel TFT can be improved. Therefore, it has become possible to secure the reliability of the channel FT having high electrical characteristics (especially high mobility) requiring strict reliability. At the same time, by forming a CMOS circuit by combining an n-channel TFT and a p-channel TFT having excellent characteristic balance, a semiconductor circuit having high reliability and excellent electric characteristics can be formed.

Further, in the present invention, since the number of catalytic elements used for crystallization of a semiconductor can be reduced, a semiconductor device with less instability can be realized. Moreover, since the step of reducing the catalytic element is performed simultaneously with the formation and activation of the source region and the drain region, the throughput does not decrease.

As described above, by increasing the reliability of a circuit formed by TFTs, it is possible to ensure the reliability of all semiconductor devices including electro-optical devices, semiconductor circuits, and electronic devices.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention. (Embodiment 1)

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention. (Embodiment 1)

FIG. 3 is a partial cross-sectional view of a gate electrode. (Embodiment 1)

FIG. 4 is a partial cross-sectional view of a semiconductor layer. (Embodiment 1)

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention. (Embodiment 2)

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention. (Embodiment 2)

FIG. 7 is a cross-sectional view of a TFT of the present invention. (Embodiment 3)

FIG. 8 is a cross-sectional view of a TFT of the present invention. (Embodiment 4)

FIG. 9 is a cross-sectional view of a TFT of the present invention. (Embodiment 4)

FIG. 10 is a diagram schematically showing a liquid crystal display device of the present invention. (Example 1)

FIG. 11 is a top view of a pixel portion and a CMOS circuit of the present invention.
(Example 1)

FIG. 12 is a cross-sectional view of the active matrix substrate of the present invention. (Example 1)

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a pixel portion of the present invention.
(Example 1)

FIG. 14 is a cross-sectional view illustrating a manufacturing process of a pixel portion of the present invention.
(Example 1)

FIG. 15 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 1)

FIG. 16 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 1)

FIG. 17 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 2)

FIG. 18 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 3)

FIG. 19 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 4)

FIG. 20 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 5)

FIG. 21 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 6)

FIG. 22 is a diagram showing a plasma generation mechanism of the ICP etching apparatus. (Example 7)

FIG. 23 is a conceptual diagram of a multi-spiral coil type ICP etching apparatus. (Example 7)

FIG. 24 is a characteristic diagram of bias power versus taper angle θ. (Example 7)

FIG. 25 is a characteristic diagram of a flow ratio of CF ₄ to a taper angle θ.
(Example 7)

FIG. 26 is a (W / resist) selectivity versus taper angle θ characteristic diagram. (Example 7)

FIG. 27 is a diagram showing a manufacturing process of a crystalline silicon film of the present invention. (Example 8)

FIG. 28 is a diagram showing a manufacturing process of a crystalline silicon film of the present invention. (Example 9)

FIG 29 is a view showing a manufacturing process of a crystalline silicon film of the present invention. (Example 10)

FIG. 30 is a diagram showing a manufacturing process of a crystalline silicon film of the present invention. (Example 11)

FIG. 31 is a cross-sectional view illustrating a manufacturing process of a CMOS circuit of the present invention. (Example 13)

FIG. 32 illustrates an example of an electronic device of the invention. (Example 22)

FIG. 33 illustrates an example of an electronic device of the invention. (Example 22)

FIG. 34 is a graph showing gate voltage-drain current characteristics of a TFT.

FIG. 35 illustrates a structure of an active matrix EL display device. (Example 16)

FIG. 36 illustrates a structure of an active matrix EL display device. (Example 17)

FIG. 37 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix EL display device. (Example 18)

38A and 38B are a top view and a circuit diagram illustrating a structure of a pixel portion of an active matrix EL display device. (Example 18)

FIG. 39 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix EL display device. (Example 19)

FIG. 40 is a circuit diagram illustrating a configuration of a pixel portion of an active matrix EL display device. (Example 20)

FIG. 41 is a diagram showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal. (Example 14)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 627G F-term (Reference) 5F052 AA02 AA17 AA24 BA02 BA07 BB01 BB07 DA01 DA02 DA03 DB02 DB03 DB07 GB05 JA01 JA10 5F110 AA06 AA26 BB02 BB04 CC02 DD01 DD02 DD03 DD12 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE05 EE06 EE09 EE14 EE15 EE23 EE44 FF02 FF03 FF04 FF09 FF10 FF28 FF30 GG13 GG03 GG01 GG02 GG03 GG03 GG03 GG02 GG03 GG02 GG03 GG02 GG03 GG03 GG03 GG02 GG03 HJ23 HL03 HL04 HL12 HL24 HM15 NN02 NN23 NN24 NN35 NN73 NN74 PP02 PP03 PP05 PP06 PP10 PP34 PP35 QQ04 QQ05 QQ11 QQ19 QQ28

Claims (38)

[Claims] A thin film transistor including a semiconductor layer, a gate insulating film formed in contact with the semiconductor layer, and a gate electrode intersecting the semiconductor layer with the gate insulating film interposed therebetween. The angle formed by the gate insulating film is in the range of 3 degrees or more and 60 degrees or less, and the semiconductor layer includes a channel formation region, a conductive first impurity region, the channel formation region, and the first impurity region And a second impurity region of the same conductivity type as the first impurity region in contact with the channel formation region, and the first impurity region sandwiched between the first impurity region and the second impurity region. A third impurity region of the same conductivity type as the impurity, wherein the second impurity region overlaps the gate electrode via the gate insulating film, and the third impurity region is the third gate region. Not overlap To pole, said second impurity region and the third impurity region of a thin film transistor in which the concentration of impurities of the conductivity type is being lower than said first impurity region. 2. The semiconductor device according to claim 1, wherein the concentration of the conductivity type impurity in the second impurity region increases from the channel formation region toward the first impurity region. Thin film transistor. 3. A thin film transistor including a semiconductor layer, a gate insulating film formed in contact with the semiconductor layer, and a gate electrode intersecting the semiconductor layer with the gate insulating film interposed therebetween. A first gate electrode formed in contact with the gate insulating film, a second gate electrode in contact with the surface of the first gate electrode and having a smaller width in a channel length direction than the first gate electrode; An angle that a side surface of the first gate electrode forms with the gate insulating film is in a range of 3 degrees or more and 60 degrees or less, and the semiconductor layer includes a channel formation region and a conductive first impurity region. A second impurity region of the same conductivity type as the first impurity region sandwiched between the channel formation region and the first impurity region and in contact with the channel formation region; And a third impurity region of the same conductivity type as the first impurity sandwiched between second impurity regions, wherein the second impurity region is provided on the first gate electrode via the gate insulating film. And the third impurity region does not overlap with the first gate electrode. In the second impurity region and the third impurity region, the conductivity type impurity concentration is higher than that of the first impurity region. A thin film transistor characterized in that it is also low. 4. The semiconductor device according to claim 3, wherein the concentration of the conductivity type impurity in the second impurity region increases from the channel formation region toward the first impurity region. Thin film transistor. 5. A semiconductor device including a circuit including a thin film transistor having a semiconductor layer, a gate insulating film formed in contact with the semiconductor layer, and a gate electrode intersecting the semiconductor layer via the gate insulating film. An angle formed by a side surface of the gate electrode with the gate insulating film is in a range of 3 degrees or more and 60 degrees or less, and the semiconductor layer includes a channel formation region and a conductive layer formed outside the channel formation region. Sex First
An impurity region, a second impurity region of the same conductivity type as the first impurity region sandwiched between the channel formation region and the first impurity region and in contact with the channel formation region; And a third impurity region of the same conductivity type as the first impurity sandwiched between the second impurity region and the second impurity region. The third impurity region does not overlap with the gate electrode, and the second impurity region and the third impurity region have an impurity concentration of the conductivity type lower than that of the first impurity region. A semiconductor device characterized by the above-mentioned. 6. The semiconductor device according to claim 5, wherein the concentration of the conductivity type impurity in the second impurity region increases from the channel formation region toward the first impurity region. Semiconductor device. 7. The capacitor according to claim 5, wherein a capacitor is connected to the thin film transistor, and the capacitor has a semiconductor layer, a dielectric film in contact with a semiconductor layer surface of the capacitor, and an electrode in contact with the dielectric film. A semiconductor device characterized by the above-mentioned. 8. The semiconductor device according to claim 7, wherein the semiconductor layer of the capacitor includes a fourth impurity region having the same conductivity type as the first impurity region, and a region having the same concentration of the conductivity type impurity as the channel formation region. A semiconductor device comprising: 9. The semiconductor device according to claim 6, wherein a semiconductor layer of the thin film transistor and a semiconductor layer of the capacitor are integrated. 10. A liquid crystal display device comprising the semiconductor device according to claim 5 provided as a pixel matrix circuit of an active matrix display device. 11. An electroluminescent display device using the semiconductor device according to claim 5 as a pixel matrix circuit of an active matrix display device. 12. A video camera, a digital camera, comprising the display device according to claim 10.
Projector, goggle type display, car navigation system, personal computer or portable information terminal. 13. An n-channel type thin film transistor and a p-type thin film transistor
A semiconductor device including a CMOS circuit including a channel thin film transistor, wherein the n-type thin film transistor includes a first semiconductor layer, a first gate insulating film in contact with the first semiconductor layer, and a second gate. A gate electrode intersecting the first semiconductor layer via an insulating film, wherein the p-type thin film transistor has a second semiconductor layer, a second gate insulating film in contact with the second semiconductor layer, A second gate electrode intersecting the second semiconductor layer with the second gate insulating film interposed therebetween, and an angle formed by a side surface of the gate electrode of the n-type thin film transistor with the gate insulating film is 3 degrees. The first semiconductor layer includes a first channel formation region, a first n-type impurity region, a first channel formation region, and the first n-type impurity region. Sandwiched, and A second n-type impurity region in contact with the first channel formation region; and a third impurity region sandwiched between the first n-type impurity region and the second n-type impurity region; The second n-type impurity region overlaps with the gate electrode via the first gate insulating film, the third n-type impurity region does not overlap with the gate electrode, and the second n-type impurity region And the third n-type impurity region has an n-type impurity concentration lower than that of the first n-type impurity region. 14. An n-channel type thin film transistor and a p-type thin film transistor
A semiconductor device including a CMOS circuit including a channel thin film transistor, wherein the n-type thin film transistor includes a first semiconductor layer, a first gate insulating film in contact with the first semiconductor layer, and a second semiconductor layer. A gate electrode intersecting the first semiconductor layer with a gate insulating film interposed therebetween, wherein the p-type thin film transistor has a second semiconductor layer and a second gate insulating film in contact with the second semiconductor layer. A second gate electrode intersecting with the second semiconductor layer with the second gate insulating film interposed therebetween, and an angle formed by a side surface of the gate electrode of the n-type thin film transistor with the gate insulating film is 3 The first semiconductor layer includes a first channel forming region, a first n-type impurity region, a first channel forming region, and the first n-type impurity. The area is pinched, A second n-type impurity region in contact with the first channel formation region; and a third n-type impurity region sandwiched between the first n-type impurity region and the second n-type impurity region. The second n-type impurity region overlaps with the first gate electrode via the first gate insulating film, and the third n-type impurity region does not overlap with the first gate electrode. The second n-type impurity region and the third n-type impurity region have an n-type impurity concentration lower than that of the first n-type impurity region, and the second semiconductor layer includes a second A channel formation region; a first p-type impurity region; a second p-type impurity sandwiched between the second channel formation region and the first p-type impurity region and in contact with the second channel formation region. A region, wherein in the second p-type impurity region, the n-type impurity is provided. The semiconductor device of concentration being lower than said first p-type impurity regions. 15. The semiconductor device according to claim 14, wherein the second p-type impurity region does not overlap with the second gate electrode. 16. The second gate electrode according to claim 14, wherein the width of the second gate electrode in a channel length direction is the first width.
A semiconductor device having a width smaller than that of the gate electrode. 17. An n-channel type thin film transistor and a p-type thin film transistor
A semiconductor device including a CMOS circuit including a channel thin film transistor, wherein the n-type thin film transistor includes a first semiconductor layer, a first gate insulating film in contact with the first semiconductor layer, and a second gate. A p-type thin film transistor having a gate electrode intersecting with the first semiconductor layer with an insulating film interposed therebetween; a second semiconductor layer; a second gate insulating film in contact with the second semiconductor layer; A gate electrode that intersects the second semiconductor layer with the second gate insulating film interposed therebetween; and a gate electrode of the n-channel thin film transistor is a first electrode formed in contact with the first gate insulating film. A gate electrode layer; and a second gate electrode in contact with the first gate electrode surface and having a smaller width in a channel length direction than the first gate electrode. No. The angle formed by the gate insulating film is in a range of 3 degrees or more and 60 degrees or less, and the first semiconductor layer includes a first channel formation region and a first channel formation region formed outside the first channel formation region. An n-type impurity region, a second n-type impurity region sandwiched between the first channel formation region and the first n-type impurity region, and in contact with the first channel formation region; -Type impurity region and a third n-type impurity region sandwiched between the second n-type impurity regions, wherein the second n-type impurity region is formed through the first gate insulating film. The third n-type impurity region does not overlap with the first gate electrode; and the second n-type impurity region and the third n-type impurity region are n-type impurity regions. Is lower than the concentration of the first n-type impurity region. The gate electrode of the film transistor, a semiconductor device characterized in that it comprises a second third gate electrode in contact with the gate insulating film, a fourth gate electrode in contact with the third gate electrode, the. 18. An n-channel thin film transistor and a p-channel thin film transistor
A semiconductor device including a CMOS circuit including a channel thin film transistor, wherein the n-type thin film transistor includes a first semiconductor layer, a first gate insulating film in contact with the first semiconductor layer, and a second gate. A p-type thin film transistor having a gate electrode intersecting with the first semiconductor layer with an insulating film interposed therebetween; a second semiconductor layer; a second gate insulating film in contact with the second semiconductor layer; A gate electrode that intersects the second semiconductor layer with the second gate insulating film interposed therebetween; and a gate electrode of the n-channel thin film transistor is a first electrode formed in contact with the first gate insulating film. A gate electrode layer; and a second gate electrode in contact with the first gate electrode surface and having a smaller width in a channel length direction than the first gate electrode. No. The angle formed by the gate insulating film is in a range of 3 degrees or more and 60 degrees or less, and the first semiconductor layer includes a first channel formation region and a first channel formation region formed outside the first channel formation region. An n-type impurity region, a second n-type impurity region sandwiched between the first channel formation region and the first n-type impurity region, and in contact with the first channel formation region; -Type impurity region and a third n-type impurity region sandwiched between the second n-type impurity regions, wherein the second n-type impurity region is provided via the first gate insulating film. The third n-type impurity region does not overlap with the first gate electrode; and the second n-type impurity region and the third n-type impurity region are n-type impurity regions. An impurity concentration lower than that of the first n-type impurity region; The gate electrode of the thin film transistor includes: a third gate electrode in contact with the second gate insulating film; and a fourth gate electrode in contact with the third gate electrode. A second p-type impurity region, a second p-type impurity region, a second p-type impurity region sandwiched between the second channel formation region and the first p-type impurity region, and in contact with the second channel formation region. A second impurity region, wherein the second p-type impurity region has a lower concentration of the n-type impurity than the first p-type impurity region. 19. The semiconductor device according to claim 18, wherein in the second p-type impurity region, a p-type impurity concentration is the same as the first p-type impurity concentration. 20. The device according to claim 17, wherein the third gate electrode and the fourth gate electrode have a smaller width in a channel length direction than the first gate electrode. Semiconductor device. 21. The semiconductor device according to claim 17, wherein the second p-type impurity region does not overlap with the fourth gate electrode. 22. The second n-type impurity region according to claim 13, wherein the second n-type impurity region extends from the first channel formation region toward the first n-type impurity region.
A semiconductor device, wherein the concentration of the n-type impurity is high. 23. An active matrix liquid crystal display device using the semiconductor device according to claim 13 in a source driver circuit or a gate driver circuit. 24. An active matrix electroluminescent display device using the semiconductor device according to claim 13 for a source driver circuit or a gate driver circuit. 25. An active matrix type electroluminescent display device using the semiconductor device according to claim 13 in a pixel matrix circuit. 26. A video camera, a digital camera, a projector, a goggle type display, a car navigation system, a personal computer, or portable information, comprising the display device according to claim 23. Terminal. 27. A step of forming an insulating film in contact with a semiconductor layer; a step of forming the gate electrode intersecting with the semiconductor layer through the insulating film; and passing at least a part of the gate electrode Adding an impurity of a predetermined conductivity type to the semiconductor layer, wherein an angle formed by a side surface of the gate electrode with the insulating film is set to a value in a range of 3 degrees or more and 60 degrees or less. Of manufacturing a semiconductor device. 28. A step of forming an insulating film in contact with a semiconductor layer; a step of forming the gate electrode that intersects with the semiconductor layer via the insulating film; and passing at least a part of the gate electrode A first addition step of adding an impurity of a predetermined conductivity type to the semiconductor layer; and a second addition step of adding the impurity to the semiconductor layer without passing through the gate electrode. A method for manufacturing a semiconductor device, wherein an angle formed between a side surface of a gate electrode and the insulating film is in a range of 3 degrees or more and 60 degrees or less. 29. The second addition step according to claim 28, wherein the impurity is added to the semiconductor layer by using a mask that covers the gate electrode and is wider in a channel length direction than the gate electrode. A method for manufacturing a semiconductor device. 30. A step of forming an insulating film in contact with the semiconductor layer, a step of forming a first conductive film in contact with the insulating film, and forming a second conductive film in contact with the first conductive film. Forming, and patterning the first and second conductive films to form a first gate electrode and a first gate electrode on the first gate electrode having a smaller width in a channel length direction than the first gate electrode. Forming at least a part of the first gate electrode,
Adding an impurity of a predetermined conductivity type to the semiconductor layer, wherein an angle formed by a side surface of the first gate electrode with the insulating film is set to a value in a range of 3 degrees or more and 60 degrees or less. A method for manufacturing a semiconductor device. 31. A step of forming an insulating film in contact with a semiconductor layer, a step of forming a first conductive film in contact with the insulating film, and forming a second conductive film in contact with the first conductive film. Patterning the first and second conductive films to form a first gate electrode and a first gate electrode on the first gate electrode having a smaller width in a channel length direction than the first gate electrode. Forming at least a part of the first gate electrode,
A first addition step of adding a predetermined conductivity type impurity to the semiconductor layer; and a second addition step of adding the conductivity type impurity to the semiconductor layer without passing through the gate electrode. The method of manufacturing a semiconductor device, wherein, in the step of forming the gate electrode, an angle formed by a side surface of the first gate electrode with the insulating film has a value in a range of 3 degrees or more and 60 degrees or less. 32. The second adding step according to claim 31, wherein the impurity is formed by using a mask that covers the first gate electrode and has a wider width in a channel length direction than the first gate electrode. Is added to the semiconductor layer. 33. An n-channel type thin film transistor and a p-type thin film transistor
A method for manufacturing a semiconductor device including a CMOS circuit including a channel thin film transistor, the method including: forming a first semiconductor layer and a second semiconductor layer; and contacting the first semiconductor layer and the second semiconductor layer. Forming an insulating film, forming a first gate wiring crossing the first semiconductor layer and the second semiconductor layer, and forming a second gate wiring on the first gate wiring. Passing at least a part of the first gate wiring,
a first adding step of adding an n-type impurity to the first semiconductor layer; and a second adding step of adding the n-type impurity to the first semiconductor layer without passing through the first gate wiring. An adding step of adding a p-type impurity to the second semiconductor layer using the first and second gate wirings as a mask. A method for manufacturing a semiconductor device, wherein the side surface of a portion intersecting with the first semiconductor layer has an angle formed with the insulating film in a range of 3 degrees or more and 60 degrees or less. 34. An n-channel thin film transistor and a p-type thin film transistor
A method for manufacturing a semiconductor device including a CMOS circuit including a channel-type thin film transistor, the method including forming a first semiconductor layer and a second semiconductor layer, and contacting the first semiconductor layer and the second semiconductor layer. Forming an insulating film, forming a first gate wiring crossing the first semiconductor layer and the second semiconductor layer, and forming a second gate wiring on the first gate wiring. A step of adding a p-type impurity to the second semiconductor layer using the first and second gate wirings as a mask; and passing at least a part of the first gate wirings. Let me
a second adding step of adding an n-type impurity to the first semiconductor layer; and a third adding the n-type impurity to the first semiconductor layer without passing through the first gate wiring. An addition step, wherein a side surface of a portion intersecting with the first semiconductor layer has an angle with the insulating film in a range of 3 degrees or more and 60 degrees or less. Production method. 35. An n-channel thin film transistor and a p-type thin film transistor
A method for manufacturing a semiconductor device including a CMOS circuit including a channel thin film transistor, the method including: forming a first semiconductor layer and a second semiconductor layer; and contacting the first semiconductor layer and the second semiconductor layer. Forming an insulating film by: a first gate line intersecting the first semiconductor layer and the second semiconductor layer; and a second gate line laminated on the first gate line. Forming a first layer, a first adding step of adding a p-type impurity to the second semiconductor layer using the first and second gate wirings as a mask, and preventing the first gate wiring from passing therethrough. A second adding step of adding an n-type impurity to the first semiconductor layer; and passing at least a part of the first gate wiring,
A third step of adding the n-type impurity to the first semiconductor layer
Wherein the angle of the side surface of the portion intersecting with the first semiconductor layer is in a range of 3 degrees or more and 60 degrees or less. Method of manufacturing. 36. An n-channel thin film transistor and a p-channel thin film transistor
A method for manufacturing a semiconductor device including a CMOS circuit including a channel thin film transistor, the method including: forming a first semiconductor layer and a second semiconductor layer; and contacting the first semiconductor layer and the second semiconductor layer. Forming an insulating film, forming a first gate wiring intersecting the first semiconductor layer and the second semiconductor layer, and forming a second gate wiring laminated on the first gate wiring. And passing at least a part of the first gate wiring,
a first adding step of adding an n-type impurity to the first semiconductor layer; and a p-type impurity adding the second semiconductor layer using the first and second gate wirings as a mask. 2) and a third adding step of adding the n-type impurity to the first semiconductor layer without passing through the first gate wiring. A method of manufacturing a semiconductor device, wherein the side surface of a portion intersecting with the first semiconductor layer has an angle formed with the insulating film in a range of 3 degrees or more and 60 degrees or less. 37. An n-channel thin film transistor and a p-type thin film transistor
A method for manufacturing a semiconductor device including a CMOS circuit including a channel thin film transistor, the method including: forming a first semiconductor layer and a second semiconductor layer; and contacting the first semiconductor layer and the second semiconductor layer. Forming an insulating film by: a first gate line intersecting the first semiconductor layer and the second semiconductor layer; and a second gate line laminated on the first gate line. Forming a gate wiring; a first adding step of adding an n-type impurity to the first semiconductor layer without passing through the first gate wiring; and the first and second gate wirings A second adding step of adding a p-type impurity to the second semiconductor layer by using at least a portion of the first gate wiring,
A third step of adding the n-type impurity to the first semiconductor layer
Wherein the side surface of the portion of the first gate wiring that intersects with the first semiconductor layer has an angle formed with the insulating film in a range of 3 degrees or more and 60 degrees or less. A method for manufacturing a semiconductor device, comprising the steps of: 38. An n-channel thin film transistor and a p-channel thin film transistor
A method for manufacturing a semiconductor device including a CMOS circuit including a channel thin film transistor, the method including: forming a first semiconductor layer and a second semiconductor layer; and contacting the first semiconductor layer and the second semiconductor layer. Forming an insulating film by: a first gate line intersecting the first semiconductor layer and the second semiconductor layer; and a second gate line laminated on the first gate line. A first adding step of adding an n-type impurity to the first semiconductor layer without passing through the first gate wiring; and passing at least a part of the first gate wiring. Let me
A second step of adding the n-type impurity to the first semiconductor layer;
And a third adding step of adding a p-type impurity to the second semiconductor layer using the first and second gate wirings as a mask. A method of manufacturing a semiconductor device, wherein an angle of a side surface of a portion intersecting with the first semiconductor layer is in a range of 3 degrees or more and 60 degrees or less.