JP3913689B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as TFT) on a substrate having an insulating surface, and a method for manufacturing the semiconductor device. For example, the present invention relates to an electro-optical device typified by a liquid crystal display device and a configuration of an electronic apparatus equipped with the electro-optical device. Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and includes the above-described electro-optical device and electronic devices in which the electro-optical device is mounted.
[0002]
[Prior art]
Technological development for manufacturing an active matrix liquid crystal display device by providing TFTs on a glass substrate or a quartz substrate is being actively promoted. In particular, a TFT having a semiconductor film having a crystal structure as an active layer (hereinafter referred to as a crystalline TFT) can obtain high mobility. Therefore, a high-definition image display can be realized by integrating functional circuits on the same substrate. Is supposed to be possible.
[0003]
Here, in the present specification, the semiconductor film having the crystal structure includes a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor, and further includes Japanese Patent Application Laid-Open Nos. H7-130652, H8-78329, The semiconductors disclosed in JP-A-10-135468, JP-A-10-135469, or JP-A-10-247735 are included.
[0004]
In order to construct an active matrix liquid crystal display device, it is necessary to provide one to two million n-channel TFTs (hereinafter referred to as pixel TFTs) of a pixel matrix circuit, and if a functional circuit provided in the periphery is added, The above crystalline TFT is necessary. The specifications required for the liquid crystal display device are strict, and in order to stably display an image, it is first necessary to ensure the reliability of each crystalline TFT.
[0005]
The characteristics of a field effect transistor such as a TFT are ideal for a linear region where the drain current and drain voltage increase proportionally, a saturation region where the drain current saturates even when the drain voltage increases, and a drain voltage applied Can be divided into a cut-off region where no current flows. In this specification, the linear region and the saturation region are referred to as the TFT on region, and the blocking region is referred to as the off region. For convenience, the drain current in the on region is referred to as on-current, and the current in the off region is referred to as off-current.
[0006]
A gate voltage having an amplitude of about 15 to 20 V is applied to the pixel TFT as a driving condition. Therefore, it is necessary to satisfy the characteristics of both the on region and the off region. On the other hand, a peripheral circuit for driving the pixel matrix circuit is configured based on a CMOS circuit, and the on-region characteristics are mainly emphasized.
[0007]
However, crystalline TFTs are still considered to be less reliable than MOS transistors (transistors fabricated on a single crystal semiconductor substrate) used in LSI and the like in terms of reliability. For example, when a crystalline TFT is continuously driven, deterioration phenomena such as field effect mobility, a decrease in on-current, and an increase in off-current may be observed. This is due to a hot carrier injection phenomenon, and hot carriers generated by a high electric field near the drain cause a deterioration phenomenon.
[0008]
In the technical field of LSI, a lightly doped drain (LDD) structure is known as a method for reducing the off-state current of a MOS transistor and relaxing a high electric field near the drain. In this structure, a low concentration impurity region is provided outside the channel formation region, and this low concentration impurity region is called an LDD region.
[0009]
It is naturally known that an LDD structure is formed even in a crystalline TFT. For example, in JP-A-7-202210, a gate electrode has a two-layer structure with different widths, an upper layer width is formed smaller than a lower layer width, and ion implantation is performed using the gate electrode as a mask. The LDD region is formed by a single ion implantation by utilizing the difference in ion penetration depth due to the difference in the thickness of the gate electrode. The gate electrode overlaps directly above the LDD region.
[0010]
Such a structure is known as a GOLD (Gate-drain Overlapped LDD) structure, a LATID (Large-tilt-angle implanted drain) structure, an ITLDD (Inverse T LDD) structure, or the like. Then, the high electric field in the vicinity of the drain can be relaxed to prevent the hot carrier injection phenomenon, and the reliability can be improved. For example, “Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97 TECHNICAL DIGEST, p523-526, 1997” has a GOLD structure with sidewalls made of silicon, but extremely superior reliability compared to TFTs with other structures. Has been confirmed to be obtained.
[0011]
However, the structure disclosed in this paper has a problem that the off-current becomes larger than that of a normal LDD structure, and a countermeasure for that is required. In particular, in the pixel TFT constituting the pixel matrix circuit, when the off-current increases, power consumption increases and an abnormality appears in image display. Therefore, the GOLD structure cannot be applied to the crystalline TFT as it is.
[0012]
[Problems to be solved by the invention]
The present invention is a technique for solving such problems, and a crystalline TFT that achieves reliability equivalent to or higher than that of a MOS transistor and at the same time obtains good characteristics in both the on region and the off region. It aims to be realized. Then, an object is to realize a highly reliable semiconductor device having a semiconductor circuit in which a circuit is formed using such a crystalline TFT.
[0013]
[Means for Solving the Problems]
FIG. 18 schematically shows the structure of the TFT and the Vg-Id (gate voltage-drain current) characteristics obtained at that time, based on the knowledge thus far. FIG. 18A-1 illustrates the simplest TFT structure in which a semiconductor layer includes a channel formation region, a source region, and a drain region. (B-1) shows the characteristics of this TFT. The + Vg side is the on region of the TFT and the -Vg side is the off region. The solid line indicates the initial characteristics, and the broken line indicates the deterioration characteristics due to the hot carrier injection phenomenon. In this structure, both the on-current and the off-current are high and the deterioration is large, so that it cannot be used as it is, for example, in the pixel TFT of the pixel matrix circuit.
[0014]
FIG. 18A-2 illustrates a structure in which a low-concentration impurity region serving as an LDD region is provided in (A-1), which is an LDD structure that does not overlap with the gate electrode. FIG. 2B-2 shows the characteristics of this TFT, which can suppress the off current to some extent, but cannot prevent the deterioration of the on current. FIG. 18A-3 shows a structure in which the LDD region completely overlaps with the gate electrode, which is also called a GOLD structure. FIG. 5B-3 shows characteristics corresponding to this, and the degradation can be suppressed to a level that does not cause a problem, but the off-current is increased on the −Vg side as compared with the structure of (A-2).
[0015]
Accordingly, in the structure shown in FIGS. 18A-1, (A-2), and (A-3), the on-region characteristics and the off-region characteristics necessary for the pixel matrix circuit are included in the reliability problem. At the same time, I could not be satisfied. However, as shown in FIG. 18A-4, when a structure in which the LDD region is overlapped with the gate electrode and a portion where the LDD region is not overlapped is formed, deterioration of on-current is sufficiently suppressed, In addition, the off current can be reduced.
[0016]
The structure of FIG. 18A-4 is derived from the following consideration. In the structure as shown in FIG. 18A-3, when a negative voltage is applied to the gate electrode of the n-channel TFT, that is, in the LDD region formed overlapping the gate electrode in the off region. As the negative voltage increases, holes are induced at the interface with the gate insulating film, and a current path by minority carriers connecting the drain region, the LDD region, and the channel region is formed. At this time, if a positive voltage is applied to the drain region, holes flow to the source region side, which is considered to be a cause of an increase in off-current.
[0017]
In order to cut off such a current path in the middle, it can be considered that an LDD region in which minority carriers are not accumulated even when a gate voltage is applied may be provided. The present invention relates to a TFT having such a configuration and a circuit using this TFT.
[0018]
Therefore, the structure of the present invention is a semiconductor in which a TFT having a semiconductor layer, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film is formed on a substrate. In the device, the gate electrode is formed on the first layer of the gate electrode formed in contact with the gate insulating film, and on the first layer of the gate electrode and inside the first layer of the gate electrode. A second layer of the gate electrode to be formed; a third layer of the gate electrode formed in contact with the first layer of the gate electrode and the second layer of the gate electrode; The layer includes a channel formation region, a first conductivity type first impurity region, and a one conductivity type second impurity region formed between the channel formation region and the first impurity region. , Part of the second impurity region of the one conductivity type is the gate electrode It is characterized in that overlaps the first layer.
[0019]
According to another aspect of the invention, there is provided a first step of forming a semiconductor layer on a substrate having an insulating surface, a second step of forming a gate insulating film in contact with the semiconductor layer, and the gate insulation. A third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the film, and etching the conductive layer (B) into a predetermined pattern to form a second layer of the gate electrode A fourth step, a fifth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer, the conductive layer (A) and the second layer of the gate electrode, A sixth step of forming a conductive layer (C), and etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern to form a third layer of the gate electrode and a first layer of the gate electrode; A seventh step of forming an eye, and an impurity element of one conductivity type is added to a selected region of the semiconductor layer It is characterized by having a eighth step.
[0020]
According to another aspect of the invention, there is provided a first step of forming a semiconductor layer on a substrate having an insulating surface, a second step of forming a gate insulating film in contact with the semiconductor layer, and the gate insulation. A third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the film, and etching the conductive layer (B) into a predetermined pattern to form a second layer of the gate electrode A fourth step, a fifth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer, the conductive layer (A) and the second layer of the gate electrode, A sixth step of forming a conductive layer (C), and etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern to form a third layer of the gate electrode and a first layer of the gate electrode; A seventh step of forming an eye, and an impurity element of one conductivity type is added to a selected region of the semiconductor layer A step of eighth, is characterized by having a ninth step of removing a portion of the third layer of the first layer and the gate electrode of the gate electrode.
[0021]
According to another aspect of the invention, there is provided a first step of forming a first semiconductor layer and a second semiconductor layer on a substrate having an insulating surface, and the first semiconductor layer and the second semiconductor layer. A second step of forming a gate insulating film, a third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film, and a predetermined step of forming the conductive layer (B). A fourth step of forming the second layer of the gate electrode by etching into the pattern of step 5, and a fifth step of adding an impurity element of one conductivity type to the selected region of the first semiconductor layer; A sixth step of forming a conductive layer (C) in contact with the conductive layer (A) and the second layer of the gate electrode, and the conductive layer (C) and the conductive layer (A) Etching to a pattern to form a third layer of the gate electrode and a first layer of the gate electrode; An eighth step of adding a physical element to a selected region of the first semiconductor layer and the second semiconductor layer; and an impurity having a conductivity type opposite to the one conductivity type is selected in the second semiconductor layer. And a ninth step of adding to the region.
[0022]
Such a TFT can be suitably used for an n-channel TFT or a pixel TFT of a CMOS circuit. In the structure of the TFT of the present invention, the first impurity region formed in the semiconductor layer functions as a source region or a drain region, and the second impurity region functions as an LDD region. Therefore, the concentration of the impurity element of one conductivity type is lower in the second impurity region than in the first impurity region.
[0023]
In addition, a storage capacitor is formed from an impurity region of one conductivity type provided at one end of the semiconductor layer, the gate insulating film, and a wiring formed from the first layer to the third layer of the gate electrode. And the storage capacitor can be connected to the source or drain of the TFT.
[0024]
Further, the first layer of the gate electrode and the third layer of the gate electrode are selected from silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo). One or more kinds of elements, or a compound containing the above elements as a component, and the second layer of the gate electrode is one or more kinds of elements selected from aluminum (Al) and copper (Cu) Or a compound containing the above element as a main component.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG. As the substrate 101 having an insulating surface, a glass substrate, a plastic substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate or a stainless steel substrate on which an insulating film such as a silicon oxide film is formed may be used. It is also possible to use a quartz substrate.
[0026]
A base film 102 is formed on the surface of the substrate 101 on the side where the TFT is formed. The base film 102 may be formed by a plasma CVD method or a sputtering method, and may be formed by a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The base film 102 is provided to prevent impurities from diffusing from the substrate 101 to the semiconductor layer. For example, a two-layer structure in which a silicon nitride film is formed to 25 to 100 nm and a silicon oxide film is formed to 50 to 200 nm may be used.
[0027]
A semiconductor layer formed in contact with the base film 102 is an amorphous semiconductor film formed by a film forming method such as a plasma CVD method, a low pressure CVD method, or a sputtering method, and a solid phase growth method using a laser annealing method or a thermal annealing method. It is desirable to use a crystalline semiconductor crystallized at Alternatively, a microcrystalline semiconductor film formed by the above film formation method can be used. Examples of the semiconductor material that can be used here include silicon, germanium, silicon germanium alloy, and silicon carbide. In addition, a compound semiconductor material such as gallium arsenide can also be used.
[0028]
Alternatively, the semiconductor layer formed over the substrate 301 may be an SOI (Silicon On Insulators) substrate in which a single crystal silicon layer is formed. Several types of SOI substrates are known depending on their structures and fabrication methods. Typically, SIMOX (Separation by Implanted Oxygen), ELTRAN (Epitaxial Layer Transfer: registered trademark of Canon Inc.) substrate, Smart- Cut (registered trademark of SOITEC) or the like can be used. Of course, other SOI substrates can also be used.
[0029]
FIG. 1 shows cross-sectional structures of an n-channel TFT and a p-channel TFT. The gate electrodes of the n-channel TFT and the p-channel TFT are composed of a first layer of the gate electrode, a second layer of the gate electrode, and a third layer of the gate electrode. The first layers 113 and 116 of the gate electrode are formed in contact with the gate insulating film 103. Then, second layers 114 and 117 of the gate electrode that are shorter in the channel length direction than the first layer of the gate electrode are provided so as to overlap the first layers 113 and 116 of the gate electrode. Further, the third layer 115, 118 of the gate electrode is formed on the first layer 113, 116 of the gate electrode and the second layer 114, 117 of the gate electrode.
[0030]
The first layers 113 and 116 of the gate electrode are materials selected from silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or these materials as components. Form with material. For example, a W—Mo compound, tantalum nitride (TaN), or tungsten nitride (WN) may be used. The thickness of the first layer of the gate electrode may be 10 to 100 nm, preferably 20 to 50 nm.
[0031]
The second layers 114 and 117 of the gate electrode are preferably made of a material having a low resistivity and containing aluminum (Al) or copper (Cu) as a component. The thickness of the second layer of the gate electrode may be 50 to 400 nm, preferably 100 to 200 nm. The second layer of the gate electrode is formed for the purpose of lowering the electrical resistance of the gate electrode, and is determined by considering both the length and resistance value of the gate wiring and bus line connected to the gate electrode. Just do it.
[0032]
The third layers 115 and 118 of the gate electrode were selected from silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo) as in the first layer of the gate electrode. It is made of materials or materials containing these materials as components. The thickness of the third layer of the gate electrode may be 50 to 400 nm, preferably 100 to 200 nm.
[0033]
In any case, the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode may be formed by sputtering to form a film of the above material. It is formed into a predetermined shape by etching. Here, in order to form the third layer of the gate electrode so as to cover the second layer of the gate electrode, the thickness of the second layer of the gate electrode is controlled as described above. It is necessary to set the sputtering conditions appropriately. For example, it is an effective means to relatively slow the film formation rate of the film to be formed.
[0034]
As the structure of the gate electrode as shown in FIG. 1, the heat resistance can be improved by making the second layer of the gate electrode surrounded by the first layer of the gate electrode and the third layer of the gate electrode. it can. As a material for the gate electrode, it is desirable to use a material having a low resistivity such as Al or Cu. However, when heated at a temperature of 450 ° C. or higher, hillocks are generated or diffused into the surrounding insulating film or semiconductor layer. There is a point. However, such a phenomenon can be prevented by using a clad structure surrounded by materials such as Si, Ti, Ta, W, and Mo, or materials containing these materials as components.
[0035]
The semiconductor layer of the n-channel TFT includes a channel formation region 104, first impurity regions 107 and 108, and second impurity regions 105, 106a, and 106b formed in contact with the channel formation region. An impurity element imparting n-type conductivity is added to both the first impurity region and the second impurity region. At this time, the concentration of the impurity element is 1 × 10 1 in the first impurity region. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three , Preferably 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three The concentration of the second impurity region is 1 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three , Typically 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three Is added. The first impurity regions 107 and 108 function as a source region and a drain region.
[0036]
On the other hand, the third impurity regions 111, 112a, and 112b of the p-channel TFT function as a source region or a drain region. The third impurity region 112b contains an impurity element imparting n-type at the same concentration as the first impurity region, but the impurity element imparting p-type at a concentration 1.5 to 3 times that of the first impurity region. Is added.
[0037]
The impurity element to the second impurity region is formed by a method in which an impurity element imparting n-type conductivity is added to the semiconductor layer through the first layer 113 of the gate electrode and the gate insulating film 103. .
[0038]
As shown in FIGS. 2A and 2B, the second impurity regions 106a and 106b are formed as second impurities that do not overlap the gate electrode and the second impurity region 106a that overlaps the gate electrode with the gate insulating film 103 interposed therebetween. It can be divided into the area 106b. That is, an LDD region that overlaps the gate electrode and an LDD region that does not overlap are formed. The formation of this region is divided into a first step of adding one conductivity type impurity element (formation of a second impurity region) and a second step of adding one conductivity type impurity element (first impurity region). In this case, a photoresist may be used as a mask.
[0039]
This is a very convenient method when manufacturing circuits with different drive voltages on the same substrate. FIG. 2B shows an example of design values of TFTs used for a logic circuit portion, a buffer circuit portion, an analog switch portion, and a pixel matrix circuit of a liquid crystal display device. At this time, it is possible to set the length of the second impurity region 106a that overlaps the gate electrode and the second impurity region 106b that does not overlap the gate electrode as well as the channel length in consideration of the driving voltage of each TFT. It becomes.
[0040]
Since the TFT of the shift register circuit of the driver circuit and the TFT of the buffer circuit are basically focused on the characteristics of the ON region, the so-called GOLD structure may be used, and the second impurity region 106b that does not overlap with the gate electrode is necessarily provided. Absent. However, when it is provided, it may be set in the range of 0.5 to 3 μm in consideration of the drive voltage. In any case, it is desirable to increase the value of the second impurity region 106b that does not overlap with the gate electrode in consideration of the withstand voltage, as the drive voltage increases.
[0041]
Further, since it is not necessary for the TFT provided in the analog switch or the pixel matrix circuit to increase the off-current, for example, when the driving voltage is 16 V, the channel length is 3 μm and the second impurity region 106 a overlapping the gate electrode is 1.5 μm. The second impurity region 106b that does not overlap with the gate electrode is 1.5 μm. Of course, the present invention is not limited to the design values shown here, and the practitioner may make a proper decision.
[0042]
As shown in FIG. 17, in the present invention, the length of the first layer 1701 of the gate electrode, the second layer 1702 of the gate electrode, and the third layer 1703 of the gate electrode in the channel length direction is This is closely related to the size of the TFT to be manufactured. The length in the channel length direction of the second layer 1702 of the gate electrode substantially corresponds to the channel length L1. At this time, L1 may be 0.1 to 10 μm, typically 0.2 to 5 μm.
[0043]
Further, the length L6 of the second impurity region 1705 can be arbitrarily set by masking with a photoresist as described above, but it is 0.2 to 6 μm, typically 0.6 to 3 μm. It is desirable to do.
[0044]
The length L4 where the second impurity region 1705 overlaps with the gate electrode is closely related to the length L2 of the first layer 1701 of the gate electrode. The length of L4 is preferably 0.1 to 4 μm, typically 0.5 to 3 μm. The length L5 at which the second impurity region 1705 does not overlap with the gate electrode is not necessarily provided as described above, but is usually 0.1 to 3 μm, typically 0.3 to It is good to set it as 2 micrometers. Here, the lengths of L4 and L5 may be determined based on the driving voltage of the TFT as described above, for example.
[0045]
In FIG. 1, the channel formation region 104 is preliminarily set to 1 × 10 6. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three Boron may be added at a concentration of. This boron is added to control the threshold voltage, and other elements can be substituted as long as the same effect can be obtained.
[0046]
As described above, in the present invention, the gate electrode is formed of the first layer 113 and 116 of the gate electrode, the second layers 114 and 117 of the gate electrode, and the third layers 115 and 118 of the gate electrode. As shown in FIG. 1, the second layer 114, 117 of the gate electrode has a clad structure surrounded by the first layer 113, 116 of the gate electrode and the third layer 115, 118 of the gate electrode. . At least the n-channel TFT is characterized in that a part of the second impurity region 106 provided in the semiconductor layer with the gate insulating film 103 interposed therebetween overlaps with such a gate electrode.
[0047]
In the n-channel TFT, the second impurity region may be provided only on the drain region side (the first impurity region 108 side in FIG. 1) with the channel formation region 104 as the center. Further, in the case where characteristics of both the on region and the off region are required as in the pixel TFT of the pixel matrix circuit, the source side (the first impurity region 107 side in FIG. 1) and the channel formation region 104 are the center. It is desirable to provide both on the drain region side (first impurity region 108 side in FIG. 1).
[0048]
On the other hand, the p-channel TFT has a structure in which a channel formation region 109 and third impurity regions 111, 112a, and 112b are formed. Of course, a structure similar to that of the n-channel TFT of the present invention may be used. However, since the p-channel TFT is originally highly reliable, it is preferable to obtain an on-current and balance the characteristics with the n-channel TFT. When the present invention is applied to a CMOS circuit as shown in FIG. 1, it is particularly important to balance this characteristic. However, there is no problem even if the structure of the present invention is applied to a p-channel TFT.
[0049]
When the n-channel TFT and the p-channel TFT are thus completed, the source wirings 120 and 121 and the drain wiring 122 are provided by covering with the first interlayer insulating film 119. In the structure of FIG. 1, after providing these, a silicon nitride film is provided as the passivation film 123. Further, a second interlayer insulating film 124 made of a resin material is provided. The second interlayer insulating film is not necessarily limited to a resin material. However, for example, when applied to a liquid crystal display device, it is preferable to use a resin material in order to ensure surface flatness.
[0050]
In FIG. 1, a CMOS circuit formed by complementary combination of an n-channel TFT and a p-channel TFT is shown as an example. However, the present invention is applied to an NMOS circuit using an n-channel TFT or a pixel matrix circuit of a liquid crystal display device. The invention can also be applied.
[0051]
The configuration of the present invention described above will be described in more detail in the following examples.
[0052]
[Example 1]
In this embodiment, a method for simultaneously manufacturing a CMOS circuit which is a basic form of a pixel matrix circuit and a driver circuit provided in the periphery of the pixel matrix circuit will be described.
[0053]
In FIG. 3A, a non-alkali glass substrate typified by a Corning 1737 glass substrate is used as the substrate 301. Then, a base film 302 is formed on the surface of the substrate 301 where the TFT is formed by a plasma CVD method or a sputtering method. Although the base film 302 is not illustrated, a silicon nitride film is formed to a thickness of 25 to 100 nm, typically 50 nm, and a silicon oxide film is formed to a thickness of 50 to 300 nm, typically 150 nm.
[0054]
Besides, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film made of O is 10 to 200 nm (preferably 50 to 100 nm), similarly SiH _Four , N ₂ A silicon oxynitride film formed from O is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm).
[0055]
Next, an amorphous silicon film having a thickness of 50 nm is formed on the base film 302 by a plasma CVD method. Although it depends on the amount of hydrogen contained in the amorphous silicon film, it is preferable that the dehydrogenation treatment is performed by heating at 400 to 550 ° C. for several hours, and the crystallization step is performed with the amount of hydrogen contained being 5 atomic% or less. . Although an amorphous silicon film may be formed by other manufacturing methods such as a sputtering method or an evaporation method, it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film.
[0056]
Here, since both the base film and the amorphous silicon film can be formed by a plasma CVD method, the base film and the amorphous silicon film may be continuously formed in a vacuum. After the formation of the base film, once the process is not exposed to the air atmosphere, surface contamination can be prevented, and variations in characteristics of TFTs to be manufactured can be reduced.
[0057]
A known laser annealing method or thermal annealing method may be used for the step of crystallizing the amorphous silicon film. In this embodiment, a pulsed oscillation type KrF excimer laser beam is condensed into a linear shape and irradiated to an amorphous silicon film to form a crystalline silicon film.
[0058]
When crystallization is performed by laser annealing, a pulse oscillation type or continuous light emission type excimer laser or argon laser is used as the light source. Alternatively, a YAG laser may be used as the light source, and its fundamental frequency, second harmonic, third harmonic, and fourth harmonic may be used as the light source. In the case of using a pulse oscillation type excimer laser, laser annealing is performed by processing laser light into a linear shape. The laser annealing conditions are appropriately selected by the practitioner. For example, the laser pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 500 mJ / cm. ² (Typically 300-400mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the linear beam superposition ratio (overlap ratio) at this time is set to 80 to 98%.
[0059]
In this embodiment, a crystalline silicon film is formed from an amorphous silicon film as a semiconductor layer. However, a microcrystalline silicon film may be used, or a crystalline silicon film may be formed directly.
[0060]
The crystalline silicon film thus formed is patterned to form island-shaped semiconductor layers 303, 304, and 305.
[0061]
Next, a gate insulating film 306 containing silicon oxide or silicon nitride as a main component is formed so as to cover the island-shaped semiconductor layers 303, 304, and 305. The gate insulating film 306 is made of N by plasma CVD. ₂ O and SiH _Four A silicon oxynitride film using as a raw material may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. Here, it is formed to a thickness of 100 nm.
[0062]
Then, a gate electrode including a first layer of the gate electrode, a second layer of the gate electrode, and a third layer of the gate electrode is formed over the gate insulating film 306. First, a conductive layer (A) 307 and a conductive layer (B) 308 are formed. The conductive layer (A) 307 may be formed of a material selected from Ti, Ta, W, and Mo, but a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. The thickness of the conductive layer (A) 307 needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, a Ti film having a thickness of 50 nm is formed by sputtering.
[0063]
Management of the thickness of the gate insulating film 306 and the conductive layer (A) 307 is important. This is because an impurity imparting n-type conductivity is added to the semiconductor layers 303 and 305 through the gate insulating film 306 and the conductive layer (A) 307 in a first impurity addition step to be performed later. Actually, the process conditions for the first impurity addition were determined in consideration of the thicknesses of the gate insulating film 306 and the conductive layer (A) 307 and the concentration of the impurity element to be added. It has been confirmed in advance that the impurity element can be added to the semiconductor layer within the above-mentioned film thickness range, but if the film thickness fluctuates 10% or more from the original value set, the impurity concentration to be added decreases.
[0064]
The conductive layer (B) is preferably made of a material selected from Al and Cu. This is provided to lower the electric resistance of the gate electrode, and is formed to a thickness of 50 to 400 nm, preferably 100 to 200 nm. When Al is used, pure Al may be used, or an Al alloy to which an element selected from Ti, Si, and Sc is added in an amount of 0.1 to 5 atomic% may be used. In the case of using copper, although not shown, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 306.
[0065]
Here, an Al film added with 0.5 atomic% of Sc is formed to a thickness of 200 nm by sputtering (FIG. 3A).
[0066]
Next, a resist mask is formed using a known patterning technique, and a step of removing part of the conductive layer (B) 308 is performed. Here, since the conductive layer (B) 308 is formed of an Al film to which 0.5 atomic% of Sc is added, the wet etching method using a phosphoric acid solution is performed. Then, as shown in FIG. 3B, second layers 309, 310, 311 and 312 of the gate electrode are formed from the conductive layer (B). The length in the channel length direction of the second layer of each gate electrode is 3 μm in the second layers 309 and 310 of the gate electrode forming the CMOS circuit, and the pixel matrix circuit has a multi-gate structure. The length of each of the second layers 311 and 312 of the gate electrode is 2 μm.
[0067]
Although this step can be performed by a dry etching method, a wet etching method is used to remove an unnecessary region of the conductive layer (B) 308 with high selectivity without damaging the conductive layer (A) 307. preferable.
[0068]
In addition, a storage capacitor is provided on the drain side of the pixel TFT constituting the pixel matrix circuit. At this time, the capacitor wiring 313 having a storage capacitor is formed using the same material as the conductive layer (B).
[0069]
Then, a resist mask 314 is formed in a region where a p-channel TFT is to be formed, and a first step of adding an impurity element imparting n-type conductivity is performed. Phosphorus (P), arsenic (As), antimony (Sb), and the like are known as impurity elements imparting n-type to crystalline semiconductor materials. Here, phosphorous is used, and phosphine (PH _Three ) Using an ion doping method. In this step, in order to add phosphorus to the semiconductor layer thereunder through the gate insulating film 306 and the conductive layer (A) 307, the acceleration voltage is set as high as 80 keV. The concentration of phosphorus added to the semiconductor layer is 1 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three In the range of 1 × 10 ¹⁸ atoms / cm ^Three And Then, regions 315, 316, 317, 318, 319, and 320 in which phosphorus is added to the semiconductor layer are formed (FIG. 3B).
[0070]
Then, after removing the resist mask 314, the conductive layer (A) 307, the second layer 309, 310, 311 and 312 of the gate electrode, and the storage capacitor wiring 313 are brought into close contact with each other to become the third layer of the gate electrode. A conductive layer (C) 321 is formed. The conductive layer (C) 321 may be formed of a material selected from Ti, Ta, W, and Mo, but a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. For example, the thickness of the conductive layer (C) 321 needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, a Ta film with a thickness of 50 nm is formed by sputtering (FIG. 3C).
[0071]
Next, a resist mask is formed using a known patterning technique, and a step of removing part of the conductive layer (C) 321 and the conductive layer (A) 307 is performed. Here, dry etching is performed. The conductive layer (C) 321 is Ta, and the dry etching condition is CF. _Four 80 SCCM, O ₂ 20 SCCM is introduced and 500 m high frequency power is applied at 100 mTorr. At this time, the etching rate of Ta is 60 nm / min. The condition for etching the conductive layer (A) 307 is SiCl. _Four 40 SCCM, Cl ₂ 5SCCM, BCl _Three 180 SCCM is introduced and high frequency power of 80 mTorr and 1200 W is applied. At this time, the etching rate of Ti is 34 nm / min.
[0072]
A slight residue may be confirmed after etching, but it can be removed by cleaning with a solution such as SPX cleaning solution or EKC. Further, under the above etching conditions, the etching rate of the underlying gate insulating film 306 is 18 to 38 nm / min, and care should be taken because the etching of the gate insulating film proceeds if the etching time is long.
[0073]
Then, the first layer 322, 323, 324, 325 of the gate electrode and the third layer 327, 328, 329, 330 of the gate electrode are formed. The lengths in the channel length direction of the first layer of the gate electrode and the third layer of the gate electrode are formed to be the same, and the first layers 322 and 323 of the gate electrode and the third layers 327 and 328 of the gate electrode are formed. Is formed to a length of 6 μm. The first layers 324 and 325 of the gate electrode and the third layers 329 and 330 of the gate electrode are formed to a length of 4 μm (FIG. 4A).
[0074]
In this manner, a gate electrode composed of the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode is formed. In addition, a storage capacitor is provided on the drain side of the pixel TFT constituting the pixel matrix circuit. At this time, wirings 326 and 331 having a storage capacitor are formed from the conductive layer (A) and the conductive layer (C).
[0075]
Then, as shown in FIG. 4B, resist masks 332, 333, 334, 335, and 336 are formed, and a second step of adding an impurity element imparting n-type conductivity is performed. This is also phosphine (PH _Three ) Using an ion doping method. Also in this step, the acceleration voltage is set to be as high as 80 keV in order to add phosphorus to the semiconductor layer thereunder through the gate insulating film 306. Then, regions 337, 338, 339, 340, 341, 342, and 343 to which phosphorus is added are formed. The concentration of phosphorus in this region is higher than that in the first step of adding an impurity element imparting n-type conductivity, and is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three Is preferred, here 1 × 10 ²⁰ atoms / cm ^Three And
[0076]
In this step, the length of the resist masks 332, 333, 334, and 335 in the channel length direction is important in determining the structure of each TFT. In particular, in an n-channel TFT, the length of the first layer and the third layer of the gate electrode and the length of the resist mask do not overlap with the region where the second impurity region overlaps with the gate electrode. The area can be freely determined within a certain range. In this embodiment, the lengths of the first layer 322 and the third layer 327 of the gate electrode are 6 μm, and the lengths of the first layers 324 and 325 and the third layers 329 and 330 of the gate electrode are 4 μm. Since the resist mask 332 was formed, the resist mask 332 was formed with a length of 9 μm, and the resist masks 334 and 335 were formed with a length of 7 μm. Of course, each length described here is an example, and therefore, it is preferable to determine the driving voltage of the TFT as described above.
[0077]
Next, a step of covering the region where the n-channel TFT is formed with resist masks 344 and 345 and adding a third impurity element imparting p-type only to the region where the p-channel TFT is formed is performed. Boron (B), aluminum (Al), and gallium (Ga) are known as impurity elements imparting p-type. Here, boron is used as the impurity element, and diborane (B ₂ H ₆ ) Using an ion doping method. Also in this case, the acceleration voltage is 80 keV and 2 × 10 ²⁰ atoms / cm ^Three Boron is added to the concentration of. Then, as shown in FIG. 4C, third impurity regions 346a, 346b, 347a, and 347b to which boron is added at a high concentration are formed. The third impurity regions 346b and 347b contain phosphorus added in the previous step, but there is no problem because boron is added at twice that concentration (FIG. 4C).
[0078]
When the steps up to FIG. 4C are completed, the resist masks 344 and 345 are removed and a first interlayer insulating film 374 is formed as shown in FIG. The first interlayer insulating film 374 is formed with a two-layer structure. First, a silicon nitride film 374a is formed to a thickness of 50 nm. The silicon nitride film is formed by plasma CVD, and SiH _Four 5SCCM, NH _Three 40 SCCM, N ₂ 100 SCCM is introduced and high frequency power of 0.7 Torr and 300 W is applied. Subsequently, the silicon oxide film 374b is formed with TEOS at 500 SCCM, O ₂ 50 SCCM is introduced, high-frequency power of 1 Torr and 200 W is applied, and a film having a thickness of 950 nm is formed. Thus, the first interlayer insulating film 374 having a total thickness of 1 μm is formed by the silicon nitride film 374a and the silicon oxide film 374b.
[0079]
The silicon nitride film formed here is necessary for performing the next heat treatment step. In this embodiment, the gate electrode having the cladding structure as described above is formed. In this structure, the second layer of the gate electrode formed of Al is surrounded by the first layer of the gate electrode formed of Ti and the third layer of the gate electrode formed of Ta. . Ta has the effect of preventing Al hillocks and seepage to the surroundings, but has a drawback that it is oxidized immediately when heated at 400 ° C. or higher at normal pressure. As a result, the electrical resistance increases. However, if the surface is covered with the silicon nitride film 374a of the first interlayer insulating film, oxidation can be prevented.
[0080]
The heat treatment step needs to be performed in order to activate the impurity element imparting n-type or p-type added at each concentration. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, the laser annealing method can be activated at a low substrate heating temperature, but it is difficult to activate the region that covers the gate electrode. Therefore, here, the activation process is performed by thermal annealing. The conditions at this time are 300 to 700 ° C., preferably 350 to 550 ° C., here 450 ° C. for 2 hours in a nitrogen atmosphere.
[0081]
The first interlayer insulating film 374 is then patterned to form contact holes that reach the source and drain regions of the respective TFTs. Then, source wirings 375, 376, and 377 and drain wirings 378 and 379 are formed. Although not shown, in this embodiment, this wiring is used as a wiring having a three-layer structure in which a Ti film is 100 nm, an Al film 300 nm containing Ti, and a Ti film 150 nm are successively formed by sputtering.
[0082]
Then, a passivation film 380 is formed so as to cover the source wirings 375, 376 and 377, the drain wirings 378 and 379, and the first interlayer insulating film 374. The passivation film 380 is a silicon nitride film with a thickness of 50 nm. Further, a second interlayer insulating film 381 made of an organic resin is formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Organic resin films other than those described above can also be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C.
[0083]
Through the above steps, a gate electrode having a clad structure is formed, and a channel formation region 348, first impurity regions 360 and 361, and second impurity regions 349a, 349b, 350a, and 350b are formed in an n-channel TFT of a CMOS circuit. Is formed. Here, the second impurity regions are formed such that the regions 349a and 350a that overlap with the gate electrode have a length of 1.5 μm, and the regions (LDD regions) 349b and 350b that do not overlap with the gate electrode have a length of 1.5 μm, respectively. Is done. The first impurity region 360 functions as a source region, and the first impurity region 361 functions as a drain region.
[0084]
In the p-channel TFT, similarly, a gate electrode having a cladding structure is formed, and a channel formation region 362 and third impurity regions 363a, 363b, 364a, and 364b are formed. The third impurity regions 363a and 363b serve as source regions, and the third impurity regions 364a and 364b serve as drain regions.
[0085]
In the pixel TFT of the pixel matrix circuit, channel formation regions 365 and 369, first impurity regions 368 and 372, and second impurity regions 366, 367, 370, and 371 are formed. This second impurity region can be divided into regions 366b, 367b, 370b, and 371b that do not overlap with regions 366a, 367a, 370a, and 371a that overlap with the gate electrode.
[0086]
Thus, as shown in FIG. 5, an active matrix substrate in which a CMOS circuit and a pixel matrix circuit are formed on a substrate 301 is manufactured. Further, a storage capacitor is simultaneously formed on the drain side of the pixel TFT of the pixel matrix circuit.
[0087]
[Example 2]
In this embodiment, as in Embodiment 1, another embodiment in which a CMOS circuit which is a basic form of a pixel matrix circuit and a driver circuit provided in the periphery thereof is manufactured at the same time will be described.
[0088]
First, similarly to Example 1, the steps from FIG. 3A to FIG. 3C and the step from FIG. 4A are performed.
[0089]
FIG. 6A shows a state in which the gate electrode is formed from the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode. Resist masks 601, 602, 603, 604, and 605 are formed on the substrate in this state, and an impurity element imparting n-type conductivity is added. Then, first impurity regions 606, 607, 608, 609, 610, 611, and 612 are formed (FIG. 6B).
[0090]
The resist masks 601 and 602 formed here have a shape in which the LDD region is formed only on the drain region side of the TFT. This is because the region for masking the second impurity region from above the gate insulating film is formed only on one side with the channel formation region as the center.
[0091]
Formation of such a resist mask is particularly effective for an n-channel TFT of a CMOS circuit. Since the LDD region is formed only on one side, the series resistance component of the TFT can be substantially reduced, and the on-current can be increased.
[0092]
Both the GOLD structure and the LDD structure described so far are provided to alleviate the high electric field in the vicinity of the drain region. If the structure is formed on the drain side of the TFT, the effect is sufficiently obtained. It is done.
[0093]
Further, resist masks 613 and 614 are formed, and a step of adding an impurity element imparting p-type conductivity is performed in the same manner as in Example 1 to form third impurity regions 615a, 615b, and 616. The third impurity region 615a contains the impurity element imparting n-type added in the previous step (FIG. 6C).
[0094]
The subsequent steps may be performed in the same manner as in the first embodiment. Source wirings 375, 376, and 377, drain wirings 378 and 379, a passivation film 380, and a second interlayer insulating film 381 made of an organic resin are formed in FIG. The active matrix substrate shown is completed. A channel formation region 617, first impurity regions 620 and 621, and second impurity regions 618 and 619 are formed in the n-channel TFT of the CMOS circuit. Here, in the second impurity region, a region (GOLD region) 619a overlapping with the gate electrode and a region (LDD region) 619b not overlapping with the gate electrode are formed. The first impurity region 620 serves as a source region, and the first impurity region 621 serves as a drain region.
[0095]
In the p-channel TFT, a channel formation region 622 and third impurity regions 624a, 624b, and 623 are formed. The third impurity region 623 serves as a source region, and the third impurity regions 624a and 624b serve as drain regions. In the pixel TFT of the pixel matrix circuit, channel formation regions 625 and 629, first impurity regions 628 and 632, and second impurity regions 626, 627, 630, and 631 are formed. This second impurity region can be divided into regions 626b, 627b, 630b, and 631b that do not overlap with the regions 626a, 627a, 630a, and 631a that overlap with the gate electrode.
[0096]
[Example 3]
In this embodiment, as in Embodiment 1, another embodiment in which a CMOS circuit which is a basic form of a pixel matrix circuit and a driver circuit provided in the periphery thereof is manufactured at the same time will be described.
[0097]
First, the steps from FIGS. 3A to 3C are performed as in the first embodiment.
[0098]
8A, resist masks 801, 802, 803, 804, and 805 are formed using a known patterning technique, and part of the conductive layer (C) 321 and the conductive layer (A) 307 is removed. Perform the process. Here, the dry etching method is used as in the first embodiment. Then, first gate electrode layers 851, 852, 853, 854, and 855 and third gate electrode layers 856, 857, 858, 859, and 860 are formed. The lengths in the channel length direction of the first layer of the gate electrode and the third layer of the gate electrode are formed to be the same, and the first layers 851 and 852 of the gate electrode of the CMOS circuit and the third layer of the gate electrode are formed. 856 and 857 are formed in a length of 9 μm longer than the final shape. Similarly, the first layers 853 and 854 of the gate electrode of the pixel matrix circuit and the third layers 858 and 859 of the gate electrode are similarly formed to a length of 7 μm.
[0099]
In addition, a storage capacitor is provided on the drain side of the pixel TFT of the pixel matrix circuit. At this time, wirings 855 and 860 having storage capacitors are formed from the conductive layer (A) and the conductive layer (C).
[0100]
Then, in the same manner as in Example 1, a second step of adding an impurity element imparting n-type is performed. In this step, regions 806, 807, 808, 811, and 812 to which phosphorus is added at a high concentration are formed by adding phosphorus to the semiconductor layer through the region of the gate insulating film that is not in contact with the gate electrode. After completion of this step, the resist masks 801, 802, 803, 804, and 805 are removed (FIG. 8A).
[0101]
Next, a photoresist film is formed again, and a patterning process is performed by exposure from the back surface. At this time, as shown in FIG. 8B, resist masks 813, 814, 815, 816, and 817 are formed in a self-aligning manner using the gate electrode as a mask. Exposure from the back side is performed using direct light and scattered light, and a resist mask is formed on the inner side of the gate electrode as shown in FIG. 8B by adjusting exposure conditions such as light intensity and exposure time. can do.
[0102]
Using the resist masks 813, 814, 815, 816, and 817, the third layer of the gate electrode and the unmasked regions of the first layer of the gate electrode are removed by a dry etching method. The dry etching conditions are the same as in Example 1. After the etching is completed, the resist masks 813, 814, 815, 816, and 817 are removed.
[0103]
8C, the first layer 818, 819, 820, 821 of the gate electrode, the third layer 823, 824, 825, 826 of the gate electrode, and the wirings 822, 827 of the storage capacitor. Is formed. By etching, the first layers 851 and 852 of the gate electrode of the CMOS circuit and the third layers 856 and 857 of the gate electrode become 6 μm in length. Similarly, the first layers 853 and 854 of the gate electrode of the pixel matrix circuit and the third layers 858 and 859 of the gate electrode are similarly formed to a length of 4 μm.
[0104]
Further, a resist mask 828, 829 is formed in a region where the n-channel TFT is formed, and a third impurity element imparting p-type conductivity is added (FIG. 8C).
[0105]
The subsequent steps may be performed in the same manner as in Example 1, and the active matrix substrate shown in FIG. 5 can be manufactured.
[0106]
[Example 4]
In this embodiment, as in Embodiment 1, another embodiment in which a CMOS circuit, which is a basic form of a pixel matrix circuit and a driving circuit provided around the pixel matrix circuit, is manufactured at the same time will be described.
[0107]
First, the steps from FIGS. 3A to 3C are performed as in the first embodiment. Then, a gate electrode is formed as shown in FIG.
[0108]
Next, a resist mask is formed using a known patterning technique, and a step of removing part of the conductive layer (C) 321 and the conductive layer (A) 307 is performed. Here, dry etching is performed. The conductive layer (C) 321 is Ta, and the dry etching condition is CF. _Four 80 SCCM, O ₂ 20 SCCM is introduced and 500 m high frequency power is applied at 100 mTorr. At this time, the etching rate of the Ta film is 60 nm / min. The condition for etching the conductive layer (A) 307 is SiCl. _Four 40 SCCM, Cl ₂ 5SCCM, BCl _Three 180 SCCM is introduced and high frequency power of 80 mTorr and 1200 W is applied. At this time, the etching rate of the Ti film is 34 nm / min.
[0109]
Then, the first layer 322, 323, 324, 325 of the gate electrode and the third layer 327, 328, 329, 330 of the gate electrode are formed. The lengths in the channel length direction of the first layer of the gate electrode and the third layer of the gate electrode are formed to be the same, and the first layers 322 and 323 of the gate electrode and the third layers 327 and 328 of the gate electrode are formed. Here, it is formed to a length of 6 μm. The first layers 324 and 325 of the gate electrode and the third layers 329 and 330 of the gate electrode are formed to a length of 4 μm.
[0110]
Under the above etching conditions, the gate insulating film 306 formed of a silicon oxynitride film is also etched. The etching rate is 18 nm / min under the Ta film etching conditions. Normally, this is performed carefully so that the gate insulating film is not etched, but this phenomenon can be actively used to make the region of the gate insulating film not in contact with the gate electrode thinner. This is a step of etching the gate electrode and can be carried out immediately if the etching time is increased as it is.
[0111]
However, in order to etch the gate insulating film, it is necessary to select a gas to be used, and CF is more preferable than chlorine-based gas. _Four And NF _Three Better results are obtained with fluorine-based gases such as
[0112]
Here, CF used when etching the Ta film _Four And O ₂ The mixed gas is used. CF _Four 80 SCCM, O ₂ 20 SCCM is introduced and 500 m high frequency power is applied at 100 mTorr. Then, with respect to the gate insulating film 306 formed with a thickness of 100 nm, the region of the gate insulating film which is not in contact with the gate electrode as shown in FIG. It can be made very thin.
[0113]
Then, similarly to Example 1, resist masks 332, 333, 334, 335, and 336 are formed, and a second step of adding an impurity element imparting n-type is performed. At this time, the regions 337, 338, 339, 340, 341, 342, and 343 to which the impurity element imparting n-type is added have a gate insulating film thickness of 50 nm. Therefore, the impurity element is efficiently applied to the semiconductor layer. Can be added.
[0114]
Since the gate insulating film is thin, the acceleration voltage in the ion doping method can be reduced from 80 keV to 40 keV, and damage to the gate insulating film and the semiconductor layer can be reduced (FIG. 9B).
[0115]
Next, as shown in FIG. 9C, the steps of forming resist masks 344 and 345 and adding an impurity element imparting p-type are performed in the same manner, and an impurity imparting p-type is added. Since the gate insulating films in contact with the regions 346a, 346b, 347a, and 347b have a thickness of 50 nm, the acceleration voltage in the ion doping method can be lowered from 80 keV to 40 keV, and the impurity element is efficiently added to the semiconductor layer. can do.
[0116]
Other steps may be performed in accordance with the first embodiment, and source wirings 375, 376, and 377, drain wirings 378 and 379, a passivation film 380, and a second interlayer insulating film 381 made of an organic resin are formed, and the active shown in FIG. A matrix substrate is completed. A channel formation region 348, first impurity regions 360 and 361, and second impurity regions 349 and 350 are formed in the n-channel TFT of the CMOS circuit. Here, in the second impurity region, regions 349a and 350a overlapping with the gate electrode and regions (LDD regions) 349b and 350b not overlapping with the gate electrode are formed. The first impurity region 360 functions as a source region, and the first impurity region 361 functions as a drain region. In the p-channel TFT, similarly, a gate electrode having a cladding structure is formed, and a channel formation region 362 and third impurity regions 363a, 363b, 364a, and 364b are formed. The third impurity regions 363a and 363b serve as source regions, and the third impurity regions 364a and 364b serve as drain regions. In the pixel TFT of the pixel matrix circuit, channel formation regions 365 and 369, first impurity regions 368 and 372, and second impurity regions 366a, 366b, 367a, 367b, 370a, 370b, 371a, and 371b are formed. . This second impurity region can be divided into regions 366b, 367b, 370b, and 371b that do not overlap with regions 366a, 367a, 370a, and 371a that overlap with the gate electrode.
[0117]
[Example 5]
In this embodiment, a method for simultaneously manufacturing a CMOS circuit which is a basic form of a pixel matrix circuit and a driver circuit provided in the periphery of the pixel matrix circuit will be described.
[0118]
In FIG. 11A, an alkali-free glass substrate typified by a Corning 1737 glass substrate is used as the substrate 1101, for example. Then, a base film 1102 is formed on the surface of the substrate 1101 where the TFT is formed by a plasma CVD method or a sputtering method. Although the base film 1102 is not illustrated, a silicon nitride film is formed to a thickness of 25 to 100 nm, typically 50 nm, and a silicon oxide film is formed to a thickness of 50 to 300 nm, typically 150 nm. Alternatively, the base film 1102 may be formed using only a silicon nitride film or a silicon oxynitride film.
[0119]
Next, an amorphous silicon film having a thickness of 50 nm is formed on the base film 1102 by plasma CVD. Although it depends on the amount of hydrogen contained in the amorphous silicon film, it is preferable that the dehydrogenation treatment is performed by heating at 400 to 550 ° C. for several hours, and the crystallization step is performed with the amount of hydrogen contained being 5 atomic% or less. . Although an amorphous silicon film may be formed by other manufacturing methods such as a sputtering method or an evaporation method, it is desirable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film.
[0120]
Here, both the base film and the amorphous silicon film are produced by the plasma CVD method. At this time, the base film and the amorphous silicon film may be continuously formed in a vacuum. After the formation of the base film, once the process is not exposed to the air atmosphere, surface contamination can be prevented, and variation in characteristics of the manufactured TFT can be reduced.
[0121]
Here, a crystalline silicon film used as a semiconductor layer is formed by a thermal crystallization method using a catalytic element. In the case of using a catalyst element, it is desirable to use the techniques disclosed in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329.
[0122]
Here, an example in the case of applying the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652 to the present invention will be described with reference to FIGS. A silicon oxide film 1902 is formed over the substrate 1901, and an amorphous silicon film 1903 is formed thereover. A nickel acetate layer solution containing 10 ppm of nickel in terms of weight is applied to the surface of the amorphous silicon film 1903 to form a nickel-containing layer 1904 (FIG. 19A).
[0123]
Next, after a dehydrogenation step at 500 ° C. for 1 hour, a heat treatment is performed at 500 to 650 ° C. for 4 to 12 hours, for example, 550 ° C. for 8 hours to form a crystalline silicon film 1905 (FIG. 19B). ).
[0124]
Further, the technique disclosed in Japanese Patent Laid-Open No. 8-78329 enables selective crystallization of an amorphous silicon film by selectively adding a catalytic element. The case where this technique is applied to the present invention will be described with reference to FIGS.
[0125]
First, a silicon oxide film 2002 and an amorphous silicon film 2003 are formed over a glass substrate 2001, and a silicon oxide film 2004 is continuously formed. At this time, the thickness of the silicon oxide film 2004 is 150 nm.
[0126]
Next, the silicon oxide film 2004 is patterned to selectively form an opening portion 2005, and then a nickel acetate salt solution containing 10 ppm of nickel in terms of weight is applied. Thus, a nickel-containing layer 2006 is formed, and the nickel-containing layer 2006 is in contact with the amorphous silicon film 2003 only at the bottom of the opening portion 2005 (FIG. 20A).
[0127]
Next, heat treatment is performed at 500 to 650 ° C. for 4 to 24 hours, for example, 570 ° C. for 14 hours, so that a crystalline silicon film 2007 is formed. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and the crystallization proceeds laterally therefrom. The crystalline silicon film 2007 formed in this way is formed by a collection of rod-like or needle-like crystals, and each crystal grows in a specific direction as viewed macroscopically, so that the crystallinity is uniform. (FIG. 20B).
[0128]
In addition to nickel (Ni), catalyst elements that can be used in the above two technologies include iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt). ), Copper (Cu), gold (Au), or other elements may be used.
[0129]
When a crystalline silicon film is formed and patterned using the above technique, the semiconductor layers 1103, 1104, and 1105 shown in FIG. 11 can be formed.
[0130]
In addition, an example is shown in which a crystalline silicon film is formed using a catalytic element and a gettering step is performed in which the catalytic element is removed from the crystalline silicon film.
[0131]
This is a technique for removing a catalyst element used for crystallization of an amorphous silicon film by using a gettering action of phosphorus after crystallization. By using this technique, the concentration of the catalytic element in the crystalline silicon film is 1 × 10 ¹⁷ atoms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atoms / cm ^Three It can be reduced to.
[0132]
FIG. 21A shows a state in which a base film 2102 and a crystalline silicon film 2103 are formed. A silicon oxide film 2104 for masking is formed to a thickness of 150 nm on the surface of the crystalline silicon film 2103, an opening is provided by patterning, and a region where the crystalline silicon film is exposed is provided. Then, a step of adding phosphorus is performed to provide a region 2105 in which phosphorus is added to the crystalline silicon film.
[0133]
In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, the region 2105 in which phosphorus is added to the crystalline silicon film functions as a gettering site, The catalytic element remaining in the crystalline silicon film 2103 can be segregated in the region 2105 to which phosphorus is added.
[0134]
Then, the silicon oxide film 2104 for the mask and the region 2105 to which phosphorus is added are removed by etching, so that the concentration of the catalytic element used in the crystallization step is 1 × 10 6. ¹⁷ atoms / cm ^Three A crystalline silicon film reduced to the following can be obtained. This crystalline silicon film can be used as the semiconductor layers 1103, 1104, and 1105 in FIG.
[0135]
Next, a gate insulating film 1106 containing silicon oxide or silicon nitride as a main component is formed so as to cover the island-shaped semiconductor layers 1103, 1104, and 1105. The gate insulating film 1106 is made of N by plasma CVD. ₂ O and SiH _Four A silicon oxynitride film made from a raw material may be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. Here, it is formed to a thickness of 100 nm.
[0136]
Then, a conductive layer (A) 1107 as a first layer of the gate electrode and a conductive layer (B) 1108 as a second layer of the gate electrode are formed on the surface of the gate insulating film 1106. The conductive layer (A) 1107 may be formed of a material selected from Ti, Ta, W, and Mo, but a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. The thickness of the conductive layer (A) 1107 needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, a Ti film having a thickness of 50 nm is formed by sputtering.
[0137]
For the conductive layer (B) 1108 which is the second layer of the gate electrode, a material selected from Al and Cu is preferably used. This is provided to lower the electric resistance of the gate electrode, and is formed to a thickness of 50 to 400 nm, preferably 100 to 200 nm. When Al is used, pure Al may be used, or an Al alloy to which an element selected from Ti, Si, and Sc is added in an amount of 0.1 to 5 atomic% may be used. In the case of using copper, although not illustrated, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 1106.
[0138]
Here, an Al film added with 0.5 atomic% of Sc is formed to a thickness of 200 nm by sputtering (FIG. 11A).
[0139]
Next, a resist mask is formed using a known patterning technique, and a step of removing part of the conductive layer (B) 1108 is performed. Here, the conductive layer (B) 1108 is formed of an Al film to which 0.5 atomic% of Sc is added, but can be performed by a wet etching method using a phosphoric acid solution. Then, as shown in FIG. 11B, second layers 1109, 1110, 1111 and 1112 of the gate electrode are formed. The length in the channel length direction of the second layer of each gate electrode is 3 μm in the second layers 1109 and 1110 of the gate electrode forming the CMOS circuit, and the pixel matrix circuit has a multi-gate structure. Thus, the length of each of the second layers 1111 and 1112 of the gate electrode is set to 2 μm.
[0140]
In addition, a storage capacitor is provided on the drain side of the pixel TFT constituting the pixel matrix circuit. At this time, a storage capacitor wiring 1113 is formed using the same material as the conductive layer (B).
[0141]
Then, a step of adding a first impurity element imparting n-type is performed. Here, phosphorus is used and phosphine (PH _Three ) Using an ion doping method. In this step, in order to add phosphorus to the semiconductor layers 1103, 1104, and 1105 under the gate insulating film 1106 and the conductive layer (A) 1107, the acceleration voltage is set to a high value of 80 keV. The concentration of phosphorus added to the semiconductor layer is 1 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three In the range of 1 × 10 ¹⁸ atoms / cm ^Three And Then, regions 1114, 1115, 1116, 1117, 1118, 1119, 1120, and 1121 to which phosphorus is added to the semiconductor layer are formed (FIG. 11B).
[0142]
Next, a region in which the n-channel TFT is formed is covered with resist masks 1122 and 1123, and a step of adding a third impurity element imparting p-type to only the region in which the p-channel TFT is formed is performed. Here, boron is used as the impurity element and diborane (B ₂ H ₆ ) Using an ion doping method. Again, the acceleration voltage is 80 keV and 2 × 10 ²⁰ atoms / cm ^Three Boron is added to the concentration of. Then, as shown in FIG. 11C, third impurity regions 1124 and 1125 to which boron is added at a high concentration are formed.
[0143]
Then, after removing the resist masks 1122 and 1123, the conductive layer (A) 1107, the second layer 1109, 1110, 1111, and 1112 of the gate electrode and the wiring 1113 of the storage capacitor are in close contact with the third layer of the gate electrode. A conductive layer (C) 1126 is formed. The conductive layer (C) 1126 may be formed using a material selected from Ti, Ta, W, and Mo, but a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. For example, the thickness of the conductive layer (C) 1126 needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, a Mo—W film with a thickness of 50 nm is formed by sputtering. (Fig. 12 (A))
[0144]
Next, a resist mask is formed using a known patterning technique, and a step of removing part of the conductive layer (C) 1126 and the conductive layer (A) 1107 is performed. Here, dry etching is performed. The conductive layer (C) 1126 is a Mo—W film, and the dry etching conditions are Cl ₂ 80 SCCM is introduced, and 350 W high frequency power is applied at 10 mTorr. At this time, the etching rate of the Mo—W film is 50 nm / min. The condition for etching the conductive layer (A) 1107 is SiCl. _Four 40 SCCM, Cl ₂ 5SCCM, BCl _Three 180 SCCM is introduced and high frequency power of 80 mTorr and 1200 W is applied. At this time, the etching rate of the Ti film is 34 nm / min.
[0145]
A slight residue may be confirmed after etching, but it can be removed by cleaning with a solution such as SPX cleaning solution or EKC. Further, under the above etching conditions, the etching rate of the underlying gate insulating film 1106 is 18 to 38 nm / min. Note that if the etching time is long, the etching of the gate insulating film proceeds.
[0146]
Then, the first layer 1127, 1128, 1129, 1130 of the gate electrode and the third layer 1132, 1133, 1134, 1135 of the gate electrode are formed. The lengths in the channel length direction of the first layer of the gate electrode and the third layer of the gate electrode are formed to be the same, and the first layers 1127 and 1128 of the gate electrode and the third layers 1132 and 1133 of the gate electrode are formed. Here, it is formed to a length of 6 μm. The first layers 1129 and 1130 of the gate electrode and the third layers 1134 and 1135 of the gate electrode are formed to have a length of 4 μm (FIG. 12B).
[0147]
In addition, a storage capacitor is provided on the drain side of the pixel TFT constituting the pixel matrix circuit. At this time, storage capacitor electrodes 1131 and 1136 are formed from the conductive layer (A) and the conductive layer (C).
[0148]
Then, as illustrated in FIG. 12C, resist masks 1137, 1138, 1139, 1140, and 1141 are formed, and a step of adding a second impurity element imparting n-type conductivity is performed. Here, phosphine (PH _Three ) Using an ion doping method. Also in this step, in order to add phosphorus to the semiconductor layer thereunder through the gate insulating film 1106, the acceleration voltage is set as high as 80 keV. Then, regions 1142, 1143, 1144, 1145, 1146, 1147, and 1148 to which phosphorus is added are formed. The concentration of phosphorus in this region is higher than that in the step of adding the first impurity element imparting n-type, and 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three Is preferred, here 1 × 10 ²⁰ atoms / cm ^Three And
[0149]
In this step, the length of the resist masks 1137, 1138, 1139, and 1140 in the channel length direction is important in determining the structure of each TFT. In particular, in an n-channel TFT, the length of the first and third layers of the gate electrode and the length of the resist mask do not overlap the region where the second impurity region overlaps with the gate electrode. The area can be freely determined within a certain range. In this embodiment, the lengths of the first layers 1127 and 1128 of the gate electrode and the third layers 1132 and 1133 of the gate electrode are 6 μm, and the first layers 1129 and 1130 of the gate electrode and the third layer of the gate electrode are formed. Since the length of the layers 1134 and 1135 is 4 μm, the length of the first and third layers of the gate electrode is 6 μm, so that the resist mask 1137 is 9 μm long, and the resist masks 1139 and 1140 are formed. Is formed with a length of 7 μm.
[0150]
When the steps up to FIG. 12C are completed, the resist masks 1137, 1138, 1139, 1140, and 1141 are removed, and a step of forming a first interlayer insulating film 1168 is performed. The first interlayer insulating film 1168 is formed with a two-layer structure. First, a silicon nitride film is formed to a thickness of 50 nm. The silicon nitride film is formed by the plasma CVD method, and SiH _Four 5SCCM, NH _Three 40 SCCM, N ₂ 100 SCCM is introduced and high frequency power of 0.7 Torr and 300 W is applied. Then, the silicon oxide film is TEOS 500 SCCM, O ₂ 50 SCCM is introduced, high-frequency power of 1 Torr and 200 W is applied, and a film having a thickness of 950 nm is formed. Accordingly, a first interlayer insulating film 1168 having a total thickness of 1 μm is formed.
[0151]
The heat treatment step needs to be performed in order to activate the impurity element imparting n-type or p-type added at each concentration. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, although the laser annealing method can be activated at a low substrate heating temperature, it is difficult to activate the semiconductor layer under the gate electrode. Therefore, here, the activation process is performed by thermal annealing. The heat treatment is performed in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550 ° C., here 450 ° C. for 2 hours.
[0152]
The first interlayer insulating film 1168 was then patterned to form contact holes reaching the source and drain regions of the respective TFTs. Then, source wirings 1169, 1170, and 1171 and drain wirings 1172 and 1173 are formed. Although not shown, in this embodiment, this wiring is used as a wiring having a three-layer structure in which a Ti film is 100 nm, an Al film 300 nm containing Ti, and a Ti film 150 nm are successively formed by sputtering.
[0153]
Then, a passivation film 1174 is formed so as to cover the source wirings 1169, 1170 and 1171, the drain wirings 1172 and 1173, and the first interlayer insulating film 1168. The passivation film 1174 is a silicon nitride film with a thickness of 50 nm. Further, a second interlayer insulating film 1175 made of an organic resin is formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Organic resin films other than those described above can also be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C.
[0154]
Through the above steps, a gate electrode having a clad structure is formed, and a channel formation region 1149, first impurity regions 1152 and 1153, and second impurity regions 1150a, 1150b, 1151a, and 1151b are formed in an n-channel TFT of a CMOS circuit. Is formed. Here, the second impurity region has a length of 1.5 μm in the region (GOLD region) 1150a, 1151a overlapping with the gate electrode and a length of 1.5 μm in the region (LDD region) 1150b, 1151b not overlapping with the gate electrode. Each is formed. The first impurity region 1152 serves as a source region, and the first impurity region 1153 serves as a drain region.
[0155]
In the p-channel TFT, similarly, a gate electrode having a clad structure is formed, and a channel formation region 1154 and third impurity regions 1155a1155b, 1156a, and 1156b are formed. The third impurity regions 1155a and 1155b serve as source regions, and the third impurity regions 1156a and 1156b serve as drain regions.
[0156]
In the pixel TFT of the pixel matrix circuit, channel formation regions 1157 and 1161, first impurity regions 1160 and 1164, and second impurity regions 1158, 1159, 1162, and 1163 are formed. Here, in the second impurity region, regions 1158b, 1159b, 1162b, and 1163b that do not overlap with the regions 1158a, 1159a, 1162a, and 1163a which overlap with the gate electrode are formed.
[0157]
Thus, as shown in FIG. 13, an active matrix substrate in which a CMOS circuit and a pixel matrix circuit are formed on a substrate 1101 is manufactured. In addition, a storage capacitor portion is simultaneously formed on the drain side of the n-channel TFT in the pixel matrix circuit.
[0158]
[Example 6]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described.
[0159]
On the active matrix substrate in the state shown in FIG. 5, a light shielding film 1601 and a third interlayer insulating film 1602 are formed on the second interlayer insulating film 381 as shown in FIG. As the light-shielding film 1601, an organic resin film containing a pigment or a metal film such as Ti or Cr is preferably used. The third interlayer insulating film 1602 is formed of an organic resin film such as polyimide. Then, a contact hole reaching the drain wiring 379 is formed in the third interlayer insulating film 1602 and the second interlayer insulating film 381, and a pixel electrode 1603 is formed. The pixel electrode 1603 may be a transparent conductive film in the case of a transmissive liquid crystal display device, and a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method, and a pixel electrode 1603 is formed.
[0160]
Etching treatment of the material of the transparent conductive film is performed with a hydrochloric acid-based solution. However, since etching of ITO tends to generate residues, an indium oxide-zinc oxide alloy (In ₂ O _Three —ZnO) may also be used. Indium zinc oxide alloy is characterized by excellent surface smoothness and thermal stability compared to ITO. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.
[0161]
Next, as shown in FIG. 16B, an alignment film 1604 is formed with a third interlayer insulating film 1602 and a pixel electrode 1603. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A transparent conductive film 1606 and an alignment film 1607 are formed on the opposite substrate 1605. After the alignment film is formed, a rubbing process is performed so that the liquid crystal molecules are aligned in parallel with a certain pretilt angle.
[0162]
Through the above steps, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembly process. Thereafter, a liquid crystal material 1608 is injected between both the substrates and completely sealed with a sealant (not shown). Thus, the active matrix liquid crystal display device shown in FIG. 16B is completed.
[0163]
Next, the structure of the active matrix liquid crystal display device of this embodiment will be described with reference to FIGS. 14 and 15A and 15B. FIG. 14 is a perspective view of the active matrix substrate of this embodiment. The active matrix substrate includes a pixel matrix circuit 1401 formed on the glass substrate 301, a scanning (gate) line driving circuit 1402, and a data (source) line driving circuit 1403. A pixel TFT 1400 of the pixel matrix circuit is an n-channel TFT, and a driver circuit provided in the periphery is configured based on a CMOS circuit. The scanning (gate) line driving circuit 1402 and the data (source) line driving circuit 1403 are connected to the pixel matrix circuit 1401 through a gate wiring 1502 and a source wiring 1503, respectively.
[0164]
FIG. 15A is a top view of the pixel matrix circuit 1401, which is a top view of almost one pixel. The pixel matrix circuit is provided with an n-channel TFT which is a pixel TFT. A gate electrode 1520 formed continuously with the gate wiring 1502 intersects the semiconductor layer 1501 thereunder via a gate insulating film (not shown). Although not shown, a source region, a drain region, and a first impurity region are formed in the semiconductor layer. Further, a storage capacitor 1507 is formed on the drain side of the pixel TFT from a semiconductor layer, a gate insulating film, and an electrode formed of the same material as the gate electrode. A capacitor wiring 1521 connected to the storage capacitor 1507 is provided in parallel with the gate wiring 1502. Further, the cross-sectional structure along AA ′ shown in FIG. 15A corresponds to the cross-sectional view of the CMOS circuit shown in FIG.
[0165]
On the other hand, in the CMOS circuit shown in FIG. 15B, the gate electrodes 1513 and 1514 extending from the gate wiring 1515 intersect with the semiconductor layers 1510 and 1512 thereunder through a gate insulating film not shown. Yes. Although not shown, similarly, a source region, a drain region, and a first impurity region are formed in the semiconductor layer of the n-channel TFT. A source region and a drain region are formed in the semiconductor layer of the p-channel TFT. As for the positional relationship, the cross-sectional structure along BB ′ corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG.
[0166]
In this embodiment, the pixel TFT 1400 has a double gate structure, but may have a single gate structure or a multi-gate structure with a triple gate. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. The structure of the present invention is characterized by the structure of the gate electrode, and the structure of the source region, drain region, and other impurity regions of the semiconductor layer provided via the gate insulating film. The practitioner should make a proper decision.
[0167]
The active matrix substrate for manufacturing the active matrix liquid crystal display device shown in this embodiment is not limited to that shown in Embodiment 1, and is manufactured based on the steps shown in Embodiments 2 to 5 and Embodiment 7. Any active matrix substrate can be applied.
[0168]
[Example 7]
In this embodiment, a method for simplifying the gettering step in the method for manufacturing the active matrix substrate shown in Embodiment 5 will be described. First, in Example 5, the semiconductor layers 1103, 1104, and 1105 shown in FIG. 11A are crystalline silicon films manufactured using a catalytic element. At this time, since the catalyst element used in the crystallization process remains in the semiconductor layer, it is desirable to perform a gettering process. In the fifth embodiment, after a crystalline silicon film is obtained, phosphorus is added to a part of the crystalline silicon film and gettering is performed. However, here, the gettering step is not performed. Then, the catalytic element is removed from the channel formation region of the TFT by the method described below.
[0169]
Here, the steps shown in FIGS. 11A to 12C are performed as they are. Then, the resist masks 1137, 1138, 1139, 1140, and 1141 are removed.
[0170]
At this time, phosphorus is added to the first impurity regions 1152, 1153, 1160, and 1164 of the n-channel TFT. Similarly, phosphorus is added to the third impurity regions 1155b and 1156b of the p-channel TFT. According to Example 5, the phosphorus concentration is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three It is.
[0171]
In this state, the gate insulating film and the gate electrode are covered with a silicon nitride film 1180 as shown in FIG. The silicon nitride film is formed by plasma CVD to a thickness of 10 to 100 nm, here 50 nm. A silicon oxynitride film may be used instead of the silicon nitride film.
[0172]
In Example 5, the third layer of the gate electrode is formed of Mo-W. In addition, Ti, Ta, Mo, W, or the like may be used. These materials are relatively easily oxidized by heat treatment at atmospheric pressure or while purging with nitrogen gas. In such a situation, oxidation can be prevented by coating the surface with silicon nitride.
[0173]
In this state, a heat treatment process is performed in a nitrogen atmosphere at 400 to 800 ° C. for 1 to 24 hours, for example, 600 ° C. for 12 hours. By this step, the added impurity element imparting n-type and p-type can be activated. Further, the region to which phosphorus is added becomes a gettering site, and the catalytic element remaining after the crystallization step can be segregated. As a result, the catalytic element can be removed from the channel formation region. As a result, an effect of reducing off-current in the completed TFT can be obtained.
[0174]
When the step of FIG. 22 is completed, the subsequent steps are performed in accordance with the steps of Example 5 to form the first interlayer insulating film, the source wiring and the drain wiring, the passivation film, and the second interlayer insulating film, thereby forming the state of FIG. Thus, an active matrix substrate can be manufactured.
[0175]
[Example 8]
In this embodiment, another example of the circuit configuration of the CMOS circuit shown in FIG. 1 will be described with reference to FIG. Note that the terminal portions a, b, c, and d in the inverter circuit diagram of FIG. 23A and the top view of the inverter circuit of FIG. 23B correspond to each other.
[0176]
A top view of the inverter circuit shown in FIG. 23A is shown in FIG. FIG. 23C shows a cross-sectional structure taken along line AA ′ of FIG. 23B. Gate electrodes 2409 and 2409 ′, a source wiring 2411 of an n-channel TFT, a source wiring 2414 of a p-channel TFT, and a common drain wiring 2413 It is composed of Here, in the gate electrodes 2409 and 2409 ′, the first layer 2408 and 2408 ′ of the gate electrode, the second layers 2409 and 2409 ′ of the gate electrode, and the third layers 2410 and 2410 ′ of the gate electrode are integrated. It represents the state.
[0177]
A second impurity region 2402 is provided in the n-channel TFT of this inverter circuit. Specifically, a second impurity region 2402a that overlaps with the gate electrode 2409 and a second impurity region (LDD region) 2402b that does not overlap are formed. Such a structure may be provided only on the drain side. Further, such an impurity region is not provided in the p-channel TFT.
[0178]
[Example 9]
In addition to the nematic liquid crystal, various liquid crystals can be used for the above-described liquid crystal display device of the present invention. For example, 1998, SID, "Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability" by H. Furue et al., 1997, SID DIGEST, 841, "A Full -Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time "by T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 671-673," Thresholdless antiferroelectricity in liquid crystals and its application to The liquid crystal disclosed in "displays" by S. Inui et al. or US Pat. No. 5,945,569 can be used.
[0179]
Ferroelectric liquid crystal (FLC) showing an isotropic phase-cholesteric phase-chiral smectic C phase transition series is used to cause a cholesteric phase-chiral smectic C phase transition while applying a DC voltage, and the cone edge is almost in the rubbing direction. The electro-optic characteristics of the matched monostable FLC are shown in FIG. The display mode using the ferroelectric liquid crystal as shown in FIG. 24 is called “Half-V-shaped switching mode”. The vertical axis of the graph shown in FIG. 24 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. Regarding “Half-V-shaped switching mode”, Terada et al., “Half-V-shaped switching mode FLCD”, Proceedings of the 46th Joint Physics Related Conference, March 1999, p. 1316, and Yoshihara et al. "Time-division full-color LCD using ferroelectric liquid crystal", Liquid Crystal, Vol. 3, No. 3, page 190.
[0180]
As shown in FIG. 24, it can be seen that when such a ferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible. For the liquid crystal display device of the present invention, ferroelectric liquid crystal exhibiting such electro-optical characteristics can also be used.
[0181]
A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optic response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) is also found. Has been.
[0182]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.
[0183]
In addition, since such a thresholdless antiferroelectric mixed liquid crystal is used for the liquid crystal display device of the present invention, low voltage driving is realized, so that low power consumption is realized.
[0184]
[Example 10]
The active matrix substrate, the liquid crystal display device, and the organic EL display device manufactured by implementing the present invention can be used for various electro-optical devices. The present invention can be applied to all electronic devices in which such an electro-optical device is incorporated as a display unit. Examples of the electronic device include a mobile phone, a video camera, a portable information terminal, a goggle type display, a recording medium player, a portable book, a personal computer, a digital camera, and a projector. Examples of these are shown in FIGS.
[0185]
FIG. 25A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display device 9004, operation switches 9005, and an antenna 9006. The present invention can be applied to a display device 9004 including an audio output unit 9002, an audio input unit 9003, and an active matrix substrate.
[0186]
FIG. 25B illustrates a video camera which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be applied to the display device 9102 and other signal control circuits.
[0187]
FIG. 25C illustrates a portable information terminal which includes a main body 9201, an image input portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205. The present invention can be applied to the display device 9205 and other signal control circuits.
[0188]
FIG. 25D illustrates a goggle type display which includes a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can also be used for other signal control circuits.
[0189]
FIG. 25E shows a player that uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded. The player includes a main body 9401, a display device 9402, a speaker portion 9403, a recording medium 9404, and an operation switch 9405. A recording medium such as a DVD (Digital Versatile Disc) or a compact disc (CD) can be used to play music programs, display images, display video games (or video games), and display information via the Internet. . The present invention can be suitably used for the display device 9402 and other signal control circuits.
[0190]
FIG. 25F illustrates a portable book, which includes a main body 9501, display devices 9502 and 9503, a storage medium 9504, operation switches 9505, and an antenna 9506. Data stored in a minidisc (MD) or DVD, The data received by the antenna is displayed. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to the display devices.
[0191]
FIG. 25G illustrates a personal computer, which includes a main body 9601 including a microprocessor, a memory, and the like, an image input portion 9602, a display device 9603, and a keyboard 9604. The present invention can form the display device 9603 and other signal processing circuits.
[0192]
FIG. 26H illustrates a digital camera, which includes a main body 9701, a display device 9702, an eyepiece 9703, operation switches 9704, and an image receiving unit (not shown). The present invention can be applied to the display device 9702 and other signal control circuits.
[0193]
FIG. 26A shows a front projector, which includes a light source optical system, a display device 2601, and a screen 2602. The present invention can be applied to display devices and other signal control circuits. FIG. 26B shows a rear projector, which includes a main body 2701, a light source optical system and display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.
[0194]
Note that FIG. 26C illustrates an example of the structure of the light source optical system and the display devices 2601 and 2702 in FIGS. 26A and 26B. The light source optical system and the display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2804 to 2806, a dichroic mirror 2803, a beam splitter 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. The projection optical system 2810 includes a plurality of optical lenses. FIG. 26C illustrates a three-plate type example using three liquid crystal display devices 2808; however, the present invention is not limited to such a method, and a single-plate optical system may be used. In addition, an appropriate optical lens, a film having a polarization function, a film for adjusting a phase, an IR film, or the like may be provided in an optical path indicated by an arrow in FIG. FIG. 26D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. The light source optical system shown in FIG. 26D is an example and is not limited to the illustrated configuration.
[0195]
Although not shown here, the present invention can also be applied to a navigation system, a reading circuit of an image sensor, and the like. As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Further, the electronic apparatus of the present embodiment can be realized by using any configuration of the embodiment and any combination of the first to ninth embodiments and the eleventh embodiment.
[0196]
[Example 11]
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described.
[0197]
FIG. 27A is a top view of an EL display device using the present invention. In FIG. 27A, reference numeral 4010 denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, and 4013 denotes a gate side driver circuit. Each driver circuit reaches an FPC 4017 through wirings 4014 to 4016 to an external device. Connected.
[0198]
At this time, a cover material 6000, a sealing material (also referred to as a housing material) 7000, and a sealing material (second sealing material) 7001 are provided so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion.
[0199]
FIG. 27B shows a cross-sectional structure of the EL display device of this embodiment. A driving circuit TFT (here, an n-channel TFT and a p-channel TFT are combined on a substrate 4010 and a base film 4021). And the pixel portion TFT 4023 (however, only the TFT for controlling the current to the EL element is shown here).
[0200]
The present invention can be used for the driver circuit TFT 4022 and the pixel portion TF 4023.
[0201]
When the driver circuit TFT 4022 and the pixel portion TFT 4023 are completed using the present invention, a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on the interlayer insulating film (planarization film) 4026 made of a resin material. A pixel electrode 4027 is formed. In the case where the pixel electrode 4027 is a transparent conductive film, it is preferable to use a p-channel TFT as the pixel portion TFT. As the transparent conductive film, a compound of indium oxide and tin oxide (referred to as ITO) or a compound of indium oxide and zinc oxide can be used. Then, after the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.
[0202]
Next, an EL layer 4029 is formed. The EL layer 4029 may have a stacked structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, a vapor deposition method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.
[0203]
In this embodiment, the EL layer is formed by vapor deposition using a shadow mask. Color display is possible by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but either method may be used. Needless to say, an EL display device emitting monochromatic light can also be used.
[0204]
After the EL layer 4029 is formed, a cathode 4030 is formed thereon. It is desirable to remove moisture and oxygen present at the interface between the cathode 4030 and the EL layer 4029 as much as possible. Therefore, it is necessary to devise such that the EL layer 4029 and the cathode 4030 are continuously formed in a vacuum, or the EL layer 4029 is formed in an inert atmosphere and the cathode 4030 is formed without being released to the atmosphere. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0205]
In this embodiment, a stacked structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 4030. Specifically, a 1 nm-thick LiF (lithium fluoride) film is formed on the EL layer 4029 by evaporation, and a 300 nm-thick aluminum film is formed thereon. Of course, you may use the MgAg electrode which is a well-known cathode material. The cathode 4030 is connected to the wiring 4016 in the region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and is connected to the FPC 4017 through a conductive paste material 4032.
[0206]
In order to electrically connect the cathode 4030 and the wiring 4016 in the region indicated by 4031, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These may be formed when the interlayer insulating film 4026 is etched (when the pixel electrode contact hole is formed) or when the insulating film 4028 is etched (when the opening before the EL layer is formed). In addition, when the insulating film 4028 is etched, the interlayer insulating film 4026 may be etched all at once. In this case, if the interlayer insulating film 4026 and the insulating film 4028 are the same resin material, the shape of the contact hole can be improved.
[0207]
A passivation film 6003, a filler 6004, and a cover material 6000 are formed so as to cover the surface of the EL element thus formed.
[0208]
Further, a sealing material is provided inside the cover material 7000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.
[0209]
At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0210]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0211]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0212]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0213]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0214]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 7000 and the sealing material 7001 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are electrically connected to the FPC 4017 through the sealing material 7000 and the sealing material 7001 in the same manner.
[0215]
[Example 12]
In this embodiment, an example of manufacturing an EL display device having a different form from that of Embodiment 11 using the present invention will be described with reference to FIGS. The same numbers as those in FIGS. 27A and 27B indicate the same parts, and the description thereof is omitted.
[0216]
FIG. 28A is a top view of the EL display device of this example, and FIG. 28B is a cross-sectional view taken along line AA ′ of FIG.
[0217]
In accordance with Example 11, a passivation film 6003 is formed to cover the surface of the EL element.
[0218]
Further, a filler 6004 is provided so as to cover the EL element. The filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0219]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0220]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0221]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0222]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0223]
Next, after the cover material 6000 is bonded using the filler 6004, the frame material 6001 is attached so as to cover the side surface (exposed surface) of the filler 6004. The frame material 6001 is bonded by a sealing material (functioning as an adhesive) 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used if the heat resistance of the EL layer permits. Note that the sealing material 6002 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, a desiccant may be added inside the sealing material 6002.
[0224]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 6002 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.
[0225]
[Example 13]
In this embodiment, FIG. 29 shows a detailed cross-sectional structure of a pixel portion of an EL display device, FIG. 30A shows a top structure, and FIG. 30B shows a circuit diagram. In FIG. 29, FIG. 30A and FIG. 30B, common reference numerals are used and may be referred to each other.
[0226]
In FIG. 29, a switching TFT 3002 provided on a substrate 3001 is formed using an n-channel TFT of the present invention (see Examples 1 to 8). In this embodiment, a double gate structure is used. However, there is no significant difference in structure and manufacturing process, and thus description thereof is omitted. However, the double gate structure substantially has a structure in which two TFTs are connected in series, and there is an advantage that the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure may be used, and a triple gate structure or a multi-gate structure having more gates may be used. Alternatively, the p-channel TFT of the present invention may be used.
[0227]
The current control TFT 3003 is formed using the n-channel TFT of the present invention. At this time, the drain wiring 3035 of the switching TFT 3002 is electrically connected to the gate electrode 3037 of the current control TFT by the wiring 3036. A wiring indicated by 3038 is a gate wiring that electrically connects the gate electrodes 3039a and 3039b of the switching TFT 3002.
[0228]
At this time, it is very important that the current control TFT 3003 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and it is also an element with a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the GOLD region (second impurity region) is provided on the drain side of the current control TFT so as to overlap the gate electrode through the gate insulating film is extremely effective.
[0229]
In this embodiment, the current control TFT 3003 is illustrated as a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.
[0230]
Further, as shown in FIG. 30A, a wiring to be the gate electrode 3037 of the current control TFT 3003 overlaps with a drain wiring 3040 of the current control TFT 3003 through an insulating film in a region indicated by 3004. At this time, a capacitor is formed in a region indicated by 3004. This capacitor 3004 functions as a capacitor for holding the voltage applied to the gate of the current control TFT 3003. The drain wiring 3040 is connected to a current supply line (power supply line) 3006, and a constant voltage is always applied.
[0231]
A first passivation film 3041 is provided on the switching TFT 3002 and the current control TFT 3003, and a planarizing film 3042 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 3042. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0232]
Reference numeral 3043 denotes a pixel electrode (a cathode of the EL element) made of a highly reflective conductive film, which is electrically connected to the drain of the current control TFT 3003. In this case, it is preferable to use an n-channel TFT as the current control TFT. As the pixel electrode 3043, a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof is preferably used. Of course, a laminated structure with another conductive film may be used.
[0233]
A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.
[0234]
There are various types of PPV organic EL materials such as “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,“ Polymers for Light Emitting ”. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and Japanese Patent Laid-Open No. 10-92576 may be used.
[0235]
As a specific light emitting layer, cyanopolyphenylene vinylene may be used for a red light emitting layer, polyphenylene vinylene may be used for a green light emitting layer, and polyphenylene vinylene or polyalkylphenylene may be used for a blue light emitting layer. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm).
[0236]
However, the above example is an example of an organic EL material that can be used as a light emitting layer, and is not necessarily limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer.
[0237]
For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0238]
In this embodiment, an EL layer having a stacked structure in which a hole injection layer 3046 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light emitting layer 3045 is used. An anode 47 made of a transparent conductive film is provided on the hole injection layer 3046. In the case of this embodiment, since the light generated in the light emitting layer 3045 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. What can form into a film at low temperature as much as possible is preferable.
[0239]
When the anode 3047 is formed, the EL element 3005 is completed. Note that the EL element 3005 here refers to a capacitor formed of a pixel electrode (cathode) 3043, a light emitting layer 3045, a hole injection layer 3046, and an anode 3047. As shown in FIG. 30A, since the pixel electrode 3043 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.
[0240]
Incidentally, in this embodiment, a second passivation film 3048 is further provided on the anode 3047. The second passivation film 3048 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to cut off the EL element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic EL material and the meaning of suppressing degassing from the organic EL material. This increases the reliability of the EL display device.
[0241]
As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 29, and includes a switching TFT having a sufficiently low off-current value and a current control TFT resistant to hot carrier injection. Have. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.
[0242]
In addition, the structure of a present Example can be implemented in combination freely with Examples 1-8 structure. Moreover, it is effective to use the EL display device of this embodiment as the display unit of the electronic apparatus of Embodiment 10.
[0243]
[Example 14]
In this embodiment, a structure in which the structure of the EL element 3005 is inverted in the pixel portion described in Embodiment 13 will be described. FIG. 31 is used for the description. Note that the only difference from the structure of FIG. 29 is the EL element portion and the current control TFT, and other descriptions are omitted.
[0244]
In FIG. 31, a current control TFT 3103 is formed using the p-channel TFT of the present invention. Examples 1 to 8 may be referred to for the manufacturing process.
[0245]
In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 3050. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Of course, a conductive film made of a compound of indium oxide and tin oxide may be used.
[0246]
Then, after the banks 3051a and 3051b made of insulating films are formed, the light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 3053 made of potassium acetylacetonate (denoted as acacK) and a cathode 3054 made of an aluminum alloy are formed thereon. In this case, the cathode 3054 also functions as a passivation film. Thus, the EL element 3101 is formed.
[0247]
In this embodiment, light generated in the light emitting layer 3052 is emitted toward the substrate on which the TFT is formed as indicated by an arrow.
[0248]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-8. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 10.
[0249]
[Example 15]
In this embodiment, FIGS. 32A to 32C show an example of a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, 3201 is a source wiring of the switching TFT 3202, 3203 is a gate wiring of the switching TFT 3202, 3204 is a current control TFT, 3205 is a capacitor, 3206 and 3208 are current supply lines, and 3207 is an EL element. .
[0250]
FIG. 32A shows an example in which the current supply line 3206 is shared between two pixels. That is, there is a feature in that two pixels are formed so as to be symmetrical with respect to the current supply line 3206. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0251]
FIG. 32B illustrates an example in which the current supply line 3208 is provided in parallel with the gate wiring 3203. Note that in FIG. 32B, the current supply line 3208 and the gate wiring 3203 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, since the exclusive area can be shared by the power supply line 3208 and the gate wiring 3203, the pixel portion can be further refined.
[0252]
In FIG. 32C, the current supply line 3208 is provided in parallel with the gate wirings 3203a and 3230b as in the structure of FIG. 32B, and two pixels are symmetrical with respect to the current supply line 3208. It is characterized in that it is formed as follows. It is also effective to provide the current supply line 3208 so as to overlap any one of the gate wirings 3203a and 3230b. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0253]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-8. In addition, it is effective to use the EL display device having the pixel structure of this embodiment as the display unit of the electronic apparatus of Embodiment 10.
[0254]
[Example 16]
In FIGS. 30A and 30B shown in Embodiment 13, the capacitor 3004 is provided to hold the voltage applied to the gate of the current control TFT 3003. However, the capacitor 3004 can be omitted. In the case of Example 13, since the n-channel TFT of the present invention as shown in Examples 1 to 8 is used as the current control TFT 3003, the GOLD region provided so as to overlap the gate electrode through the gate insulating film (Second impurity region). A parasitic capacitance generally called a gate capacitance is formed in the overlapped region, but this embodiment is characterized in that the parasitic capacitance is positively used in place of the capacitor 3004.
[0255]
Since the capacitance of the parasitic capacitance varies depending on the area where the gate electrode and the GOLD region overlap, the capacitance of the parasitic capacitance is determined by the length of the GOLD region included in the overlapping region.
[0256]
Similarly, in the structure of FIGS. 32A, 32B, and 32C shown in the fifteenth embodiment, the capacitor 3205 can be omitted.
[0257]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-8. In addition, it is effective to use the EL display device having the pixel structure of this embodiment as the display unit of the electronic apparatus of Embodiment 10.
[0258]
【The invention's effect】
By implementing the present invention, a stable operation could be obtained even when a gate voltage of 15 to 20 V was applied to the n-channel TFT of the pixel matrix circuit to drive it. As a result, the reliability of a semiconductor device including a CMOS circuit made of crystalline TFTs, and more specifically, a pixel matrix circuit of a liquid crystal display device and a drive circuit provided in the periphery thereof is improved for long-time use. A durable liquid crystal display device could be obtained.
[0259]
Further, according to the present invention, in the second impurity region formed between the channel formation region and the drain region of the n-channel TFT, the region where the second impurity region overlaps the gate electrode (GOLD region) It is possible to easily create different lengths of non-overlapping regions (LDD regions). Specifically, the length of the region (LDD region) where the second impurity region does not overlap with the gate electrode (GOLD region) can be determined according to the driving voltage of the TFT. When TFTs are operated with different driving voltages in the same substrate, TFTs corresponding to the respective driving voltages can be manufactured in the same process.
[0260]
Further, such a feature of the present invention is very suitable for an active matrix type liquid crystal display device in which driving voltage and required TFT characteristics are different between a pixel matrix circuit and a driver circuit.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a TFT according to an embodiment.
FIG. 2 is a diagram illustrating a positional relationship between a gate electrode and a second impurity region.
FIG. 3 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.
7 is a cross-sectional view illustrating a manufacturing process of a TFT. FIG.
FIG. 8 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 9 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 10 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 11 is a cross-sectional view illustrating a manufacturing process of a TFT.
12 is a cross-sectional view showing a manufacturing process of a TFT. FIG.
FIG. 13 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 14 is a perspective view of an active matrix substrate.
FIG. 15 is a top view of an active matrix circuit and a CMOS circuit.
FIG. 16 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device.
FIG. 17 shows a structure of a gate electrode.
18A and 18B illustrate a structure and electrical characteristics of a TFT.
FIG. 19 is a diagram showing a manufacturing process of a crystalline silicon film.
FIG. 20 is a view showing a manufacturing process of a crystalline silicon film.
FIG. 21 is a view showing a manufacturing process of a crystalline silicon film.
FIG. 22 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 23 is an inverter circuit diagram, a top view, and a cross-sectional structure diagram.
FIG. 24 is a view showing light transmittance characteristics of a ferroelectric mixed liquid crystal.
FIG 25 illustrates an example of a semiconductor device.
FIG. 26 is a diagram illustrating a configuration of a projector.
FIGS. 27A and 27B are a top view and a cross-sectional view of an active matrix EL display device. FIGS.
28A and 28B are a top view and a cross-sectional view of an active matrix EL display device.
FIG. 29 is a cross-sectional view of a pixel portion of an active matrix EL display device.
30A and 30B are a top view and a circuit diagram of a pixel portion of an active matrix EL display device.
FIG. 31 is a cross-sectional view of a pixel portion of an active matrix EL display device.
FIG. 32 is a circuit diagram of a pixel portion of an active matrix EL display device.

Claims (13)

A semiconductor device in which a TFT having a semiconductor layer, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film is formed on a substrate having an insulating surface ,
The gate electrode includes an island-shaped first conductive layer formed in contact with the gate insulating film, an island-shaped second conductive layer formed on the island-shaped first conductive layer, and the island-shaped conductive layer. An island-shaped third conductive layer formed in contact with the first conductive layer and the island-shaped second conductive layer;
The island-shaped second conductive layer is shorter than the length of the island-shaped first conductive layer in the channel length direction, and is surrounded by the island-shaped first conductive layer and the island-shaped third conductive layer. ,
The semiconductor layer is formed between a channel formation region, a source region and a drain region to which an impurity element of one conductivity type is added, and between the channel formation region, the source region, and the drain region, respectively. An LDD region to which an impurity element of a type is added,
The island-shaped first conductive layer and the island-shaped third conductive layer have matching ends.
The island-shaped second conductive layer and the channel formation region have ends coincident with each other through the gate insulating film,
An LDD region formed between the channel formation region and the source region overlaps the gate electrode,
A part of an LDD region formed between the channel formation region and the drain region overlaps with the gate electrode. A semiconductor device in which a TFT having a semiconductor layer, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film is formed on a substrate having an insulating surface ,
The gate electrode includes an island-shaped first conductive layer formed in contact with the gate insulating film, an island-shaped second conductive layer formed on the island-shaped first conductive layer, and the island-shaped conductive layer. An island-shaped third conductive layer formed in contact with the first conductive layer and the island-shaped second conductive layer;
The island-shaped second conductive layer is shorter than the length of the island-shaped first conductive layer in the channel length direction, and is surrounded by the island-shaped first conductive layer and the island-shaped third conductive layer. ,
The semiconductor layer is formed between a channel formation region, a source region and a drain region to which an impurity element of one conductivity type is added, and between the channel formation region, the source region, and the drain region, respectively. An LDD region to which an impurity element of a type is added,
The island-shaped first conductive layer and the island-shaped third conductive layer have matching ends.
The island-shaped second conductive layer and the channel formation region have ends coincident with each other through the gate insulating film,
A part of the LDD region overlaps the gate electrode,
The thickness of the gate insulating film is smaller in a region not in contact with the gate electrode than in a region in contact with the gate electrode.   3. The island-shaped first conductive layer according to claim 1, wherein the island-shaped first conductive layer is one or more elements selected from silicon, titanium, tantalum, tungsten, and molybdenum, or a compound containing the element as a component. A semiconductor device.   4. The island-shaped second conductive layer according to claim 1, wherein the island-shaped second conductive layer is one or more elements selected from aluminum and copper, or a compound containing the element as a main component. Semiconductor device.   5. The island-shaped third conductive layer according to claim 1, wherein the island-shaped third conductive layer is made of one or more elements selected from silicon, titanium, tantalum, tungsten, and molybdenum, or a compound containing the element as a component. There is a semiconductor device.   6. The semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device.   6. The semiconductor device according to claim 1, wherein the semiconductor device is an electroluminescence display device. 6. The semiconductor device according to claim 1, wherein the semiconductor device includes a mobile phone, a video camera, a portable information terminal, a goggle type display, a player using a recording medium, a portable book, a personal computer, a digital camera, a projector , and a navigation system. Any one of the selected semiconductor devices. A method for manufacturing a semiconductor device in which a TFT having a semiconductor layer, a gate insulating film, and an island-shaped gate electrode including first to third conductive layers is formed over a substrate having an insulating surface .
The semiconductor layer is formed on the substrate having the insulating surface,
Forming a gate insulating film in contact with the semiconductor layer;
A first conductive layer and a second conductive layer are sequentially formed on the gate insulating film;
After etching part of the second conductive layer to form the island-shaped second conductive layer,
An impurity element of one conductivity type is added to the semiconductor layer using the island-shaped second conductive layer as a mask,
Thereafter, a third conductive layer is formed in contact with the first conductive layer and the island-shaped second conductive layer,
Etching a part of the first conductive layer and the third conductive layer to form the island-shaped first conductive layer and the island-shaped third conductive layer surrounding the island-shaped second conductive layer, respectively. ,
After forming a resist mask so as to cover the upper surface and one side surface of the island-shaped first to third conductive layers,
The impurity element of one conductivity type is added to a selected region of the semiconductor layer using the resist mask as a mask, and between the source region and the drain region, the channel formation region, the source region, and the drain region. Forming each formed LDD region;
An LDD region formed between the channel formation region and the source region overlaps the gate electrode,
A method for manufacturing a semiconductor device, wherein a part of an LDD region formed between the channel formation region and the drain region overlaps with the gate electrode. A method for manufacturing a semiconductor device in which a TFT having a semiconductor layer, a gate insulating film, and an island-shaped gate electrode including first to third conductive layers is formed over a substrate having an insulating surface .
The semiconductor layer is formed on the substrate having the insulating surface,
Forming a gate insulating film in contact with the semiconductor layer;
A first conductive layer and a second conductive layer are sequentially formed on the gate insulating film;
After etching part of the second conductive layer to form the island-shaped second conductive layer,
An impurity element of one conductivity type is added to the semiconductor layer using the island-shaped second conductive layer as a mask,
Thereafter, a third conductive layer is formed in contact with the first conductive layer and the island-shaped second conductive layer,
The first conductive layer and the third conductive layer are partially etched to form the island-shaped first conductive layer and the island-shaped third conductive layer that surround the island-shaped second conductive layer, respectively. And reducing the thickness of the gate insulating film other than the region in contact with the island-shaped first conductive layer,
After forming a resist mask so as to cover the top and side surfaces of the island-shaped first to third conductive layers,
The impurity element of one conductivity type is added to a selected region of the semiconductor layer using the resist mask as a mask, and between the source region and the drain region, the channel formation region, the source region, and the drain region. Forming each formed LDD region;
A method for manufacturing a semiconductor device, wherein a part of the LDD region overlaps with the gate electrode.   11. The island-shaped first conductive layer according to claim 9, wherein one or a plurality of elements selected from silicon, titanium, tantalum, tungsten, and molybdenum, or a compound containing the element as a component is used as the island-shaped first conductive layer. A method for manufacturing a semiconductor device.   12. The island-shaped second conductive layer according to claim 9, wherein one or more elements selected from aluminum and copper, or a compound containing the element as a main component is used as the island-shaped second conductive layer. A method for manufacturing a semiconductor device.   13. The island-shaped third conductive layer according to claim 9, wherein one or more elements selected from silicon, titanium, tantalum, tungsten, and molybdenum, or a compound containing the element as a component is used as the island-shaped third conductive layer. A method for manufacturing a semiconductor device, characterized by being used.

Images