JP2001210832A - Semiconductor device and method of manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the operating characteristics and reliability of a semiconductor device, represented by the active matrix type display device, by appropriately constituting TFTs arranged in various kinds of circuits in accordance with the functions of the circuits and, at the same time, to reduce the manufacturing cost and improve the yield of the device by reducing the number of processes. SOLUTION: In this semiconductor device having a semiconductor layer, an insulating film which is formed in contact with the semiconductor layer, and a gate electrode which has a tapered section and is formed on the insulating film, the semiconductor layer has a channel forming area, a first impurity area which forms a source or drain area containing an impurity element of one conductivity type, and a second impurity area which is formed in contact with the channel forming area and forms an LDD area. The second impurity area is formed in such a way that the part of the area overlaps the gate electrode and the concentration of the impurity element of one conductivity type contained in the area becomes higher as the area becomes more distant from the channel forming area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit formed of thin film transistors (hereinafter, referred to as TFTs) on a substrate having an insulating surface, and a method for manufacturing the same. In particular, the present invention can be suitably used for an electro-optical device typified by a liquid crystal display device or an EL display device in which a pixel portion and a driver circuit are provided over the same substrate, and an electronic device equipped with such an electro-optical device. Provide technology. In this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and a device equipped with the electro-optical device in its category.

[0002]

2. Description of the Related Art A display device in which pixel elements are formed by arranging active elements is called an active matrix type display device, and a liquid crystal display device, an electroluminescence (hereinafter referred to as EL) display device and the like have been developed. An insulated gate transistor is used for the active element, and a TFT is preferably used.
Is used. In a TFT, a semiconductor film is formed over a substrate such as glass by a vapor deposition method or the like, and a channel formation region, a source region, a drain region, and the like are formed using the semiconductor film. For the semiconductor film, silicon or a material mainly containing silicon such as silicon / germanium is preferably used. Semiconductor films can be classified into amorphous semiconductor films typified by amorphous silicon and crystalline semiconductor films typified by polycrystalline silicon depending on their manufacturing methods. In addition, in recent years, a technique of forming a pixel portion with an insulated gate transistor formed on a single crystal silicon substrate has been developed.

A TFT having an active layer formed of an amorphous semiconductor (typically, amorphous silicon) film has an electric field of 10 cm ² / V · sec or more due to electronic physical factors due to an amorphous structure or the like. It was almost impossible to obtain an effective mobility. Therefore, in an active matrix type liquid crystal display device, even if it can be used as a switching element for driving liquid crystal in a pixel portion (this switching element is formed of a TFT, hereinafter referred to as a pixel TFT), an It is impossible to form a drive circuit for performing display. Therefore, the driving circuit is TAB (Tape Automated Bonded).
A technology for mounting a driver IC or the like using an ng) method or a COG (Chip on Glass) method is used.

On the other hand, a TFT having a semiconductor film having a crystal structure (hereinafter, referred to as a crystalline semiconductor) (typically, crystalline silicon or polycrystalline silicon) as an active layer has high field-effect mobility. Therefore, various functional circuits can be formed and driven, and a shift register circuit,
It has become possible to realize a level shifter circuit, a buffer circuit, a sampling circuit, and the like. The driving circuit is a CMOS comprising an n-channel TFT and a p-channel TFT.
It is formed on a circuit basis. Based on the mounting technology of such a driving circuit, in order to promote weight reduction and thinning of a liquid crystal display device, a crystalline semiconductor layer in which a driving circuit in addition to a pixel portion can be integrally formed on the same substrate is used as an active layer. Is considered to be suitable.

[0005]

From the viewpoint of TFT characteristics, it is better to form an active layer with a crystalline semiconductor layer. However, in order to manufacture a TFT corresponding to various circuits in addition to a pixel TFT, There is a problem that the manufacturing process becomes complicated and the number of processes increases. It is clear that an increase in the number of steps not only causes an increase in manufacturing cost, but also causes a reduction in manufacturing yield.

[0006] The operating conditions of the pixel TFT and the TFT of the drive circuit are not necessarily the same, and the characteristics required for the TFT are not less different. A pixel TFT formed of an n-channel TFT is driven by applying a voltage to a liquid crystal as a switching element. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often used. The pixel TFT is required to have a sufficiently low off-current value (drain current flowing when the TFT is turned off) in order to hold the charge accumulated in the liquid crystal layer for one frame period. on the other hand,
Since a high drive voltage is applied to a buffer circuit or the like of the drive circuit, it is necessary to increase the breakdown voltage so that the buffer circuit is not broken even when the high voltage is applied. Further, in order to increase the current driving capability, it is necessary to sufficiently secure an on-current value (a drain current flowing when the TFT is turned on).

As a structure of a TFT for reducing an off-current value, a lightly doped drain (LDD) is used.
n) Structure is known. In this structure, a region doped with an impurity element at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. This region is referred to as an LDD region. Calling. As means for preventing deterioration of the on-current value due to hot carriers, a so-called GD in which an LDD region is arranged so as to overlap with a gate electrode via a gate insulating film is provided.
There is an OLD (Gate-drain Overlapped LDD) structure. With such a structure, it is known that a high electric field near the drain is relieved, hot carrier injection is prevented, and deterioration is effectively prevented.

However, the bias state of the pixel TFT is not always the same as that of the TFT of a driving circuit such as a shift register circuit or a buffer circuit. For example, the pixel T
In the FT, a large reverse bias (negative voltage in an n-channel TFT) is applied to the gate.
The FT basically does not operate in the reverse bias state.
The GOLD structure has a high effect of preventing the deterioration of the on-current value, but the off-current value is increased by simply arranging it on the gate electrode. On the other hand, the ordinary LDD structure has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain to prevent deterioration due to hot carrier injection. Such a problem is particularly problematic in crystalline silicon TF
At T, the characteristics have been improved, and the performance required for the active matrix type liquid crystal display device has become more prominent. Therefore, considering the difference in the operation state of the TFT and preventing the hot carrier effect,
It is necessary to optimize the impurity concentration and distribution of the DD region.

The present invention is a technique for solving such a problem. In a semiconductor device typified by an active matrix type display device manufactured using a TFT,
By making the structure of the TFTs arranged in various circuits appropriate according to the functions of the circuits, the operating characteristics and reliability of the semiconductor device are improved, and the number of steps is reduced to reduce the manufacturing cost and the yield. The purpose is to achieve the improvement.

[0010]

In order to reduce the manufacturing cost and achieve the yield, reduction of the number of steps can be applied as one means. Specifically, it is necessary to reduce the number of photomasks required for manufacturing a TFT. A photomask is used in a photolithography technique to form a resist pattern used as a mask in an etching step on a substrate. This photomask is 1
The use of two or more sheets, in addition to the steps of film formation and etching in the preceding and subsequent steps, a resist peeling, washing and drying steps, etc. are added, and in the photolithography step, resist coating, pre-baking, exposure, This means that complicated steps such as development and post-baking are performed.

Even if the number of photomasks is reduced, the structures of the TFTs arranged in various circuits are made appropriate according to the functions of the circuits. Specifically, a TFT for a switching element provided in a pixel portion preferably has a structure in which emphasis is placed on reducing an off-current value rather than an operation speed. As such a structure, a multi-gate structure is employed. On the other hand, a TFT provided in a driver circuit that requires high-speed operation requires a structure that emphasizes increasing the operation speed and at the same time, suppressing deterioration due to hot carrier injection, which is a significant problem. The structure is realized by devising the LDD region. In other words, the LDD region provided between the channel forming region and the drain region has a concentration gradient such that the concentration of the impurity element for controlling the conductivity type gradually increases as the region approaches the drain region. The effect of alleviating the concentration of the electric field in the depletion layer can be enhanced. Part of the LDD region may be provided so as to overlap with the gate electrode.

In order to form an LDD region having an impurity element concentration gradient as described above, an ionized impurity element for controlling conductivity is accelerated by an electric field to form a part of a gate electrode and a gate insulating film (the present invention). In this case, a gate insulating film provided in close contact with the gate electrode and the semiconductor layer and between the gate electrode and the semiconductor layer and an insulating film extending from the gate insulating film to a peripheral region thereof are referred to as a gate insulating film. Then, a method of doping the semiconductor layer is used. Further, the shape of the gate electrode is a so-called tapered shape in which the thickness gradually increases from the end of the gate electrode toward the inside, and the change in the thickness is used to control the concentration of the impurity element doped into the semiconductor layer. . That is, an LDD region where the impurity element concentration gradually changes in the channel length direction of the TFT is formed.

More specifically, a first etching process is performed on a conductive layer forming a gate electrode to remove a conductive layer in a predetermined region and expose a gate insulating film in a partial region on the semiconductor layer. Let it. At this time, the conductive layer has a tapered shape whose thickness gradually increases from the end toward the inside. And
A first doping process for adding an impurity element of one conductivity type is performed to form a first low-concentration impurity region. Next, a second etching process and a second doping process are similarly performed to form a second low-concentration impurity region. L
The DD region is formed from the first and second low concentration impurity regions. In this case, the shape of the gate electrode is determined by the second etching treatment, and a part of the LDD region can be provided so as to overlap with the gate electrode if the conditions of the second doping treatment are set to be appropriate.

As described above, the present invention is characterized in that an etching process and a doping process are repeated a plurality of times to form an LDD region. As a result, a plurality of LDD regions having different concentrations in the channel length direction can be formed, and the impurity concentration of the LDD region can be changed stepwise or continuously.

The conductive layer forming the gate electrode is preferably made of a heat-resistant conductive material.
An element selected from tantalum (Ta) and titanium (Ti),
Alternatively, it is formed from a compound or an alloy containing the above element as a component. In order to etch such a heat-resistant conductive material at high speed and with high accuracy and to further form a tapered end portion, it is preferable to apply a dry etching method using high-density plasma. Microwave and inductively coupled plasma (InductivelyCoupled P
An etching apparatus using lasma (ICP) is suitable. In particular, the ICP etching apparatus can easily control the plasma and can cope with an increase in the area of the substrate.

As described above, the structure of the present invention provides a semiconductor device having a semiconductor layer, an insulating film formed in contact with the semiconductor layer, and a gate electrode having a tapered portion on the insulating film. The semiconductor layer includes a channel formation region, a first impurity region which forms a source region or a drain region containing an impurity element of one conductivity type, and a second impurity region which is in contact with the channel formation region and forms an LDD region. A part of the second impurity region is provided so as to overlap with the gate electrode;
The concentration of the one-conductivity-type impurity element included in the second impurity region increases as the distance from the channel formation region increases.

The structure of the present invention as described above,
It can be suitably used for a semiconductor device in which T is formed.
In a semiconductor device having an n-channel TFT and a p-channel TFT, the semiconductor layer of the n-channel TFT includes:
A channel formation region, a first impurity region forming a source region or a drain region containing an impurity element of one conductivity type, and a second impurity region forming an LDD region in contact with the channel formation region.
And a part of the second impurity region is provided so as to overlap with the gate electrode. The concentration of the one conductivity type impurity element included in the second impurity region increases as the distance from the channel formation region increases. The semiconductor layer of the p-channel TFT has a channel formation region, a third impurity region forming a source region or a drain region, and a fourth impurity region in contact with the channel formation region and forming an LDD region. The third impurity region and the fourth impurity region include
It is characterized in that it contains an impurity element of one conductivity type and an impurity element of a conductivity type opposite to the one conductivity type.

In a semiconductor device having a pixel portion, the semiconductor layer of at least one TFT provided in each pixel includes a channel formation region and a first or second source or drain region containing an impurity element of one conductivity type. An impurity region and a second impurity region which is in contact with the channel formation region and forms an LDD region; part of the second impurity region is provided so as to overlap with the gate electrode and is included in the second impurity region; The concentration of the one-conductivity-type impurity element increases as the distance from the channel formation region increases.

Further, a method for manufacturing a semiconductor device according to the present invention
A first step of forming an insulating film over the semiconductor layer, a second step of forming a conductive layer over the insulating film, and selectively etching the conductive layer to form a first tapered conductive layer A third step of doping, a fourth step of doping the semiconductor layer with an impurity element of one conductivity type after the third step, and a second step of selectively etching the conductive layer having the first tapered shape. A fifth step of forming a conductive layer having a tapered shape; and a sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step, wherein doping is performed in the sixth step. The concentration of the one conductivity type impurity element is lower than the concentration of the one conductivity type impurity element doped in the fourth step.

The structure of the present invention as described above,
It can be suitably used for a method for manufacturing a semiconductor device in which T is formed. In a semiconductor device having an n-channel thin film transistor and a p-channel thin film transistor, a first step of forming an insulating film over each semiconductor layer;
A second step of forming a conductive layer over the insulating film, a third step of selectively etching the conductive layer to form a conductive layer having a first tapered shape, and one conductive layer after the third step. A fourth step of doping the semiconductor layer with an impurity element of the type, a fifth step of selectively etching the conductive layer having the first tapered shape to form a conductive layer having the second tapered shape, A sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step, and an impurity element of a conductivity type opposite to the one conductivity type in the semiconductor layer of the p-channel thin film transistor after the sixth step And doping in the sixth step, wherein the concentration of the one-conductivity-type impurity element in the sixth step is lower than the concentration of the one-conductivity-type impurity element in the fourth step. And

In the method for manufacturing a semiconductor device having a pixel portion, a first step of forming an insulating film on a semiconductor layer for forming a TFT provided in each pixel and a second step of forming a conductive layer on the insulating film are provided. And a third step of selectively etching the conductive layer to form a conductive layer having a first tapered shape.
And a fourth step of doping the semiconductor layer with an impurity element of one conductivity type after the third step, and selectively etching the conductive layer having the first tapered shape to form a second tapered shape. A fifth step of forming a conductive layer having the first conductive layer, and a sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step. It is characterized in that the concentration of the impurity element is lower than the concentration of the one conductivity type impurity element doped in the fourth step.

[0022]

1 and 2 show an embodiment of the present invention.
This will be described with reference to FIG. In FIG. 1A, a substrate 1001
In addition to glass substrates such as barium borosilicate glass and aluminoborosilicate glass typified by Corning's # 7059 glass and # 1737 glass, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sal A plastic substrate having no optical anisotropy, such as FON (PES), can be used. Further, a quartz substrate may be used. When using a glass substrate, 10 to 20 ° C higher than the glass strain point
Preliminary heat treatment at a low temperature can prevent the substrate from being deformed in a subsequent step.

On the surface of the substrate 1001 where the TFT is to be formed,
In order to prevent impurity diffusion from the substrate 1001, a base film 1002 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed with a thickness of 10 to 200 nm. The base film may be formed with one layer of the insulating film, or may be formed with a plurality of layers.

The island-shaped semiconductor layer 1003 is formed from a crystalline semiconductor film obtained by crystallizing a semiconductor film having an amorphous structure by a laser annealing method, a thermal annealing method, or a rapid thermal annealing method (RTA method). Alternatively, the insulating film may be formed from a crystalline semiconductor film formed by a sputtering method, a plasma CVD method, a thermal CVD method, or the like. Or Japanese Patent Laid-Open No. 7-1
According to the technique disclosed in Japanese Patent No. 30652, the crystalline semiconductor layer 103b can be formed by a crystallization method using a catalytic element. In the crystallization step, first, it is preferable to release hydrogen contained in the amorphous semiconductor layer.
Crystallization after heat treatment at 0 to 500 ° C. for about 1 hour to reduce the amount of hydrogen contained to 5 atomic% or less is preferable because roughness of the film surface can be prevented. In any case, the crystalline semiconductor film thus formed is selectively etched to form an island-shaped semiconductor layer 1003 at a predetermined position.

Alternatively, an SOI (Silicon On Insulators) substrate in which a single crystal silicon layer is formed over the substrate 1001 may be used. Several types of SOI substrates are known depending on the structure and manufacturing method.
MOX (Separation by Implanted Oxygen), ELTR
An AN (Epitaxial Layer Transfer: registered trademark of Canon Inc.) substrate, Smart-Cut (registered trademark of SOITEC Inc.) and the like can be used. Of course, other SOI substrates can be used.

The gate insulating film has a thickness of 40 to 150 nm by a plasma CVD method, a sputtering method, a low pressure CVD method or the like.
As an insulating film containing silicon. For example, it is formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. This is applied to the first shape gate insulating film 100.
4 is assumed. Then, the first shape gate insulating film 1004
A conductive layer 1005 for forming a gate electrode is formed thereover. The conductive layer 1005 is desirably formed from a conductive material having heat resistance, and may be formed as a single layer, or may have a stacked structure including a plurality of layers such as two layers or three layers as needed. For example, it is formed using an element selected from tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo), an alloy containing the above elements, or an alloy film in which the above elements are combined. In addition, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (T
iN), a laminated structure of molybdenum nitride (MoN), a silicide such as tungsten silicide, tantalum silicide, titanium silicide, molybdenum silicide, or the like may be formed. Then, the first shape mask 10
06 is formed. The first shape mask 1006 is formed using a resist material by using a photolithography technique.

Then, a first etching process shown in FIG. 1B is performed. This etching treatment is taper etching, and the conductive layer 1005 is formed into a first shape mask 1006.
The etching process is performed so that a tapered portion is formed at the end of the substrate. The etching treatment is performed using a dry etching method, preferably using an ICP etching apparatus. By using a mixed gas of CF ₄ and Cl _{2 as} an etching gas and applying a bias voltage to the substrate, the conductive layer 100 having the first tapered shape is formed on at least the island-shaped semiconductor layer 1003.
8 is formed. The shape of the tapered portion can be changed by the mixing ratio of the etching gas, the pressure at the time of etching, and the bias voltage applied to the substrate side. The most controllable taper shape is the bias voltage applied to the substrate side.

The dry etching is performed by an element such as fluorine (F) or chlorine (Cl) or a neutral or ionic species of a molecule containing the element. Usually, if etching by a neutral species is dominant, the etching proceeds isotropically, and it becomes difficult to form a tapered shape. Anisotropic etching is performed by applying a positive or negative bias voltage to the substrate side. In the etching for forming the tapered shape, a bias voltage is applied to the substrate side, and at the same time, a difference in etching rate between the coating film and the resist (also referred to as a selectivity, which is represented by an etching rate of a workpiece / an etching rate of a resist). The etching is performed while simultaneously etching the resist as a value within a certain range. By appropriately setting the shape of the resist to be formed first, the resist is gradually etched from the end of the resist, so that a tapered shape can be formed in the underlying film. First shape mask 1006
Is changed, and the mask 1007 having the second shape is formed. Further, as the etching proceeds, the surface of the gate insulating film 1004 under the conductive layer 1005 is exposed, and the gate insulating film is also etched to some extent from the surface to form the second-shaped gate insulating film 1009.

Thereafter, a first doping process is performed using the resist 1009 as a mask, and the island-shaped semiconductor layer 100 is formed.
3, an impurity element of one conductivity type is added. The doping process is performed by an ion doping method or an ion implantation method in which an impurity element is ionized, accelerated by an electric field, and injected into a semiconductor layer. The one-conductivity-type impurity element is added to the underlying semiconductor layer through the gate insulating film. Some of the impurity elements of one conductivity type have a first tapered conductive layer 10 in which a tapered shape is formed.
08 can be added to the semiconductor layer thereunder through and near the end.

In the first impurity region 1011, the concentration of an impurity element of one conductivity type is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3.
To be included at a concentration of In the second impurity region (A) 1012, the concentration of the impurity element added to the semiconductor layer is reduced by the increase in the thickness of the gate insulating film 1009 in the second shape as compared to the first impurity region 1011. And the second
Although a uniform concentration distribution cannot always be obtained in the impurity region (A) 1012 of 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ³
The impurity element is added within the concentration range of.

In FIG. 1B, a region 10 surrounded by a dotted line is shown.
An enlarged view of No. 17 is shown in FIG. FIG. 2 (A
-2) may be a diagram schematically showing the concentration distribution of the impurity element in an arbitrary unit amount. The impurity region is formed below the gate insulating film and the tapered portion of the gate electrode. The concentration distribution of the impurity element is shown by a line 1030, and the first impurity region 101
Decreases away from 1. The rate of this decrease depends on conditions such as the acceleration voltage and the dose in ion doping, the angle θ1 of the tapered portion, the first shape of the gate electrode 1008, and the like.
It depends on the thickness of the

Next, a second etching process is performed as shown in FIG. The second etching treatment is anisotropic etching, and the gate electrode 1008 having the first shape is used.
Is etched so as to shorten the width in the channel length direction. The method of etching is the same as that of the first etching process, and uses an ICP etching apparatus. Similarly, a mixed gas of CF ₄ and Cl ₂ is used as an etching gas, and a bias voltage is applied to the substrate side to form a conductive layer 1015 having a second tapered shape. Also in the second etching process, a part of the gate insulating film serving as a base is etched from the surface, so that the second-shaped gate insulating film 101 is formed.
6 are formed. An area 101 surrounded by a dotted line in FIG.
9B is an enlarged view of FIG. 9B. Although a tapered portion is also formed at the end of the conductive layer 1015 having the second tapered shape, emphasis is placed on reducing the width in the channel length direction. , The taper angle θ2 becomes larger than θ1.

Then, a second doping process is performed using the resist 1014 as a mask, and the island-shaped semiconductor layer 100 is formed.
3, an impurity element of one conductivity type is added. In this case, some of the impurity elements are formed in the conductive layer 10 having the second tapered shape.
It can be added to the semiconductor layer therebelow through the end portion 15 and its vicinity.

In the second doping process, 1
An impurity element of one conductivity type is contained at a concentration of × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . As shown in FIG. 2B-2, in this process, the first impurity region 1011 and the second impurity region (A) 1012 formed by the first doping process are also overlapped with one conductivity type impurity. The element is added, but the effect is negligible because the addition amount is low. Newly formed second impurity region (B) 101
8 has a concentration of one conductivity type impurity element of 1 × 10 ^{16 to} 5 ×.
It should be contained at a concentration of 10 ¹⁸ atoms / cm ³ . In the second impurity region (B) 1018, the concentration of the impurity element added to the semiconductor layer is reduced by the increase in the thickness of the conductive layer 1016 having the second tapered shape, and the second impurity region (B) 1018 is formed. Although it is not always possible to obtain a uniform concentration distribution within the above, the impurity element is contained within the above concentration range.

The second impurity region (B) 1018 is formed below the tapered portion of the gate insulating film 1016 having the second shape and the conductive layer 1015 having the second tapered shape. The concentration distribution of the impurity element is indicated by a line 1031 and decreases as the distance from the first impurity region 1011 increases. The conductive layer 1015 having the second tapered shape is used as a gate electrode. As described above, by forming the end portion of the gate electrode into a tapered shape and doping the impurity element through the tapered portion, an impurity such that the concentration of the impurity element gradually changes in the semiconductor layer existing under the tapered portion. Regions can be formed. The present invention actively utilizes such an impurity region. By forming such an impurity region, a high electric field generated in the vicinity of the drain region can be reduced, hot carriers can be prevented from being generated, and deterioration of the TFT can be prevented.

As described above, the island-shaped semiconductor layer 1003
A first impurity region serving as a source or drain region, and a second forming an LDD region not overlapping with the gate electrode.
Region (A), LDD partially overlapping with gate electrode
A second impurity region (B) forming a region and a channel formation region 1023 are formed. After that, as shown in FIG. 1D, an interlayer insulating film 1020 may be formed as necessary, and a wiring 1021 for forming a contact with a source or drain region may be formed.

[0037]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, the pixel TFT and the storage capacitor of the pixel portion and the TFT of the driving circuit provided around the pixel portion
Will be described in detail according to the steps.

In FIG. 3A, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass, a quartz substrate, or the like is used as the substrate 101.
In the case of using a glass substrate, the glass strain point should be 10
The heat treatment may be performed in advance at a temperature lower by about 20 ° C. Then, on the surface of the substrate 101 on which the TFT is formed,
In order to prevent impurity diffusion from the substrate 101, a base film 102 including an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. For example, SiH ₄ in plasma CVD, NH _3, the N ₂ O silicon oxynitride film 102a made from 10 to 200 nm (preferably 50 to 100 nm), as well oxynitride made from SiH _4, N ₂ O The hydrogenated silicon film 102b is
The layer is formed to a thickness of 0 nm (preferably 100 to 150 nm). Here, the base film 102 has a two-layer structure; however, the base film 102 may be a single-layer film of the insulating film or a stack of two or more layers.

The silicon oxynitride film is formed by using a parallel plate type plasma CVD method. Silicon oxynitride film 10
2a is SiH ₄ at 10 SCCM, NH ₃ at 100 SCCM, N ₂
O was introduced into the reaction chamber at 20 SCCM, and the substrate temperature was 325.
° C, a reaction pressure of 40 Pa, a discharge power density of 0.41 W / cm ² , and a discharge frequency of 60 MHz. On the other hand, the hydrogenated silicon oxynitride film 102b is made of ₅ SCCM of SiH ₄ and 120 SCC of N ₂ O.
M and H ₂ were introduced into the reaction chamber at 125 SCCM, and the substrate temperature was 4
00 ° C, reaction pressure 20 Pa, discharge power density 0.41 W / c
m ² , and the discharge frequency was 60 MHz. These films can be continuously formed only by changing the substrate temperature and switching the reaction gas.

The silicon oxynitride film 102a manufactured in this manner has a density of 9.28 × 10 ²² / cm ³ , 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and ammonium fluoride (NH ₄ HF ₂ ). 20% of a mixed solution (trade name: LAL500, manufactured by Stella Chemifa) containing 15.4% of NH ₄ F).
The etching rate at a temperature of ° C. is as low as about 63 nm / min, and the film is dense and hard. Use of such a film as a base film is effective in preventing an alkali metal element from a glass substrate from diffusing into a semiconductor layer formed thereover.

Next, 25 to 80 nm (preferably 30 to 6 nm)
Semiconductor layer 103a having a thickness of 0 nm) and having an amorphous structure.
Is formed by a method such as a plasma CVD method or a sputtering method. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. In the case where an amorphous silicon film is formed by a plasma CVD method, both the base film 102 and the amorphous semiconductor layer 103a can be formed continuously. For example, as described above, after the silicon oxynitride film 102a and the silicon oxynitride hydride film 102b are continuously formed by the plasma CVD method, the reaction gas is changed from SiH ₄ , N ₂ O, and H ₂ to SiH ₄ and H _2.
Alternatively, by switching to only SiH _4, continuous formation can be performed without once exposing it to the atmosphere. As a result, contamination of the surface of the hydrogenated silicon oxynitride film 102b can be prevented, and variation in characteristics of a TFT to be manufactured and fluctuation in threshold voltage can be reduced.

Then, a crystallization step is performed to form a crystalline semiconductor layer 103b from the amorphous semiconductor layer 103a. Laser annealing, thermal annealing (solid phase growth), or rapid thermal annealing (RTA)
Law) can be applied. When a glass substrate or a plastic substrate having low heat resistance as described above is used, it is particularly preferable to apply a laser annealing method. RT
In the method A, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. Alternatively, according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652, the crystalline semiconductor layer 10 is formed by a crystallization method using a catalytic element.
3b can also be formed. First, in the crystallization process,
It is preferable to release hydrogen contained in the amorphous semiconductor layer, and heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen contained to 5 atomic% or less. It is good because it can be prevented.

In the step of forming an amorphous silicon film by plasma CVD, SiH ₄ and argon (Ar) are used as reaction gases, and the substrate temperature during film formation is 400 to 450 ° C.
When formed, the hydrogen concentration in the amorphous silicon film can be reduced to 5 atomic% or less. In such a case, heat treatment for releasing hydrogen becomes unnecessary.

When crystallization is performed by laser annealing, a pulse oscillation type or continuous emission type excimer laser or argon laser is used as the light source. When a pulse oscillation type excimer laser is used, laser annealing is performed by processing the laser beam into a linear shape. Laser annealing conditions are appropriately selected by the practitioner, for example,
The laser pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 500 mJ / cm ² (typically 300
４００400 mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 80 to 98%. In this way, as shown in FIG.
3b can be obtained.

Then, a first layer is formed on the crystalline semiconductor layer 103b.
Lithography using a photomask (PM1)
A resist pattern is formed using the
The crystalline semiconductor layer is divided into islands by etching, and FIG.
Forming island-shaped semiconductor layers 104 to 108 as shown in FIG.
I do. CF for dry etching of crystalline silicon film _Four
And O_TwoIs used.

In order to control the threshold voltage (Vth) of the TFT, an impurity element imparting p-type is added to such an island-like semiconductor layer at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . The concentration may be added to the entire surface of the island-shaped semiconductor layer. The impurity element imparting p-type to the semiconductor includes boron (B),
Elements of Group 13 of the periodic table, such as aluminum (Al) and gallium (Ga), are known. As the method, an ion implantation method or an ion doping method (or an ion shower doping method) can be used, but the ion doping method is suitable for treating a large-area substrate. In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is added. The implantation of such an impurity element is not always necessary and may be omitted. However, it is a method preferably used for keeping the threshold voltage of the n-channel TFT within a predetermined range.

The gate insulating film 109 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, 120
It is formed from a silicon oxynitride film with a thickness of nm. Also, S
A silicon oxynitride film formed by adding O ₂ to iH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. In addition, SiH ₄
A silicon oxynitride film formed from N ₂ O and H ₂ is preferable because the density of interface defects with the gate insulating film can be reduced.
Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TE
Mix OS (Tetraethyl Ortho Silicate) with O ₂ ,
It can be formed by discharging at a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, as shown in FIG. 3D, a heat-resistant conductive layer 111 for forming a gate electrode on the gate insulating film 109 of the first shape has a thickness of 200 to 400 nm (preferably 250 to 350 nm). It is formed with a thickness. The heat-resistant conductive layer may be formed as a single layer, or may have a laminated structure including a plurality of layers such as two layers or three layers as necessary.
The heat-resistant conductive layer referred to in this specification includes Ta, Ti, W, and Mo.
And alloys containing the above elements or alloy films combining the above elements are included. These heat-resistant conductive layers are formed by a sputtering method or a CVD method, and it is preferable to reduce the concentration of impurities contained in order to reduce the resistance.
It is good to be 0 ppm or less. In this embodiment, the W film is 300
It is formed with a thickness of nm. The W film may be formed by sputtering using W as a target, or tungsten hexafluoride (W
It can also be formed by a thermal CVD method using F ₆ ). In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, when the sputtering method is used, the purity is 99.
By using a 9999% W target and forming the W film with sufficient care so as not to mix impurities from the gas phase during film formation, a resistivity of 9 to 20 μΩcm can be realized.

On the other hand, when a Ta film is used for the heat-resistant conductive layer 111, it can be similarly formed by a sputtering method. The Ta film uses Ar as a sputtering gas. Also, if an appropriate amount of Xe or Kr is added to the gas during sputtering,
The internal stress of the film to be formed can be relaxed to prevent the film from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode.
The resistivity of the film was about 180 μΩcm, and was not suitable for use as a gate electrode. Since the TaN film has a crystal structure close to the α-phase, if a TaN film is formed under the Ta film, an α-phase Ta film can be easily obtained. Although not shown, phosphorus (P) having a thickness of about 2 to 20 nm is formed under the heat-resistant conductive layer 111.
It is effective to form a silicon film doped with a. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the heat-resistant conductive layer 111 diffuses into the gate insulating film 109 of the first shape. Can be prevented. In any case, the heat-resistant conductive layer 111 has a resistivity of 10 to 50 μΩ.
It is preferable to set it in the range of cm.

Next, using the second photomask (PM2), resist masks 112 to 117 are formed by photolithography. Then, a first etching process is performed. In this embodiment, an ICP etching apparatus is used, and Cl ₂ and CF ₄ are used as etching gases.
Plasma is formed by applying RF (13.56 MHz) power of 3.2 W / cm ² at a pressure of 1 Pa. RF (13.56 MHz) power of 224 mW / cm ² is also applied to the substrate side (sample stage), whereby a substantially negative self-bias voltage is applied. Under these conditions, the etching rate of the W film is about 100 nm / m
in. The first etching process estimates the time when the W film is just etched based on this etching rate,
The time obtained by increasing the etching time by 20% was defined as the etching time.

The conductive layers 118 to 123 having the first tapered shape are formed by the first etching process. As shown in FIG. 2A, the angle of the tapered portion is 15 to 30.
° is formed. In order to perform etching without leaving a residue, over-etching is performed to increase the etching time at a rate of about 10 to 20%. Since the selectivity of the silicon oxynitride film (the first shape gate insulating film 109) to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film Etch about 20-50nm first
A second shape gate insulating film 134 having a tapered shape is formed near the end of the conductive layer having the tapered shape.

Then, a first doping process is performed to add an impurity element of one conductivity type to the island-shaped semiconductor layer. Here, a step of adding an n-type impurity element is performed. First
The masks 112 to 117 on which the conductive layers having the shapes shown in FIGS.
Using 123 as a mask, an impurity element imparting n-type in a self-aligned manner is added by an ion doping method. In order to add the impurity element imparting n-type through the tapered portion at the end of the gate electrode and the gate insulating film so as to reach the semiconductor layer located thereunder, the dose is set to 1 × 10 ^{13 to} 5 × 1.
This is performed at 0 ¹⁴ atoms / cm ² and an acceleration voltage of 80 to 160 keV. As an impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically, phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. By such an ion doping method, an impurity element imparting n-type is added to the first impurity regions 124 to 128 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atomic / cm ³ , and the first impurity regions 124 to 128 are formed below the tapered portion. The second impurity region (A) to be formed is not necessarily uniform in the region, but is 1 × 10 ¹⁷ to 1 × 10 ²⁰ atomic / cm ^3.
Is added within the concentration range of n.

In this step, in the second impurity regions (A) 129 to 133, the change in the concentration of the impurity element imparting n-type contained in at least the portion overlapping the first shape conductive layers 118 to 123 is as follows: This reflects the change in the thickness of the tapered portion. That is, the second impurity region (A) 129
The concentration of phosphorus (P) added to the layers 133 to 133 gradually decreases from the end of the conductive layer toward the inside in a region overlapping the conductive layer of the first shape. This is because the concentration of phosphorus (P) reaching the semiconductor layer changes depending on the difference in the thickness of the tapered portion.
As shown in 2).

Next, a second etching process is performed as shown in FIG. The etching process is similarly performed by an ICP etching apparatus, and CF ₄ and Cl ₂ are used as etching gases.
RF power 3.2W / cm ² (13.56MHz)
Etching is performed at a bias power of 45 mW / cm ² (13.56 MHz) and a pressure of 1.0 Pa. Conductive layers 140 to 145 having the second shape formed under these conditions are formed. A tapered portion is formed at the end, and the tapered shape gradually increases inward from the end. As compared with the first etching process, the ratio of the isotropic etching is increased by the lower bias power applied to the substrate side, and the angle of the tapered portion is 30 to 60 °. Further, the surface of the second shape gate insulating film 134 is etched by about 40 nm,
A third shape gate insulating film 170 is newly formed.

Then, an impurity element for imparting n-type is doped under a condition of a high acceleration voltage with a lower dose than in the first doping process. For example, when the accelerating voltage is 70 to 120
keV, at a dose of 1 × 10 ¹³ atoms / cm ² ,
The impurity concentration in a region overlapping with the conductive layers 140 to 145 having the second shape is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ . Thus, second impurity regions (B) 146 to 150 are formed.

In the island-shaped semiconductor layers 104 and 106 forming the p-channel type TFT, impurity regions 156 and 157 having a conductivity type opposite to one conductivity type are formed. Also in this case, an impurity element imparting p-type is added using the second shape conductive layers 140 and 142 as a mask to form an impurity region in a self-aligned manner. At this time, resist masks 151 to 153 are formed using the third photomask (PM3) to cover the entire surface of the island-shaped semiconductor layers 105, 107, and 108 forming the n-channel TFT. The impurity regions 156 and 157 formed here are formed by an ion doping method using diborane (B ₂ H ₆ ). The concentration of the impurity element imparting p-type in impurity regions 156 and 157 is 2 × 10 ²⁰ to 2 × 10
It should be ²¹ atoms / cm ³ .

However, the impurity regions 156, 1
Numeral 57 designates 3 containing an impurity element imparting n-type.
It can be divided into two areas. The third impurity regions 156a and 157a are 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm.
The fourth impurity regions (A) 156b and 157b include an impurity element that imparts n-type at a concentration of ^{3 and have} a concentration of 1 × 10 ¹⁷ to 1 ×
The fourth impurity regions (B) 156c and 157c have an impurity element imparting n-type at a concentration of 10 ²⁰ atoms / cm ³ ,
Contains an impurity element imparting n-type at a concentration of × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . However, the concentration of the impurity element imparting p-type in these impurity regions 156b, 156c, 157b, and 157c is set to 1 × 10 ¹⁹ atoms / cm ³ or more, and in the third impurity regions 156a and 157a, By making the concentration of the impurity element giving the mold 1.5 to 3 times, there is no problem because the third impurity region functions as the source region and the drain region of the p-channel TFT. . Part of the fourth impurity regions (B) 156c and 157c
Is formed so as to partially overlap with the conductive layer 140 or 142 having a tapered shape.

Thereafter, as shown in FIG. 5A, a first interlayer insulating film 158 is formed on the gate electrode and the gate insulating film.
To form The first interlayer insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first
Is formed from an inorganic insulating material. The thickness of the first interlayer insulating film 158 is 100 to 200 nm. Here, when a silicon oxide film is used, TEOS and O ₂ are mixed by a plasma CVD method, and a reaction pressure of 40 P
a, a substrate temperature of 300 to 400 ° C., and a high frequency (13.5
6 MHz) It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . When a silicon oxynitride film is used, SiH ₄ , N ₂ O, NH ₃
A silicon oxynitride film made from SiH ₄ ,
N ₂ O may be formed by a silicon oxynitride film made from. The production conditions in this case are a reaction pressure of 20 to 200 Pa,
The substrate can be formed at a substrate temperature of 300 to 400 ° C. and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² .
Alternatively, a hydrogenated silicon oxynitride film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method.

Then, a step of activating the n-type or p-type impurity element added at each concentration is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less,
Preferably in a nitrogen atmosphere of 0.1 ppm or less 400 ~
The heat treatment is performed at 700 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours.
When a plastic substrate having a low heat-resistant temperature is used as the substrate 101, a laser annealing method is preferably applied.

Following the activation step, the atmosphere gas is changed
And in an atmosphere containing 3 to 100% hydrogen,
Heat treatment at 450 ° C. for 1 to 12 hours to form an island-shaped semiconductor layer
Is carried out. This process was thermally excited
10 in the island-like semiconductor layer due to hydrogen¹⁶-10¹⁸/cm^ThreeNo da
This is a step of terminating the ringing bond. Other hydrogenation
As a means, plasma hydrogenation (excited by plasma
Using hydrogen). In any case, the island
Defect density in the semiconductor layers 104 to 108 is 10 ¹⁶/cm^ThreeLess than
It is preferable to set the hydrogen content to 0.01 to
What is necessary is just to give about 0.1 atomic%.

As described above, the surface can be satisfactorily planarized by forming the second interlayer insulating film from the organic insulating material. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. But,
Since it has moisture absorption and is not suitable as a protective film, it is preferable to use it in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 158 as in this embodiment.

Thereafter, using a fourth photomask (PM4), a resist mask having a predetermined pattern is formed, and a contact hole is formed in each island-like semiconductor layer and reaches an impurity region serving as a source region or a drain region. I do. The contact hole is formed by a dry etching method. In this case, the second interlayer insulating film 159 made of organic resin material using a mixed gas of CF _4, O _2, He as an etching gas is first etched, then followed by the first etching gas as CF _4, O ₂ Is etched. Further, in order to increase the selectivity with respect to the island-shaped semiconductor layer, a contact hole can be formed by switching the etching gas to CHF ₃ and etching the third shape gate insulating film 170.

Then, a conductive metal film is formed by a sputtering method or a vacuum deposition method, a resist mask pattern is formed by a fifth photomask (PM5), and the source lines 160 to 164 and the drain lines 165 to 168 are etched.
To form The pixel electrode 169 is formed together with the drain line. The pixel electrode 171 represents a pixel electrode belonging to an adjacent pixel. Although not shown, in this embodiment, this wiring is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with an impurity region forming a source or drain region of the island-shaped semiconductor layer, and forming the Ti film. Aluminum (Al) is formed in a thickness of 300 to 400 nm on top of this (FIG. 5).
(C), and a transparent conductive film was formed thereon with a thickness of 80 to 120 nm (shown by 160b to 169b in FIG. 5C). Indium oxide zinc oxide alloy (In ₂ O _3-
ZnO) and zinc oxide (ZnO) are also suitable materials. Further, zinc oxide (ZnO: Ga) to which gallium (Ga) is added in order to increase the transmittance and conductivity of visible light can be preferably used. .

In this way, a substrate having a TFT of a driving circuit and a pixel TFT of a pixel portion can be completed on the same substrate by using five photomasks. The driving circuit includes a first p-channel TFT 200, a first n-channel TFT 201, a second p-channel TFT 202, and a second p-channel TFT 202.
N-channel type TFT 203, and the pixel portion has a pixel TFT 2
04, a storage capacitor 205 is formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

First p-channel TFT 20 of drive circuit
0, a conductive layer having a second tapered shape has a function as a gate electrode 220, and a third impurity region 207a functioning as a channel formation region 206, a source region or a drain region in the island-shaped semiconductor layer 104; Fourth impurity region (A) 207b forming an LDD region not overlapping gate electrode 220, and fourth impurity region (B) 207c forming an LDD region partially overlapping gate electrode 220
It has a structure having.

In the first n-channel TFT 201, a conductive layer having a second tapered shape has a function as a gate electrode 221, and the island-shaped semiconductor layer 105 serves as a channel forming region 208, a source region or a drain region. A first impurity region 209a that functions and a second impurity region (A) that forms an LDD region that does not overlap with the gate electrode 221.
209b, and a second impurity region (B) 209c which forms an LDD region partly overlapping the gate electrode 221. For a channel length of 2 to 7 μm, the second
The length of the portion where the impurity region (B) 209c overlaps with the gate electrode 221 is 0.1 to 0.3 μm. The length of Lov is controlled from the thickness of the gate electrode 221 and the angle of the tapered portion. Such an LD in an n-channel TFT
By forming the D region, a high electric field generated near the drain region is relaxed, and the generation of hot carriers is prevented.
Deterioration of the TFT can be prevented.

The second p-channel TFT 20 of the driving circuit
Similarly, the island-shaped semiconductor layer 106 has a second tapered conductive layer serving as the gate electrode 222.
A channel formation region 210, a third impurity region 211 a functioning as a source region or a drain region, a fourth impurity region (A) 211 b forming an LDD region which does not overlap with the gate electrode 222, part of which overlaps with the gate electrode 222. Fourth impurity region (B) 21 forming LDD region
1c.

The second n-channel TFT 20 of the driving circuit
3, a conductive layer having a second tapered shape has a function as a gate electrode 223, and a channel formation region 212, a first impurity region 213 a which functions as a source region or a drain region in the island-shaped semiconductor layer 107, Second impurity region (A) 213b that forms an LDD region that does not overlap with gate electrode 223, and second impurity region (B) 213c that forms an LDD region that partially overlaps with gate electrode 223
It has a structure having. Second n-channel TFT
Similarly to 201, the length of the portion where the second impurity region (B) 213c overlaps with the gate electrode 223 is 0.1 to 0.3 μm.
And

The drive circuit is formed by a logic circuit such as a shift register circuit or a buffer circuit, or a sampling circuit formed by analog switches. In FIG. 5B, the TFTs forming them have a single-gate structure in which one gate electrode is provided between a pair of sources and drains. A gate structure may be used.

In the pixel TFT 204, a conductive layer having a second tapered shape has a function as a gate electrode 224, and a channel forming region 214 a is formed in the island-shaped semiconductor layer 108.
214b, first impurity regions 215a and 217 functioning as a source region or a drain region, and a gate electrode 22
4, the second impurity region (A) 215b forming an LDD region that does not overlap with the gate electrode 224
The structure has a second impurity region (B) 215c that forms the D region. Second impurity region (B) 213
The length of the portion where c overlaps with the gate electrode 224 is 0.1 to
0.3 μm. In addition, a semiconductor extending from the first impurity region 217 and having a second impurity region (A) 219b, a second impurity region (B) 219c, and a region 218 to which an impurity element which determines a conductivity type is not added is provided. Layer and third
A storage capacitor is formed from an insulating layer formed of the same layer as the gate insulating film having the shape described above and a capacitor wiring 225 formed from the second tapered conductive layer.

FIG. 11 is a top view showing almost one pixel of the pixel portion. The cross section AA ′ shown in the drawing corresponds to the cross-sectional view of the pixel portion shown in FIG. The gate electrode 224 of the pixel TFT 204 intersects the island-shaped semiconductor layer 108 thereunder via a gate insulating film (not shown), and extends over a plurality of island-shaped semiconductor layers to serve also as a gate wiring. Although not shown, FIG.
The source region, the drain region, and the LDD region described in (B) are formed. 230 is a source wiring 164
231 is a contact portion between the pixel electrode 169 and the drain region 217. The storage capacitor 205 is formed in a region where the semiconductor layer extending from the drain region 217 of the pixel TFT 204 and the capacitor wiring 225 overlap with a gate insulating film interposed therebetween. In this structure, an impurity element for controlling valence electrons is not added to the semiconductor layer 218.

The above configuration enables the structure of the TFT constituting each circuit to be optimized according to the specifications required by the pixel TFT and the driving circuit, thereby improving the operation performance and reliability of the semiconductor device. . Further, the activation of the LDD region, the source region, and the drain region is facilitated by forming the gate electrode with a conductive material having heat resistance. Further, when forming the LDD region overlapping with the gate electrode via the gate insulating film, the LDD region is formed by giving a concentration gradient to the impurity element added for the purpose of controlling the conductivity type, particularly in the vicinity of the drain region. Can be expected to increase the electric field relaxation effect.

In the case of an active matrix type liquid crystal display device, the first p-channel TFT 200 and the first n-channel TFT 201 are used for forming a shift register circuit, a buffer circuit, a level shifter circuit, etc. which emphasize high-speed operation. . FIG. 5B illustrates these circuits as logic circuit units. First n-channel type TFT2
The second impurity region (B) 209c of No. 01 has a structure that emphasizes hot carrier measures. Further, in order to increase the withstand voltage and stabilize the operation, as shown in FIG.
T280 and the first n-channel TFT 281 may be used. This TFT has a structure in which two transistors
It has a double gate structure provided with two gate electrodes, and such a TFT can be similarly manufactured using the steps of this embodiment. In the first p-channel TFT 280, channel formation regions 236 a and 236 b and a third impurity region 238 functioning as a source or drain region are formed in the island-shaped semiconductor layer.
a, 239a, 240a, a fourth impurity region (A) 238b, 239b, 240b serving as an LDD region and a fourth impurity region (B) 238c, 239c, 240c, which partially overlaps the gate electrode 237 and serves as an LDD region. It has a structure having. In the first n-channel TFT 281, channel formation regions 241 a and 241 are formed in the island-shaped semiconductor layer.
b, first impurity regions 243a, 244a, 245a functioning as source or drain regions and second impurity regions (A) 243b, 244b, 24 serving as LDD regions
5b and the second impurity regions (B) 243c, 244c, and 24 which partly overlap with the gate electrode 242 and serve as LDD regions.
5c. The channel length is 3 to 7 μm, the LDD region overlapping with the gate electrode is Lov, and the length in the channel length direction is 0.1 to 0.3 μm.

Further, a second p-channel TFT 202 and a second n-channel TFT 203 having the same configuration can be applied to a sampling circuit composed of analog switches. Since the sampling circuit emphasizes measures against hot carriers and low off-current operation, as shown in FIG. 9B, the TFT of this circuit is replaced with a second p-channel type TF.
T282 and the second n-channel TFT 283 may be used. The second p-channel TFT 282 has a triple gate structure in which three gate electrodes are provided between a pair of source and drain, and such a TFT can be manufactured in the same manner by using the steps of this embodiment. Second p-channel type T
The FT 282 includes a channel forming region 24 in the island-shaped semiconductor layer.
6a, 246b, 246c Third impurity regions 249a, 250a,
51a, 252a, fourth impurity regions (A) 249b, 250b, 251b, 252b serving as LDD regions and fourth impurity regions (B) 249c, 250c, 251c which partially overlap the gate electrode 247 and serve as LDD regions. 25
2c. Second n-channel type T
The FT 283 includes a channel forming region 25 in the island-shaped semiconductor layer.
3a, 253b, first impurity regions 255a, 256a, 257a functioning as source or drain regions and second impurity regions (A) 255b,
56b, 257b and the second impurity region (B) 255c, which partly overlaps with the gate electrode 254 and becomes an LDD region.
56c and 257c. Channel length is 3-7μ
m, the LDD region overlapping the gate electrode is Lov, and the length in the channel length direction is 0.1 to 0.3 μm.

As described above, whether the configuration of the gate electrode of the TFT is a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided between a pair of source and drain is determined depending on the characteristics of the circuit. It is only necessary for the person to choose appropriately. Then, by using the active matrix substrate completed in this embodiment, a reflective liquid crystal display device can be manufactured.

[Embodiment 2] Embodiment 1 shows an example in which a heat-resistant conductive material such as W or Ta is used as a material of a gate electrode.
The reason for using such a material is that it is necessary to activate the impurity element added to the semiconductor layer by thermal annealing at 400 to 700 ° C. for the purpose of controlling the conductivity type after forming the gate electrode. This is because the gate electrode needs to have heat resistance. However, such a heat-resistant conductive material has a sheet resistance of about 10Ω,
It is not necessarily suitable for a display device having a screen size of 4 inches or more. If the gate line connected to the gate electrode is formed of the same material, the wiring length on the substrate is inevitably increased, and the problem of wiring delay due to the influence of wiring resistance cannot be ignored.

For example, when the pixel density is VGA, 480
Gate lines and 640 source lines are formed, and XG
In the case of A, 768 gate wirings and 1024 source wirings are formed. When the screen size of the display area is 13 inches, the length of the diagonal line is 340 mm, and
In the case of the 8-inch class, it is 460 mm. In this embodiment, as a means for realizing such a liquid crystal display device, a method for forming a gate wiring with a low-resistance conductive material such as Al or copper (Cu) will be described with reference to FIGS.

First, FIG. 3A to FIG.
The step shown in FIG. 4C is performed. Then, for the purpose of controlling the conductivity type, a step of activating the impurity element added to each of the island-shaped semiconductor layers is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 50 ppm.
0 to 600 ° C., and in this embodiment, 500 ° C.
For 4 hours.

In this heat treatment, conductive layers (C) 172a to 172f are formed with a thickness of 5 to 80 nm from the surface of conductive layers 140 to 145 having the second tapered shape.
For example, when the conductive layer having the second tapered shape is W, tungsten nitride is formed, and when the conductive layer is Ta, tantalum nitride is formed. Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-shaped semiconductor layer.
In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed (FIG. 6A).

After the activation and hydrogenation, the gate lines are formed of a low-resistance conductive material. Low resistance conductive material is Al or C
The main component is u, and a gate line is formed from a low-resistance conductive layer formed of such a material. For example,
An Al film containing 0.1 to 2% by weight of Ti is formed on the entire surface as a low-resistance conductive layer (not shown). The low resistance conductive layer is 200
It is formed to a thickness of 400 nm (preferably 250 to 350 nm). Then, a predetermined resist pattern is formed and an etching process is performed to form gate lines 173 and 174. At this time, a capacitor line 175 connected to a storage capacitor provided in the pixel portion is formed using the same material. In the case where the low-resistance conductive layer is made of a material containing Al as a main component, the gate line can be formed by wet etching with a phosphoric acid-based etching solution while maintaining selectivity with the base. The first interlayer insulating film 176 is formed in the same manner as in Embodiment 1 (FIG. 6B).

Then, the second interlayer insulating film 159 made of an organic insulating material and the source line 160 are formed in the same manner as in the first embodiment.
To 164, drain lines 165 to 168, pixel electrode 16
9 and 171 can be formed to complete the active matrix substrate. FIGS. 7A and 7B are top views in this state. FIG. 7A is a cross-sectional view taken along the line BB ′ of FIG.
The cross section taken along the line CC 'in FIG. 5B is taken along the lines BB' and C-
C '. 7A and 7B, the gate insulating film, the first interlayer insulating film, and the second interlayer insulating film are omitted, but the island-shaped semiconductor layers 104, 105, and 108 are not shown. Source lines 160, 161, 164 and drain lines 165, 166,
And the pixel electrode 169 are connected via a contact hole. FIG. 7A is a sectional view taken along the line DD ′ of FIG.
FIGS. 8A and 8B show cross sections EE ′ of FIG. The gate line 173 is connected to the gate electrode 220, and the gate line 174 is connected to the gate electrode 225 and the island-shaped semiconductor layer 104.
The gate electrode and the low-resistance conductive layer are formed so as to overlap each other outside of the contact hole 108 and are electrically connected to each other without interposing the contact hole. By forming the gate line with a low-resistance conductive material in this manner, the wiring resistance can be sufficiently reduced. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inch class or more.

[Embodiment 3] The active matrix substrate manufactured in Embodiment 1 can be applied to a reflection type display device as it is. On the other hand, in the case of a transmissive liquid crystal display device, a pixel electrode provided for each pixel in the pixel portion may be formed of a transparent electrode. Embodiment 1 In this embodiment, a method for manufacturing an active matrix substrate corresponding to a transmission type liquid crystal display device will be described with reference to FIGS.
Explanation will be made using 0.

The active matrix substrate is manufactured in the same manner as in the first embodiment. In FIG. 10A, a conductive metal film is formed for a source wiring and a drain wiring by a sputtering method or a vacuum evaporation method. This configuration is illustrated in FIG. 10 using the drain line 256 as an example.
To explain in detail in (B), the Ti film 256a is
A contact is formed with a semiconductor film forming a source or drain region of an island-shaped semiconductor layer with a thickness of 50 nm. The Al film 256b is overlapped with the Ti film 256a by 3
Formed to a thickness of 100 to 400 nm, and further, a Ti film 256 c
Alternatively, a three-layer structure is formed by forming a titanium nitride (TiN) film with a thickness of 100 to 200 nm. After that, a transparent conductive film is formed over the entire surface, and a pixel electrode 257 is formed by patterning and etching using a photomask.
The pixel electrode 257 is formed on the second interlayer insulating film made of an organic resin material, and the pixel electrode 257 does not pass through the contact hole.
A portion overlapping the drain line 256 of the FT 204 is provided to form an electrical connection.

In FIG. 10C, first, a transparent conductive film is formed on the second interlayer insulating film, a patterning process and an etching process are performed to form a pixel electrode 258, and then the drain line 259 is connected to the pixel electrode 258. This is an example in which a connection portion is formed without passing through a contact hole. The drain line 259 is
As shown in FIG. 10D, the Ti film 259a is
A contact is formed with a semiconductor film forming a source or drain region of an island-shaped semiconductor layer, and an Al film 259b is formed on the Ti film 259a so as to have a thickness of 300 nm.
It is formed and provided with a thickness of 400 nm. With this configuration,
The pixel electrode 258 contacts only the Ti film 259a forming the drain wiring 259. As a result, it is possible to reliably prevent the transparent conductive film material from directly reacting with Al.

The material of the transparent conductive film is indium oxide (I
n ₂ O ₃ ) and indium tin oxide alloy (In ₂ O ₃ —S
nO ₂ ; ITO) or the like can be formed by a sputtering method, a vacuum evaporation method, or the like. The etching of such a material is performed using a hydrochloric acid-based solution. However, in particular, since etching of ITO easily generates residues, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used in order to improve the etching processability. Since the indium oxide zinc oxide alloy has excellent surface smoothness and excellent thermal stability with respect to ITO, the aluminum film 25 is formed on the end face of the drain wiring 256 in the configuration shown in FIGS.
6b can be prevented from contacting the pixel electrode 257 and causing a corrosion reaction. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to increase the transmittance and conductivity of visible light.
Etc. can be used.

In the first embodiment, an active matrix substrate on which a reflection type liquid crystal display device can be manufactured is manufactured using five photomasks. An active matrix substrate corresponding to the device can be completed. In this embodiment, the same steps as those in the first embodiment have been described. However, such a configuration can be applied to the active matrix substrate described in the second embodiment.

[Embodiment 4] In this embodiment, another manufacturing method of the crystalline semiconductor layer for forming the active layer of the TFT of the active matrix substrate shown in Embodiments 1 to 3 will be described. The crystalline semiconductor layer is formed by crystallizing an amorphous semiconductor layer by a thermal annealing method, a laser annealing method, an RTA method, or the like. In addition, a catalytic element disclosed in JP-A-7-130652 is used. A crystallization method can also be applied. An example in that case will be described with reference to FIG.

As shown in FIG. 12A, a base film 1102a and a base film 1102a are formed on a glass substrate 1101 in the same manner as in the first embodiment.
1102b, two semiconductor layers 1103 having an amorphous structure
It is formed with a thickness of 5 to 80 nm. The amorphous semiconductor layer includes an amorphous silicon (a-Si) film, an amorphous silicon germanium (a-SiGe) film, and an amorphous silicon carbide (a-Si).
C) film, amorphous silicon tin (a-SiSn) film and the like can be applied. These amorphous semiconductor layers contain 0.1% of hydrogen.
It may be formed so as to contain about 40 atomic%. For example, an amorphous silicon film is formed with a thickness of 55 nm. Then, a layer 1104 containing a catalyst element is formed by a spin coating method in which an aqueous solution containing a catalyst element of 10 ppm by weight is applied by rotating the substrate with a spinner. The catalytic elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), and lead (P
b), cobalt (Co), platinum (Pt), copper (Cu),
Gold (Au) or the like. Layer 11 containing this catalytic element
In 04, the catalyst element layer may be formed to a thickness of 1 to 5 nm by a printing method, a spray method, a bar coater method, a sputtering method or a vacuum evaporation method other than the spin coating method.

Then, in the crystallization step shown in FIG. 12B, first, a heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atomic% or less. If the hydrogen content of the amorphous silicon film has this value from the beginning after film formation, this heat treatment is not always necessary. Then, thermal annealing is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours using a furnace annealing furnace. Through the above steps, a crystalline semiconductor layer 1105 made of a crystalline silicon film can be obtained (FIG. 12).
(C)). However, when the crystalline semiconductor layer 1105 formed by this thermal annealing is macroscopically observed with an optical microscope, an amorphous region may be locally observed to remain locally. Similarly, in Raman spectroscopy, an amorphous component having a broad peak at 480 cm ^-1 is observed. Therefore, increasing the crystallinity by treating the crystalline semiconductor layer 1105 by the laser annealing method described in Embodiment 1 after the thermal annealing can be applied as an effective means.

FIG. 17 shows an embodiment of a crystallization method similarly using a catalytic element, in which a layer containing a catalytic element is formed by sputtering. First, in the same manner as in the first embodiment, base films 1202a and 1202 are formed on a glass substrate 1201.
2b, the semiconductor layer 1203 having an amorphous structure
It is formed with a thickness of 0 nm. Then, an oxide film (not shown) of about 0.5 to 5 nm is formed on the surface of the semiconductor layer 1203 having an amorphous structure. For the oxide film having such a thickness, a corresponding film may be positively formed by a plasma CVD method, a sputtering method, or the like. The surface of the semiconductor layer 1203 having a crystalline structure may be exposed, or the semiconductor layer 1 having an amorphous structure may be exposed to a solution containing aqueous hydrogen peroxide (H ₂ O ₂ ).
203 may be formed by exposing the surface. Alternatively, ozone is generated by irradiating ultraviolet light in an atmosphere containing oxygen,
Semiconductor layer 12 having an amorphous structure in the ozone atmosphere
03 can also be formed.

Thus, a layer 1204 containing the catalyst element is formed by a sputtering method on the semiconductor layer 1203 having an amorphous structure having a thin oxide film on the surface. The thickness of this layer is not limited, but may be about 10 to 100 nm. For example, with Ni as a target, Ni
Forming a film is an effective method. In the sputtering method, a part of the high-energy particles composed of the catalyst element accelerated by an electric field also fly to the substrate side, and an oxide formed near the surface of the semiconductor layer 1203 having an amorphous structure or on the surface of the semiconductor layer. Driven into the film. The ratio varies depending on the plasma generation conditions and the bias state of the substrate, but preferably, the amount of the catalytic element implanted into the vicinity of the surface of the semiconductor layer 1203 having an amorphous structure or into the oxide film is reduced to 1%.
It is preferable that the density be about 10 ¹¹ to 1 10 ¹⁴ atoms / cm ² .

After that, the layer 1204 containing the catalyst element is selectively removed. For example, when this layer is formed of a Ni film, it can be removed with a solution such as nitric acid, or can be treated with an aqueous solution containing hydrofluoric acid to obtain a Ni film.
The oxide film formed over the film and the semiconductor layer 1203 having an amorphous structure can be removed at the same time. In any case, the amount of the catalyst element near the surface of the semiconductor layer 1203 having an amorphous structure is set to be about 1 × 10 ¹¹ to 1 × 10 ¹⁴ atoms / cm ² . Then, as shown in FIG.
The crystallization step by thermal annealing is performed in the same manner as (B), and a crystalline semiconductor layer 1205 can be obtained (FIG. 1).
7 (C)).

The crystalline half prepared in FIG. 12 or FIG.
From the conductor layers 1105 and 1205 to the island-shaped semiconductor layers 104-1
08, the active mask is formed in the same manner as in the first embodiment.
A trix substrate can be completed. But the crystal
Catalyst element that promotes silicon crystallization in the crystallization process
Is used, a very small amount (1 × 10 ¹⁷
~ 1 × 10¹⁹atoms / cm^ThreeCatalyst element) remains.
Of course, TFT can be completed even in such a state.
Function, but removes the remaining catalytic elements at least in channel form
It was more preferable to remove it from the growing area. This catalyst source
One of the means to remove element is getterin by phosphorus (P)
There is a means to utilize the squeezing action.

The gettering process using phosphorus (P) for this purpose can be performed simultaneously in the activation step described with reference to FIG. This will be described with reference to FIG. The concentration of phosphorus (P) necessary for gettering may be substantially the same as the impurity concentration of the high-concentration n-type impurity region. The thermal annealing in the activation step causes the catalyst to be removed from the channel formation regions of the n-channel TFT and the p-channel TFT. The element can be segregated at its concentration into the impurity region containing phosphorus (P) (the direction of the arrow shown in FIG. 13). As a result, about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ of a catalytic element segregated in the impurity region. The TFT thus manufactured has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and good characteristics can be achieved. The configuration of this embodiment can be combined with the first to third embodiments.

[Embodiment 5] In this embodiment, a process for manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described. First, as shown in FIG. 14A, a spacer including a columnar spacer is formed on the active matrix substrate in the state of FIG. 5B. The spacer may be provided by scattering particles of several μm, but here, a method of forming a resin film over the entire surface of the substrate and then patterning the resin film is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Corporation is applied by a spinner and then formed into a predetermined pattern by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The shape of the spacer manufactured in this manner can be varied depending on the conditions of the exposure and the development processing. When combined, the mechanical strength of the liquid crystal display panel can be secured. The shape is not particularly limited, such as a conical shape or a pyramid shape. For example, when the shape is a conical shape, specifically, the height is 1.
The average radius is 5 to 7 μm, and the ratio of the average radius to the bottom radius is 1: 1.5. At this time, the taper angle of the side surface is set to ± 15 ° or less.

The arrangement of the spacers may be arbitrarily determined, but preferably, as shown in FIG. 14A, in the pixel portion, the columnar spacer is overlapped with the contact portion 231 of the pixel electrode 169 so as to cover that portion. 406 may be formed. Since the flatness of the contact portion 231 is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 406 is formed in such a manner that the contact portion 231 is filled with the resin for the spacer, so that disclination or the like is performed. Can be prevented. In addition, the driving circuit T
Spacers 405a to 405e are also formed on the FT. This spacer may be formed over the entire surface of the drive circuit portion, or may be provided so as to cover the source line and the drain line as shown in FIG.

After that, an alignment film 407 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The area not rubbed in the rubbing direction from the end of the columnar spacer 406 provided in the pixel portion was set to 2 μm or less. In the rubbing treatment, generation of static electricity often poses a problem, but the effect of protecting the TFT from static electricity can be obtained by the spacers 405a to 405e formed on the TFT of the driving circuit. Although not explained in the figure,
After forming the alignment film 407 first, the spacers 406, 4
05a to 405e may be formed.

The opposing substrate 401 on the opposing side has a light shielding film 40
2. A transparent conductive film 403 and an alignment film 404 are formed.
The light-shielding film 402 includes a Ti film, a Cr film, an Al film,
It is formed with a thickness of 300 nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached with a sealant 408. A filler (not shown) is mixed in the sealant 408, and the two substrates are bonded at a uniform interval by the filler and the spacers 406 and 405a to 405e. After that, a liquid crystal material 409 is injected between the two substrates. A known liquid crystal material may be used as the liquid crystal material. For example, in addition to the TN liquid crystal, a thresholdless antiferroelectric mixed liquid crystal exhibiting electro-optical response in which the transmittance continuously changes with respect to an electric field can be used. In this thresholdless antiferroelectric mixed liquid crystal,
Some exhibit a V-shaped electro-optical response characteristic. Thus, the active matrix liquid crystal display device shown in FIG. 14B is completed.

FIG. 15 is a top view of such an active matrix substrate, and is a top view showing a positional relationship between a pixel portion and a driving circuit portion, a spacer, and a sealant. A scanning signal driving circuit 605 and an image signal driving circuit 606 are provided as driving circuits around the pixel portion 604 on the glass substrate 101 described in Embodiment 1. In addition, other CPU
A signal processing circuit 607 such as a memory and a memory may be added. These drive circuits are connected to an external input / output terminal 602 by a connection wiring 603. Pixel section 6
In 04, a pixel is formed by intersecting a group of gate wirings 608 extending from the scanning signal driving circuit 605 and a group of source wirings 609 extending from the image signal driving circuit 606 in a matrix. Capacity 2
05 is provided.

In FIG. 14, the columnar spacer 406 provided in the pixel portion may be provided for all the pixels, but is provided every several to several tens of pixels arranged in a matrix as shown in FIG. May be. That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion is 20 to
It can be 100%. Further, the spacers 405a to 405e provided in the drive circuit portion may be provided so as to cover the entire surface or may be provided in accordance with the positions of the source and drain wirings of each TFT. In FIG. 15, the arrangement of the spacers provided in the drive circuit portion is indicated by 610 to 612. Then, the sealant 619 shown in FIG. 15 is provided outside the pixel portion 604, the scan signal drive circuit 605, the image signal drive circuit 606, and other signal processing circuits 607 on the substrate 101 and inside the external input / output terminal 602. Formed.

The structure of such an active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. FIG.
6, the active matrix substrate is a glass substrate 1
01, a pixel portion 604, a scanning signal driving circuit 605, an image signal driving circuit 606, and another signal processing circuit 607. The pixel portion 604 includes a pixel T
An FT 204 and a storage capacitor 205 are provided, and a driving circuit provided around the pixel portion is configured based on a CMOS circuit. From the scanning signal driver circuit 605 and the image signal driver circuit 606, a gate line (equivalent to 224 in FIG. 5B when formed continuously with the gate electrode) and a source line 164 are provided to the pixel portion 604. Extend, the pixel T
Connected to FT204. Also, a flexible printed circuit (FPC) 613 is used.
Are connected to the external input terminal 602 and are used to input image signals and the like. The FPC 613 is firmly bonded by a reinforcing resin 614. The connection wiring 603 is connected to each drive circuit. Also, the counter substrate 40
1, a light shielding film and a transparent electrode, not shown, are provided.

The liquid crystal display device having such a structure can be formed by using the active matrix substrates shown in the first to third embodiments. When the active matrix substrate described in Embodiment 1 is used, a reflection type liquid crystal display device can be obtained. When the active matrix substrate described in Embodiment 3 is used, a transmission type liquid crystal display device can be obtained.

Embodiment 6 FIG. 18 shows an example of the circuit configuration of the active matrix substrate shown in Embodiments 1 to 3, and is a diagram showing the circuit configuration of a direct-view display device. This active matrix substrate includes an image signal driving circuit 606, scanning signal driving circuits (A) and (B) 605, and a pixel portion 604. Note that the driving circuit described in this specification is:
This is a general term including the image signal driving circuit 606 and the scanning signal driving circuit 605.

The image signal driving circuit 606 includes a shift register circuit 501a, a level shifter circuit 502a, a buffer circuit 503a, and a sampling circuit 504.
Each of the scanning signal driving circuits (A) and (B) 185 includes a shift register circuit 501b, a level shifter circuit 502b, and a buffer circuit 503b.

The shift register circuits 501a and 501b have a driving voltage of 5 to 16 V (typically 10 V), and the TFT of the CMOS circuit forming this circuit is shown in FIG.
Of the first p-channel TFT 200 and the first n-channel TFT 201. Alternatively, a first p-channel TFT 280 and a first n-channel TFT 281 illustrated in FIG. 9A may be used. Further, the level shifter circuits 502a and 502b and the buffer circuits 503a and 503
In FIG. 9A, since the drive voltage becomes as high as 14 to 16 V, FIG.
It is desirable to have a multi-gate TFT structure as shown in FIG. Forming a TFT with a multi-gate structure increases the breakdown voltage, which is effective in improving the reliability of the circuit.

The sampling circuit 504 is composed of an analog switch and has a drive voltage of 14 to 16 V. However, since the polarity is alternately inverted and the off-state current value needs to be reduced, the sampling circuit 504 shown in FIG. It is desirable to form the second p-channel type TFT 202 and the second n-channel type TFT 203 as shown by. Alternatively, in order to effectively reduce the off-current value, the second p-channel type T shown in FIG.
The FT 282 and the second n-channel TFT 283 may be used.

The driving voltage of the pixel portion is 14 to 16 V, and it is required to further reduce the off-current value as compared with the sampling circuit from the viewpoint of low power consumption.
A multi-gate structure is basically used like the pixel TFT 204 shown in FIG.

The structure of this embodiment can be easily realized by fabricating a TFT according to the steps shown in the first to third embodiments. In the present embodiment, only the configuration of the pixel unit and the driving circuit is shown. However, according to the steps of Embodiments 1 to 3, the signal dividing circuit, the frequency dividing circuit, the D / A converter, the γ correcting circuit, An operational amplifier circuit, a signal processing circuit such as a memory circuit or an arithmetic processing circuit, or a logic circuit can be formed over the same substrate. As described above, the present invention can realize a semiconductor device including a pixel portion and a driver circuit over the same substrate, for example, a liquid crystal display device including a signal control circuit and a pixel portion.

[Embodiment 7] In this embodiment, a self-luminous display panel (hereinafter, referred to as an EL display device) using an electroluminescent (EL) material by using the active matrix substrate of the fifth embodiment. An example of manufacturing will be described. FIG. 19A is a top view of an EL display panel using the present invention. 19A, reference numeral 10 denotes a substrate, 11 denotes a pixel portion, 12 denotes a source-side drive circuit, and 13 denotes a gate-side drive circuit. Each drive circuit reaches the FPC 17 via wirings 14 to 16 and is connected to an external device. Connected to

FIG. 19B is a cross-sectional view taken along the line AA ′ of FIG. 19A. At this time, the opposing plate 80 is provided at least over the pixel portion, preferably over the driving circuit and the pixel portion. The opposing plate 80 is bonded to the active matrix substrate on which the TFT and the EL layer are formed with the sealing material 19.
A filler (not shown) is mixed in the sealant 19, and the two substrates are bonded with a substantially uniform interval by the filler. Further, the outside of the seal member 19 and the upper surface and the periphery of the FPC 17 are sealed with a sealant 81. The sealant 81 uses a material such as a silicone resin, an epoxy resin, a phenol resin, and butyl rubber.

As described above, when the active matrix substrate 10 and the counter substrate 80 are bonded by the sealant 19, a space is formed therebetween. The space is filled with a filler 83. The filler 83 also has the effect of bonding the opposing plate 80. Filler 83 is made of PVC (polyvinyl chloride), epoxy resin, silicone resin, P
VB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Also, E
The L layer is susceptible to moisture and moisture and easily deteriorates. Therefore, it is desirable to mix a desiccant such as barium oxide into the filler 83 because a moisture absorbing effect can be maintained. Also,
A passivation film 82 formed of a silicon nitride film, a silicon oxynitride film, or the like is formed over the EL layer, and a filler 83
It has a structure to prevent corrosion due to alkali elements and the like contained in.

A glass plate, an aluminum plate, a stainless steel plate, FRP (Fiberglass-Reinforced Pl)
astics) plate, PVF (polyvinyl fluoride) film, mylar film (trade name of DuPont), polyester film, acrylic film or acrylic plate. Further, moisture resistance can be enhanced by using a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or mylar films. In this way, the EL element is in a sealed state and is isolated from the outside air.

In FIG. 19B, a TFT for a driving circuit (here, a C-type TFT combining an n-channel TFT and a p-channel TFT) is formed on the substrate 10 and the base film 21.
2 illustrates a MOS circuit. 22) and TFT for pixel portion
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
Among the FTs, an n-channel TFT, in particular, is provided with an LDD region having the structure shown in this embodiment in order to prevent a decrease in on-current due to the hot carrier effect and a decrease in characteristics due to Vth shift and bias stress.

For example, the driving circuit TFT 22 is used as shown in FIG.
The p-channel TFTs 200 and 202 and the n-channel TFTs 201 and 203 shown in FIG. Also,
The pixel TFT 2 shown in FIG.
04 or p-channel type TF having a structure similar thereto
T may be used.

In order to manufacture an EL display device from the active matrix substrate in the state shown in FIG. 5B or FIG. 6B, an interlayer insulating film (flattening film) 26 made of a resin material is formed on source and drain lines. Formed, and a TFT for pixel section
A pixel electrode 27 made of a transparent conductive film electrically connected to the drain of the pixel 23 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. When the pixel electrode 27 is formed, the insulating film 2 is formed.
8 is formed, and an opening is formed on the pixel electrode 27.

Next, an EL layer 29 is formed. EL layer 29
Are known EL materials (a hole injection layer, a hole transport layer, a light emitting layer,
An electron transport layer or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials.
When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

The EL layer is formed by evaporation using a shadow mask,
Alternatively, it is formed by an inkjet method, a dispenser method, or the like. In any case, light emitting layers capable of emitting light of different wavelengths for each pixel (red light emitting layer, green light emitting layer, and blue light emitting layer)
Is formed, color display becomes possible. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Needless to say, a monochromatic EL display device can be used.

After the EL layer 29 is formed, the cathode 3
0 is formed. It is desirable to remove moisture and oxygen existing at the interface between the cathode 30 and the EL layer 29 as much as possible. Therefore, it is necessary to devise a method of continuously forming the EL layer 29 and the cathode 30 in a vacuum, or forming the EL layer 29 in an inert atmosphere and forming the cathode 30 in a vacuum without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 30 is made of Li
A laminated structure of an F (lithium fluoride) film and an Al (aluminum) film is used. Specifically, one layer is formed on the EL layer 29 by vapor deposition.
A LiF (lithium fluoride) film having a thickness of nm is formed, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via an anisotropic conductive paste material 32. A resin layer 80 is further formed on the FPC 17 to increase the adhesive strength at this portion.

In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming a contact hole for a pixel electrode) or at the time of etching the insulating film 28 (at the time of forming an opening before forming an EL layer). Further, when the insulating film 28 is etched, the etching may be performed all at once up to the interlayer insulating film 26. In this case, if the interlayer insulating film 26 and the insulating film 28 are made of the same resin material, the shape of the contact hole can be made good.

The wiring 16 is electrically connected to the FPC 17 through a gap between the seal 19 and the substrate 10 (however, closed by a sealant 81). Although the wiring 16 has been described here, the other wirings 14 and 15 are also electrically connected to the FPC 17 under the sealing material 18 in the same manner.

FIG. 20 shows a more detailed sectional structure of the pixel portion, FIG. 21A shows a top view structure thereof, and FIG.
It is shown in (B). In FIG. 20A, the switching TFT 2402 provided on the substrate 2401 is the same as that of the first embodiment.
5 (B) of FIG. 5B. With a double gate structure, substantially two TFs
There is an advantage that the structure is such that T is connected in series, and the off-current value can be reduced. In this embodiment, a double gate structure is used, but a triple gate structure or a multi-gate structure having more gates may be used.

The current controlling TFT 2403 is the same as that shown in FIG.
It is formed using an n-channel TFT 201 shown in FIG. At this time, the drain line 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. A wiring indicated by 38 is a gate line that electrically connects the gate electrodes 39a and 39b of the switching TFT 2402.

At this time, it is very important that the current control TFT 2403 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, by providing the current control TFT with an LDD region that partially overlaps the gate electrode, deterioration of the TFT is prevented,
Operation stability can be improved.

In this embodiment, the current controlling TFT 24 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

As shown in FIG. 21A, the wiring which becomes the gate electrode 37 of the current controlling TFT 2403 has 24
In a region indicated by 04, the region overlaps with the drain line 40 of the current control TFT 2403 via an insulating film. At this time, 24
In a region indicated by 04, a capacitor is formed. The capacitor 2404 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 2403. The drain line 40 is a current supply line (power supply line) 2
501, a constant voltage is always applied.

The first passivation film 4 is formed on the switching TFT 2402 and the current control TFT 2403.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
403 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed. A groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin).
The light emitting layer 44 is formed in the inside. Although only one pixel is shown here, R (red), G (green), B (blue)
The light emitting layers corresponding to the respective colors may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.
There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Gelsen, E. Kl
uge, W. Kreuder and H. Spreitzer, “Polymers for Ligh
t Emitting Diodes ”, Euro Display, Proceedings, 1999,
p.33-37 "and a material described in JP-A-10-92576 may be used.

As a specific light emitting layer, cyanopolyphenylenevinylene is used for a red light emitting layer, polyphenylene vinylene is used for a green light emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light emitting layer. Good. Thickness is 30-150nm
(Preferably 40 to 100 nm). However, the above example is an example of an organic EL material that can be used as a light emitting layer, and there is no need to limit the invention to this.
An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a polymer material is used as the light emitting layer has been described.
A low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
The EL layer has a laminated structure in which a hole injection layer 46 made of (polythiophene) or PAni (polyaniline) is provided. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 2
405 is completed. Note that the EL element 2405 referred to here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, and the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

FIG. 20B shows an example in which the structure of the EL layer is inverted. The current controlling TFT 2601 corresponds to p
It is formed using a channel type TFT 200. Embodiment 1 can be referred to for the manufacturing process. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 2602 is formed. In the case of this embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed as indicated by the arrow. In the case of the structure as in this embodiment, it is preferable that the current control TFT 2601 be formed of a p-channel TFT.

The configuration of this embodiment is different from that of the first and second embodiments in that
FT configurations can be implemented in any combination. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the ninth embodiment.

[Embodiment 8] In this embodiment, FIG. 22 shows an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. 21B is used. In this embodiment, 2701
270 is the source wiring of the switching TFT 2702, 270
3 is a gate wiring of the switching TFT 2702, 27
04 is a current control TFT, 2705 is a capacitor, 27
Reference numerals 06 and 2708 denote current supply lines, and 2707 denotes an EL element.

FIG. 22A shows an example in which a current supply line 2706 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 2706. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 22B shows a current supply line 270.
8 is provided in parallel with the gate wiring 2703. Note that in FIG. 22B, the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other; however, if both wirings are formed in different layers,
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 2708 and the gate wiring 2703 can share an occupied area, the pixel portion can have higher definition.

In FIG. 22C, a current supply line 2708 is provided in parallel with the gate wiring 2703 similarly to the structure of FIG. 22B, and two pixels are connected to the current supply line 2708.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 2708 so as to overlap with one of the gate wirings 2703. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition. FIG.
22A and 22B, a capacitor 240 is used to hold a voltage applied to the gate of the current controlling TFT 2404.
5 is provided, but the capacitor 2405 can be omitted.

The current control TFT 2404 shown in FIG.
Since the n-channel TFT of the present invention as shown in FIG. 1A is used, an LDD region is provided so as to overlap with a gate electrode via a gate insulating film. Although a parasitic capacitance generally called a gate capacitance is formed, this embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 2405. The capacitance of the parasitic capacitance is determined by the gate electrode and the LDD region. And changes in the area that overlaps,
It is determined by the length of the LDD region included in the overlapping region. In the structures of FIGS. 22A, 22B, and 22C, the capacitor 2705 can be omitted in the same manner.

The structure of this embodiment is different from that of the first and second embodiments in that
FT configurations can be implemented in any combination. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the ninth embodiment.

[Embodiment 9] In this embodiment, the TFT of the present invention is used.
A semiconductor device incorporating an active matrix liquid crystal display device using circuits will be described with reference to FIGS.

Such a semiconductor device includes a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer,
TV and the like. Examples of these are shown in FIGS.
Shown in

FIG. 23A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention is an audio output unit 900
2. The present invention can be applied to a display device 9004 including an audio input unit 9003 and an active matrix substrate.

FIG. 23B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention provides a voice input unit 9103,
910 provided with active matrix substrate
2. It can be applied to the image receiving unit 9106.

FIG. 23C shows a mobile computer or a portable information terminal.
02, an image receiving section 9203, operation switches 9204, and a display device 9205. The present invention relates to an image receiving unit 920.
3 and display device 9 including active matrix substrate
205 can be applied.

FIG. 23D shows a head-mounted display, which comprises a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 23E shows a rear type projector, which includes a main body 9401, a light source 9402, a display device 9403,
Polarizing beam splitter 9404, reflector 940
5, 9406 and a screen 9407. The invention can be applied to the display device 9403.

FIG. 23F shows a portable book, and a main body 95.
01, display devices 9502 and 9503, storage medium 950
4, comprising an operation switch 9505 and an antenna 9506 for displaying data stored on a mini disk (MD) or a DVD or data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 24A shows a personal computer, which includes a main body 9601, an image input section 9602, and a display device 9.
603 and a keyboard 9604.

FIG. 24B shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 9701, a display device 9702, and a speaker unit 97.
03, a recording medium 9704, and operation switches 9705. This device uses a DVD (Digi
(tal Versatile Disc), CDs, etc., to enjoy music, movies, games and the Internet.

FIG. 24C shows a digital camera, which comprises a main body 9801, a display device 9802, an eyepiece 9803, operation switches 9804, and an image receiving unit (not shown).

FIG. 25A shows a front type projector, which comprises a display device 3601 and a screen 3602. The present invention can be applied to a display device and other signal control circuits.

FIG. 25B shows a rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3. It is composed of a screen 3704. The present invention can be applied to a display device and other signal control circuits.

FIG. 25C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 25A and 25B. Projection devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380
9. It is composed of a projection optical system 3810. Projection optical system 38
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 25D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 25C. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, a lens array 3813,
814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system shown in FIG. 25D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

In addition, the present invention can be applied to an image sensor and an EL display device. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

[Embodiment 10] In the first etching process and the second etching process shown in Embodiment 1, the elements selected from W, Ta, Ti, and Mo on the assumption that the gate electrode is formed, or these elements are used. It is intended for a conductive film made of an alloy obtained by combining the above. In the etching, it is necessary to particularly consider the etching rate of the target conductive film and the selectivity of the underlying insulating film. If the selectivity is small, the selective processing becomes difficult, and a desired TFT cannot be formed.

Evaluation of the etching rate was performed using a sample in which a W film or a silicon oxynitride film was formed on a glass substrate. The resist forming the mask was formed to a thickness of 1500 nm, and the etching rate was also evaluated. Etching is performed using an ICP etching apparatus, and a mixed gas of CF ₄ and Cl ₂ is used as an etching gas (condition 1), and a mixed gas of CF ₄ , Cl ₂ and O ₂ is used (condition 2). Was examined. Table 1 shows the results.

[0161]

[Table 1]

Table 2 shows the amount of decrease in the thickness of the silicon oxynitride film with respect to the etching time. As for the etching, the conditions 1 and 2 were compared in the same manner as described above. A sample in which a 30-nm silicon film and a 200-nm silicon oxynitride film were stacked over a glass substrate was used. Similarly, FIG. 26 shows a graph of the amount of decrease in the film thickness with respect to the etching time.

[0163]

[Table 2]

In the results of Tables 1 and 2, when O ₂ is added to the etching gas, the etching rate of the W film is higher and the etching rate of the silicon oxynitride film is lower. In other words, this indicates that the selectivity with respect to the base is improved. The increase in the etching rate of the W film is caused by the O
This is because the addition of 2 increases the amount of fluorine radicals. Also, the etching rate of the silicon oxynitride film decreases because the addition of O2 combines carbon, which is a component of the resist, with oxygen to form CO2, and the amount of carbon decreases. It can be considered to decrease.

The shape of the conductive film processed by etching was observed with a scanning electron microscope (SEM). As a sample evaluated, a 200-nm-thick silicon oxynitride film and a 400-nm W film formed on a glass substrate were used.
In the first etching process (taper etching), Cl ₂ gas flows at 30 SCCM and CF ₄ gas flows at 30 SCCM, an RF (13.56 MHz) power of 3.2 W / cm ^{2 is} applied at a pressure of 1 Pa, and the substrate side ( 224 mW / cm ² RF (13.56 MHz) power was also applied to the sample stage. FIG. 27 shows the result of observing the cross-sectional shape of a sample obtained by performing an etching process under these conditions by SEM. The angle of the tapered portion formed at the end of the W film is about 30 degrees.

Thereafter, a second etching process (anisotropic etching) was performed under the above conditions 1 and 2, and a comparative evaluation was performed. FIG. 28 shows a sample treated under the condition 1, and FIG.
Shows the result of observing the sample treated under the condition 2 by SEM. 28 and 29, the same shape is obtained. However, since the etching rate of the W film and the etching rate of the resist are improved by adding O ₂ to the mixed gas of CF ₄ and Cl ₂ , the sample formed under the condition 2 shown in FIG. 29 is thinner. . However, from the viewpoint of the decrease in the thickness of the silicon oxynitride film, it can be determined that the condition 2 is smaller and is superior in performing selective processing.

From the above experimental results, it is possible to use a mixed gas of CF ₄ , Cl ₂ and O ₂ as an etching gas in the first etching process and the second etching process. Even if such an etching gas is selected, whether to perform taper etching or anisotropic etching can be performed by controlling the bias power applied to the substrate side.

In the actual TFT, the design of the LDD is W
Film thickness and taper angle θ by the first etching process
1 and the amount of etching of the resist by the second etching process. For example, in FIG. 2, when the thickness of the W film is 400 nm, the angle θ1 of the Taber portion formed by the first etching process is 30 °.
In this case, the length of the second impurity region (A) 1012 in the channel length direction is 700 nm. According to Table 2, the amount of reduction of the resist by the second etching treatment is 94 nm / mi.
n, the LDD of 825 nm (Lo
It can be estimated that ff) is formed. Actually, there is some variation in the film thickness and the etching rate, so there is a slight increase or decrease.
μm LDDs can be formed.

FIG. 30 shows Table 2 as the first etching process.
The gate voltage (Vg) -drain current (Id) characteristics of the TFT manufactured by adopting the condition of Table 2 and adopting the condition of Table 2 as the second etching process are shown. The dimensions of the TFT are 7.5 μm in channel length and 8 μm in channel width, and the LDD (L
off) is estimated to be 1 μm. FIG. 30 shows the characteristics of an n-channel TFT. An off-current of 6.5 pA at a gate voltage of -4.5 V and a drain voltage of 14 V is obtained by LDD (Loff).

[0170]

According to the present invention, in a semiconductor device having a plurality of functional circuits formed on the same substrate (specifically, an electro-optical device in this case) according to the specifications required by the functional circuits. It is possible to arrange TFTs having appropriate performance, and the operating characteristics thereof can be greatly improved.

According to the method for manufacturing a semiconductor device of the present invention,
P-channel TFT and N-channel TFT for drive circuit
In addition, an active matrix substrate having an LDD structure in which a pixel TFT partially overlaps with a gate electrode can be manufactured with five photomasks, and the concentration of one conductivity type impurity element in an LDD region can be adjusted to be appropriate. it can. A reflective liquid crystal display device can be manufactured from such an active matrix substrate. Further, according to this step, a transmission type liquid crystal display device can be manufactured with six photomasks.

According to the method for manufacturing a semiconductor device of the present invention,
The gate electrode is formed of a heat-resistant conductive material, and the gate wiring is formed of a low-resistance conductive material. The manufactured active matrix substrate can be manufactured with six photomasks, and a reflection-type liquid crystal display device can be manufactured from such an active matrix substrate. Further, according to this step, a transmission type liquid crystal display device can be manufactured with seven photomasks.

[Brief description of the drawings]

FIG. 1 illustrates a method for manufacturing a TFT of the present invention.

FIG. 2 is a diagram illustrating a concentration distribution of an impurity element in an LDD region corresponding to FIG.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 7 is a top view illustrating a structure of a TFT and a pixel TFT of a driving circuit.

FIG. 8 is a cross-sectional view illustrating a structure of a TFT and a pixel TFT of a driving circuit.

FIG. 9 is a cross-sectional view illustrating a structure of a TFT of a driver circuit.

FIG. 10 is a cross-sectional view illustrating a configuration of a pixel TFT.

FIG. 11 is a top view illustrating pixels in a pixel portion.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 14 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 15 is a top view illustrating input / output terminals, wiring, circuit arrangement, spacers, and sealants of a liquid crystal display device.

FIG. 16 is a perspective view illustrating a structure of a liquid crystal display device.

FIG. 17 is a cross-sectional view illustrating a manufacturing step of a crystalline semiconductor layer.

FIG. 18 is a block diagram illustrating a circuit configuration of an active matrix display device.

19A and 19B are a top view and a cross-sectional view illustrating a structure of an EL display device.

FIG. 20 is a cross-sectional view of a pixel portion of an EL display device.

21A and 21B are a top view and a circuit diagram of a pixel portion of an EL display device.

FIG. 22 is an example of a circuit diagram of a pixel portion of an EL display device.

FIG 23 illustrates an example of a semiconductor device.

FIG 24 illustrates an example of a semiconductor device.

FIG. 25 illustrates a configuration of a projection type liquid crystal display device.

FIG. 26 is a graph showing the etching time and the amount of decrease in the thickness of the silicon oxynitride film.

FIG. 27 shows W processed by a first etching process.
SEM image showing the cross-sectional shape of the film.

FIG. 28 is a diagram showing S showing a cross-sectional shape of a W film processed by a second etching process using a mixed gas of CF ₄ and Cl _2.
EM image.

FIG. 29 is an SEM image showing a cross-sectional shape of a W film processed by a second etching process using a mixed gas of CF ₄ , Cl _2, and O ₂ .

FIG. 30 is a graph showing static characteristics of a TFT.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 616A 617K

Claims (12)

[Claims] In a semiconductor device having a semiconductor layer, an insulating film formed in contact with the semiconductor layer, and a gate electrode having a tapered portion on the insulating film, the semiconductor layer includes
A channel formation region, a first impurity region forming a source region or a drain region containing an impurity element of one conductivity type, and a second impurity region in contact with the channel formation region and forming an LDD region; Part of the second impurity region is provided so as to overlap with the gate electrode, and the concentration of the one-conductivity-type impurity element included in the second impurity region increases as the distance from the channel formation region increases. Semiconductor device. 2. A semiconductor device having an n-channel thin film transistor, wherein the n-channel thin film transistor has a semiconductor layer, an insulating film formed in contact with the semiconductor layer, and a gate having a tapered portion on the insulating film. An electrode, and the semiconductor layer forms a channel formation region, a first impurity region forming a source or drain region containing an impurity element of one conductivity type, and an LDD region in contact with the channel formation region. A second impurity region, a part of the second impurity region is provided so as to overlap with a gate electrode,
The semiconductor device according to claim 1, wherein a concentration of the one-conductivity-type impurity element included in the second impurity region increases as the distance from the channel formation region increases. 3. A semiconductor device having an n-channel thin film transistor and a p-channel thin film transistor, wherein the n-channel thin film transistor and the p-channel thin film transistor each include a semiconductor layer and an insulating film formed in contact with the semiconductor layer. A gate electrode having a tapered portion over the insulating film, wherein the semiconductor layer of the n-channel thin film transistor forms a channel formation region and a source region or a drain region containing an impurity element of one conductivity type; L in contact with the impurity region and the channel formation region.
A second impurity region forming a DD region;
A part of the impurity region is provided so as to overlap with the gate electrode, and the concentration of the one conductivity type impurity element contained in the second impurity region increases as the distance from the channel formation region increases, and the p-channel thin film transistor The semiconductor layer has a channel formation region, a third impurity region forming a source region or a drain region, and a fourth impurity region in contact with the channel formation region and forming an LDD region. The region and the fourth impurity region include:
A semiconductor device comprising the one conductivity type impurity element and an impurity element having a conductivity type opposite to the one conductivity type. 4. A semiconductor device having a pixel portion, wherein at least one thin film transistor provided in each pixel of the pixel portion includes a semiconductor layer, an insulating film formed in contact with the semiconductor layer, and a thin film transistor on the insulating film. And a gate electrode having a tapered portion, wherein the semiconductor layer has a channel formation region,
A first impurity region forming a source region or a drain region containing an impurity element of one conductivity type; and a second impurity region forming an LDD region in contact with the channel formation region; A semiconductor device in which a part is provided so as to overlap with a gate electrode, and a concentration of the one-conductivity-type impurity element included in the second impurity region increases as the distance from the channel formation region increases. 5. The semiconductor device according to claim 1, wherein an angle of the tapered portion of the gate electrode having the tapered portion is 30 degrees to 60 degrees. 6. The gate electrode according to claim 1, wherein the gate electrode having the tapered portion is made of an element selected from tungsten, tantalum, and titanium, or a compound or alloy containing the element as a component. A semiconductor device, comprising: 7. A first step of forming an insulating film on a semiconductor layer, a second step of forming a conductive layer on the insulating film, and a first taper by selectively etching the conductive layer. A third step of forming a conductive layer having a shape, a fourth step of doping the semiconductor layer with an impurity element of one conductivity type after the third step, and a conductive layer having the first tapered shape A second step of selectively etching a conductive layer having a second tapered shape, and a sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step. Wherein the concentration of the one conductivity type impurity element doped in the sixth step is lower than the concentration of the one conductivity type impurity element doped in the fourth step. Production method. 8. A method for manufacturing a semiconductor device having an n-channel thin film transistor, comprising: a first step of forming an insulating film on a semiconductor layer forming the n-channel thin film transistor; and forming a conductive layer on the insulating film. A second step of selectively etching the conductive layer to form a conductive layer having a first tapered shape, and removing the one conductivity type impurity element after the third step. A fourth step of doping the semiconductor layer, a fifth step of selectively etching the conductive layer having the first tapered shape to form a conductive layer having the second tapered shape, A sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the step, wherein the concentration of the impurity element of one conductivity type doped in the sixth step is the same as that of the fourth step. Do The method for manufacturing a semiconductor device, characterized in that is lower than the concentration of the impurity element imparting one conductivity type to ping. 9. A semiconductor device having an n-channel thin film transistor and a p-channel thin film transistor, wherein a first step of forming an insulating film on each of the semiconductor layers forming the n-channel thin film transistor and the p-channel thin film transistor; A second step of forming a conductive layer on the insulating film; a third step of selectively etching the conductive layer to form a conductive layer having a first tapered shape; A fourth step of later doping the semiconductor layer with an impurity element of one conductivity type, and a step of selectively etching the conductive layer having the first tapered shape to form a conductive layer having a second tapered shape. Step 5, a sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step, and a p-channel after the sixth step. And a seventh step of doping a semiconductor layer of the semiconductor thin film transistor with an impurity element of a conductivity type opposite to the one conductivity type, wherein a concentration of the one conductivity type impurity element doped in the sixth step is: A method for manufacturing a semiconductor device, characterized in that the concentration is lower than the concentration of one conductivity type impurity element doped in the fourth step. 10. A method for manufacturing a semiconductor device having a pixel portion, comprising: a first step of forming an insulating film on a semiconductor layer forming a thin film transistor provided in each pixel of the pixel portion; A second step of forming a layer;
A third step of selectively etching the conductive layer to form a conductive layer having a first tapered shape; and a fourth step of doping the semiconductor layer with an impurity element of one conductivity type after the third step. A step of selectively etching the conductive layer having the first tapered shape to form a conductive layer having the second tapered shape; and a step of forming one conductive type after the fifth step. And a sixth step of doping the semiconductor layer with an impurity element. The concentration of the one conductivity type impurity element doped in the sixth step is the fourth
A method for manufacturing a semiconductor device, characterized in that the concentration is lower than the concentration of one conductivity type impurity element doped in the step (d). 11. The manufacturing method of a semiconductor device according to claim 7, wherein the angle of the tapered portion of the gate electrode having the tapered portion is 30 degrees to 60 degrees. Method. 12. The gate electrode according to claim 7, wherein the gate electrode having the tapered portion is made of an element selected from tungsten, tantalum, and titanium, or a compound or alloy containing the element as a component. A method for manufacturing a semiconductor device, which is formed.