JP2000208778A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of high reliability by forming a concentration gradient at an LDD part seen in MOSFET from a plurality of impurity regions. SOLUTION: The active layer of NTFT is formed of a channel forming region 102, first impurity region 103, second impurity region 104, and third impurity region 105. Here, the impurity concentration of each impurity region is set higher receding from the channel formation region 102. Furthermore, the first impurity region 102 is provided so as to overlap a sidewall 108, providing a substantial gate overlap structure with the sidewall 108 functioning as an electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, the present invention relates to an electro-optical device represented by a liquid crystal display panel and a configuration of an electronic device having such an electro-optical device as a component. Note that in this specification, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are also semiconductor devices.

[0002]

2. Description of the Related Art Recently, a TFT using a polysilicon film has been developed.
An active matrix type liquid crystal display device having a circuit constituted by the above has attracted attention. This is to realize a high-definition image display by controlling the electric field applied to the liquid crystal in a matrix by a plurality of pixels arranged in a matrix.

In such an active matrix type liquid crystal display device, as the resolution becomes higher, such as XGA and SXGA, the number of pixels alone exceeds one million. A driver circuit for driving all of them is very complicated and formed by many TFTs.

The specifications required for an actual liquid crystal display device (also called a liquid crystal panel) are strict, and high reliability is required for both pixels and drivers in order for all pixels to operate normally. In particular, when an abnormality occurs in the driver circuit, it leads to a defect called a line defect in which pixels in one column (or one row) are completely annihilated.

However, a TF using a polysilicon film is used.
T is an MO that is still used for LSIs etc. in terms of reliability.
It is said to be inferior to SFETs (transistors formed on a single crystal semiconductor substrate). Unless this weakness is overcome, it is becoming increasingly difficult to form an LSI circuit using TFTs.

[0006] Applicants have recognized that MOSFETs have three advantages in terms of reliability. And the reason was as follows. The MOS shown in FIG.
FIG. 2 is a schematic diagram of an FET. 201 is a drain region formed on the single crystal silicon substrate, and 202 is an LDD (lightly doped drain) region. Reference numeral 203 denotes a field insulating film, and a gate insulating film 205 immediately below the gate wiring 204.

At this time, it was considered that there were three advantages in terms of reliability. First, the first advantage is that the impurity concentration has a gradient from the LDD region 202 toward the drain region 201. As shown in FIG.
In the FET, the impurity concentration gradually increases from the LDD region 202 toward the drain region 201. We thought that this gradient was effective in increasing reliability.

[0008] A second advantage is that the LDD region 202 and the gate wiring 204 overlap. This structure is called GOLD (gate-drain overlapped LDD) or L
ATID (large-tilt-angle implanted drain) is known. By doing so, the impurity concentration of the LDD region 202 can be reduced, the effect of relaxing the electric field is increased, and the hot carrier resistance is increased.

A third advantage is that a certain distance exists between the LDD region 202 and the gate wiring 204. This is due to the fact that the field insulating film 203 is formed in such a manner as to enter under the gate wiring. That is,
Since the thickness of the gate insulating film is increased only in the overlap portion, effective electric field relaxation can be expected.

Thus, the conventional MOSFET is a TFT
It has several advantages compared to and, as a result, is believed to have high reliability.

Further, the advantage of such a MOSFET is T
Attempts have been made to apply it to FT. For example,
`` M.Hatano, H.Akimoto, and T.Sakai, IEDM97 TECHNICAL
In DIGEST, p523-526, 1997, a GOLD structure is realized using sidewalls made of silicon.

However, the structure disclosed in the same paper has a problem that the off-state current (current flowing when the TFT is in an off-state) is larger than that of the normal LDD structure. Was.

[0013]

As described above, the applicant of the present invention has found that a TFT structural problem affects reliability (particularly hot carrier resistance) when comparing a TFT with a MOSFET. Thought.

The present invention is a technique for overcoming such a problem, and it is an object of the present invention to realize a TFT having a reliability equal to or higher than that of a MOSFET. It is another object of the present invention to realize a highly reliable semiconductor device including a semiconductor circuit in which a circuit is formed using such a TFT.

[0015]

SUMMARY OF THE INVENTION The present invention discloses an NTFT and PTFT having an active layer, an insulating film in contact with the active layer, and a wiring in contact with the insulating film.
A semiconductor device including a CMOS circuit comprising:
Only the TFT has a sidewall on the side of the wiring, and the active layer of the NTFT includes a channel formation region and at least three types of impurity regions containing elements belonging to Group 15 at different concentrations. Of the impurity regions, the impurity region in contact with the channel formation region overlaps with the sidewall via the insulating film,
The active layer of the PTFT includes a channel formation region and two types of impurity regions containing an element belonging to Group 13 at the same concentration. Both the NTFT and the PTFT have an impurity region furthest from the channel formation region. The catalyst element used for crystallization of the active layer is 1 × 10 ¹⁷ to 1 × 10 ²⁰ at.
It is characterized by being present at a concentration of oms / cm ³ .

According to another aspect of the present invention, there is provided a semiconductor device including a CMOS circuit including NTFT and PTFT having an active layer, an insulating film in contact with the active layer, and a wiring in contact with the insulating film. Only the NTFT has a sidewall on a side of the wiring, and the active layer of the NTFT has a structure in which a channel formation region, a first impurity region, a second impurity region, and a third impurity region are arranged in this order; The first impurity region, the second impurity region, and the third impurity region each include an element belonging to Group 15 at different concentrations, and the first impurity region overlaps the sidewall via the insulating film; The active layer of the PTFT has a structure in which a channel formation region, a fourth impurity region, and a fifth impurity region are arranged in this order, and the fourth impurity region and the fifth impurity region have the same concentration. Comprising an element belonging to, wherein the third impurity region and the fifth impurity regions, the catalytic element used for crystallization of the active layer is ^{1 × 10 17 ~1 × 10 20} atoms / cm
It is characterized by being present in a concentration of ³ .

According to another aspect of the present invention, there is provided a semiconductor device including a CMOS circuit including an NTFT and a PTFT having an active layer, an insulating film in contact with the active layer, and a wiring in contact with the insulating film. Only the NTFT has a sidewall on a side portion of the wiring, and the active layer of the NTFT includes a channel formation region and at least three types of impurity regions containing elements belonging to Group 15 at different concentrations. In the three types of impurity regions, the concentration of the element belonging to Group 15 increases as the distance from the channel formation region increases, and the active layer of the PTFT includes the element belonging to Group 13 at the same concentration as the channel formation region. And the NTFT and the PTFT, both of which are located farthest from the channel formation region, are used for crystallization of the active layer. The catalytic element is 1 × 10 ¹⁷ ~1 × 10 was
It is characterized by being present at a concentration of ²⁰ atoms / cm ³ .

According to another aspect of the present invention, there is provided a semiconductor device including a CMOS circuit including NTFT and PTFT having an active layer, an insulating film in contact with the active layer, and a wiring in contact with the insulating film. Only the NTFT has a sidewall on a side of the wiring, and the active layer of the NTFT has a structure in which a channel formation region, a first impurity region, a second impurity region, and a third impurity region are arranged in this order; The first impurity region, the second impurity region, and the third impurity region include the same impurity at different concentrations, respectively, and the first impurity region, the second impurity region, and the third impurity region in order of the impurity. The active layer of the PTFT has a high concentration, and has a structure in which a channel forming region, a fourth impurity region, and a fifth impurity region are arranged in this order, and the fourth impurity region and the fifth impurity region are the same. Comprising an element belonging to Group 13 in degrees, wherein the third impurity region and the fifth impurity regions, the catalytic element is 1 × 10 ¹⁷ ~1 × 10 used for crystallization of the active layer
It is characterized by being present at a concentration of ²⁰ atoms / cm ³ .

In the present invention, the structure of the active layer (particularly, N
There is a great feature in the case of a channel type TFT, and therefore, there is also a feature in the manufacturing method. The structure of the invention relating to a manufacturing method for carrying out the present invention includes a first step of forming a semiconductor film including a crystal on a substrate having an insulating surface using a catalytic element, and patterning the semiconductor film including the crystal. A second step of forming a first active layer and a second active layer, a third step of forming an insulating film on the first active layer and the second active layer, and forming a wiring on the insulating film A fourth step of adding an element belonging to Group 15 to the first active layer and the second active layer using the wiring as a mask, and a sixth step of forming a sidewall on a side portion of the wiring. Forming a resist mask on the first active layer by adding a group 15 element to the first active layer and the second active layer using the wiring and the sidewall as a mask; And the second active layer is made of group 13 An eighth step of adding an element to be formed, forming a resist mask on the first active layer and the second active layer, and forming a group 15 group on a part of the first active layer and a part of the second active layer. A ninth step of adding an element belonging to, a tenth step of forming a silicon nitride film, and a heat treatment for moving the catalytic element to a part of the first active layer and a part of the second active layer by heat treatment. And 11 steps.

According to another aspect of the invention, there is provided a first step of forming an active layer containing a catalytic element for promoting crystallization on a substrate having an insulating surface, and forming a first insulating film on the active layer. A second step of forming, a third step of forming a wiring on the first insulating film, a fourth step of adding an element belonging to Group 15 to the active layer using the wiring as a mask, A fifth step of forming a sidewall on a side portion, a sixth step of adding an element belonging to Group 15 to the active layer using the wiring and the sidewall as a mask, and removing a part of the first insulating film A seventh step of exposing a part of the active layer formed in the sixth step, an eighth step of adding an element belonging to Group 15 to the active layer exposed in the seventh step, Ninth forming the second insulating film in contact with the upper part
And a tenth step of performing a heat treatment for reducing the concentration of the catalytic element in the active layer.

According to another aspect of the present invention, a first step of forming a first active layer and a second active layer containing a catalytic element for promoting crystallization on a substrate having an insulating surface; Forming a first insulating film on the layer and the second active layer;
A step of forming a wiring on the first insulating film, and a fourth step of adding an element belonging to Group 15 to the first active layer and the second active layer using the wiring as a mask. A fifth step of forming a sidewall on a side portion of the wiring, and a sixth step of adding an element belonging to Group 15 to the first active layer and the second active layer using the wiring and the sidewall as a mask. A seventh step of selectively removing the first insulating film and exposing a part of the first active layer and a part of the second active layer formed in the sixth step; An eighth step of adding an element belonging to Group 15 to the first active layer and the second active layer exposed in the step,
A ninth step of forming a second insulating film in contact with the upper part of the wiring, a tenth step of performing a heat treatment for reducing the concentration of a catalytic element in the first active layer and the second active layer, and An eleventh step of selectively removing the insulating film and exposing a part of the second active layer formed in the tenth step; and a twelfth step of removing the second active layer exposed in the eleventh step. A thirteenth step of selectively removing the first insulating film and exposing a part of the second active layer; and a thirteenth step of adding an element belonging to Group 13 to the second active layer exposed in the thirteenth step. And 14 steps.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG. Note that FIG. 1 shows a cross-sectional view, and FIG. 11 shows a view from above. In FIG. 1, reference numeral 101 denotes a substrate having an insulating surface. For example, a glass substrate provided with a silicon oxide film, a quartz substrate, a stainless steel substrate, a metal substrate, a ceramic substrate, or a silicon substrate can be used.

The present invention is characterized by an N-channel TFT.
(Hereinafter referred to as NTFT) active layer. NT
The FT active layer includes a channel forming region 102 and a pair of first
An impurity region 103, a pair of second impurity regions 104, and a pair of third impurity regions 105 are formed. Note that the impurity added to each impurity region is an element belonging to Group 15 (typically, phosphorus or arsenic).

At this time, the channel forming region 102 (110
Is the same as the intrinsic semiconductor layer or 1 × 10 ^{16 to} 5 × 10 ¹⁸ at
It is a semiconductor layer to which boron is added at a concentration of oms / cm ³ .
Boron is an impurity for controlling the threshold voltage and preventing punch-through, and can be replaced with another element as long as it produces the same effect. Also in that case, the concentration is added to the same degree as that of boron.

The semiconductor layer that can be used in the present invention includes a silicon layer or a silicon germanium layer.
In addition to a semiconductor layer containing silicon as a main component, a compound semiconductor layer such as gallium arsenide or a germanium single layer can be used. In addition, the present invention is applicable to a TFT using an amorphous semiconductor (such as amorphous silicon) for the active layer as well as a TFT using a semiconductor containing a crystal (including a single crystal semiconductor thin film, a polycrystalline semiconductor thin film, and a microcrystalline semiconductor thin film). Can also be applied.

The first impurity region 103 of the NTFT has a length of 0.1 to 1 μm (typically 0.1 to 0.5 μm, preferably 0.1 to 0.2 μm) and has a length of 1 × 10 ¹⁵ ~
1 × 10 ¹⁷ atoms / cm ³ (typically 5 × 10 ^{15 to} 5 × 1
0 ¹⁶ atoms / cm ³ , preferably 1 × 10 ¹⁶ to 2 × 10 ¹⁶ ato
ms / cm ³ ) and contains an element belonging to Group 15 (typically phosphorus). Note that the impurity concentration at this time is represented by (n ⁻ ) (in this specification, the n ⁻ region is referred to as a first impurity region).

In this specification, the term “impurity” refers to an element belonging to Group 13 or Group 15 unless otherwise specified. In addition, the size (area) of each impurity region changes in the course of the manufacturing process, but in this specification, the same reference numerals will be used unless the concentration changes even if the area changes.

The second impurity region 104 has a thickness of 0.5 to
It has a length of 2 μm (typically 1 to 1.5 μm) and 1 ×
10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ (typically 1 × 10 ¹⁷ atoms / cm ³
5 × 10 ¹⁸ atoms / cm ³ , preferably 5 × 10 ¹⁷ to 1 ×
Contains elements belonging to Group 15 at a concentration of 10 ¹⁸ atoms / cm ³ ). The concentration of the impurity contained in the second impurity region may be adjusted to be 5 to 10 times the concentration of the impurity contained in the first impurity region. The impurity concentration at this time is (n)
(In this specification, the n region is referred to as a second impurity region.)

Further, the third impurity region 105 has
μm (typically 3 to 10 μm) and 1 × 10
¹⁹ to 1 × 10 ²¹ atoms / cm ³ (typically 1 × 10 ^{20 to} 5
It contains elements belonging to Group 15 at a concentration of × 10 ²⁰ atoms / cm ³ ). The third impurity region 105 becomes a source region or a drain region for electrically connecting the source wiring or the drain wiring to the TFT. Note that the impurity concentration at this time is represented by (n ⁺ ) (in this specification, the n ⁺ region is referred to as a third impurity region).

Further, in the present invention, the third impurity region 105 plays a very important role in gettering the catalyst element used for crystallization of the channel formation region from inside the channel formation region 102. The effect will be briefly described.

In the present invention, a catalyst element (typically, nickel) for promoting crystallization is used in crystallization of the amorphous semiconductor film. However, since nickel is a metal element, if nickel remains in the channel formation region, it may cause a leak current. That is, it is desirable to provide a step for removing the catalyst element from at least the inside of the channel formation region after using the catalyst element.

The present invention is characterized in that an element belonging to Group 15 (preferably phosphorus) existing in the source region and the drain region is used for removing the catalytic element. That is,
Source region and drain region (third impurity region 105)
Is formed, heat treatment is performed so that nickel remaining in the channel formation region is gettered (captured) in the third impurity region 105. Thus, the catalyst element used for crystallization can be removed from inside the channel formation region 102.

Therefore, gettered catalytic elements are gathered and exist in the third impurity region 105 at a high concentration. As a result of an examination by SIMS (Mass Secondary Ion Analysis), the applicant has found that 1 × 10 ¹⁸ to 1 × 10 ²¹ atoms / cm ³ (typically 5 × 10 ²¹ atoms / cm ³ )
It was found that the catalyst element was present at a concentration of × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm ³ ). However, the third impurity region 10
Since the element 5 only has to function as an electrode, no problem occurs even if a large amount of the catalytic element is present.

On the other hand, the concentration of the catalytic element in the channel forming region 102 was greatly reduced (or removed) by the gettering action. As a result of an examination by SIMS performed by the present applicant, the concentration of the catalyst element in the channel formation region 102 is 2 ×
10 ¹⁷ atoms / cm ³ or less (typically 1 × 10 ^{14 to} 5 × 1
0 ¹⁶ atoms / cm ³ ). As described above, even in the same active layer, there is a large difference in the concentration of the catalytic element depending on the position (a difference of 100 to 1000 times).
Is also a feature of the present invention.

As described above, the active layer of the NTFT of the present invention is characterized in that it finally includes at least three types of impurity regions containing the same impurity at different concentrations in addition to the channel formation region. With such a structure, the channel formation region 102 to the first impurity region 103 and the second
It is possible to realize a configuration in which the impurity (element belonging to Group 15) concentration gradually increases as the distance from the impurity region 104 and the third impurity region 105 increases (the distance from the channel formation region increases).

The intention of the present applicant is to realize the concentration gradient in the LDD portion seen in the MOSFET as described in the conventional example by intentionally forming a plurality of impurity regions. Therefore, three or more impurity regions may exist.

A gate insulating film 106 is formed on the active layer thus formed. Also, the gate insulating film 1
The gate wiring 107 is provided on 06. As a material of the gate wiring 107, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), chromium (Cr), tungsten (W), tungsten nitride (WN), molybdenum (M
o), silicon (Si), aluminum (Al) or copper (C
A single metal layer such as u) or a laminated structure combining these may be used.

Typical examples of the laminated structure include Ta / Al and Ta / Ta
N, Ti / Al, Cu / W, Al / W, W / WN or W / Mo laminated structure. In addition, a structure provided with a metal silicide (specifically, Si / WSix, Si / TiSix, Si / CoSix or Si / MoSix
A structure in which conductive silicon such as Six and metal silicide are combined) may be used.

However, when forming the sidewall made of silicon, it is preferable that a material having a high etching selectivity with respect to silicon appears on the upper surface. This is to prevent the gate wiring from being etched during the formation of the sidewall. Otherwise,
When forming the sidewall, it is necessary to protect the upper surface with a protective film as a stopper.

As will be described later, in the CMOS circuit of the present invention, a structure in which the PTFT is not provided with a sidewall is effective. Therefore, since a step of removing only the sidewall is included later, it is necessary to select a material so that the gate wiring is not etched when the sidewall is removed. In that regard, the paper described in the conventional example has a structure in which the silicon gate and the silicon sidewall are in direct contact with each other.
The CMOS circuit of the present invention cannot be realized by using the structure of the same paper as it is.

At the time of the heat treatment in the gettering step, attention must be paid to the heat resistance of the gate wiring 107 (or 113). When a low melting point metal such as aluminum is included, the heat treatment temperature is limited. Further, since tantalum is very easily oxidized, it is necessary to provide a protective film such as a silicon nitride film to protect the tantalum from contact with the heat treatment atmosphere.

The silicon nitride film 108 shown in FIG. 1 is a protective film provided for that purpose. This silicon nitride film 1
It is effective to add a small amount of boron to 08.
By doing so, the thermal conductivity is increased, and a heat radiation effect can be provided.

A side wall 109 is provided on a side wall (side portion) of the gate wiring 107. In the present invention, a layer containing silicon as a main component as the sidewall 109 (specifically, a silicon layer or a silicon germanium layer)
Is used. In particular, it is desirable to use an intrinsic silicon layer. Of course, any of amorphous, crystalline, or microcrystalline may be used.

In the present invention, the side wall 109 is the first
Overlapping the impurity region 103 (the insulating film 10
6, the first impurity region 103 and the side wall 10
9 overlap). With such a structure, advantages such as the GOLD structure and the LATID structure of the MOSFET can be obtained.

In order to realize such a structure, the first impurity region 10 is formed by the side wall 109.
It is necessary to apply a voltage to 3. If the sidewalls are formed of an intrinsic silicon layer, the resistance value is high, but a leak current is generated to some extent, so that there is an advantage that a residual voltage due to the storage capacitance is not generated in the sidewall portions.

In the case of a TFT, the thickness of the active layer is 20
When operating, the depletion layer extends completely to the bottom of the active layer and is fully depleted (FD type: Fully-
Depression type). By making the FD type TFT a gate overlap type, an electric field is formed in a direction in which hot carriers are not easily generated. Conversely, if the FD type TFT has a general offset structure, an electric field may be formed in a direction to promote hot carrier injection.

With the above-described structure, the NTFT of the present invention can realize high reliability equal to or higher than that of the MOSFET. Also, sidewall 1
By applying a gate voltage to the first impurity region 103 by using the transistor 09, the same effect as in the gate overlap structure can be obtained.

Next, by arranging the first impurity region 103, the second impurity region 104, and the third impurity region 105, the impurity concentration gradually increases from the channel forming region 102 toward the source region (or drain region) 105. It is possible to realize a structure that is high. By doing this, T
The off current of the FT can be effectively suppressed.

Further, since the second impurity region 104 is provided at a certain distance from the gate voltage,
The effect of relaxing the electric field is obtained as in the overlapping portion of the MOSFET shown in FIG. In addition, since hot carriers generated in the first impurity region 103 are injected toward the sidewall 109 directly above, a trap level is not formed immediately above the channel formation region 102.

The above is the description of the NTFT of the present invention. However, a P-channel TFT (hereinafter referred to as PTFT) basically has a structure in which no LDD region or offset region is provided. Of course, a structure in which an LDD region or an offset region is provided may be used. However, since PTFT is inherently high in reliability, it is preferable to obtain ON current and balance the characteristics with NTFT. As shown in FIG.
This characteristic balance is particularly important when applied to a circuit. However, the structure of the present invention may be applied to a PTFT.

In FIG. 1, the active layer of the PTFT includes a channel forming region 110, a fourth impurity region 111, and a fifth impurity region 112. In this specification, the fourth impurity region 111 and the fifth impurity region 1
12 are distinguished from each other, but both actually function as a source region or a drain region of the PTFT.

At this time, in the fourth impurity region 111, an element selected from Group 13 (typically, boron) is 5 × 1.
It is added at a concentration of 0 ^{20 to} 5 × 10 ²¹ atoms / cm ³ .
This impurity concentration is represented by (p ⁺⁺ ) (in this specification, the p ⁺⁺ region is referred to as a fourth impurity region).

In the fifth impurity region 112, an element selected from Group 13 is present at the same concentration as in the fourth impurity region 111. Further, in this region, an element selected from Group 15 exists at the same concentration as the third impurity region 105. Therefore, the fifth impurity region 112 is referred to as an (n ⁺ , p ⁺⁺ ) region (the n ⁺ , p ⁺⁺ region is referred to as a fifth impurity region in this specification). However, since more elements belonging to Group 13 are added than elements belonging to Group 15, the P-type is still present.

That is, since the fifth impurity region 112 contains not only an element belonging to Group 13 but also an element belonging to Group 15 at a high concentration, a sufficient gettering effect is exhibited. Therefore, the catalyst element used for crystallization is also 1 × 10 ¹⁸ to 1 × 10 ²¹ atoms / cm ³ (typically, 5
It exists at a concentration of × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm ³ ).
Of course, the concentration of the catalyst element contained in the channel formation region 110 is 1/100 to 1/100 of the fifth impurity region 112.
0, and the concentration is 2 × 10 ¹⁷ atoms / cm ³ or less (typically, 1 × 10 ^{14 to} 5 × 10 ¹⁶ atoms / cm ³ ).

One of the features of the CMOS circuit according to the present invention is that the NTFT has the side wall 109 and the PTFT has the side wall removed so that it does not remain. This is because the NTFT has a gate overlap structure and the PTFT has a structure in which neither LDD nor offset is provided.

After the NTFT and PTFT are formed in this manner, the NTFT and PTFT are covered with the first interlayer insulating film 114, and the source wiring 115,
116 and a drain wiring 117 are provided. In the structure of FIG. 1, after these wirings are provided, a silicon nitride layer 118 is formed as a protective film to enhance the passivation effect.
A second interlayer insulating film 119 made of a resin material is provided on the silicon nitride layer 118. It is not necessary to use a resin material, but it is effective to use a resin material in order to secure flatness.

The CMOS circuit formed by combining NTFT and PTFT complementarily has been described as an example. However, the present invention can be applied to an NMOS circuit using NTFT or a pixel TFT formed by NTFT. is there. Of course, the present invention can be applied to a more complicated semiconductor circuit using a CMOS circuit as a basic unit.

The most characteristic point of the present invention is that NT
The FT LDD region is provided in multiple stages so that the impurity concentration increases as the distance from the channel formation region increases, and the catalytic element (element used for crystallization) in the channel formation region interferes with the electrical characteristics of the TFT. The point is that it has been reduced to a level that is not messy.

Therefore, as long as this structure is included, the TFT structure does not need to be limited, and the present invention can be applied to both top gate structure (typically, planar structure) and bottom gate structure (typically, inverted staggered structure). Can be applied.

(Advantages of NTFT Structure of the Present Invention) The NTFT of the present invention has a first impurity region (1st LDD region) and a second impurity region.
There is a structural feature in which a plurality of LDD regions are provided, such as an impurity region (2nd LDD region), and a gate electrode overlaps one of the LDD regions.

Here, the superiority of the present invention will be described in comparison with a conventional structure. FIGS. 32A and 32B show NTFTs without an LDD structure and their electrical characteristics (gate voltage Vg versus drain current Id characteristics). Similarly, FIGS. 32 (C) and (D) show the case of the normal LDD structure, FIGS. 32 (E) and (F) show the case of the so-called GOLD structure, and FIGS. 32 (G) and (H)
Shows the case of the NTFT of the present invention.

In the drawings, n ⁺ represents a source region or a drain region, channel represents a channel formation region, and n ⁻
Indicates an LDD region (n is a second LDD region). Also, I
d is a drain current, and Vg is a gate voltage.

As shown in FIGS. 32A and 32B, LDD
When there is no structure, the off-state current is high, and the on-state current (drain current when the TFT is in the on-state) and the off-state current are likely to deteriorate.

Next, in the case of the LDD structure, the off current is considerably suppressed, and the deterioration of both the on current and the off current can be suppressed.
However, the deterioration of the on-current is not completely suppressed. (FIGS. 32C and 32D)

Next, there is a structure in which the LDD region and the gate electrode overlap (FIGS. 32C and 32D).
This structure focuses on suppressing the deterioration of the ON current in the conventional LDD structure.

In this case, while the deterioration of the ON current can be sufficiently suppressed, there is a problem that the OFF current is slightly higher than that of the ordinary LDD structure. The paper described in the conventional example employs this structure, and the present invention recognized the problem of high off-state current and sought a structure to solve it.

The structure of the present invention is shown in FIG.
As shown in (H), the inner (closer to the channel forming region) LDD region overlaps with the gate electrode,
The outer LDD region was formed so as not to overlap with the gate electrode. By employing this structure, it is possible to reduce the off-current while maintaining the effect of suppressing the deterioration of the on-current.

The present applicant has guessed why the off-state current becomes high in the case of the structure shown in FIGS. 32 (E) and (F) as follows. This will be described with reference to FIG.

When the NTFT is off, a negative voltage such as minus several tens of volts is applied to the gate electrode 41. If a positive voltage of plus several tens of volts is applied to the drain region 42 in this state, an extremely large electric field is formed at the drain-side end of the gate insulating film 43.

At this time, as shown in FIG.
Holes 45 are induced in the region 44. An energy band diagram at this time is shown in FIG. That is, a current path is formed by minority carriers connecting the drain region 42, the LDD region 44, and the channel forming region 46. This current path was considered to cause an increase in off-state current.

The present applicant has considered that in order to cut off such a current path halfway, it is necessary to provide another resistor, that is, a second LDD region at a position not overlapping with the gate electrode. Thus, the structure of the present invention has been reached.

The configuration of the present invention as described above will be described in more detail with reference to the following embodiments.

[0073]

[Embodiment 1] In this embodiment, the CM shown in FIG.
A method for manufacturing an OS circuit is described with reference to FIGS.

First, a base film made of a silicon oxide film 302 was formed on a glass substrate 301 to a thickness of 200 nm. As the base film, a silicon nitride film may be stacked, or only a silicon nitride film may be used. As a film formation method, a plasma CVD method, a thermal CVD method, or a sputtering method may be used. Of course, adding boron to the silicon nitride film is effective in enhancing the heat radiation effect.

Next, an amorphous silicon film (amorphous silicon film) having a thickness of 50 nm was formed on the silicon oxide film 302 by a plasma CVD method, a thermal CVD method, or a sputtering method. Thereafter, the amorphous silicon film is crystallized using the technique described in JP-A-7-130652,
A semiconductor film including a crystal was formed. About this process, FIG.
This will be described with reference to FIG.

First, a silicon oxide film 502 was provided as a base film on a glass substrate 501, and an amorphous silicon film 503 was formed thereon. In this embodiment, the silicon oxide film 502 and the amorphous silicon film 503 are continuously formed by a sputtering method. Next, a nickel acetate solution containing nickel at 10 ppm by weight was applied to form a nickel-containing layer 504. (FIG. 5 (A))

In addition to the nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn),
One or more elements selected from elements such as lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold (Au), and silicon (Si) may be used.

Next, after a hydrogenation step at 500 ° C. for 1 hour, the mixture is heated at 500 ° C. to 650 ° C. for 4 to 24 hours (in this embodiment, 5 hours).
A heat treatment at 50 ° C. for 14 hours)
5 was formed. The polysilicon film 505 thus obtained
Has been found to have very good crystallinity.
(FIG. 5 (B))

At this time, however, nickel used for crystallization was present at a high concentration inside the polysilicon film 505. As a result of the SIMS measurement performed by the applicant, 1 × 10 ¹⁸
It was found that it was present at a concentration of １1 × 10 ¹⁹ atoms / cm ³ . Since this nickel can be easily silicided in the channel formation region, there is a concern that the nickel may function as a low-resistance current path (a path for leak current).

Incidentally, the present applicant has examined the electrical characteristics of the actual TFT.
It has been confirmed that T has no significant adverse effect on the electrical characteristics. However, it can be said that it is desirable to remove at least from the channel formation region as long as there is a possibility that it may have an adverse effect. The gettering process for that will be described later.

After forming the polysilicon film 505 in this manner, the polysilicon film 505 is patterned into an island shape, and the active layer 3 shown in FIG.
03 and 304 were formed.

After the formation of the polysilicon film 505, the crystallinity may be improved by irradiating the second, third and fourth harmonics of excimer laser light or YAG laser light. Alternatively, it may be performed after forming the active layers 303 and 304. A known technique may be used for the step of irradiating the excimer laser light, and thus the description is omitted.

Next, a gate insulating film 305 made of a silicon oxynitride film (represented by SiOxNy) is formed so as to cover the active layers 303 and 304, and a gate wiring (stacked structure of tantalum and tantalum nitride) is formed thereon. (Including gate electrode) 30
6, 307 were formed. (FIG. 3 (A))

The thickness of the gate insulating film 305 was 120 nm. Of course, in addition to the silicon oxynitride film, a silicon oxide film,
A stacked structure of a silicon oxide film and a silicon nitride film may be used. Further, other metals can be used for the gate wirings 306 and 307, but a material having a high etching selectivity with respect to silicon is preferable in consideration of a later step.

When the state shown in FIG. 3A is obtained,
A first phosphorus doping step (a step of adding phosphorus) was performed.
In this case, the acceleration voltage is set to be as high as 80 KeV because of the addition through the gate insulating film 305. The first impurity regions 308 and 309 thus formed were adjusted so that the length (width) was 0.5 μm and the phosphorus concentration was 1 × 10 ¹⁷ atoms / cm ³ . Note that arsenic could be used instead of phosphorus.

The first impurity regions 308 and 309 were formed in a self-aligned manner using the gate wirings 306 and 307 as a mask. At this time, an intrinsic polysilicon layer remains immediately below the gate wirings 306 and 307, and the channel formation region 31
0, 311 were formed. However, since there is a portion that is actually wrapped around the inside of the gate wiring and is added, the gate wirings 306 and 307 and the first impurity regions 308 and 309 are added.
And overlapped. (FIG. 3
(B))

Next, the gate wirings 306 and 307 are covered with 0.1 to 1 μm (typically 0.2 to 0.3 μm).
m) An amorphous silicon layer having a thickness of m) was formed, and sidewalls 312 and 313 were formed by performing anisotropic etching using a chlorine-based gas. Side wall 3
The width of each of 12, 12 and 313 (thickness as viewed from the side of the gate wiring) was 0.2 μm. (FIG. 3 (C))

In this embodiment, a sidewall made of an intrinsic silicon layer (undoped silicon layer) was formed because an amorphous silicon layer to which no impurity was added was used.

When the state shown in FIG. 3C was obtained, a second phosphorus doping step was performed. Also in this case, the acceleration voltage was set to 80 KeV as in the first time. In the second impurity regions 314 and 315 formed this time, phosphorus is 1 × 10 ¹⁸ atoms / cm 2.
^The dose was adjusted to be included at a concentration of ³ . .

In the phosphorus doping step shown in FIG. 3D, the first impurity regions 308 and 309 remain only under the sidewalls 312 and 313. That is, in this step, the first impurity region 103 shown in FIG. 1 was defined. The first impurity region 308 functions as a first LDD region of the NTFT.

In the step of FIG. 3D, phosphorus was also added to the side walls 312 and 313. Actually, the acceleration voltage is high, so the tail of the phosphorus concentration profile
Was distributed over the inside of the sidewall. The resistance component of the sidewalls can be adjusted by the phosphorus. On the other hand, if the concentration distribution of the phosphorus extremely varies, the gate voltage applied to the first impurity region 308 may be a factor that varies from element to element. Requires precise control.

Next, a resist mask 31 covering the NTFT is used.
6 was formed, and the side wall 313 of the PTFT was removed. Thereafter, a boron doping step (a step of adding boron) was performed. Here, the acceleration voltage was set to 70 KeV, and the dose was adjusted so that the formed fourth impurity region 317 contained boron at a concentration of 3 × 10 ²¹ atoms / cm ³ . The boron concentration at this time is represented by (p ⁺⁺ ). (FIG. 4
(A))

The first impurity region 309 and the second impurity region 315 formed on the PTFT side by this boron doping process are completely inverted to become P-type. The concentration of boron added at this time must be set higher than the concentration of phosphorus added in the third phosphorus doping step to be performed next. This will be described later.

Next, the resist mask 316 is removed,
New resist masks 318 and 319 were formed. Thereafter, a third phosphorus doping step was performed. Acceleration voltage is 90
KeV. In this embodiment, the third impurity region 320 is used.
And 5 × 10 ²⁰ atoms / cm of phosphorus in the fifth impurity region 321
^The dose was adjusted to be included at a concentration of ³ . (FIG. 4
(B))

In this step, phosphorus is not added to the portion shielded by the resist mask 318 (NTFT side), so that the second impurity region 314 remains in that portion. That is, the second impurity region 104 shown in FIG. 1 was defined by this process. At the same time, the third impurity region 105 shown in FIG. 1 was defined. This second impurity region 314
Function as a second LDD region, and the third impurity region 105
Function as a source region or a drain region.

Further, the fourth impurity region 317 remains below the portion shielded by the resist mask 319 in the active layer to be a PTFT. That is, the fourth impurity region 111 shown in FIG. 1 was defined by this process. At the same time, the fifth impurity region 112 shown in FIG. 1 was defined.

In this embodiment, the third impurity region 320
And the phosphorus concentration of the fifth impurity region 321 is at least 1 ×
10 ¹⁹ atoms / cm ³ or more (preferably 1 × 10 ^{20 to} 5 × 1
It is desirable to adjust the amount of phosphorus added so as to be 0 ²¹ atoms / cm ³ ). If the concentration is lower than this, the gettering effect by phosphorus may not be expected.

Since the concentration of phosphorus added in this step is lower than the concentration of boron added during the above-described boron doping, the fifth impurity region 321 remains P-type. Therefore, the fourth impurity region 317 and the fifth impurity region 3
21 may be considered as a source region or a drain region.

In this embodiment, the LD is applied to the PTFT.
Although neither the D region nor the offset region is formed, the PTFT
There is no problem because the reliability is originally high.
In some cases, it is convenient to provide no region or the like because the on-current can be increased.

Thus, finally, as shown in FIG. 4B, a channel forming region, a first impurity region, a second impurity region, and a third impurity region are formed in the active layer of the NTFT, and the active layer of the PTFT is formed. A channel forming region, a fourth impurity region and a fifth impurity region are formed in the semiconductor device.

When the state shown in FIG. 4B was obtained, the resist masks 318 and 319 were removed, and a silicon nitride film 322 was formed as a protective film. At this time,
The thickness of the silicon nitride film is 1 to 100 nm (typically 5 to 100 nm).
50 nm, preferably 10 to 30 nm).

Next, at 500 to 650 ° C. (typically 55
A heat treatment process was performed at a processing temperature of 0 to 600 ° C. for 2 to 24 hours (typically 4 to 12 hours). In this embodiment, the heat treatment is performed at 600 ° C. for 12 hours in a nitrogen atmosphere. (FIG. 4
(C))

This heat treatment step is performed in the first impurity region 30.
8, the impurities (phosphorus and boron) added to the second impurity region 314, the third impurity region 320, the fourth impurity region 317, and the fifth impurity region 321 are activated and, at the same time, remain in the channel formation regions 310 and 311. This is performed for the purpose of gettering nickel.

In this heat treatment step, the third impurity region 32
0 and phosphorus added to the fifth impurity region 321 are nickel.
Getter Kel. That is, nickel is in the direction of the arrow
To be captured by binding to phosphorus. So
Therefore, the third impurity region 323 shown in FIG.
Nickel is concentrated at a high concentration in the five impurity regions 324.
Was. Specifically, 1 × 10¹⁸~ 1 × 10
^{twenty one}atoms / cm^Three(Typically 5 × 10¹⁸~ 5 × 10¹⁹atoms
/cm^ThreeNickel was present at a concentration of. At the same time,
The nickel concentration in the tunnel formation regions 310 and 311 is 2 × 1
0¹⁷atoms / cm ^ThreeThe following (typically 1 × 10¹⁴~ 5 × 10
¹⁶atoms / cm^Three).

At this time, the silicon nitride film 322 provided as the protective film prevents the tantalum film used as the material of the gate wiring from being oxidized. Is the gate wiring difficult to oxidize?
There is no problem as long as the oxide film formed by oxidation is easily etched. However, the tantalum film is not only easily oxidized, but the tantalum oxide film is very difficult to be etched. Therefore, the silicon nitride film 322 is provided. That was desirable.

When the heat treatment step (gettering step) shown in FIG. 4C is completed, the first interlayer insulating film 325 is formed.
Was formed to a thickness of 1 μm. As the first interlayer insulating film 325, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment, an acrylic resin film is employed.

After forming the first interlayer insulating film 325, source wirings 326 and 327 and a drain wiring 328 made of a metal material were formed. In this embodiment, a laminated wiring having a structure in which an aluminum film containing titanium is sandwiched between titanium is used.

The first interlayer insulating film 325 is made of BCB.
When a resin film called (benzocyclobutene) is used, the flatness is improved and, at the same time, copper can be used as a wiring material. Copper is very effective as a wiring material because of its low wiring resistance.

After forming the source wiring and the drain wiring in this way, a 50 nm thick silicon nitride film 329 was formed as a passivation film. Further thereon, a second interlayer insulating film 330 was formed as a protective film. The same material as that of the first interlayer insulating film 325 can be used for the second interlayer insulating film 330. In this embodiment, a structure in which an acrylic resin film is laminated on a silicon oxide film having a thickness of 50 nm is employed.

Through the above steps, a CMOS circuit having a structure as shown in FIG. 4D is completed. In the CMOS circuit formed according to the present embodiment, NTFT has excellent reliability, and thus the reliability of the entire circuit is greatly improved. In addition, it has been found that the structure as in this embodiment improves the characteristic balance (balance of electric characteristics) between the NTFT and the PTFT, thereby making it difficult to cause an operation failure.

The influence of nickel (catalytic element) in the channel formation region, which was a concern when the technique described in Japanese Patent Application Laid-Open No. Hei 7-130652 was used, was evaluated by the gettering step shown in this embodiment. Solved by doing.

The structure described in this embodiment is merely an example, and need not be limited to the structures shown in FIGS. An important point in the present invention is the structure of the active layer of the NTFT, and the effects of the present invention can be obtained unless the point is different.

[Embodiment 2] In Embodiment 1, undoped-Si (intrinsic silicon layer or undoped silicon layer) without intentionally adding impurities is used as a sidewall.
In this embodiment, a phosphorus-doped silicon layer (n ⁺ -Si layer) or a boron-doped silicon layer (p ⁺ -
Si layer). Of course, it may be amorphous or crystalline,
Fine crystals were also good.

By using a silicon layer to which phosphorus or boron is added, the resistance of the sidewall portion is reduced as a whole,
It was possible to eliminate the possibility of characteristic fluctuation due to the phosphorus concentration profile fluctuation which was a concern in the process of FIG.

[Embodiment 3] In the embodiment 1, undoped-Si without intentionally adding impurities is used as the sidewall, but in this embodiment, any of carbon (C), nitrogen (N) and oxygen (O) is used. The resistance component of the sidewall was increased by using the silicon layer containing the silicon. Of course, the silicon layer was either amorphous, crystalline or microcrystalline. Also,
Oxygen was the best impurity used.

That is, when forming a silicon layer serving as a sidewall, 1 to 50 atomic% (typically, 10 to 30 atomic%) is used.
tomic%) of carbon, nitrogen or oxygen. In this embodiment, 20 atomic% of oxygen was added.

Since the resistance component caused by the side wall is increased by adopting the structure of this embodiment, the capacitance component using the side wall as a dielectric material is dominant with respect to the application of the gate voltage. And could be. In other words, an effective gate voltage can be applied to the side wall portion when driving at a high frequency.

[Embodiment 4] In this embodiment, a semiconductor film containing a crystal to be an active layer in the embodiment 1 is formed by the method described in
An example in which crystallization is performed using the technique described in JP-A-8329 will be described. Note that Japanese Patent Application Laid-Open No. 8-78329
The technique described in Japanese Patent Application Publication No. JP-A-2003-115873 enables selective crystallization of a semiconductor film by selectively adding a catalyst element. FIG. 6 illustrates a case where the technique is applied to the present invention.

First, a silicon oxide film 602 was provided on a stainless steel substrate 601, and an amorphous silicon film 603 and a silicon oxide film 604 were continuously formed thereon. At this time, the thickness of the silicon oxide film 604 was set to 150 nm.

Next, the opening 605 was selectively formed by patterning the silicon oxide film 604, and then a nickel acetate solution containing 100 ppm by weight of nickel was applied. The formed nickel-containing layer 606 has openings 60.
5 was in contact with the amorphous silicon film 602 only at the bottom. (FIG. 6 (A))

Next, a heat treatment was performed at 500 to 650 ° C. for 4 to 24 hours (in this embodiment, 580 ° C. for 14 hours) to crystallize the amorphous silicon film. In this crystallization process, the portion in contact with nickel is first crystallized, and crystal growth proceeds in a direction substantially parallel to the substrate. It has been confirmed crystallographically that it proceeds in the <111> axis direction.

The polysilicon film 607 thus formed
Since the rod-shaped or needle-shaped crystals are aggregated, and each rod-shaped crystal macroscopically grows in a specific direction, there is an advantage that the crystallinity is uniform.

In the technology described in the above publication, germanium (Ge) and iron (F) are also used in addition to nickel (Ni).
e), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold (Au), silicon (Si) A plurality of elements can be used.

A semiconductor film including a crystal (including a polysilicon film and a polysilicon germanium film) may be formed by using the above-described technique, and may be patterned to form an active layer formed of a semiconductor film including a crystal. . Subsequent steps may follow the first embodiment. Of course, a combination with the second and third embodiments is also possible.

When a TFT is manufactured using a semiconductor film containing a crystal crystallized by using the technique of this embodiment, high field-effect mobility (mobility) can be obtained, but high reliability is required. . However, the T of the present invention
By adopting the FT structure, it is possible to manufacture a TFT that makes full use of the technology of this embodiment.

[Embodiment 5] This embodiment is different from Embodiment 1 in Japanese Patent Application Laid-Open No. 10-135468 or
An example in which the techniques described in JP-A-135469 are combined will be described.

The technique described in the publication is a technique for removing nickel used for crystallization of a semiconductor by using gettering action of a halogen element (typically chlorine) after crystallization. By using this technique, the nickel concentration in the active layer is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less (preferably 1 × 10 ¹⁶ ato
ms / cm ³ or less).

The structure of this embodiment will be described with reference to FIG. First, a quartz substrate 701 having high heat resistance was used as a substrate. Of course, a silicon substrate or a ceramic substrate may be used. When a quartz substrate is used, there is no contamination from the substrate side even if a silicon oxide film is not provided as a base film.

Next, a polysilicon film (not shown) was formed using the means of Example 1 or Example 4 and patterned to form active layers 702 and 703. Further, the gate insulating film 70 made of a silicon oxide film covers the active layers.
4 was formed. (FIG. 7 (A))

After forming the gate insulating film 704, heat treatment was performed in an atmosphere containing a halogen element. In this embodiment, the processing atmosphere is an oxidizing atmosphere in which oxygen and hydrogen chloride are mixed, the processing temperature is 950 ° C., and the processing time is 30 minutes. The processing temperature may be selected from 700 to 1150 ° C (typically 800 to 1000 ° C), and the processing time may be selected from 10 minutes to 8 hours (typically 30 minutes to 2 hours). Just choose. (FIG. 7 (B))

At this time, nickel becomes volatile nickel chloride and is released into the processing atmosphere, and the nickel concentration in the polysilicon film is reduced. Therefore, the nickel concentration contained in the active layers 705 and 706 shown in FIG.
It was reduced to 10 ¹⁷ atoms / cm ³ or less.

An active layer is formed by using the present embodiment having the above-described technique, and the subsequent steps may be in accordance with the first embodiment. Of course, a combination with any of the second to fifth embodiments is also possible. In particular, it has been found that the combination of this embodiment and the fourth embodiment can realize a polysilicon film having extremely high crystallinity.

(Knowledge on Crystal Structure of Active Layer) The active layer formed in accordance with the above-described manufacturing process has a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) gathered and arranged microscopically. It has a crystal structure. This is TEM
(Transmission electron microscopy) could be easily confirmed.

In addition, electron diffraction and X-ray (X-ray)
Using diffraction, it was confirmed that the main orientation plane was the {110} plane, although the surface of the active layer (portion forming the channel) contained some deviation in the crystal axis. As a result of the applicant's detailed observation of an electron beam diffraction photograph with a spot diameter of about 1.5 μm, diffraction spots corresponding to the {110} plane clearly appear, but each spot has a distribution on a concentric circle. confirmed.

Further, the present applicant has observed by HR-TEM (high-resolution transmission electron microscopy) the grain boundaries formed by the contact of individual rod-shaped crystals, and found that the crystal lattices at the grain boundaries have continuity. It was confirmed. This was easily confirmed from the fact that the observed lattice fringes were continuously connected at the crystal grain boundaries.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

In particular, the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

As a result of the applicant's detailed observation of the polysilicon film obtained by carrying out the present invention by using a TEM, it was found that most (90% or more, typically 95% or more) of the crystal grain boundary was $ 3.
, That is, a {211} twin grain boundary.

In a grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3.

In the polysilicon film of this embodiment, the lattice fringes of the adjacent crystal grains at the crystal grain boundary are continuous at an angle of about 70.5 °.
We arrived at the conclusion that it was a 1｝ twin grain boundary.

When θ = 38.9 °, a corresponding grain boundary of Σ9 is obtained, but such other crystal grain boundaries also exist.

Such corresponding grain boundaries are formed only between crystal grains having the same plane orientation. That is, since the polysilicon film obtained by carrying out this embodiment has a plane orientation of approximately {110}, such a corresponding grain boundary can be formed over a wide range.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, it can be considered that the semiconductor thin film having such a crystal structure has substantially no crystal grain boundary.

Further, it has been confirmed by TEM observation that the defects existing in the crystal grains have almost disappeared by the heat treatment step at a high temperature of 700 to 1150 ° C. This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, the spin density of the polysilicon film manufactured according to the manufacturing process of this embodiment is at least 5 × 10 17 spins / cm 3 or less (preferably 3 × 10 17 spins / cm 3).
pins / cm3 or less). However,
Since this measurement is close to the detection limit of existing measuring equipment,
The actual spin density is expected to be even lower.

As described above, since the polysilicon film obtained by carrying out this embodiment has substantially no crystal grains and no crystal grain boundaries, it is a single crystal silicon film or a substantially single crystal silicon film. You can think. The present applicant has applied a polysilicon film having such a crystal structure to a CGS (Continuous Gr
ain Silicon).

Descriptions on CGS are described in Japanese Patent Application Nos. 10-044659 and 10-152316 by the present applicant.
No., Japanese Patent Application No. 10-152308 or Japanese Patent Application No. 10-1
No. 52305 may be referred to.

(Knowledge Regarding Electrical Characteristics of TFT) The TFT manufactured in this example exhibited electrical characteristics comparable to those of the MOSFET. The following data is obtained from the TFT prototyped by the present applicant.

(1) The sub-threshold coefficient as an index of the switching performance (the agility of switching on / off operation) is 60 to 100 mV / decade (typically 60 to 85 mV) for both the N-channel TFT and the P-channel TFT. / decade)
And small. (2) The field effect mobility (μFE) as an index of the operation speed of the TFT is 200 to 650 cm 2 / Vs for the N-channel TFT.
(Typically 300-500cm2 / Vs), P-channel type TF
100-300cm2 / Vs at T (typically 150-200cm2 / Vs
) And big. (3) The threshold voltage (V
th) is as small as -0.5 to 1.5 V for an N-channel TFT and -1.5 to 0.5 V for a P-channel TFT.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

(Knowledge Regarding Circuit Characteristics) Next, the frequency characteristics of a ring oscillator manufactured using the TFT formed by carrying out the present embodiment will be described. The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered stage ring shape, and is used to determine a delay time per one stage of the inverter circuit. The configuration of the ring oscillator used in the experiment is as follows. Number of steps: 9 Steps Thickness of gate insulating film of TFT: 30 nm and 50 nm Gate length of TFT: 0.6 μm

As a result of examining the oscillation frequency with this ring oscillator, it was possible to obtain an oscillation frequency of 1.04 GHz as the maximum value. Further, a shift register, which is one of the TEGs of the LSI circuit, was actually manufactured, and the operating frequency was confirmed. As a result, the thickness of the gate insulating film was 30 nm, and the gate length was 0.6.
An output pulse with an operating frequency of 100 MHz was obtained in a shift register circuit of 50 μm, a power supply voltage of 5 V, and 50 stages.

The surprising data of the ring oscillator and the shift register as described above is that the TFT of this embodiment is a MOS transistor.
Performance comparable to or superior to FET (electrical characteristics)
Has been shown.

[Embodiment 6] In the present invention, the catalytic element used for crystallization is gettered by using the portion to be the source region or the drain region of the active layer. It is also possible to getter the catalytic element from the semiconductor film including the crystal.

In that case, Japanese Patent Application Laid-Open No.
-270363 or JP-A-10-247735
It is preferable to use the technology described in Japanese Patent Application Laid-Open No. H10-260,000.

The technique described in the above publication is to selectively add an element belonging to Group 15 (typically, phosphorus) into a semiconductor film including a crystal and to make the region function as a gettering region. .

By combining this embodiment with the gettering technique shown in Embodiment 1, it becomes possible to further reduce the amount of the catalytic element remaining in the channel formation region. Note that the technology of the present embodiment may be combined with the technology of the fifth embodiment. Further, combinations with the embodiments 2 to 4 are also possible.

[Embodiment 7] In this embodiment, a case where the third impurity region and the fifth impurity region are formed in a step different from that of the first embodiment will be described with reference to FIGS.

First, according to the steps of Embodiment 1, FIG.
Before the phosphorus doping process. In this embodiment, after forming the resist masks 318 and 319, the gate insulating film 305 is etched to form the gate insulating films 801 and 802.

Then, a phosphorus doping step was performed in this state. In the case of this embodiment, since the phosphorus is directly added to the exposed active layer, the acceleration voltage is set to be as low as 10 keV.

Thus, a third impurity region 803 and a fifth impurity region 804 were formed. Note that the third and fifth impurity regions contain phosphorus at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ (typically, 1 × 10 ^{20 to} 5 × 10 ²⁰ atoms / cm ³ ). The dose was adjusted as described above. (FIG. 8A)

Thereafter, after removing the resist masks 318 and 319, a silicon nitride film 805 was formed and a heat treatment step for gettering was performed. Embodiment 1 may be referred to for the conditions of this heat treatment step. (FIG. 8
(B))

By this heat treatment step, nickel collects in the third impurity region 803 and the fifth impurity region 804, and 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ³ (typically 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ³ ).
The third impurity region 806 and the fifth impurity region 80 containing nickel at a concentration of × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm ³ )
7 was formed. These regions function as electrodes connecting the TFT and each wiring. The relationship between the nickel concentration and the channel formation region is as described above.

The subsequent steps may be in accordance with the first embodiment.
The basic structure is similar to that of FIG. 1 or FIG. In the case of the present embodiment, the gate insulating film of the NTFT finally contacts the channel forming region, the first impurity region and the second impurity region, and does not contact the third impurity region.
Another feature is that the gate insulating film of the PTFT is in contact with the channel formation region and the fourth impurity region but not with the fifth impurity region.

The structure of this embodiment can be freely combined with any of the embodiments 2 to 6.

[Eighth Embodiment] In this embodiment, the step of forming the silicon nitride film 322 used in the gettering step (FIG. 4C) shown in the first embodiment is performed at a different point from the first embodiment. An example is shown in FIG.

First, the steps up to the step shown in FIG. 3B are performed according to the steps of the first embodiment, and thereafter, 1 to 10 nm (preferably 2 to 5 nm).
nm) thick silicon nitride film 901 was provided. If the thickness of the silicon nitride film 901 is too large,
Therefore, it is preferable to make the gate overlap structure thinner, since it becomes impossible to realize the gate overlap structure. However, care must be taken so that the effect of preventing oxidation of the gate wiring (in the case of tantalum) is not impaired in the subsequent heat treatment step.

Then, an amorphous silicon film (not shown) was formed on the silicon nitride film 901, and side walls 902 and 903 were formed by anisotropic etching.
(FIG. 9A)

It is to be noted that the configuration of the side walls 902 and 903 can be configured as in the second or third embodiment.

Next, a phosphorus addition step was performed in the state of FIG. 9A to form a second impurity region 904. The conditions for adding phosphorus may be substantially the same as those in Embodiment 1, but it is desirable to optimize the acceleration voltage and the like in consideration of the thickness of the silicon nitride film 901. Although not shown, at this time, the second impurity region was also formed on the PTFT side.

After forming the second impurity region 904, a resist mask 905 was formed, and a boron doping process was performed. The conditions at this time may be almost the same as those in the first embodiment, but it is necessary to consider the thickness of the silicon nitride film 901. Thus, the second impurity region (not shown) formed in the above-described phosphorus doping step is inverted to P-type, and the fourth impurity region 906 is formed.
Was formed. (FIG. 9 (B))

Next, the resist mask 905 was removed, and new resist masks 907 and 908 were formed. Then, in this state, a phosphorus addition step was performed again to form a third impurity region 909 and a fifth impurity region 910. The doping condition may be in accordance with the first embodiment, but it goes without saying that the thickness of the silicon nitride film is taken into consideration. (FIG. 9 (C))

Next, after removing the resist masks 907 and 908, a heat treatment step for gettering was performed under the same conditions as in the first embodiment. After this heat treatment step, the third impurity region 911 and the fifth impurity region 912 have 1 × 10 ¹⁷ to
1 × 10 ²⁰ atoms / cm ³ (typically 1 × 10 ^{18 to} 5 × 1
Nickel was present at a concentration of 0 ¹⁹ atoms / cm ³ ). The relationship between the nickel concentration and the channel formation region is as described above.

After the above steps, the same steps as in the first embodiment were sequentially performed to complete the CMOS circuit. The structure of the CMOS circuit manufactured according to this embodiment and the structure of the CMOS circuit shown in FIG. 1 are the same except for the point where the silicon nitride film 901 is formed.

The structure of this embodiment can be freely combined with any of the structures of the second to seventh embodiments.

[Embodiment 9] In this embodiment, an example in which Embodiments 7 and 8 are combined will be described with reference to FIG.

First, the steps up to the step of phosphorus doping of FIG. Thus, the silicon nitride film 901 and the gate insulating film (not shown) were etched using the resist masks 907 and 908 as masks to form gate insulating films 11 and 12 and silicon nitride films 13 and 14.

After the etching of the silicon nitride film and the gate insulating film is completed, a step of adding phosphorus is performed according to the conditions of the seventh embodiment, and the third impurity region 15 and the fifth impurity region 1 are formed.
6 was formed. (FIG. 10A)

Next, the resist masks 907 and 908 are removed.
After removal, getters were obtained under the same conditions as in Example 7 (Example 1).
A heat treatment step for the ring was performed. This heat treatment process
After that, the third impurity region 17 and the fifth impurity region 18 have 1
× 10¹⁷~ 1 × 10²⁰atoms / cm ^Three(Typically 1 × 10
¹⁸~ 5 × 10¹⁹atoms / cm^Three) Concentration of nickel
Was. The relationship between the nickel concentration and the channel formation region has already been described.
It is exactly as stated.

After the above steps, the same steps as those of the first embodiment are sequentially performed to complete the CMOS circuit. The structure of the CMOS circuit manufactured according to this embodiment and the structure shown in FIG. 1 are the same except for the shape of the silicon nitride film covering the gate wiring and the shape of the gate insulating film.

The structure of this embodiment can be freely combined with any of the structures of the second to sixth embodiments.

[Embodiment 10] In the embodiment 1, the CMOS circuit has been described as an example. In this embodiment, a case where the present invention is applied to a pixel matrix circuit in an active matrix type liquid crystal display panel will be described. FIG. 12 is used for the description. Note that AA ′ in FIG.
12B corresponds to FIG. 12B, and an equivalent circuit thereof corresponds to FIG. 12C. Further, since the pixel TFT shown in FIG. 12B has a double gate structure in which NTFTs having the same structure are connected in series, only one of them will be described with reference numerals.

First, according to the process of the first embodiment, the substrate 14
The base film 1401, the channel formation region 1402,
First impurity region 1403, second impurity region 1404, third impurity regions 1405 and 1406, gate insulating film 140
7, a gate wiring 1409, a sidewall 1408, a silicon nitride film 1410, a first interlayer insulating film 1411, a source wiring 1412, and a drain wiring 1413 were formed.

Then, a silicon nitride film 1414 as a passivation film and a second interlayer insulating film 1415 are formed on each wiring.
And formed. Further, a third interlayer insulating film 141 is further formed thereon.
6, and a pixel electrode 1418 made of a transparent conductive film such as ITO or SnO ₂ was formed. Reference numeral 1417 denotes a pixel electrode.

The capacitor portion has a capacitor wiring 1422 as an upper electrode and an undoped silicon layer (intrinsic semiconductor layer or 1).
A semiconductor layer to which boron is added at a concentration of × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ) 1419 and an impurity region 1420 (first semiconductor layer).
The insulating film 1421 (extending from the gate insulating film 1407) is formed between the lower electrode including the impurity region 1403 and the same concentration of phosphorus. Note that the capacitance wiring 142
2 was formed simultaneously with the gate wiring 1409 of the pixel TFT, and was connected to ground or a fixed voltage.

The insulating film 1421 was made of the same material as the gate insulating film 1407 of the pixel TFT. Also,
The undoped silicon layer 1419 was made of the same material as the channel forming region 1402 of the pixel TFT.

As described above, the pixel TFT is formed on the same substrate.
, The capacitor part and the CMOS circuit were simultaneously manufactured and integrated. In this embodiment, as an example, a transmission type LC
Although D has been described as an example, it is needless to say that the present invention is not limited to this.

For example, a reflective LCD can be manufactured by using a reflective conductive material as the material of the pixel electrode and changing the pattern of the pixel electrode or adding / deleting some steps as appropriate. .

In this embodiment, the gate wiring of the pixel TFT of the pixel matrix circuit has a double gate structure. However, a multi-gate structure such as a triple gate structure may be used in order to reduce variation in off current. Further, a single gate structure may be used to improve the aperture ratio.

The structure of this embodiment can be freely combined with any of the structures of the first to ninth embodiments.

[Embodiment 11] In this embodiment, the tenth embodiment will be described.
FIG. 13 shows an example in which a capacitance portion having a structure different from that of FIG.
Since the basic configuration is almost the same as that of the tenth embodiment, only the differences will be described. The capacitor portion of this embodiment includes an impurity region (including phosphorus having the same concentration as the second impurity region) 1502 connected to the third impurity region 1501, an insulating film 1503 extending from the gate insulating film, and a capacitor wiring 1504. It is formed with.

Further, a black mask 1505 was provided on the TFT forming side substrate. Note that the capacitor wiring 1504 is connected to the pixel TF
It is formed simultaneously with the source wiring and drain wiring of T, and is connected to ground or a fixed voltage. In this way, the pixel TFT, the capacitor, and the CMOS circuit can be simultaneously manufactured and integrated on the same substrate. Of course, Examples 1 to
Combinations with any of the nine embodiments are possible.

[Embodiment 12] In this embodiment, Embodiment 1 will be described.
FIG. 14 shows an example in which a capacitance portion different from 0 and 11 is formed. Since the basic configuration is almost the same as that of the tenth embodiment, only the differences will be described. First, a second interlayer insulating film 1602 and a black mask 1603 made of a light-shielding conductive material were formed according to Example 1. Further, a third interlayer insulating film is formed thereon, and ITO, SnO
_A pixel electrode 1604 made of a transparent conductive film such as ₂ was formed.

The black mask 1603 corresponds to the pixel TF
The T part is covered, and the drain wiring 1601 and the capacitance part are formed. At this time, the dielectric of the capacitance part is the second interlayer insulating film 1602. Further, a part of the second interlayer insulating film 1602 is etched to expose the silicon nitride film 1605 provided as a passivation film,
It is also possible to adopt a structure using only 05 as a dielectric.

As described above, the pixel TFT is formed on the same substrate.
, A capacitor portion, and a CMOS circuit can be simultaneously manufactured and integrated. Of course, a combination with any of the first to ninth embodiments is also possible.

[Embodiment 13] This embodiment will be described with reference to FIG. In this embodiment, the back gate electrodes 1702 and 1703 are formed below the channel forming region of the pixel TFT with the insulating film 1701 interposed therebetween. Note that the back gate electrode here is an electrode provided for the purpose of controlling a threshold voltage or reducing off-state current, and is provided on the opposite side of a gate wiring with an active layer (channel formation region) interposed therebetween. Means a pseudo gate electrode.

The back gate electrodes 1702 and 1703 can be used without any problem as long as they are conductive materials. However, in the present invention, 550 to 650 are required in the step of gettering the catalytic element.
Since there is a heat treatment process at about ° C, heat resistance that can withstand the temperature is required. For example, it is effective to use a silicon gate electrode using a polysilicon film (either intrinsic or doped with impurities).

Since the insulating film 1701 functions as a gate insulating film of the back gate electrode, an insulating film with good quality and few pinholes is used. Although a silicon oxynitride film is used in this embodiment, a silicon oxide film or a silicon nitride film can be used instead. However, TF
Since T is manufactured, a material that can realize a flat surface as much as possible is desirable.

In this embodiment, the back gate electrode 1702,
By applying a voltage to 1703, the electric field distribution in the channel formation region is electrically changed, so that the threshold voltage can be controlled and the off-state current can be reduced. In particular, it is effective for the pixel TFT as in this embodiment.

The structure of this embodiment can be freely combined with any of the first to twelfth embodiments.

[Embodiment 14] This embodiment will be described with reference to FIG. This embodiment is an example in which the gate insulating film and the protective film are different from the structure shown in the embodiment. Note that FIG. 16 shows a cross-sectional view, and a diagram viewed from above corresponds to FIG. In FIG. 16, reference numeral 401 denotes a substrate having an insulating surface.

The active layer of the NTFT is composed of the channel formation region 4
02, a pair of first impurity regions 403, a pair of second impurity regions 404, and a pair of third impurity regions 405.

The channel formation region 402 (409 also
The same) is an intrinsic semiconductor layer or 1 × 10 ¹⁶~ 5 × 10¹⁸atom
s / cm^ThreeAnd a semiconductor layer to which boron is added at a concentration of

The gate insulating films 406 and 411 are formed on the active layer thus formed. In the case of FIG. 16, the gate insulating film 406 is formed so as to overlap the second impurity region 404. This is a process structure when the second impurity region 404 is formed. In other words, the gate insulating film 406 includes the channel formation region 402, the first impurity region 403, and the second impurity region 4.
04 is provided.

The gate wirings 407 and 412 are provided on the gate insulating films 406 and 411. Note that it is preferable to form a protective film so that the gate wiring can withstand heat treatment.

Further, reference numeral 408 denotes a side wall, 413 denotes a protective film, 414 denotes a first interlayer insulating film, and 415 and 416.
Is a source wiring, 417 is a drain wiring, 418 is a silicon nitride layer, and 419 is a second interlayer insulating film.

An example of a process for obtaining the structure shown in FIG. 16 will be described below with reference to FIGS. Note that the top view is the same as FIG.

First, in the same manner as in Embodiment 1,
A base film made of a silicon oxide film 1002 was formed thereon to a thickness of 200 nm. Note that as the substrate 1001, for example, a glass substrate or a quartz substrate can be used.

Next, an amorphous silicon film (amorphous silicon film) having a thickness of 30 nm was formed on the silicon oxide film 1002 by a plasma CVD method in the same manner as in Example 1, and after a dehydrogenation treatment, a catalytic element was used. Polycrystalline silicon film (crystalline silicon film or polycrystalline silicon film) by thermal crystallization
Was formed.

Next, the crystalline silicon film was patterned to form active layers 1003 and 1004 made of island-shaped silicon layers as shown in FIG. After forming the polysilicon film, the crystallinity may be improved by irradiating an excimer laser beam. Alternatively, it may be performed after the formation of the active layers 1003 and 1004. A known technique may be used for the step of irradiating the excimer laser light, and thus the description is omitted.

Next, the active layer 100 is formed in the same manner as in the first embodiment.
3, 1004, a gate insulating film 1005 made of a silicon oxide film is formed, and a gate wiring (including a gate electrode) 10 having a laminated structure of tantalum and tantalum nitride is formed thereon.
06 and 1007 were formed. Gate insulating film 10 here
The film thickness of 05 was 100 nm. (FIG. 17A)

When the state shown in FIG. 17A was obtained, a first phosphorus doping step (a step of adding phosphorus) was performed in the same manner as in Example 1. The first impurity regions 1008 and 1009 thus formed have a length (width) of 0.5.
The dose was adjusted so that the concentration was 1 μm and the phosphorus concentration was 1 × 10 ¹⁷ atoms / cm ³ . As in the first embodiment, the phosphorus concentration at this time is represented by (n−).

The first impurity regions 1008 and 1009 were formed in a self-aligned manner using the gate wirings 1006 and 1007 as masks. At this time, an intrinsic crystalline silicon layer remains immediately below the gate wirings 1006 and 1007, and channel formation regions 1010 and 1011 were formed. However, actually, there is a part that is added around the inside of the gate wiring, so that the structure is such that the gate wirings 1006 and 1007 and the first impurity regions 1008 and 1009 overlap. (FIG. 17B)

Next, as in the first embodiment, the gate wiring 1
An amorphous silicon layer having a thickness of 0.1 to 1 μm (typically 0.2 to 0.3 μm) is formed so as to cover 006 and 1007, and anisotropic etching is performed to form a side wall 1012. , 1013 were formed. The width of the side walls 1012 and 1013 (the thickness as viewed from the side wall of the gate wiring) was 0.2 μm. (FIG. 17C)

In this embodiment, as in the first embodiment, since an amorphous silicon layer to which no impurity is added is used, a sidewall made of an intrinsic silicon layer is formed.

When the state shown in FIG. 17C is obtained, the embodiment will be described.
A second phosphorus doping step was performed in the same manner as in 1. this
In this case, the acceleration voltage was set to 80 KeV as in the first time. Ma
The second impurity regions 1014 and 1015 formed this time
Has 1 × 10 phosphorus¹⁸atoms / cm ^ThreeAt a concentration of
The dose was adjusted. The phosphorus at this time is the same as in the first embodiment.
Let the concentration be represented by (n).

In the phosphorus doping step shown in FIG. 17D, the first impurity regions 1008 and 1009 remain only under the sidewalls 1012 and 1013. That is, in this step, the first impurity region 403 shown in FIG. 16 was defined.
This first impurity region 403 functions as a 1st LDD region.

Next, a resist mask 1016 covering a part of the NTFT and a resist mask 1016 covering a part of the PTFT
17 was formed. Then, in this state, the gate insulating film 10 is formed.
Gate insulating film 1 processed by dry etching 05
018 was formed. (FIG. 17E) At this time, the PTFT
A resist mask 10 covering a part of the PTFT
17, the distance X (1 to 2) shown in FIG.
0 μm, typically 2 μm) to expose the edge of the active layer.

At this time, the length of the portion where the gate insulating film 1018 protrudes outside the sidewall 1012 (the gate insulating film 1018 is
16) determines the length (width) of the second impurity region 404 shown in FIG. Therefore, mask alignment of the resist masks 1016 and 1017 needs to be performed with high accuracy. Conventionally, since there was only one LDD region, variations in the width greatly affected the electrical characteristics. However, in the present embodiment, since there are substantially two LDD regions, the second impurity region has A slight variation in width did not matter.

When the state shown in FIG. 17E was obtained, a third phosphorus doping step was performed. In this case, since the phosphorus is added to the exposed active layer, the acceleration voltage is set to be as low as 10 KeV. Note that phosphorus formed in the third impurity regions 1019 and 1020 thus formed is 5 × 10 ²⁰ atoms / cm ^3.
The dose was adjusted so as to be contained at a concentration of. The phosphorus concentration at this time is represented by (n +). (FIG. 18
(A))

In this step, since phosphorus is not added to the portion shielded by the resist mask 1016, the second impurity region 1014 remains in that portion. Therefore, the second impurity region 404 shown in FIG. 16 is defined here. At the same time, the third impurity region 405 shown in FIG. 16 was defined.

The second impurity region 1014 has a 2nd LDD
The third impurity region 405 functions as a source region or a drain region.

In the present embodiment, the third impurity region 101
The concentration of 9, 1020 is at least 1 × 10 ¹⁹ atoms / cm ³
(Preferably 1 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm ³ )
It is desirable to adjust the amount of phosphorus added so that
If the concentration is lower than this, an effective gettering effect by phosphorus may not be expected.

Next, resist masks 1016 and 1017
Is removed, and the protective film 10 covering the entire NTFT and PTFT is removed.
21 was formed. At this time, the silicon nitride film provided as the protective film 1021 prevents the tantalum film used as the material of the gate wiring from being oxidized. There is no problem as long as the gate wiring is not easily oxidized or the oxide film formed by oxidation is easily etched, but the tantalum film is not only easily oxidized, but also the tantalum oxide film is very difficult to etch. Therefore, it is desirable to provide the silicon nitride film 1021. Instead of the silicon nitride film 1021, a silicon oxide film, a silicon nitride oxide film, or a stacked film thereof can be used.
30 nm, preferably 5 to 20 nm (in this embodiment, the film thickness is 10
nm silicon nitride film). A silicon nitride film containing boron by a sputtering method (using a silicon target containing boron and using an Ar gas and a nitrogen gas) is preferable because it has a high thermal conductivity and functions as a heat dissipation layer.

Next, at 500-650 ° C., typically 5
The heat treatment was performed at 50 to 600 ° C. for 2 to 24 hours, typically 4 to 12 hours (in this example, at 600 ° C. for 12 hours in a nitrogen atmosphere). (FIG. 18B) This heat treatment removes nickel remaining in the active layer. In the present embodiment, as a technique for removing nickel, a technique described in JP-A-10-270363 was used. JP-A-10-27036
The technique described in Japanese Patent Publication No. 3 is a technique for removing nickel used for crystallization of a semiconductor after crystallization by using a gettering action of an element belonging to Group 15 (typically, phosphorus). The catalyst element (nickel in this embodiment) remaining in the active layer by this heat treatment moves in the direction of the arrow and is captured (gettered) in the third impurity regions 1019 and 1020. However, before heat treatment,
1 × 10 ¹⁹ atoms / cm in impurity regions 1019 and 1020
³ or more, preferably 1 × 10 ^{20 to} 5 × 10 ²¹ atoms
It is necessary to contain phosphorus at a concentration of / cm ³ . These third impurity regions 1019 and 1020 are called gettering regions.

The channel region 1 thus formed is
The nickel concentration contained in 010 and 1011 is 2 × 10
¹⁷ atoms / cm ³ or less, typically 1 × 10 ^{14 to} 5 × 10 ¹⁶ a
It has been reduced to toms / cm ³ . The third impurity region 10
The nickel concentration contained in 19 and 1020 is 1 × 10 ¹⁸
１1 × 10 ²¹ atoms / cm ³ , typically 5 × 10 ¹⁸ -5 ×
10 ¹⁹ atoms / cm ³ . Further, impurities (phosphorus and boron) in the film can be activated by this heat treatment. Note that since the upper portions of the gate wirings 1006 and 1007 are in contact with the silicon nitride film 1021 and the side portions of the wiring are in contact with the sidewalls 1012 and 1013, there is almost no deterioration (oxidation or the like) of the wiring due to heat treatment.

Next, a resist mask 1022 covering the entire NTFT was formed. Then, first, the silicon nitride film 1021 of the PTFT was removed. (FIG. 18 (C))

Subsequently, the side wall 101 of the PTFT
The third and third impurity regions 1020 were removed. (FIG. 18
(D)) The width of the active layer of the PTFT is determined by this removing step.

Further, the gate insulating film 1005 was dry-etched to form a gate insulating film 1023 having the same shape as the gate wiring 1007. (FIG. 19A) Here, the base film is also etched at the same time, but is not shown.

When the state shown in FIG. 19A was obtained, a boron doping step (a step of adding boron) was performed. Here, the acceleration voltage is set to 10 KeV, and the formed fourth impurity region 10 is formed.
The dose was adjusted so that 24 contained boron at a concentration of 3 × 10 ²¹ atoms / cm ³ . The boron concentration at this time is (p
++). (FIG. 19B)

At this time, since boron was also added to the inside of the gate wiring 1007 and added, the channel formation region 10
Reference numeral 11 is formed inside the gate wiring 1007. Also,
In this step, the first impurity region 1009 and the second impurity region 1015 formed on the PTFT side are inverted with boron to be P-type. Therefore, actually the first
Although the resistance value changes between the portion that was the impurity region and the portion that was the second impurity region, there is no problem because boron is added at a sufficiently high concentration.

Thus, the fourth impurity region 410 shown in FIG. 16 is defined. The fourth impurity region 1024 is formed in a completely self-aligned manner using the gate wiring 1007 as a mask, and functions as a source region or a drain region. In this embodiment, neither the LDD region nor the offset region is formed with respect to the PTFT. However, the PTFT is inherently high in reliability, so that there is no problem. May be better.

As a result, as shown in FIG. 19B, a channel forming region, a first impurity region, a second impurity region, and a third impurity region are finally formed in the active layer of the NTFT, and the active layer of the PTFT is formed. Only the channel formation region and the fourth impurity region are formed.

When the state shown in FIG. 19B was obtained in this way, the resist mask 1022 was removed, and then boron thermal activation or laser activation was performed. At this time, a film for protecting the gate electrode from heat may be formed. Next, a first interlayer insulating film 1025 was formed to a thickness of 1 μm. A silicon oxide film as the first interlayer insulating film 1025;
A silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment, an acrylic resin film is employed.

After forming the first interlayer insulating film 1025, a contact hole was formed to form a source wiring 1026, 1027 and a drain wiring 1028 made of a metal material. In this embodiment, a three-layer wiring having a structure in which an aluminum film containing titanium is sandwiched between titanium is used.

Also, as the first interlayer insulating film 1025, BC
When a resin film called B (benzocyclobutene) is used, flatness is improved and copper can be used as a wiring material. Copper is very effective as a wiring material because of its low wiring resistance.

After forming the source wiring and the drain wiring in this manner, a 50-nm-thick silicon nitride film 1029 was formed as a passivation film. Further, a second interlayer insulating film 1030 was formed thereon. This second interlayer insulating film 103
As 0, the same material as that of the first interlayer insulating film 1025 can be used. In this embodiment, a structure in which an acrylic resin film is laminated on a silicon oxide film having a thickness of 50 nm is employed.

Through the above steps, a CMOS circuit having a structure as shown in FIG. 19C is completed. In the CMOS circuit formed according to the present embodiment, NTFT has excellent reliability, and thus the reliability of the entire circuit is greatly improved. In addition, when the structure is as in this embodiment, NTFT
It has been found that since the characteristic balance (balance of electric characteristics) between the TFT and the PTFT is improved, an operation failure is less likely to occur.

The influence of nickel (catalytic element) in the channel formation region, which was a concern when using the conventional technique described in Japanese Patent Application Laid-Open No. Hei 7-130652, was confirmed by the gettering step shown in this embodiment. Solved by doing.

However, the structure described in this embodiment is merely an example, and need not be limited to the structures shown in FIGS. An important point in the present invention is the structure of the active layer of the NTFT, and the effects of the present invention can be obtained unless the point is different.

This embodiment can be freely combined with Embodiments 2 to 6.

[Embodiment 15] This embodiment shows an example in which a crystalline semiconductor film to be an active layer is formed by laser light or strong light in the crystallization step of Embodiment 1 or 14. 3 on silicon oxide film formed on glass substrate
0nm thick amorphous silicon film (amorphous silicon film)
Was formed by a plasma CVD method, and after dehydrogenation treatment, excimer laser annealing was performed to form a polysilicon film (a crystalline silicon film or a polycrystalline silicon film).

For this crystallization step, a known laser crystallization technique or thermal crystallization technique may be used. As a laser to be used, an ultraviolet laser such as various excimer lasers, an infrared ray such as a YAG laser, a glass laser and a ruby laser, and a visible light laser are preferable.
Further, a continuous wave laser such as an argon laser may be used. In the present embodiment, the amorphous silicon film was crystallized by processing a pulsed laser KrF excimer laser into a linear shape.

In this embodiment, the polysilicon film is obtained by crystallizing the initial film as an amorphous silicon film by laser annealing, but a microcrystalline silicon film may be used as the initial film, or the polysilicon film may be formed directly. It may be a film. Of course, laser annealing may be performed on the formed polysilicon film. Further, furnace annealing may be performed instead of laser annealing. Before the laser crystallization, a catalytic element (eg, nickel) may be added to the initial film.

A crystalline semiconductor film (including a crystalline silicon film and a crystalline silicon germanium film) may be formed by using the above-described techniques, and may be patterned to form an active layer. Subsequent steps may follow the first embodiment or the fourteenth embodiment.

[Embodiment 16] In this embodiment, FIG.
FIG. 20 shows an example in which boron doping is performed via the gate insulating film without performing the step of forming the gate insulating film 1023 in Embodiment 14 shown in FIG. This embodiment is the same as the first embodiment up to the step shown in FIG. 18D, so that the step is omitted.

In this embodiment, according to Embodiment 14, FIG.
After obtaining the state shown in (D), a boron addition step was performed. (FIG. 20A) Here, the gate insulating film 112 is used.
3 into the fourth impurity region 1124 at 3 × 10 ²⁰ atoms /
The dose and the acceleration voltage were adjusted so that boron was contained at a concentration of cm ³ .

When the state shown in FIG. 20A was obtained in this manner, the resist mask was removed, and then boron was thermally activated or laser activated. At this time, a film for protecting the gate electrode from heat may be formed. Next, in the same manner as in Example 14, the first interlayer insulating film 1125, the source wirings 1126 and 1127 made of a metal material, and the drain wiring 1
128, a passivation film 1129, and a second interlayer insulating film 1130 were formed. In consideration of the etching rate, the gate insulating film 11 is formed so as not to damage the active layer.
27 and the thickness of the silicon nitride film,
It is preferable to form contact holes for forming the drain wirings 26, 1123 and the drain wiring 1128 at substantially the same depth.

Through the above steps, a CMOS circuit having a structure as shown in FIG. 20B is completed. By doing so, the process could be simplified. In the case of this embodiment, the gate insulating film of the NTFT finally contacts the channel forming region, the first impurity region, and the second impurity region,
It is characterized in that it is not in contact with the third impurity region and that the gate insulating film of the PTFT is in contact with the channel formation region and the fourth impurity region. Of course, a combination with the fifteenth embodiment is also possible.

[Embodiment 17] In this embodiment, Embodiment 14 is described.
FIG. 21 shows an example in which a protective film is formed at a time different from the above. In the fourteenth embodiment, the protective film is formed after the third phosphorus doping step. However, in the present embodiment, the protective film 1200 is formed after the state shown in FIG. 17C is obtained. Since the basic configuration is the same as that of the first embodiment, only the differences will be described. However, for the sake of simplicity, the same reference numerals as those in Example 14 were used for the reference numerals other than the protective film.

First, the same state as that of FIG. 17C is formed according to the fourteenth embodiment. Next, a 20 nm-thick protective film 1200 made of a silicon nitride film was formed. (FIG. 21
(A))

Next, a second phosphorus doping step (a step of adding phosphorus) was performed to form a second impurity region. However, the doping conditions (dose amount, acceleration voltage, and the like) are adjusted in consideration of the thickness of the protective film 1200. Alternatively, the protective film 1200 may be formed after the second phosphorus doping step without forming the protective film before the second phosphorus doping step.

Next, resist masks 1016 and 101
7 was formed. Next, the resist masks 1016, 10
Using 17 as a mask, the protective film and the gate insulating film were selectively removed. The protective film 1201 and the gate insulating film 1018 thus formed have the same patterning shape, and a part of the active layer is exposed. Next, a third phosphorus doping step was performed to form third impurity regions 1019 and 1020.
(FIG. 21 (B))

When the state shown in FIG. 21B was obtained, the resist masks 1016 and 1017 were removed. Next, a heat treatment process similar to that in Example 14 was performed to getter the catalyst element in the film to the third impurity regions 1019 and 1020. (FIG. 21 (C))

Next, a resist mask 1022 covering the entire NTFT was formed. Then, first, the protective film 1 of the PTFT
201 was removed. Subsequently, the sidewall 1013 and the third impurity region 1020 of the PTFT were removed. Further, the gate insulating film 1018 was dry-etched to form a gate insulating film 1023 having the same shape as the gate wiring. Next, the same boron doping as in Example 14 was performed to form a fourth impurity region 1024. (FIG. 21D)

According to the fourteenth embodiment, the subsequent steps are performed as shown in FIG.
The TFT shown in (E) is completed. Example 14
Combinations with any of the embodiments 1 to 16 are also possible.

By adopting such a process, deterioration of the gate electrode due to oxidation or the like can be effectively prevented by the protective film. Further, the source wiring 1026 and the drain wiring 1
In forming 027, since a protective film was not provided in contact with the third impurity region and the fourth impurity region, formation of a contact hole was facilitated.

[Embodiment 18] In this embodiment, Embodiment 14 will be described.
FIG. 22 shows an example in which a protective film is formed at a time different from the above. In the fourteenth embodiment, the protective film is formed after the third phosphorus doping step. In the present embodiment, the protective film 1210 is formed after the state shown in FIG. 17B is obtained. Since the basic configuration is the same as that of the first embodiment, only the differences will be described. However, for the sake of simplicity, the same reference numerals as those in Example 14 were used for the reference numerals other than the protective film.

First, the same state as that of FIG. 17B is formed according to the fourteenth embodiment. Next, a 5 nm-thick protective film 1210 made of a silicon nitride film was formed. Next, a sidewall was formed on the protective film. The thickness range of the protective film 1210 is 1 to 10 nm, preferably 2 to 5 nm. If the silicon nitride film 1210 is too thick, a gate overlap structure using sidewalls cannot be realized. However, care must be taken so that the effect of preventing oxidation of the gate wiring (in the case of tantalum) is not impaired in the subsequent heat treatment step. Then 2
A second phosphorus doping step (a step of adding phosphorus) is performed,
Impurity regions 1014 and 1015 were formed. (FIG. 22
(A)) However, doping conditions (dose amount, acceleration voltage, and the like) are adjusted in consideration of the thickness of the protective film 1210.
Alternatively, the protective film may be formed before the second phosphorus doping step without forming the protective film after the second phosphorus doping step.

Next, resist masks 1016 and 101
7 was formed. Next, the resist masks 1016, 10
Using 17 as a mask, the protective film and the gate insulating film were selectively removed. The protective film 1211 and the gate insulating film 1018 thus formed have the same shape, and a part of the active layer is exposed. Next, a third phosphorus doping step was performed to form third impurity regions 1019 and 1020. (FIG. 22
(B))

When the state shown in FIG. 22B was obtained, the resist masks 1016 and 1017 were removed. Next, the same heat treatment as in Example 14 was performed to getter the catalytic element in the active layer to the third impurity regions 1019 and 1020. (FIG. 22 (C))

Next, a resist mask 1022 covering the entire NTFT was formed. Then, first, the protective film 1 of the PTFT
211 was removed. Subsequently, the sidewall 1013 and the third impurity region 1020 of the PTFT were removed. Further, the gate insulating film 1018 was dry-etched to form a gate insulating film 1023 having the same shape as the gate wiring. Next, the same boron doping as in Example 14 was performed to form a fourth impurity region 1024. (FIG. 22 (D))

The subsequent steps are the same as those in FIG.
The TFT shown in (E) is completed. Example 14
Combinations with any of the embodiments 1 to 17 are also possible.

By adopting such a process, deterioration of the gate electrode due to oxidation or the like can be effectively prevented by the protective film 1211. Further, at the time of forming the source wiring 1026 and the drain wiring 1027, since a protective film was not provided in contact with the third impurity region and the fourth impurity region, formation of a contact hole was facilitated. In forming the sidewall, the protective film may be used as an etching stopper.

[Embodiment 19] In this embodiment, Embodiment 18 will be described.
FIG. 23 shows an example of a process different from that shown in FIG. In this embodiment, after the state shown in FIG. 22B is obtained, the protective film is removed. Since the basic configuration is the same as that of the eighteenth embodiment, only the differences will be described. However, for the sake of simplicity, the same reference numerals as in Example 18 were used for the reference numerals other than the protective film. Note that FIG. 22B and FIG. 23A are the same.

First, the same state as that shown in FIG. When the state of FIG. 22B was obtained, the resist masks 1016 and 1017 were removed. Further, the protective film 1211 was removed using the sidewalls as a mask, and a protective film 1212 was formed. ((FIG. 23
(B))

Next, the same heat treatment as in Example 14 was performed to getter the catalyst element to the third impurity regions 1019 and 1020. (FIG. 23 (C))

Next, a resist mask 1022 covering the entire NTFT was formed. Then, first, the protective film 1 of the PTFT
212 was removed. Subsequently, the sidewall 1013 and the third impurity region 1020 of the PTFT were removed. Further, the gate insulating film 1018 was dry-etched to form a gate insulating film 1023 having the same shape as the gate wiring. Next, the same boron doping as in Example 1 was performed to form a fourth impurity region 1024. (FIG. 23 (D))

The subsequent steps are the same as those in FIG.
The TFT shown in (E) is completed. Example 14
Combinations with any of the embodiments of the present invention are also possible.

[Embodiment 20] In this embodiment, according to Embodiment 14, after obtaining the state shown in FIG. 17D, resist masks 1016 and 1017 are formed, and a third phosphorus addition step is performed. Was. (FIG. 24A) Here, the third impurity regions 1019 and 1019 are interposed via the gate insulating film 1005.
The dose and the accelerating voltage were adjusted so that ²⁰ contained phosphorus at a concentration of 1 × 10 ²⁰ atoms / cm ³ .

When the state shown in FIG. 24A is obtained as described above, after the gate insulating film 1005 is selectively removed,
The resist mask was removed. Thereafter, a protective film 1021 was formed in the same manner as in Example 1, and heat treatment was performed. (Figure 2
4 (B))

Although the gate insulating film 1005 is etched in this embodiment, it is possible to omit this step and leave the gate insulating film 1005 until the final step.
In this case, since the active layer is not exposed after the gate insulating film 1005 is formed, there is no fear of contamination from the processing atmosphere.

The following steps are performed according to the fourteenth embodiment.
Is completed. Of course, a combination with any one of Embodiments 14 to 19 is also possible.

[Embodiment 21] In this embodiment, a circuit is composed of TFTs formed by carrying out the present invention, and a driver circuit (a shift register circuit, a buffer circuit, a sampling circuit, a signal amplifying circuit, etc.) and a pixel are formed on the same substrate. An example in which an active matrix liquid crystal display device in which a matrix circuit is integrally formed is manufactured will be described.

In the fourteenth embodiment, a CMOS circuit has been described as an example. However, in the present embodiment, a CMOS circuit (see FIGS.
A driver circuit having 5) as a basic unit and a pixel matrix circuit (FIG. 25) using NTFT as a pixel TFT were formed on the same substrate. FIG. 25 is a cross-sectional structural view taken along line AA ′ in FIG. FIG. 25
Has a double gate structure in which NTFTs having the same structure are connected in series, and only one of them will be described with reference numerals.

It is to be noted that the pixel TFT may have a structure in which a source electrode and a drain wiring are formed in accordance with the process of Embodiment 14, and a pixel electrode is formed so as to be connected to the drain wiring. The manufacturing method is briefly described below.

First, according to the process of the fourteenth embodiment, the substrate 1
A base film 1301 and a channel formation region 130
2, first impurity region 1303, second impurity region 130
4. Third impurity regions 1305 and 1306, gate insulating film 1307, gate wiring 1309, sidewall 130
8, a protective film 1310, a first interlayer insulating film 1311, a source wiring 1312, and a drain wiring 1313 were formed.

Then, the first layer on which the protective film 1310 is formed is formed.
A second interlayer insulating film 1315 is formed over the interlayer insulating film.
Further, a third interlayer insulating film 1316 is formed thereon,
Pixel electrode 131 made of a transparent conductive film such as TO or SnO ₂
8 was formed. Reference numeral 1317 denotes a pixel electrode.

The capacitor portion has a capacitor wiring 1322 as an upper electrode and an undoped silicon layer (intrinsic semiconductor layer or a semiconductor layer doped with boron at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ) 1319. And a lower electrode including the impurity region 1320 with the insulating film 1321 interposed therebetween.
Note that the capacitor wiring 1322 was formed simultaneously with the gate wiring of the pixel TFT, and was connected to ground or a fixed voltage. Further, the insulating film 1321 is used as the gate insulating film 13 of the pixel TFT.
07 are made of the same material. The intrinsic region 1319 is made of the same material as the channel forming region of the pixel TFT. Further, the impurity region 1320 is
It is made of the same material as the first impurity region of the NTFT of the OS circuit. In this way, the pixel TFT is provided on the same substrate.
, A capacitor portion, and a CMOS circuit can be simultaneously manufactured and integrated.

[Embodiment 22] In this embodiment, Embodiment 21 is described.
An example in which a capacitor having a structure different from that of FIG. Since the basic configuration is almost the same as that of the twenty-first embodiment, only the differences will be described. The capacitor of the present embodiment includes a second impurity region 3002 connected to the third impurity region 3001,
The insulating film 3003 and the capacitor wiring 3004 are formed.
FIG. 26 shows a cross-sectional structural view of a TFT forming side substrate provided with this capacitance portion.

Further, a black mask 3005 was provided on the TFT forming side substrate. Note that the capacitor wiring 3004 is connected to the pixel TF
It is formed simultaneously with the source wiring and drain wiring of T, and is connected to ground or a fixed voltage. In this way, the pixel TFT, the capacitor, and the CMOS circuit can be simultaneously manufactured and integrated on the same substrate. Example 14
Combinations with any of the embodiments of the present invention are also possible.

[Embodiment 23] In this embodiment, Embodiment 2 will be described.
An example in which a capacitance portion different from 0 and 21 is formed is shown. Since the basic configuration is almost the same as that of the twenty-first embodiment, only the differences will be described. First, according to the fourteenth embodiment, the second interlayer insulating film 310 is formed on the first interlayer insulating film on which the protective film is formed.
2 and a black mask 3103 made of a conductive material having a light-shielding property. Further, a third interlayer insulating film is formed thereon, and a pixel electrode 3104 made of a transparent conductive film such as ITO or SnO ₂ is connected.

[0284] The black mask 3103 corresponds to the pixel TF.
The T portion is covered, and the drain wiring 3101 and the capacitor portion are formed. FIG. 27 shows a cross-sectional structural view of a TFT forming side substrate provided with this capacitance portion. In this way, the pixel TFT, the capacitor, and the CMOS circuit can be simultaneously manufactured and integrated on the same substrate. Of course, Examples 14 to 2
0 can be combined with any of the embodiments.

[Embodiment 24] In this embodiment, FIG. 28 shows an example in which a back gate electrode 3201 is formed below an insulating film 3202 below a channel formation region.

By injecting electrons into back gate electrode 3201, the threshold voltage can be changed to control the threshold voltage to a desired value. In particular, in the pixel TFT as in this embodiment, it is desirable to appropriately control the threshold voltage to reduce power consumption. Of course, a combination with any one of Embodiments 14 to 24 is also possible.

[Embodiment 25] In this embodiment, a circuit is composed of TFTs formed by carrying out the present invention, and a driver circuit (a shift register circuit, a buffer circuit, a sampling circuit, a signal amplifier circuit, etc.) and a pixel are formed on the same substrate. An example in which an active matrix liquid crystal display panel in which a matrix circuit is integrally formed is manufactured will be described.

In the first embodiment, a CMOS circuit has been described as an example. In the present embodiment, a driver circuit having a CMOS circuit as a basic unit and a pixel matrix circuit having an NTFT as a pixel TFT are formed on the same substrate. Note that the pixel T
The FT may have a so-called multi-gate structure such as a double gate structure or a triple gate structure.

The pixel TFT may have a structure in which a source electrode and a drain line are formed in accordance with the steps of Embodiment 1 or Embodiment 14, and a pixel electrode is formed so as to be connected to the drain line. The invention of the present application is characterized by the structure of the NTFT, and it is easy to apply this to the pixel TFT by a known technique, and therefore the description is omitted.

After the driver circuit and the pixel matrix circuit are formed on the same substrate, an alignment film is formed to substantially complete the TFT forming substrate (active matrix substrate).
Then, an opposing substrate having an opposing electrode and an alignment film is prepared, and a liquid crystal material is sealed between the active matrix substrate and the opposing substrate. An active matrix type liquid crystal display device having a structure as shown in FIG. Panel or liquid crystal module) is completed. The step of enclosing the liquid crystal material may use a known cell assembly step, and a detailed description thereof will be omitted.

In FIG. 29, reference numeral 21 denotes a substrate having an insulating surface, 22 denotes a pixel matrix circuit, 23 denotes a source driver circuit, 24 denotes a gate driver circuit, 25 denotes a counter substrate, 26 denotes an FPC (flexible printed circuit), and 27 denotes It is a signal processing circuit such as a D / A converter and a γ correction circuit. Note that a complicated signal processing circuit may be formed with an IC chip, and the IC chip may be mounted on a substrate like a COG.

Further, in this embodiment, a liquid crystal display device has been described as an example. However, if the display device is an active matrix type display device, an EL (electroluminescence) display device, an EC (electrochromics) display panel, an It is also possible to apply to other electro-optical devices such as a sensor.

The electro-optical device of this embodiment is the same as that of the first embodiment.
To 24 can be realized.

[Embodiment 26] The TFT structure of the present invention can be applied not only to the electro-optical device shown in Embodiment 25, but also to any semiconductor circuit. That is, RISC
The present invention may be applied to a microprocessor such as a processor or an ASIC processor, or may be applied to a high frequency circuit for a portable device (a mobile phone, a PHS, a mobile computer) from a signal processing circuit such as a D / A converter.

Further, it is also possible to realize a semiconductor device having a three-dimensional structure in which an interlayer insulating film is formed on a conventional MOSFET and a semiconductor circuit is formed thereon using the present invention. As described above, the present invention can be applied to all semiconductor devices using LSIs at present. That is, a SOI structure (such as SIMOX, Smart-Cut (registered trademark of SOITEC), and ELTRAN (registered trademark of Canon Inc.)) (T
The present invention may be applied to an FT structure).

The semiconductor circuit of this embodiment is similar to those of the first to third embodiments.
The present invention can be realized by using any combination of the 25 combinations.

[Embodiment 27] A TFT formed by carrying out the present invention can be applied to various electro-optical devices and semiconductor circuits. That is, the invention of the present application can be applied to all electronic devices in which the electro-optical device and the semiconductor circuit are incorporated as components of a display unit.

Examples of such electronic devices include a video camera, a digital camera, a projection TV, a head-mounted display (goggle type display), a car navigation system, a personal computer, and a portable information terminal (mobile computer, mobile phone, electronic book, etc.). And the like. One example of them is shown in FIG.

FIG. 30A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.

FIG. 30B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6. The present invention can be applied to the display portion 2102, the audio input portion 2103, and other signal control circuits.

FIG. 30C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display section 2205. The present invention is applied to the display unit 2205.
And other signal control circuits.

FIG. 30D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 The present invention can be applied to the display portion 2302 and other signal control circuits.

FIG. 30E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Dig) as a recording medium.
It is possible to enjoy listening to music, watching movies, playing games, and using the Internet using an IT (Versatile Disc), CD, or the like. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 30F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, and an image receiving section (not shown).
The present invention can be applied to the display portion 2502 and other signal control circuits.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using any combination of the embodiments 1 to 26.

[Embodiment 28] The present invention can be applied to a projector using the electro-optical device shown in Embodiment 25. That is, the invention can be applied to a projector in which an electro-optical device is incorporated in a display device.

FIG. 31A shows a front type projector, which comprises a projection device 2601 and a screen 2602. The present invention can be applied to a liquid crystal display device of a projection device and other signal control circuits.

FIG. 31B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3. It is composed of a screen 2704. The present invention can be applied to a liquid crystal display device of a projection device and other signal control circuits.

FIG. 31C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 31A and 31B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 31D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 31C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 31D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

[0311] As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the embodiments 1 to 24.

[Embodiment 29] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 34A is a top view of an EL display device using the present invention. In FIG. 34A, 4010
Denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, and 4013 denotes a gate side driver circuit. Each of the driver circuits is connected to an FPC 4017 through wirings 4014 to 4016.
And connected to the external device.

At this time, at least the pixel portion, preferably the drive circuit and the pixel portion are surrounded so as to surround the cover material 600.
0, a sealing material 7000, and a sealing material (a second sealing material) 7001 are provided.

FIG. 34B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
The FT may use a known structure (top gate structure or bottom gate structure).

The present invention is directed to a TFT 4022 for a driving circuit,
It can be used for the TFT 4023 for the pixel portion.

By using the present invention, the TFT 402 for the driving circuit
2. When the pixel portion TFT 4023 is completed, the pixel portion TFT is formed on an interlayer insulating film (flattening film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the FT 4023 is formed. Pixel electrode 4027
Is a transparent conductive film, the TFT for the pixel portion is made of P
It is preferable to use a channel type TFT. As the transparent conductive film, a compound of indium oxide and tin oxide (IT
O) or a compound of indium oxide and zinc oxide. Then, the pixel electrode 4027
Is formed, an insulating film 4028 is formed, and the pixel electrode 40 is formed.
An opening is formed on 27.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

[0319] In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After the EL layer 4029 is formed, a cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 4030 is
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region indicated by 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Further, a sealing material is provided inside the cover material 6000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0326] A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have a light transmitting property.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

[Embodiment 30] In this embodiment, an example in which an EL display device different from that of Embodiment 29 is manufactured by using the present invention will be described with reference to FIGS. 35 (A) and 35 (B). I do. 34A and 34B denote the same parts, and a description thereof will not be repeated.

FIG. 35A is a top view of the EL display device of this embodiment, and FIG. 35B is a cross-sectional view taken along line AA ′ of FIG.

According to Embodiment 29, a passivation film 6003 is formed to cover the surface of the EL element.

[0334] Further, a filler 6004 is provided so as to cover the EL element. This filler 6004 is used as the cover material 6
000 also functions as an adhesive for bonding. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0335] A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover member 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have a light-transmitting property.

[0339] Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of a sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

[Embodiment 31] In this embodiment, a more detailed sectional structure of a pixel portion in an EL display panel is shown in FIG.
FIG. 37A shows a top view structure, and FIG. 37B shows a circuit diagram. In FIG. 36, FIG. 37 (A) and FIG. 37 (B), the same reference numerals are used, so that they may be referred to each other.

In FIG. 36, the switching TFT 3502 provided on the substrate 3501 is the NTF of the present invention.
It is formed using T. In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, by adopting a double gate structure, a structure in which two TFTs are substantially connected in series,
There is an advantage that an off-current value can be reduced.
Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. Further, it may be formed using the PTFT of the present invention.

The current control TFT 3503 is formed using the NTFT of the present invention. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. The wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.

At this time, it is very important that the current control TFT 3503 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the first side of the drain of the current controlling TFT is
The structure of the present invention in which the impurity region and the second impurity region are provided is extremely effective.

In this embodiment, the current controlling TFT 35 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 37A, the wiring to be the gate electrode 37 of the current controlling TFT 3503 has a length of 35 mm.
In a region indicated by 04, the region overlaps with the drain wiring 40 of the current control TFT 3503 via an insulating film. At this time, 3
In the region indicated by 504, a capacitor is formed. This capacitor 3504 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is constantly applied.

The first passivation film 5 is formed on the switching TFT 3502 and the current control TFT 3503.
And a planarizing film 52 made of a resin insulating film thereon.
Is formed. It is very important to flatten the step due to the TFT using the flattening film 52. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 53 denotes a pixel electrode (cathode of an EL element) made of a highly reflective conductive film.
503 is electrically connected to the drain. In this case, it is preferable to use an n-channel TFT as the current control TFT. As the pixel electrode 53, a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof is preferably used. Of course, a stacked structure with another conductive film may be employed.

A light-emitting layer 55 is formed in a groove (corresponding to a pixel) formed by banks 54a and 54b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As specific light emitting layers, cyanopolyphenylene vinylene is used for a red light emitting layer, polyphenylene vinylene is used for a green light emitting layer, and polyphenylene vinylene or polyalkylphenylene is used for a blue light emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 55.
The EL layer has a laminated structure in which a hole injection layer 56 made of (polythiophene) or PAni (polyaniline) is provided. An anode 57 made of a transparent conductive film is provided on the hole injection layer 56. In the case of this embodiment, since the light generated in the light emitting layer 55 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 57 is formed, the EL element 3
505 is completed. Note that the EL element 3505 mentioned here
Are the pixel electrode (cathode) 53, the light emitting layer 55, the hole injection layer 5
6 and a capacitor formed by the anode 57. FIG.
As shown in FIG. 2A, the pixel electrode 53 substantially matches the area of the pixel, and thus the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In this embodiment, a second passivation film 58 is further provided on the anode 57. Second
As the passivation film 58, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 36, and a switching TFT having a sufficiently low off-current value and a current control device which is strong against hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

In addition, it is effective to use the EL display device of this embodiment as a display portion of the electronic apparatus of the embodiment 27.

[Embodiment 32] In this embodiment, Embodiment 31 is described.
A structure in which the structure of the EL element 3505 is inverted in the pixel portion shown in FIG. FIG. 38 is used for the description. It should be noted that the point different from the structure of FIG. 36 is only the EL element portion and the current controlling TFT, and the other description is omitted.

In FIG. 38, the current control TFT 360
3 is formed using the PTFT of the present invention.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 60. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, banks 61a and 61b made of an insulating film are used.
Is formed, a light emitting layer 62 made of polyvinyl carbazole is formed by solution coating. An electron injection layer 63 made of potassium acetylacetonate (denoted as acacK) and a cathode 64 made of an aluminum alloy are formed thereon. In this case, the cathode 64 also functions as a passivation film. Thus, an EL element 3605 is formed.

In the case of this embodiment, the light generated in the light emitting layer 62 is radiated toward the substrate on which the TFT is formed as indicated by the arrow.

[0364] It is effective to use the EL display device of this embodiment as the display unit of the electronic apparatus of the twenty-seventh embodiment.

[Embodiment 33] In the present embodiment, FIG.
FIGS. 39A to 39C show examples in which a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, reference numeral 3801 denotes a switching TFT 380.
2 is a source wiring, and 3803 is a switching TFT 38.
02, a gate wiring 3804, a current controlling TFT 38,
05 is a capacitor, 3806 and 3808 are current supply lines,
Reference numeral 3807 denotes an EL element.

FIG. 39A shows an example in which the current supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 39 (B) shows the current supply line 380
8 is provided in parallel with the gate wiring 3803. Note that although FIG. 39B illustrates a structure in which the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other, if the wiring is formed in a different layer,
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

In FIG. 39C, a current supply line 3808 is provided in parallel with the gate wiring 3803 in the same manner as in the structure of FIG. 39B, and two pixels are connected to the current supply line 3808.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of this embodiment can be implemented by freely combining with the structure of Embodiment 29 or 30. In addition, it is effective to use the EL display device having the pixel structure of this embodiment as the display portion of the electronic device of Embodiment 27.

[Embodiment 34] FIG. 37 shown in Embodiment 31
37A and 37B, a capacitor 350 is used to hold a voltage applied to the gate of the current controlling TFT 3503.
4, but the capacitor 3504 can be omitted. In the case of the embodiment 31, since the NTFT of the present invention is used as the current control TFT 3503, it has the first impurity region provided so as to overlap the sidewall made of silicon via the gate insulating film. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the first impurity region overlap with each other, the first capacitance included in the overlapping region may be changed.
It is determined by the length of the impurity region.

In addition, FIGS. 39 (A) to 39 (A) to
Similarly, in the structure of (C), the capacitor 3805 can be omitted.

The structure of this embodiment is similar to that of Embodiments 29 to 3
3 can be freely combined with the configuration. In addition, it is effective to use the EL display device having the pixel structure of this embodiment as the display portion of the electronic device of Embodiment 27.

[0374]

According to the present invention, the reliability of the NTFT can be improved. Therefore, high electrical characteristics that require strict reliability (especially high mobility)
It has become possible to ensure the reliability of NTFTs having the above. At the same time, NTFT and PT with excellent characteristic balance
By forming a CMOS circuit by combining with FT,
A semiconductor circuit having high reliability and excellent electrical characteristics was formed.

Further, in the present invention, since the number of catalytic elements used for crystallization of a semiconductor can be reduced, a semiconductor device with less instability can be realized. Moreover, since the step of reducing the catalytic element is performed simultaneously with the formation and activation of the source region and the drain region, the throughput does not decrease.

As described above, by improving the reliability of a circuit formed by TFTs, it is possible to ensure the reliability of all semiconductor devices including electro-optical devices, semiconductor circuits, and electronic devices. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross section of a CMOS circuit.

FIG. 2 is a diagram showing a cross-sectional structure of a MOSFET.

FIG. 3 is a diagram illustrating a manufacturing process of a CMOS circuit.

FIG. 4 is a diagram showing a manufacturing process of a CMOS circuit.

FIG. 5 is a view showing a manufacturing process of a polysilicon film.

FIG. 6 is a diagram showing a manufacturing process of a polysilicon film.

FIG. 7 is a view showing a manufacturing process of a polysilicon film.

FIG. 8 is a diagram illustrating a manufacturing process of a CMOS circuit.

FIG. 9 illustrates a manufacturing process of a CMOS circuit.

FIG. 10 illustrates a manufacturing process of a CMOS circuit.

FIG. 11 is a diagram of a CMOS circuit viewed from above.

FIG. 12 illustrates a structure of a pixel matrix circuit.

FIG. 13 illustrates a structure of a pixel matrix circuit.

FIG. 14 illustrates a structure of a pixel matrix circuit.

FIG. 15 illustrates a structure of a pixel matrix circuit.

FIG. 16 is a diagram showing a cross section of a CMOS circuit.

FIG. 17 illustrates a manufacturing process of a CMOS circuit.

FIG. 18 is a diagram illustrating a manufacturing process of a CMOS circuit.

FIG. 19 is a diagram illustrating a manufacturing process of a CMOS circuit.

FIG. 20 illustrates a manufacturing process of a CMOS circuit.

FIG. 21 illustrates a manufacturing process of a CMOS circuit.

FIG. 22 illustrates a manufacturing process of a CMOS circuit.

FIG. 23 illustrates a manufacturing process of a CMOS circuit.

FIG. 24 illustrates a manufacturing process of a CMOS circuit.

FIG. 25 illustrates a structure of a pixel matrix circuit.

FIG. 26 illustrates a structure of a pixel matrix circuit.

FIG. 27 illustrates a structure of a pixel matrix circuit.

FIG. 28 illustrates a structure of a pixel matrix circuit.

FIG. 29 illustrates an appearance of an electro-optical device.

FIG. 30 illustrates an example of an electronic device.

FIG. 31 illustrates an example of an electronic device.

FIG. 32 is a diagram for comparing various TFT structures.

FIG. 33 illustrates an energy band of an NTFT (off state).

FIG. 34 illustrates an EL display device.

FIG. 35 illustrates an EL display device.

FIG. 36 illustrates a cross-sectional structure of an EL display device.

FIG. 37 shows a top view and a circuit diagram of an EL display device.

FIG. 38 illustrates a cross-sectional structure of an EL display device.

FIG. 39 is a circuit diagram of an EL display device.

Claims (30)

[Claims] An active layer, an insulating film in contact with the active layer,
NTFT and PTF having wiring in contact with the insulating film
A semiconductor device including a CMOS circuit made of T, wherein only the NTFT has a sidewall on a side portion of the wiring, and an active layer of the NTFT includes a channel formation region and an element belonging to Group 15 at a different concentration. And at least three types of impurity regions, of the at least three types of impurity regions, an impurity region in contact with the channel formation region overlaps with the sidewall with the insulating film interposed therebetween. , A channel formation region, and two types of impurity regions containing an element belonging to Group 13 at the same concentration. In both the NTFT and the PTFT, an impurity region furthest from the channel formation region includes crystallization of the active layer. 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm
A semiconductor device characterized by being present at a concentration of ³ . 2. An active layer, an insulating film in contact with the active layer,
NTFT and PTF having wiring in contact with the insulating film
A semiconductor device including a CMOS circuit made of T, wherein only the NTFT has a sidewall on a side of the wiring, and an active layer of the NTFT has a channel forming region, a first impurity region, a second impurity region, A first impurity region, a second impurity region, and a third impurity region.
The impurity regions include elements belonging to Group 15 at different concentrations, the first impurity region overlaps the sidewall with the insulating film interposed therebetween, and the active layer of the PTFT includes a channel forming region, a fourth impurity region And a fifth impurity region, wherein the fourth impurity region and the fifth impurity region each include an element belonging to Group 13 at the same concentration, and the third impurity region and the fifth impurity region The catalyst element used for crystallization of the active layer is 1 × 10 ¹⁷ to 1 × 1;
A semiconductor device characterized by being present at a concentration of 0 ²⁰ atoms / cm ³ . 3. An active layer, an insulating film in contact with the active layer,
NTFT and PTF having wiring in contact with the insulating film
A semiconductor device including a CMOS circuit made of T, wherein only the NTFT has a sidewall on a side portion of the wiring, and an active layer of the NTFT contains a channel formation region and an element belonging to Group 15 at different concentrations. At least three types of impurity regions, wherein the at least three types of impurity regions have a higher concentration of the element belonging to Group 15 as the distance from the channel formation region increases, and the active layer of the PTFT includes a channel formation region. And two types of impurity regions containing elements belonging to Group 13 at the same concentration. In both the NTFT and the PTFT, the impurity region furthest from the channel formation region includes a catalyst used for crystallization of the active layer. Element is 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm
A semiconductor device characterized by being present at a concentration of ³ . 4. An active layer; an insulating film in contact with the active layer;
NTFT and PTF having wiring in contact with the insulating film
A semiconductor device including a CMOS circuit made of T, wherein only the NTFT has a sidewall on a side of the wiring, and an active layer of the NTFT has a channel forming region, a first impurity region, a second impurity region, A first impurity region, a second impurity region, and a third impurity region.
The impurity regions contain the same impurity at different concentrations, and the concentration of the impurities is higher in the order of the first impurity region, the second impurity region, and the third impurity region. The active layer of the PTFT includes a channel forming region, A fourth impurity region and a fifth impurity region arranged in this order; the fourth impurity region and the fifth impurity region each include an element belonging to Group 13 at the same concentration; In the impurity region, the catalyst element used for crystallization of the active layer is 1 × 10 ¹⁷ to 1 × 1.
A semiconductor device characterized by being present at a concentration of 0 ²⁰ atoms / cm ³ . 5. The semiconductor device according to claim 1, wherein said active layer is a single-crystal semiconductor thin film. 6. The catalyst element according to claim 1, wherein the catalyst element is Ni, Ge, Co, Fe, Pd, Sn, Pb, Pt, Cu,
A semiconductor device comprising one or more elements selected from Au or Si. 7. The semiconductor device according to claim 1, wherein at least a part of the wiring is covered with a silicon nitride film. 8. The semiconductor device according to claim 1, wherein said sidewall is formed of a material containing silicon as a main component. 9. The method according to claim 1, wherein said N
A semiconductor device, wherein elements belonging to Group 15 are present at the same concentration in an impurity region of the TFT and the PTFT in which the catalyst element is present. 10. The semiconductor device according to claim 2, wherein the third impurity region and the fifth impurity region have the same concentration of the element belonging to Group XV. 11. The semiconductor device according to claim 10, wherein the concentration of the element belonging to Group 15 is less than the concentration of the element 13 present in the fifth impurity region.
A semiconductor device, which is lower in concentration than an element belonging to group III. 12. The method according to claim 2, wherein the concentration of the impurity contained in the first impurity region is 1 × 10
¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ , and the concentration of the impurity contained in the second impurity region is 1 × 10 ¹⁶ to 1 × 10 ¹⁹
A semiconductor device characterized by atoms / cm ³ . 13. The semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display panel, an EL display device, or an image sensor. 14. The semiconductor according to claim 1, wherein the semiconductor device is a video camera, a digital camera, a projector, a goggle type display, a car navigation system, a personal computer, or a personal digital assistant. apparatus. 15. A first step of forming a semiconductor film including a crystal on a substrate having an insulating surface using a catalytic element, and patterning the semiconductor film including a crystal to form a first active layer and a second active layer. A second step of forming; a third step of forming an insulating film on the first active layer and the second active layer; a fourth step of forming a wiring on the insulating film; The first active layer and the second
A fifth step of adding an element belonging to Group 15 to the active layer, a sixth step of forming a sidewall on a side portion of the wiring, and using the wiring and the sidewall as a mask, the first active layer and the first A seventh step of adding an element belonging to Group 15 to the second active layer; an eighth step of forming a resist mask on the first active layer and adding an element belonging to Group 13 to the second active layer; A ninth step of forming a resist mask on the first active layer and the second active layer and adding an element belonging to Group 15 to a part of the first active layer and a part of the second active layer; A tenth step of forming a silicon nitride film; and an eleventh step of moving the catalyst element to a part of the first active layer and a part of the second active layer by heat treatment. Of manufacturing a semiconductor device. 16. The method according to claim 15, wherein the concentration of the element belonging to Group 15 added in the ninth step is lower than the concentration of the element belonging to Group 13 added in the eighth step. Of manufacturing a semiconductor device. 17. The method for manufacturing a semiconductor device according to claim 15, wherein the sidewall is formed of a material containing silicon as a main component. 18. The method for manufacturing a semiconductor device according to claim 15, wherein the semiconductor film including the crystal is a single crystal semiconductor thin film. 19. The semiconductor device according to claim 15, wherein a channel formation region, and first, second and third impurity regions containing an element belonging to Group XV are finally formed in the first active layer. The second active layer has the same concentration as the channel forming region at 1%.
A fourth impurity region and a fifth impurity region containing an element belonging to Group 3 are formed, and the fifth impurity region contains an element belonging to Group 15 at the same concentration as the third impurity region. Of manufacturing a semiconductor device. 20. The method according to claim 19, wherein the concentration of the element belonging to Group 15 is increased in the order of the first impurity region, the second impurity region, and the third impurity region. . 21. A first step of forming an active layer containing a catalytic element for promoting crystallization on a substrate having an insulating surface; a second step of forming a first insulating film on the active layer; A third step of forming a wiring on the first insulating film, a fourth step of adding an element belonging to Group 15 to the active layer using the wiring as a mask, and forming a sidewall on a side portion of the wiring A fifth step of adding an element belonging to Group 15 to the active layer using the wiring and the sidewall as a mask; and removing a part of the first insulating film. A seventh step of exposing a part of the formed active layer, an eighth step of adding an element belonging to Group 15 to the active layer exposed in the seventh step, and a second insulation in contact with the upper part of the wiring A ninth step of forming a film; The method for manufacturing a semiconductor device, characterized in that it comprises a tenth step of performing a heat treatment for reducing the degree, the. 22. A first step of forming a first active layer and a second active layer containing a catalytic element for promoting crystallization on a substrate having an insulating surface; and the first active layer and the second active layer. A second step of forming a first insulating film on the first insulating film, a third step of forming a wiring on the first insulating film, and the first active layer and the second
A fourth step of adding an element belonging to Group 15 to the active layer, a fifth step of forming a sidewall on a side portion of the wiring, and using the wiring and the sidewall as a mask, the first active layer and the first A sixth step of adding an element belonging to Group 15 to the second active layer; and selectively removing the first insulating film to form a part of the first active layer formed in the sixth step and the second active layer. A seventh step of exposing a part of the layer; an eighth step of adding an element belonging to Group 15 to the first active layer and the second active layer exposed in the seventh step; A ninth step of forming a second insulating film by heat treatment; a tenth step of performing a heat treatment to reduce the concentration of a catalyst element in the first active layer and the second active layer; and selectively forming the second insulating film. Removing to expose a part of the second active layer formed in the tenth step An eleventh step, a twelfth step of removing the second active layer exposed in the eleventh step, and a thirteenth step of selectively removing the one insulating film and exposing a part of the second active layer. And a fourteenth step of adding an element belonging to Group 13 to the second active layer exposed in the thirteenth step. 23. The semiconductor device according to claim 22, wherein the first active layer has a different concentration from the channel forming region.
A method for manufacturing a semiconductor device, comprising: forming at least three types of impurity regions containing an element belonging to Group V; and forming only a channel formation region and a fourth impurity region in the second active layer. 24. The semiconductor device according to claim 22, wherein the first active layer has a channel formation region, a first impurity region, and a second impurity region.
An impurity region and a third impurity region are formed, and only a channel formation region and a fourth impurity region are formed in the second active layer. 25. The method for manufacturing a semiconductor device according to claim 24, wherein the concentration of the element belonging to Group 15 is higher in the order of the first impurity region, the second impurity region, and the third impurity region. 26. The method according to claim 21, wherein
Finally, a method for manufacturing a semiconductor device, wherein a channel formation region and at least three types of impurity regions containing elements belonging to Group 15 at different concentrations are formed in the first active layer. 27. The method according to claim 24 or 25,
The method for manufacturing a semiconductor device, wherein the sidewall is formed above the first impurity region. 28. The method according to claim 24, wherein
A method for manufacturing a semiconductor device, comprising increasing the concentration of an element belonging to Group 15 in the order of the first impurity region, the second impurity region, and the third impurity region. 29. The method for manufacturing a semiconductor device according to claim 15, wherein the semiconductor device is a liquid crystal display panel, an EL display device, or an image sensor. 30. The semiconductor device according to claim 15, wherein the semiconductor device is a video camera, a digital camera, a projector, a goggle type display, a car navigation system, a personal computer, or a personal digital assistant. Method for manufacturing the device.