JP4531177B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device using a crystalline semiconductor film. Note that the semiconductor device of the present invention is not limited to an element such as a thin film transistor or a MOS transistor, but also an electronic apparatus having a semiconductor circuit formed of these insulated gate semiconductor elements, or an electro-optic display device including an active matrix substrate (typically In addition, an electronic device such as a personal computer or a digital camera provided with a liquid crystal display device is also included in the category.
[0002]
[Prior art]
Currently, a thin film transistor (TFT) is known as a semiconductor element using a semiconductor film. TFTs are used in various integrated circuits, and in particular, are used as switching elements for matrix circuits in active matrix liquid crystal display devices. Further, in recent years, TFTs have been increased in mobility, and TFTs are also used as elements of driver circuits for driving matrix circuits. For use in a driver circuit, it is necessary to use a crystalline silicon film having a higher mobility than the amorphous silicon film as the semiconductor layer. This crystalline silicon film (also referred to as a crystalline silicon film) is called polycrystalline silicon, polysilicon, microcrystalline silicon, or the like.
[0003]
Conventionally, in order to form a crystalline silicon film, a method of directly forming a crystalline silicon film and an amorphous silicon film are formed by a CVD method, followed by heat treatment at a temperature of 600 to 1100 ° C. for 20 to 48 hours. A method for crystallizing amorphous silicon is known. The crystalline silicon film formed by the latter method has larger crystal grains, and the fabricated semiconductor device has better characteristics.
[0004]
When the crystalline silicon film is formed on the glass substrate by the latter method, the upper limit of the crystallization process temperature is about 600 ° C., and the crystallization process takes a long time. Further, the temperature of 600 ° C. is close to the lowest temperature for crystallizing silicon, and if it becomes 500 ° C. or less, it cannot be crystallized in industrial time.
[0005]
In order to shorten the crystallization time, it is only necessary to use a quartz substrate having a high strain point and raise the crystallization temperature to about 1000 ° C. However, the quartz substrate is very expensive as compared with the glass substrate, and is large. It is difficult to increase the area. For example, Corning 7059 glass widely used for active liquid crystal display devices has a glass strain point of 593 ° C., and heating and heating for several hours at a temperature of 600 ° C. or higher causes the substrate to shrink or bend. For this reason, it is required to lower the temperature and shorten the time of the crystallization process so that a glass substrate such as Corning 7059 glass can be used.
[0006]
Crystallization technology using an excimer laser is one of the technologies that enables process temperature reduction and time reduction. Excimer laser light can give a semiconductor film energy in a short period of time comparable to thermal annealing at around 1000 ° C. with little thermal effect on the substrate, and can form a highly crystalline semiconductor film. it can. However, since the excimer laser varies in energy distribution on the irradiated surface, the crystallinity of the obtained crystalline semiconductor film also varies, and the device characteristics for each TFT also vary.
[0007]
In view of this, the present applicant has disclosed a technique in which the crystallization temperature is lowered while using heat treatment in JP-A-6-232059, JP-A-7-321339, and the like. In the technique of the above publication, an element that promotes a small amount of crystallization (referred to as a crystallization promoting element for convenience) is introduced into an amorphous silicon film as a catalyst, and then heat treatment is performed to obtain a crystalline silicon film. Is. As an element that promotes or promotes crystallization, an element selected from Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, and Ge is used.
[0008]
In the crystallization of the above publication, the heat treatment causes the crystallization promoting element to move (also referred to as diffusion) in the amorphous silicon film, and the crystallization of the amorphous silicon proceeds. By using the crystallization technique of the above publication, crystalline silicon can be formed by heat treatment at 450 to 600 ° C. for 4 to 24 hours, and a glass substrate can be used.
[0009]
However, the crystallization of the above publication has a problem that the crystallization promoting element remains in the crystalline silicon film. Such a crystallization promoting element impairs the semiconductor characteristics of the silicon film, and the stability and reliability of the device to be fabricated is impaired.
[0010]
Therefore, in order to solve this problem, the present applicant examined a method for removing (gettering) the crystallization promoting element from the crystalline silicon film. One method is a heat treatment in an atmosphere containing a halogen element such as chlorine. In this method, the crystallization promoting element in the film is vaporized as a halide.
[0011]
The second method is a method in which phosphorus is selectively added to the crystalline silicon film and heat treatment is performed. By performing the heat treatment, the crystallization promoting element is moved to the phosphorus addition region and captured in this region.
[0012]
However, in the first method, in order to obtain the gettering effect, the heat treatment temperature needs to be 800 ° C. or higher, and a glass substrate cannot be used. On the other hand, the second method can reduce the heating temperature to 600 ° C. or less, but has the disadvantage that the processing time is more than 10 hours.
[0013]
[Problems to be solved by the invention]
An object of the present invention is to provide a method for efficiently performing the step of removing the crystallization promoting element when using the technique for removing the crystallization promoting element of the second method.
[0014]
Another object of the present invention is to make it possible to form a high-performance semiconductor element on a glass substrate at a process temperature of 600 ° C. or lower.
[0015]
[Means for Solving the Problems]
As shown in FIG. 2, it takes time to remove the crystallization promoting element, as shown in FIG. 2, a region 70 for reducing the crystallization promoting element (referred to as a gettering region for convenience) and a phosphorus-added region for sucking and capturing the element. This is because 71 (gettering region) is separated.
[0016]
Therefore, if the gettering region is formed in contact with the gettering region, the moving distance to the region where the crystallization promoting element is captured is shortened, and the time for removing the crystallization promoting element can be shortened and the temperature can be lowered.
[0017]
Here, the region 70 (gettering region) in which the crystallization promoting element is reduced is a region including a region that becomes a channel formation region in which good and bad characteristics are most affected by semiconductor characteristics. Switching characteristics and mobility values are greatly affected by the characteristics of the channel formation region. If the crystallization promoting element remains irregularly in the channel formation region, the semiconductor characteristics such as switching characteristics and mobility are impaired, and the stability and reliability of the element are impaired. Therefore, reducing the crystallization promoting element remaining in the channel formation region is indispensable for the production of a stable and reliable device.
[0018]
Further, it is preferable that the gettering region 70 includes a region to be a low concentration impurity region adjacent to the region in addition to a region to be a channel formation region. The low-concentration impurity region is a region that reduces the leakage current at the OFF time. Therefore, by reducing the crystallization promoting elements remaining in the low-concentration impurity region, it is possible to obtain an element that is stable and reliable with respect to reduction of leakage current.
[0019]
Note that the low-concentration impurity region is a high-resistance region whose impurity concentration is lower than that of the source region or the drain region. Its impurity concentration is 10 ¹⁶ -10 ¹⁹ atoms / cm ^Three It is. However, the impurity concentration of the low concentration impurity region does not necessarily have to be lower than that of the source region or the drain region. The low concentration impurity region may have a higher resistance than the source region and the drain region. Therefore, instead of lowering the impurity concentration of the low concentration impurity region, if the low concentration impurity region is ion-implanted or laser-irradiated so as to have a higher resistance region than the source region or drain region, the same impurity concentration as the source region or drain region is obtained. It does not matter.
[0020]
The gettering region that captures the crystallization promoting element is considered to be in contact with the gettering region, to have a size capable of capturing the crystallization promoting element contained in the gettering region, and to reduce the number of steps. In total, the region needs to include at least a region to be a source region and a region to be a drain region. By adding a Group 15 element such as phosphorus to a region including a source region and a drain region, an impurity element for reducing the resistance of the source region and the drain region at the same time is added. Introduction can be performed, and an impurity element introduction step can be omitted.
[0021]
Therefore, in the present invention, as shown in FIG. 1, at least a region 81 serving as a source region in contact with a region to be a channel formation region or a gettering region 80 including a region to be a channel formation region and a region to be a low concentration impurity region, and A group 15 element is added to the hatched region 83 including the drain region 82, and the crystallization promoting element in the gettering region 80 is moved to the gettering region 83 and captured as shown by the arrow 85. The main structure is to remove the crystallization promoting element from the gettering region 80.
[0022]
In FIG. 1A, a region 81 serving as a source region and a region 82 serving as a drain region are used as a gettering region 83, a group 15 element is added, and the crystallization promoting element in the gettering region 80 is removed. In FIG. 1A, since the area of the gettering region 83 that captures the crystallization promoting element is the minimum necessary size, the concentration of the crystallization promoting element captured in the gettering region 83 can be increased. The resistance of the region 81 and the drain region 82 can be reduced.
[0023]
In FIG. 1B, phosphorus is added in a band shape, and alignment of the phosphorus-added region 83 and the island-shaped semiconductor layer 86 in the lateral direction (the length direction of the band) becomes unnecessary. Further, in FIG. 1B, since the area of the gettering region 83 is larger than that in FIG. 1A, the time for removing the crystallization promoting element can be shortened and the temperature can be lowered. At the same time, in FIG. 1B, since the width of the band of the phosphorus-added region 83 is the width of the source region 81 and the drain region 82, the phosphorus-added region 83 is strip-shaped and its area is minimized. The concentration of the crystallization promoting element trapped in the source region 81 and the drain region 82 can be made highest among those that do not require horizontal alignment, and the resistance of the source region 81 and the drain region 82 can be reduced. .
[0024]
FIG. 1C is similar to FIG. 1B in which phosphorus is added in a band shape, and the same effect as in FIG. 1B can be obtained. In FIG. 1C, the width of the phosphorus-added region 83 is made wider than the width of the region 81 that becomes the source region and the region 82 that becomes the drain region as shown in FIG. 1B. Therefore, the time for crystallization promotion element removal and the temperature reduction can be further reduced as compared with FIG. Further, since the band-like width is wider than the width of the region serving as the source region and the region serving as the drain region, it is not necessary to align the phosphorus-added region 83 and the island-shaped semiconductor layer 86 in the lateral direction (band length direction). In addition, it is not necessary to strictly align the phosphorus-added region 83 and the island-shaped semiconductor layer 86 in the vertical direction (band width direction). Therefore, FIG. 1C can improve the reliability most.
[0025]
In FIG. 1D, phosphorus is added so as to surround a region 84 (or a region that becomes a channel formation region and a low-concentration impurity region) to be a channel formation region. Can be achieved.
[0026]
The present invention for solving the above-described problems is as follows.
A step A of forming a semiconductor film;
A step B of introducing an element for promoting crystallization into the semiconductor film;
Step C for crystallizing the semiconductor film after introducing the element for promoting crystallization;
A step D of selectively adding a group 15 element to the crystallized semiconductor film;
After adding the group 15 element, the step E of heat-treating the semiconductor film;
A step F of patterning the semiconductor film to form an island-shaped semiconductor layer,
The patterning is performed so that the region to which the group 15 element is added becomes a source region and a drain region, and the region to which the group 15 element is not added becomes a channel formation region.
This is the main structure.
[0027]
In the semiconductor film formation step A, the semiconductor film is a semiconductor film having no crystallinity, or a semiconductor film having crystallinity but having few crystal grains on the order of 100 nm or more, specifically an amorphous semiconductor film Refers to a microcrystalline semiconductor film. The microcrystalline semiconductor film is a semiconductor film in which a microcrystal including crystal grains with a size of several nanometers to several tens of nanometers and an amorphous phase are mixed.
[0028]
More specifically, the semiconductor film is an amorphous silicon film, a microcrystalline silicon film, an amorphous germanium film, a microcrystalline germanium film, or an amorphous Si film. ₁ Ge _1-x (0 <x <1), and these semiconductor films are formed by a chemical vapor phase method such as a plasma CVD method or a low pressure CVD method.
[0029]
In addition, when the semiconductor film is formed, the semiconductor film and the inorganic insulating film may be continuously formed. By doing so, adhesion of impurities to the surface of the semiconductor film can be prevented. Further, the continuously formed inorganic insulating film may be used as a gate insulating film or a part of the gate insulating film. Impurities at the interface between the semiconductor film and the gate insulating film cause damage to the semiconductor characteristics. However, if the semiconductor film and the gate insulating film are continuously formed, the adhesion of impurities to the interface between the semiconductor film and the gate insulating film should be prevented. Can do.
[0030]
In the introduction step B, an element that promotes crystallization (crystallization promoting element) is an element that has a function of promoting and promoting crystallization of a semiconductor, particularly silicon, and is Ni, Fe, Co, Ru, Rh, Pd. One or more elements selected from Os, Ir, Pt, Cu, Au, and Ge can be used.
[0031]
As a method for introducing the crystallization promoting element, a method of adding a crystallization promoting element to the semiconductor film or a method of forming a film containing the crystallization promoting element in contact with the upper surface or the lower surface of the semiconductor film can be used.
[0032]
In the former method, after the semiconductor film is formed, a method of adding a crystallization promoting element to the semiconductor film by an ion implantation method, a plasma doping method, or the like can be used.
[0033]
In the latter method, in order to form a film containing a crystallization promoting element, there are a deposition method such as a CVD method and a sputtering method, and a coating method in which a solution containing the crystallization promoting element is applied using a spinner. In addition, either the formation of the film containing the crystallization promoting element or the formation of the semiconductor film may be performed first. If the semiconductor film is formed first, the film containing the crystallization promoting element is in close contact with the upper surface of the semiconductor film. If formed and the order of formation is reversed, the film containing the crystallization promoting element is formed in close contact with the lower surface of the semiconductor film. In the present invention, close contact means not only literally close contact between the semiconductor film and the crystallization promoting element, but if the crystallization promoting element can move into the semiconductor film, an oxide film having a thickness of about 10 nm or a natural oxidation film is formed between the films. A configuration in which a film or the like is present is also included.
[0034]
For example, when nickel (Ni) is used as the crystallization promoting element in the introducing step, a Ni film or a Ni silicide film may be formed by a deposition method.
[0035]
In addition, when using the coating method, nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, nickel sulfate, and other nickel salts as solutes, water, alcohol, acid, A solution using ammonia as a solvent or a solution containing nickel as a solute and benzene, toluene, xylene, carbon tetrachloride, chloroform, or ether as a solvent can be used. Alternatively, a material such as an emulsion in which nickel is dispersed in a medium may be used even if nickel is not completely dissolved.
[0036]
Alternatively, a method of forming an oxide film containing nickel by dispersing nickel alone or a nickel compound in a solution for forming an oxide film may be used. As such a solution, Oka (Ohka Diffusion Source) manufactured by Tokyo Ohka Kogyo Co., Ltd. can be used. If this OCD solution is used, a silicon oxide film can be easily formed by coating on the surface to be formed and baking at about 200 ° C. The same applies to other crystallization promoting elements.
[0037]
As a method for introducing the crystallization promoting element, the concentration of the crystallization promoting element in the semiconductor film can be adjusted most easily by the coating method, compared with the doping method or the method of forming the Ni film by the sputtering method. Is also simplified.
[0038]
Further, the crystallization step C is performed while moving (also referred to as diffusion) the crystallization promoting element in the semiconductor film. When the semiconductor film into which the crystallization promoting element is introduced is subjected to heat treatment, the crystallization promoting element immediately moves into the semiconductor film. While the crystallization promoting element moves, it exerts a catalytic action on the molecular chain in the amorphous state to crystallize the semiconductor film.
[0039]
The effect of promoting this crystallization is disclosed by the present applicant in Japanese Patent Application Laid-Open Nos. 06-244103 and 06-244104. Silicon in contact with the crystallization promoting element is bonded to the crystallization promoting element, and silicide is formed. It was found that the crystallization proceeds due to the reaction between the silicide and the amorphous silicon bond. This is because the interatomic distance between the crystallization promoting element and silicon is very close to the interatomic distance of single crystal silicon, and the Ni—Si distance is closest to the single crystal Si—Si distance, which is 0.6%. Short enough.
[0040]
When modeling the reaction of crystallizing an amorphous silicon film using Ni as a crystallization promoting element,
Si [a] -Ni (silicide) + Si [b] -Si [c] (amorphous)
→ Si [a] -Si [b] (crystalline) + Ni-Si [c] (silicide)
It can be expressed by the reaction formula
[0041]
In the above reaction formula, the indices [a], [b], and [c] represent Si atom positions.
[0042]
In the above reaction formula, since the Ni atom in the silicide is replaced with the Si [b] atom of the silicon in the amorphous part, the distance between Si [a] -Si [b] is almost the same as that of the single crystal. Is shown. Further, it is shown that Ni is crystal-grown while diffusing in the semiconductor film. In addition, when the crystallization reaction is completed, Ni is bound to Si and is localized at the terminal end (or the tip of crystal growth). That is, NiSi _x It is irregularly distributed in the film after crystallization in the silicide state represented by The presence of this silicide can be confirmed as a hole by subjecting the crystallized film to FPM treatment.
[0043]
FPM treatment is an FPM that can remove nickel silicide in a short time (50% HF and 50% H ₂ O ₂ The etching is performed by FPM for about 30 seconds, and the presence of nickel silicide can be confirmed by the presence or absence of holes by etching.
[0044]
In the silicon film crystallized by the FPM treatment, holes due to FPM were generated irregularly. This indicates that nickel is localized in the crystallized region, and silicide is formed by bonding with silicon in the localized portion.
[0045]
It has been found that in order to give energy for advancing this crystallization reaction, it is sufficient to heat at 450 ° C. or higher in a heating furnace. Moreover, the upper limit of heating temperature shall be 650 degreeC. This is to prevent the crystallization of the amorphous semiconductor film from proceeding at a portion that does not react with the crystallization promoting element. If crystallization occurs in a portion that does not react with the crystallization promoting element, the crystallization promoting element cannot diffuse into the portion, so that the crystal grains cannot be enlarged and the particle size also varies.
[0046]
In the crystallization step, a semiconductor film crystallized by heat treatment may include defects in crystal grains, and an amorphous portion may remain. Therefore, it is preferable to perform the heat treatment again in order to crystallize the amorphous part and eliminate defects in the grains. This heating temperature is higher than the heat treatment during crystallization, specifically 500 to 1100 ° C., more preferably 600 to 1100 ° C. Needless to say, the upper limit of the actual temperature is determined by the heat-resistant temperature of the substrate.
[0047]
Note that in this step, excimer laser light can be irradiated instead of heat treatment. However, as described above, the excimer laser has an unavoidable variation in irradiation energy, which may cause variations in crystallization of the amorphous portion. In particular, when there is a variation in the distribution of the amorphous portion for each film, not only the characteristics between elements vary in one semiconductor device, but also there may be a variation in characteristics between the semiconductor devices.
[0048]
Therefore, when the excimer laser light is irradiated after the crystallization step, it is desired to heat-treat the amorphous portion to crystallize and reduce defects. Therefore, when an excimer laser is used in the next light annealing step, it is important to perform a treatment for improving crystallinity by a heat treatment.
[0049]
Further, as a heating method equivalent to the heat treatment in the heating furnace, an RTA that irradiates infrared light having a peak at a wavelength of 0.6 to 4 μm, more preferably 0.8 to 1.4 μm for several tens to several hundreds of seconds. The law is known. Since the absorption coefficient for infrared light is high, the semiconductor film is heated to 800 to 1100 ° C. in a short time by irradiation with infrared light. However, since the RTA method has a longer irradiation time than the excimer laser beam, heat is easily absorbed by the substrate, and attention must be paid to the occurrence of warpage when a glass substrate is used.
[0050]
Other methods include pulse oscillation type YAG laser and YVO. _Four There is a method using a laser. In particular, when a laser diode excitation type laser device is used, a high output and a high pulse oscillation frequency can be obtained. Any one of the second harmonic (532 nm), the third harmonic (354.7 nm), and the fourth harmonic (266 nm) is used. For example, a laser pulse oscillation frequency of 1 to 20000 Hz (preferably 10 to 10,000 Hz), a laser Energy density 200-600mJ / cm ² (Typically 300-500mJ / cm ² ). Then, the linear beam is irradiated over the entire surface of the substrate, and the linear beam superposition ratio (overlap ratio) at this time is set to 80 to 90%. When the second harmonic is used, heat is uniformly transferred to the inside of the semiconductor layer, and crystallization is possible even if the irradiation energy range varies somewhat. As a result, a processing margin can be obtained, and variations in crystallization are reduced. Further, since the pulse frequency is high, the throughput is improved.
[0051]
An object of the present invention is to remove (getter) crystallization promoting elements localized in a crystallized semiconductor film. In the present invention, a group 15 element is used to getter the crystallization promoting element. Here, the group 15 elements are P, As, N, Sb, and Bi. P has the highest gettering ability, and then Sb.
[0052]
In the present invention, the crystallization promoting element is removed by selectively adding a group 15 element to the crystallized crystalline semiconductor film to form a region containing the group 15 element, and heat-treating to contain the group 15 element. The crystallization promoting element is moved to the region to be captured and captured. In the step D of adding a group 15 element to the crystalline semiconductor film, a gas phase method such as a plasma doping method or an ion implantation method can be used as in the method of introducing a crystallization promoting element into the semiconductor film.
[0053]
The region to which a group 15 element is added (gettering region) does not include a region that becomes a channel formation region of a crystallized semiconductor film or a region that becomes a channel formation region and a low concentration impurity region, and that becomes a channel formation region Alternatively, a region in contact with a channel formation region and a region to be a low concentration impurity region, specifically, a region including a region to be a source region and a region to be a drain region. By adding a Group 15 element to the source region and the drain region, an impurity element introduction process for reducing resistance can be performed at the same time, and the process can be simplified.
[0054]
As a mask for adding the Group 15 element, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film is preferably used.
[0055]
As long as the region to which the group 15 element is added (gettering region) has at least the size of the region to be the source region and the region to be the drain region, it is sufficient for removing the crystallization promoting element. However, it is preferable if the region to which the group 15 element is added is large, because the removal process is shortened and the temperature is lowered. Therefore, after the step of removing the element that promotes crystallization, the step of patterning the semiconductor film to form the island-shaped semiconductor layer can make the addition region of the group 15 element larger than the source region and the drain region. This is preferable because it is possible.
[0056]
The concentration of the group 15 element in the region to which the group 15 element is added is 10 times the concentration of the crystallization promoting element remaining in the semiconductor film. In the crystallization method of the present invention, 10 ¹⁸ -10 ²⁰ atoms / cm ^Three Since the crystallization promoting element remains in the order, the group 15 element concentration is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three And
[0057]
The removal (gettering) of the crystallization promoting element is performed by the heat treatment step E. By the heat treatment, the crystallization promoting element moves to the region to which the group 15 element is added (gettering region) and is captured (gettering). This step of removing the crystallization promoting element can be regarded as a step of sucking (gettering) the crystallization promoting element in the region to which the group 15 element has been added.
[0058]
This heat treatment is performed before forming the gate electrode and the gate wiring (the gate wiring and the gate electrode are often formed integrally). The temperature at the time of crystallization of the semiconductor film and at the time of removal of the crystallization promoting element must be raised to the highest temperature in the production of the semiconductor device. Therefore, by performing formation of the gate electrode after completion of these steps, a conductive material with low heat resistance can be used as the gate electrode. The characteristic of the gate electrode material required when using the semiconductor device is low resistance, but the characteristic of the gate electrode material required when manufacturing the semiconductor device is heat resistance. Heat resistance is an important characteristic required in order not to impair the reliability of a semiconductor device. A conductive material with low heat resistance could not be used as a gate electrode material no matter how low the resistance was. However, by using the present invention, a gate electrode can be formed using a conductive material with low heat resistance. it can.
[0059]
In the present invention, it is preferable to irradiate the crystallized crystalline semiconductor film with laser light or strong light before this step in order to lower the temperature and shorten the time for removing the crystallization promoting element. By this light irradiation (light annealing), the crystallization promoting element localized in the crystalline semiconductor film can be easily moved.
[0060]
The crystallization promoting element is NiSi _x As shown in the figure, it is distributed in the semiconductor film in a state of being bonded to the semiconductor molecule, but the Ni—Si bond is broken by the energy of light annealing, and the crystallization promoting element is changed to the atomic state, or Ni— This is because since the Si bond energy is lowered, the remaining crystallization promoting element is easily moved in the crystalline semiconductor film.
[0061]
Since the energy required to move the crystallization promoting element can be lowered by the light annealing, the crystallization promoting element can be moved by heating at 500 ° C. or higher, and the processing time can be shortened. You can also Furthermore, since the gettering region is formed in the element formation region, it is not necessary to newly provide a gettering region, and the portion where the element can be formed can be enlarged. The upper limit of the heating temperature in the step of removing the crystallization promoting element is a temperature at which the group 15 element contained in the gettering region does not move, and is 800 ° C. to 850 ° C.
[0062]
In the light annealing step, the portion to be irradiated with light may be irradiated to the portion of the semiconductor film that becomes the semiconductor layer constituting the semiconductor element, and at least a region where the depletion layer of the semiconductor layer is formed (channel formation region) To include.
[0063]
An excimer laser can be used as a light source used for light annealing. For example, KrF excimer laser (wavelength 248 nm), XeCl excimer laser (wavelength 308 nm), XeF excimer laser (wavelength 351, 353 nm), ArF excimer laser (wavelength 193 nm), XeF excimer laser (wavelength 483 nm), or the like can be used. Further, an ultraviolet lamp can be used. Alternatively, an infrared lamp such as a xenon lamp or an arc lamp can be used. Pulsed excimer laser light can be used.
[0064]
Other methods include pulse oscillation type YAG laser and YVO. _Four There is a method using a laser. In particular, when a laser diode excitation type laser device is used, a high output and a high pulse oscillation frequency can be obtained. One of the fundamental wave (1064 nm), the second harmonic (532 nm), the third harmonic (354.7 nm), and the fourth harmonic (266 nm) is used. For example, the laser pulse oscillation frequency is 1 to 20000 Hz (preferably 10-10000Hz), laser energy density 200-600mJ / cm ² (Typically 300-500mJ / cm ² ). Then, the linear beam is irradiated over the entire surface of the substrate, and the linear beam superposition ratio (overlap ratio) at this time is set to 80 to 90%. Further, since the pulse frequency is high, the throughput is improved.
[0065]
In the island-shaped semiconductor layer forming step F, patterning is performed so that the region to which the group 15 element is added becomes a source region and a drain region, and the region to which the group 15 element is not added is a channel formation region or channel. This is performed so as to be a formation region and a low concentration impurity region.
[0066]
After that, a gate electrode is formed through a gate insulating film provided in contact with the semiconductor layer, and the semiconductor layer facing the gate electrode is used as a channel formation region. The gate electrode is formed on the island-like semiconductor layer on the region to which the group 15 element is not added (gettering region) via the gate insulating film.
[0067]
The present invention does not form the source region and the drain region in a self-aligned manner in alignment with the gate electrode. Therefore, by changing the size of the gate electrode, a region in which a group 15 element is added (source region and drain region) when viewed from above and the gate electrode may be overlapped. The region to which the group element is added (source region and drain region) and the gate electrode may be formed so as to be substantially in contact with each other, or the region to which the group 15 element is added (source region and drain region) and the gate electrode are viewed from above. It is also possible to adopt a structure in which the distance between the two is constant.
[0068]
Further, after forming the region to which the group 15 element is added (source region and drain region) and the gate electrode to have a certain distance, that is, in the region of the island-like semiconductor layer to which the group 15 element is not added. A gate electrode is formed on a part (a region to be a channel formation region of a region to be a channel formation region and a low concentration impurity region) through the gate insulating film, and then an impurity element is added using the gate electrode as a mask. When viewed from above, a low-concentration impurity region can be formed between the source and drain regions and the gate electrode.
[0069]
Further, after the low concentration impurity region is formed, a second conductive film is formed as a part of the gate electrode on the first conductive film already formed as the gate electrode, and the low concentration impurity region and the second conductive region are formed. By patterning the second conductive film so that the films overlap, a gate-overlapped LDD (GOLD) structure having a region where the gate electrode and the low-concentration impurity region overlap can be obtained. The GOLD structure can prevent deterioration of the semiconductor device due to hot electron injection. Moreover, although the case where the gate electrode has two layers has been described as an example, a multilayer structure of three or more layers may be used.
[0070]
As described above, according to the present invention, elements having different structures can be manufactured only by changing the size of the gate electrode. Therefore, for example, the element structures of the matrix circuit and the driver circuit on the same panel can be easily changed. Similarly, the N-channel TFT and the P-channel TFT of the matrix circuit can be easily configured differently.
[0071]
It has been found that the removal effect higher than that of the group 15 element can be obtained by adding not only the group 15 element but also the group 13 element to the region for capturing the crystallization promoting element. In this case, the group 13 element concentration is set to 1.3 to 2 times the group 15 element concentration. Group 13 elements are B, Al, Ga, In, and Ti.
[0072]
By the crystallization promoting element removing step of the present invention, the crystallization promoting element concentration is 5 × 10 5. ¹⁷ atoms / cm ^Three The following (preferably 2 × 10 ¹⁷ atoms / cm ^Three A crystalline semiconductor region reduced to the following is obtained.
[0073]
Currently, the lower limit of detection by SIMS (mass secondary ion analysis) is 2 × 10. ¹⁷ atoms / cm ^Three Therefore, it is not possible to examine the concentration below that. However, by performing the removal step shown herein, at least 1 × 10 ¹⁴ ~ 1x10 ¹⁵ atoms / cm ^Three To some extent, it is estimated that crystallization promoting elements are reduced.
[0074]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment of the present invention will be described with reference to FIGS. Note that the group 15 element is an element that imparts N-type conductivity to a semiconductor, and in the embodiment of the present invention, a region that becomes an N-type source region and a region that becomes a drain region are used as gettering regions.
[0075]
Embodiment 1 This embodiment will be described with reference to FIG. As shown in FIG. 3A, a substrate 10 is prepared, and a base film 11 is formed on the surface of the substrate 10. The substrate 10 includes an insulating substrate such as a glass substrate, a quartz substrate, a ceramic substrate, a single crystal silicon substrate, a stainless steel substrate, a Cu substrate, a refractory metal material such as Ta, W, Mo, Ti, Cr, or an alloy thereof ( For example, a conductive substrate such as a substrate made of a nitrogen-based alloy) can be used.
[0076]
The base film 11 has a function of preventing impurities from diffusing from the substrate in the semiconductor device, and a function of improving adhesion of a semiconductor film and a metal film formed on the substrate 10 to prevent peeling. As the base film 11, an inorganic insulating film such as a silicon oxide film formed by a CVD method or the like, or a silicon nitride film or a silicon nitride oxide film can be used. For example, when a silicon substrate is used, the base film can be formed by oxidizing the surface by thermal oxidation. When a heat resistant substrate such as a quartz substrate or a stainless steel substrate is used, an amorphous silicon film may be formed and the silicon film may be thermally oxidized.
[0077]
Further, as the base film 11, a laminated film in which a high melting point metal film such as tungsten, chromium or tantalum or a film having high conductivity such as an aluminum nitride film is formed in the lower layer and the above-described inorganic insulating film is stacked in the upper layer is used. May be. In this case, since the heat generated in the semiconductor device is radiated from the coating under the base film 11, the operation of the semiconductor device can be stabilized.
[0078]
A semiconductor film 12 is formed on the base film 11 by a vapor phase method such as plasma CVD, low pressure CVD, or thermal CVD. Here, an amorphous silicon film is formed to a thickness of 10 to 150 nm by a low pressure CVD method. The plasma CVD method is more productive than the low pressure CVD method, but the low pressure CVD method takes time to form a film, but has an advantage that a denser film can be formed than the plasma CVD method. (Fig. 3 (A))
[0079]
Next, a crystallization promoting element is introduced into the semiconductor film 12. Here, a method of forming a film 13 containing a crystallization promoting element on the surface of the semiconductor film 12 is used. For example, in a spinner, Ni acetate solution is applied and this state is maintained for several minutes. A Ni film is formed as the film 13 by drying using a spinner. When the concentration of nickel in the solution is 1 ppm or more, preferably 10 ppm or more, it becomes practical. The Ni film is not necessarily in the form of a film, but it can be used even if it is not in the form of a film. (Fig. 3 (B))
[0080]
Then, in the heating furnace, the semiconductor film 12 into which the crystallization promoting element is introduced is heat-treated to form the crystalline semiconductor film 15. Regarding the heat treatment conditions, the atmosphere is an inert atmosphere such as nitrogen, and the temperature is 450 ° C. to 650 ° C., preferably 500 ° C. to 650 ° C., and the time is 4 to 24 hours. In this embodiment, since nickel element is in contact with the entire surface of the semiconductor film, the moving direction of nickel moves from the semiconductor film surface to the base film direction, that is, a direction substantially perpendicular to the substrate surface, and crystallization proceeds in that direction. . (Figure 3 (C))
[0081]
Next, a group 15 element is selectively added to a region including a region to be a source region and a drain region of the crystalline semiconductor film 15. First, the mask insulating film 16 is formed over a region to be a channel formation region of the semiconductor film 15 or a region including a channel formation region and a region to be a low concentration impurity region. As the mask insulating film 16, a resist, silicon oxide, or the like can be used, but an inorganic insulating film is preferable. Here, a silicon oxide film having a thickness of 100 nm is formed and patterned to form the mask insulating film 16. Then, a group 15 element is selectively added by a plasma doping method, a coating method, or the like to form a group 15 addition region 15 a in the semiconductor film 15. For convenience, the region 15b to which no group 15 element is added is referred to as a gettering region. (Fig. 3 (D))
[0082]
The group 15 element concentration in the region 15a is 10 times the crystallization promoting element concentration in the gettering region 15b. In the method of this embodiment, the area 15b has 10 ¹⁹ -10 ²⁰ atoms / cm ^Three Since the crystallization promoting element remains in the order, the concentration of the group 15 element in the region 15a is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three And
[0083]
Next, a region including a region that serves as a source region and a drain region for the crystallization promoting element remaining in the gettering region 15b by heat treatment at 500 to 850 ° C., more preferably 550 ° C. to 650 ° C. for 4 to 8 hours. It moves to the group 15 element addition area | region 15a which is, and is made to absorb there. The crystallization promoting element that has reached the regions to be the source region and the drain region is combined with the Group 15 element. For example, when the crystallization promoting element is Ni and the group 15 element is P, NiP is used in the source and drain regions. ₁ , NiP ₂ Ni ₂ It exists in a combined state such as. This coupling state is very stable and hardly affects the operation of the TFT. (Figure 3 (E))
By this heat treatment, the concentration of the crystallization promoting element (Ni) in the region 15b is 2 × 10. ¹⁷ atoms / cm ^Three Reduced to: Further, the resistance of the region serving as the source region and the region serving as the drain region can be reduced by activating the group 15 element added to the region serving as the source region and the region serving as the drain region.
[0084]
Then, after the step of removing the crystallization promoting element, the region 15 is patterned into an island shape so that all or part of the region 15a becomes a source region and a drain region, thereby forming an island-shaped semiconductor layer 17. A semiconductor element such as a TFT may be manufactured using the semiconductor layer 17.
[0085]
In the present invention, since the group 15 element is added to the source region and the drain region in contact with the gettering region from which the crystallization promoting element is removed before the crystallization promoting element removing step, the time required for the removing step is increased. Can be shortened.
In this embodiment, since the regions to be the source region and the drain region are used for the group 15 added region which is the gettering region, that is, the group 15 added region which is the gettering region is formed in the element forming portion, the elements can be integrated. .
[0086]
Embodiment 2 This embodiment will be described with reference to FIG. The present embodiment is a modification of the catalyst introduction method of the first embodiment. In addition, a method for forming a gate insulating film after the semiconductor layer is formed will be described. The rest is the same as in the first embodiment.
[0087]
The substrate described in Embodiment 1 is prepared, and a base film 21 is formed on the surface of the substrate 20. Next, an amorphous silicon film is formed as the semiconductor film 22 by low pressure thermal CVD. The film thickness of the amorphous silicon film is 20 to 100 nm (preferably 40 to 75 nm). Here, the film thickness is 65 nm. Note that a plasma CVD method may be used as long as a film quality equivalent to an amorphous silicon film formed by a low pressure thermal CVD method can be obtained.
[0088]
Next, a mask insulating film 23 is formed on the semiconductor film 22 made of an amorphous silicon film. An opening 23a is provided in the mask insulating film 23 by patterning. The opening 23a defines a region where the crystallization promoting element is added. As the mask insulating film 23, a resist or a silicon oxide film can be used. Here, a silicon oxide film with a thickness of 120 nm is formed.
[0089]
Next, a solution in which nickel acetate containing nickel of 5 to 10 ppm by weight is dissolved in ethanol is applied by a spin coating method and dried to form a Ni film as a mask insulating film 23 as a film 24 containing a crystallization promoting element. Form on top. In this state, nickel is in contact with the semiconductor film 22 in the opening 23 a provided in the mask insulating film 23. (Fig. 4 (A))
[0090]
Next, after dehydrogenating at 450 ° C. for about 1 hour in a heating furnace, nickel is moved from the region 22a to which nickel is added to the semiconductor film 22, so that an inert atmosphere, a hydrogen atmosphere or an oxygen atmosphere is used in the heating furnace. , Heat treatment is performed at a temperature of 450 to 650 ° C. for a heating time of 4 to 24 hours. By heating, nickel is crystallized while moving in the semiconductor film 22 as schematically indicated by arrows. Here, a heat treatment is performed at 570 ° C. for 8 hours to form a crystalline semiconductor film 25 containing nickel. (Fig. 4 (B))
[0091]
In this step, a crystal region (referred to as a lateral growth region) 25b is formed which proceeds preferentially from the nickel silicide reacted in the region 22a to which nickel is added and grows substantially parallel to the substrate surface of the substrate 20. The laterally grown region 25b has an advantage of being excellent in overall crystallinity because individual crystal grains are gathered in a relatively aligned state. Note that the region 25a is a region into which a crystallization promoting element is introduced, and is crystallized, but the crystallization promoting element remains at a high concentration, and thus is unsuitable for an element. The non-crystallized region 25c is a region where the crystallization promoting element has not moved, and is a region where crystallization has not progressed. Therefore, only the lateral growth region 25b is suitable for forming a high-performance element.
[0092]
According to TEM (transmission electron microscopy) observation, the crystal grains in the lateral growth region 25b in the crystalline semiconductor film are rod-shaped or flat rod-shaped, and the orientations of these crystal grains are almost uniform. Almost all of these crystal grains are roughly {110} oriented, the directions of the <100> axis and the <111> axis are the same for each crystal grain, and the <110> axis is slightly less than 2 ° between the crystal grains. It is shaking. As described above, since the orientations of the crystal axes are aligned in the lateral growth region 26b, the bonding of atoms at the crystal grain boundary becomes smooth, and the number of dangling bonds becomes small.
[0093]
On the other hand, since conventional polycrystalline silicon has irregular crystal axis directions for each crystal grain, there are many atoms that cannot be bonded at grain boundaries. In this respect, the crystal structure of the lateral growth region 25b of this embodiment and the conventional polycrystalline silicon film are completely different. In the lateral growth region 25b, the bonding of almost all atoms is not interrupted at the crystal grain boundary, and the two crystal grains are joined with extremely good consistency. The trap level due to the above is very difficult to make.
[0094]
Next, as in the first embodiment, a mask insulating film 27 made of a silicon oxide film is formed. The lateral growth region 25b is included in the gettering region 26a which is a channel formation region or a region that becomes a channel formation region and a low concentration impurity region. Then, P (phosphorus) is added as a group 15 element to form a group 15 element added region 26c. The nickel concentration remaining in the lateral growth region 25a is about 1/10 that of the first embodiment, that is, 10%. ¹⁸ -10 ¹⁹ atoms / cm ^Three Therefore, the concentration of phosphorus in the region 26c is 1 × 10 ¹⁹ ~ 1x10 ²⁰ atoms / cm ^Three And (Fig. 4 (C))
[0095]
Note that the Group 15 element passes through the region 26c film and is also added to the base film 21 and the substrate 20, so that only a specific region in the base film 21 or the substrate 22 contains a high concentration of Group 15 element. However, such a group 15 element does not adversely affect the TFT characteristics.
[0096]
Then, after forming the addition region 26c, heat treatment is performed at 500 to 850 ° C. for 2 to 24 hours, and the crystallization promoting element in the gettering region 26a is moved to the group 15 element addition region 26c. Let 26c absorb (the direction of movement is indicated by an arrow). Thus, the crystallization promoting element is 5 × 10 ¹⁷ atoms / cm ^Three 1 × 10 below ¹⁴ ~ 1x10 ¹⁵ atoms / cm ^Three A lateral growth region with a reduced thickness can be obtained. (Fig. 4 (D))
[0097]
After the crystallization accelerating element removal step is completed, after removing the mask insulating film 27, the region 26a is formed into a channel formation region or a channel formation region so that the region 26c becomes a source region and a drain region. Then, the island-shaped semiconductor layer 28 is formed by patterning into an island shape so as to be a low-concentration impurity region.
[0098]
Next, an insulating film 30 made of silicon nitride oxide is formed so as to cover the semiconductor layer 28 by plasma CVD or low pressure thermal CVD. This insulating film 30 constitutes a gate insulating film, and its film thickness is 50 to 150 nm.
[0099]
Next, a gate electrode 31 is formed on the insulating film 30. For example, refractory metals such as silicon, Al, Ta, W, Mo, Ti, Cr added with P or alloys thereof (for example, alloys of refractory metals, alloys of refractory metals and nitrogen, etc.) Can be used.
[0100]
A TFT can be manufactured by using the semiconductor layer 28, the insulating film 30, and the gate electrode 31 obtained through the above steps.
[0101]
Embodiment 3 This embodiment will be described with reference to FIG.
In the present embodiment, the crystallization promoting element is removed after the formation of the island-like semiconductor layer (after patterning). Others are the same as those in the first or second embodiment.
First, the semiconductor film is crystallized according to the steps described in Embodiment 1 or Embodiment 2, and the obtained crystalline semiconductor film is patterned to form the island-shaped semiconductor layer 35. (Fig. 5 (A))
[0102]
Next, as in the first and second embodiments, a mask insulating film 37 made of a silicon oxide film is formed. Then, P (phosphorus) is added as a group 15 element to the source region and the drain region to form a group 15 element added region 36c. (Fig. 5B)
[0103]
Then, after forming the addition region 36c, heat treatment is performed at 500 to 850 ° C. for 2 to 24 hours, and the crystallization promoting element in the gettering region 36d is moved to the group 15 element addition region 36c and absorbed. (The direction of movement is indicated by an arrow). Thus the catalyst is 5 × 10 ¹⁷ atoms / cm ^Three 1 × 10 below ¹⁴ ~ 1x10 ¹⁵ atoms / cm ^Three A reduced area is obtained. (Fig. 5 (C))
[0104]
Since the source region and the drain region of the semiconductor layer obtained by the above steps have a high nickel element concentration, the resistance of the source region and the drain region can be reduced as compared with the first and second embodiments.
[0105]
Embodiment 4 This embodiment will be described with reference to FIG.
In the present embodiment, a low concentration impurity region is formed using a gettering region as a channel formation region and a low concentration impurity region. The present embodiment can also be applied to the first to third embodiments.
First, according to the steps described in the first to third embodiments, the formation of the island-like semiconductor layer 48 from which the crystallization promoting element in the gettering region 46d is removed is performed, and the gate insulating film 50 is formed thereon. (Fig. 6 (A))
[0106]
Next, the gate electrode 51 is formed. For example, refractory metals such as silicon, Al, Ta, W, Mo, Ti, Cr added with P or alloys thereof (for example, alloys of refractory metals, alloys of refractory metals and nitrogen, etc.) Use to form. The gate electrode 51 is formed on a part of the gettering region 46d (a region to be a channel formation region among regions to be a channel formation region and a low concentration impurity region). (Fig. 6 (B))
[0107]
Next, an impurity is added using the gate electrode as a mask to form a low concentration impurity region 52. Impurity was added by doping at a high acceleration and a low dose so that phosphorus was added to the semiconductor layer through the gate insulating film. The conditions are an acceleration voltage of 80 kV and a set dose of 6 × 10 ¹³ atoms / cm ^Three And the addition amount is 1 × 10 ¹⁶ ~ 1x10 ¹⁹ atoms / cm ^Three And
[0108]
Through the above steps, a low concentration impurity region can be formed without using a new mask.
[0109]
Further, after the low concentration impurity region is formed using this embodiment, a second conductive film is formed as a part of the gate electrode on the first conductive film already formed as the gate electrode, and the low concentration impurity region is formed. A gate overlapped LDD (GOLD) structure having a region where the gate electrode and the low concentration impurity region overlap may be obtained by patterning the second conductive film so that the second conductive film overlaps. Is possible. The GOLD structure can prevent deterioration of the semiconductor device due to hot electron injection. Further, the gate electrode may have a multilayer structure of three or more layers instead of two layers.
[0110]
【Example】
Embodiments of the present invention will be described with reference to FIGS. Embodiments 1 to 4 may be applied to the examples.
[0111]
[Embodiment 1] This embodiment is an example in which the present invention is applied to a TFT, and shows an example in which an N-channel TFT and a P-channel TFT are formed on the same substrate to produce a CMOS circuit. 7 to 9 are used for the description.
[0112]
FIG. 7 shows a schematic top view of a CMOS circuit. In FIG. 7, 111 is a gate wiring, 108 is an N-channel TFT semiconductor layer, and 109 is a P-channel TFT semiconductor layer. Reference numerals 161 and 162 denote contact portions between the semiconductor layers 108 and 109 and the source wiring, and reference numerals 163 and 164 denote contact portions between the semiconductor layers 108 and 109 and the drain wiring. Reference numeral 165 denotes a contact portion (gate contact portion) between the gate wiring 111 and the extraction wiring.
[0113]
The TFT manufacturing process will be described with reference to FIGS. 8 and 9, a cross-sectional view of the N-channel TFT is shown on the left side, and a cross-sectional view of the P-channel TFT is shown on the right side. The sectional view of each TFT corresponds to the sectional view taken along the chain line AA ′ and the chain line BB ′ in FIG.
[0114]
First, a 1737 glass substrate manufactured by Corning is used as the substrate 100. A silicon oxide film 101 having a thickness of 300 nm is formed on the glass substrate 100 as a base film.
[0115]
When a substrate having an insulating surface is thus prepared, an amorphous silicon film 102 is formed using disilane as a source gas as a semiconductor film by low pressure thermal CVD. The film thickness of the amorphous silicon film 102 is 55 nm. Next, a mask insulating film 103 made of a silicon oxide film having a thickness of 120 nm is formed on the amorphous silicon film 102. The mask insulating film 103 is provided with openings 103a and 103b by patterning.
[0116]
Next, a solution obtained by dissolving nickel acetate containing 10 ppm of nickel in weight in ethanol is applied by a spin cotter and dried to form the Ni film 104. The Ni film 104 is in contact with the amorphous silicon film 102 in the openings 103 a and 103 b provided in the mask insulating film 103. Note that since the amorphous silicon film 102 has poor infiltration, if an oxide film of about several nm is formed by UV irradiation or the like before the mask insulating film 103 is formed, the Ni film 104 has openings 103a and 103b. It becomes easy to form in the state which touched by. (Fig. 8 (A))
[0117]
When the state of FIG. 8A is obtained in this manner, heat treatment is performed in a heating furnace at 450 ° C. for about 1 hour to release hydrogen from the amorphous silicon film 102, and then in the heating furnace, a nitrogen atmosphere, 570 A heat treatment is performed at 14 ° C. for 14 hours. Ni moves from the Ni film 104 into the amorphous silicon film 102, and crystallization progresses to form a crystalline silicon film 106 having lateral growth regions 106a and 106b. (Fig. 8 (B))
[0118]
When the crystallization step is completed, it is preferable to heat the crystalline silicon film 106 at 600 ° C. for 1 to 4 hours to crystallize the amorphous portion and improve the crystallinity. Further, it is preferable to irradiate the crystalline silicon film 106 with KrF excimer laser light so that Ni localized in the film can be easily moved. The excimer laser is processed into a linear laser beam with a width of 0.5 mm and a length of 12 cm by an optical system, and the substrate is scanned in one direction relative to the linear laser beam. To do. Alternatively, laser light can be processed and irradiated on a rectangle having a side of about 5 to 10 cm.
[0119]
Next, a mask insulating film 118 is formed over a channel formation region of the semiconductor film or a gettering region including a channel formation region and a region that becomes a low-concentration impurity region, and a group 15 element is added to the semiconductor film. A region to be a source region and a drain region of the type TFT is formed. P (phosphorus) is added to the doping gas using phosphine diluted to 5% with hydrogen. Doping is performed at a low acceleration and a high dose. The doping condition is such that the P concentration is 10 times the Ni concentration remaining in the semiconductor film 106, the acceleration voltage is 80 kV, and the set dose is 6 × 10. ¹³ atoms / cm ^Three And the addition amount is 1 × 10 ¹⁹ ~ 1x10 ^{twenty two} atoms / cm ^Three And (Fig. 8 (C))
[0120]
N in the semiconductor film 106 ⁺ A mold region 107 is formed. Here, N of the semiconductor film 106 ⁺ A part of the mold region 107 becomes a source and drain region, and the region 123 becomes a channel formation region and a low concentration impurity region.
[0121]
By performing heat treatment in this state, N ⁺ The nickel in the regions 123 and 133 in which phosphorus is not added to the mold region 107 can be absorbed. Ni which is intentionally added for crystallization of the amorphous silicon film is formed from the channel formation region or the regions 123 and 133 including the channel formation region and the low-concentration impurity region as schematically shown by arrows in FIG. The region moves to the source region and the drain region. As a result, Ni in the channel formation region and the region serving as the low concentration impurity region is reduced, while the Ni concentration in the source region and drain region used for the gettering sink is higher than that in the channel formation regions 123 and 133. Get higher.
[0122]
Next, the crystalline silicon film 106 is patterned into an island shape to form semiconductor layers 108 and 109. Note that the above-described excimer laser irradiation may be performed after the semiconductor layers 108 and 109 are formed. (Fig. 8 (D))
[0123]
Next, SiH is performed by plasma CVD. _Four And N ₂ A silicon nitride oxide film 110 is formed to a thickness of 120 nm using O as a source gas. Next, a tantalum film (Ta film) having a thickness of 40 nm is formed on the silicon nitride oxide film 110 by a sputtering apparatus and patterned to form the gate electrode 111. The gate electrode is disposed over a part of a region to which phosphorus is not added (a region that becomes a channel formation region among a region that becomes a channel formation region and a low-concentration impurity region of an N-channel TFT). The above excimer laser light irradiation may be performed before the Ta film is formed. In this embodiment, at least a region to be a channel formation region may be irradiated with laser light. (Fig. 8 (E))
[0124]
Then, low concentration impurity regions 124 and 125 are formed by adding impurities using the gate electrode 111 as a mask. Impurity was added by doping at a high acceleration and a low dose so that phosphorus was added to the semiconductor layer through the gate insulating film. The conditions are an acceleration voltage of 80 kV and a set dose of 6 × 10 ¹³ atoms / cm ^Three And the addition amount is 1 × 10 ¹⁶ ~ 1x10 ¹⁹ atoms / cm ^Three And (Fig. 9 (A))
[0125]
Next, B (boron) which is a group 13 element is added to the semiconductor layer 109 of the P-channel TFT. After the N-channel TFT is covered with the resist mask 140, B is added to the semiconductor layer 109. Diborane diluted to 5% with hydrogen is used as the doping gas, and P ⁺ Regions 141 and 142 to be a source region and a drain region of the mold are formed. (Fig. 9 (B))
[0126]
After the regions to be the source region and the drain region are formed, the resist mask 140 is removed, and heat treatment is performed in an electric furnace at 350 ° C. to 550 ° C., here 450 ° C. for 2 hours. By this heat treatment, phosphorus and boron added to the source and drain regions 121, 122, 141, 142 and the low-concentration impurity regions 124, 125 are activated.
[0127]
Next, an interlayer insulating film 150 made of a silicon oxide film is formed. After a contact hole is formed in the interlayer insulating film 150, a laminated film made of titanium / aluminum / titanium is formed as an electrode material and patterned to form wirings 151 to 153. Here, an N-channel TFT and a P-channel TFT are connected by a wiring 153 to form a CMOS circuit. Furthermore, a lead-out wiring for the gate wiring connected to the gate electrode 111 (not shown) is also formed. Finally, hydrogenation treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere, and hydrogen termination treatment is performed on the entire TFT. (Figure 9 (C))
[0128]
Example 2 This example will be described with reference to FIG. The present embodiment is an example in which a GOLD structure is formed by modifying the first embodiment. The GOLD structure of the present embodiment may be applied to the first embodiment.
[0129]
The process is performed in the same manner as in Example 1 until the island-shaped semiconductor region in which the crystallization promoting element is reduced is formed. Next, a 20 nm thick silicon nitride film / 100 nm thick silicon nitride oxide film 210 is formed as a gate insulating film.
[0130]
Next, a gate electrode and a low concentration impurity region are formed. A first conductive film 215 and a second conductive layer 216 are formed over the surface of the silicon nitride oxide film 210. The first conductive film 215 may be formed of a material selected from Ti, Ta, W, and Mo or a material thereof. Further, a conductive material containing the above material as a main component may be used in consideration of electric resistance and heat resistance. The thickness of the first conductive film needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, a Ti film having a thickness of 50 nm was formed by sputtering.
[0131]
The second conductive layer 216 is preferably formed using a material selected from Al and Cu. This is provided to lower the electric resistance of the gate electrode, and is formed to a thickness of 50 to 400 nm, preferably 100 to 200 nm. When Al is used, pure Al may be used, or an Al alloy to which an element selected from Ti, Si, and Sc is added in an amount of 0.1 to 5 atom% may be used. In the case of using copper, although not shown, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 210.
[0132]
Here, an Al film added with 0.5 atom% of Sc was formed to a thickness of 200 nm by sputtering. (Fig. 10 (A))
Then, a step of forming a resist mask 314 in a region where a P-channel TFT is formed and adding a first impurity element imparting N-type conductivity was performed. Phosphorus (P), arsenic (As), antimony (Sb), and the like are known as impurity elements imparting N-type to crystalline semiconductor materials. Here, phosphorous is used, and phosphine (PH _Three ) Using an ion doping method. In this step, in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 210 and the first conductive film 215, the acceleration voltage was set to be as high as 80 keV. The concentration of phosphorus added to the semiconductor layer is 1 × 10 ¹⁶ ~ 1x10 ¹⁹ atoms / cm ^Three In the range of 1 × 10 ¹⁸ atoms / cm ^Three It was. Then, regions 315 and 316 in which phosphorus was added to the semiconductor layer at a low concentration were formed. (Fig. 10 (B))
[0133]
Then, after removing the resist mask 314, a third conductive film (not shown) was formed in close contact with the first conductive film 215 and the second conductive layer 216. The third conductive film may be formed of a material selected from Ti, Ta, W, and Mo, but a compound containing the above material as a main component may be used in consideration of electric resistance and heat resistance. For example, the thickness of the third conductive film needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, a Ta film having a thickness of 50 nm was formed by sputtering. After that, the first conductive film and the third conductive film were simultaneously patterned to form the first conductive layer 217 and the third conductive layer 218 having the same length in the channel length direction. (Fig. 10 (C))
Next, B (boron) which is a group 13 element is added to the semiconductor layer 209 of the P-channel TFT. After the N-channel TFT is covered with the resist mask 240, B is added to the semiconductor layer 209. Diborane diluted to 5% with hydrogen is used as the doping gas, and P ⁺ Form source and drain regions 241 and 242 are formed. (Figure 10 (D))
[0134]
After forming the source region and the drain region, the resist mask 240 is removed, and heat treatment is performed at 450 ° C. for 2 hours in an electric furnace. Simultaneously with gettering by this heat treatment, phosphorus and boron added to the source and drain regions 211, 212, 241, 242, and the low-concentration impurity regions 315, 316 are activated.
[0135]
Next, an interlayer insulating film 256 made of a silicon oxide film is formed. After a contact hole is formed in the interlayer insulating film 256, a laminated film made of titanium / aluminum / titanium is formed as an electrode material and patterned to form wirings 251 to 253. Here, an N-channel TFT and a P-channel TFT are connected by a wiring 253 to form a CMOS circuit. Further, an extraction wiring for the gate wiring 111 (not shown) is also formed. Finally, hydrogenation treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere, and hydrogen termination treatment is performed on the entire TFT. (Fig. 10 (E))
[0136]
Example 3 This example will be described with reference to FIG. In this embodiment, the gate electrode is formed after the activation process, and the lowering of the reliability due to the poor heat resistance of the gate electrode can be further prevented than in the first and second embodiments. The present embodiment may be applied to the first embodiment or the second embodiment.
[0137]
The same process as in Example 1 is performed until the addition of Group 15 elements. By performing heat treatment in this state, N ⁺ Although nickel in the regions 323 and 333 to which phosphorus is not added can be absorbed into the mold regions 311, 312, and 313, in this embodiment, a group 13 element B (boron) is formed in a region that becomes a P-channel TFT. After adding, crystallization promoting element removal step is performed.
[0138]
Therefore, after covering the N-channel TFT with the resist mask 340, B is added to the semiconductor film to be the P-channel TFT. Diborane diluted to 5% with hydrogen is used as the doping gas, and P ⁺ The source and drain regions 341 and 342 and the region 343 to be a channel formation region are formed. (Fig. 11 (B))
[0139]
In order to cause the P-channel source and drain regions 341 and 342 to absorb the crystallization promoting element, the concentration of boron ions is set to about 1.3 to 2 times the concentration of phosphorus ions added to the regions.
[0140]
After impurities are added to the source region and the drain region, heat treatment is performed at 500 ° C. for 2 hours in an electric furnace. By this heat treatment, Ni intentionally added for crystallization of the amorphous silicon film is supplied from the gettering regions 323 and 343 to the respective sources as schematically shown by arrows in FIG. The region and drain regions 321, 322, 341 and 342 are moved. As a result, Ni in the gettering regions 323 and 343 decreases, and on the other hand, the Ni concentration in the source and drain regions 321, 322, 341 and 342 used for the gettering sink is higher than that in the gettering regions 323 and 343. Also gets higher. (Fig. 11 (C))
[0141]
Further, phosphorus and boron added to the source and drain regions 321, 322, 341, and 342 are activated simultaneously with the gettering by this heat treatment.
Next, SiH is performed by plasma CVD. _Four And N ₂ A silicon nitride oxide film 310 is formed to a thickness of 120 nm using O as a source gas. Next, the P-channel TFT on the silicon nitride oxide film 310 is covered with a resist mask or mask insulating film 350, and a resist mask or mask insulating film 351 is formed on the channel formation region of the N-channel TFT. Add phosphorus. The concentration of phosphorus added to the semiconductor layer is 1 × 10 ¹⁶ ~ 1x10 ¹⁹ atoms / cm ^Three In the range of 1 × 10 ¹⁸ atoms / cm ^Three It was. In this way, low-concentration impurity regions 355 and 356 of the N-channel TFT are formed. (Fig. 11 (D))
[0142]
Then, it is preferable to heat-process at 450 degreeC for 2 hours in an electric furnace. By this heat treatment, phosphorus and boron added to the source and drain regions 321, 322, 341, and 342 and the low-concentration impurity regions 355 and 356 are activated.
[0143]
Next, a conductive film for forming the gate wiring 360 is formed. Here, tantalum nitride (TaN _x ) / Tantalum (Ta) / tantalum nitride (TaN) _x 3 layers were formed by sputtering. TaN _x The thickness of the film is 50 nm, and the thickness of the Ta film is 250 nm. Then, the three-layer film is patterned to form a gate wiring 360. In this embodiment, the N-channel TFT has a GOLD structure, and the P-channel TFT has a structure without a low concentration impurity region. (Figure 11 (E))
[0144]
Next, an interlayer insulating film 370 made of a silicon oxide film is formed. After forming contact holes in the interlayer insulating film 370, a laminated film made of titanium / aluminum / titanium is formed as an electrode material and patterned to form wirings 371 to 373. Here, an N-channel TFT and a P-channel TFT are connected by a wiring 373 to form a CMOS circuit. Further, an extraction wiring for the gate wiring 360 (not shown) is also formed. Finally, hydrogenation treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere, and hydrogen termination treatment is performed on the entire TFT. (Fig. 11 (F))
[0145]
[Embodiment 4] In this embodiment, the TFT described in Embodiment 1 is applied to an active matrix substrate. The active matrix substrate of this embodiment is used for a flat-plate electro-optical device such as a liquid crystal display device or an EL display device. The present embodiment may be applied to the second embodiment or the third embodiment.
[0146]
The present embodiment will be described with reference to FIGS. 12 to 14, the same reference numerals denote the same components. FIG. 12 is a schematic perspective view of the active matrix substrate of this embodiment. The active matrix substrate includes a pixel portion 401, a scanning line driving circuit 402, and a signal line driving circuit 403 formed on the glass substrate 400. The scanning line driving circuit 402 and the signal line driving circuit 403 are connected to the pixel portion 401 by the scanning line 502 and the signal line 503, respectively, and these driving circuits 402 and 403 are mainly composed of CMOS circuits.
[0147]
The scanning line 502 is formed for each row of the pixel portion 401, and the signal line 503 is formed for each column. In the vicinity of the intersection of the scanning line 502 and the signal line 503, a pixel TFT 406 connected to each of the wirings 502 and 503 is formed. A pixel electrode 407 and a storage capacitor 408 are connected to the pixel TFT 406.
[0148]
First, according to the TFT manufacturing process of Embodiment 1, the N-channel TFT and the P-channel TFT of the drive circuits 402 and 403 and the pixel TFT 406 of the pixel portion 401 are completed.
[0149]
FIG. 13A is a top view of the pixel portion 401 and is a top view of almost one pixel. FIG. 13B is a top view of a CMOS circuit included in the driver circuits 402 and 403. FIG. 14 is a cross-sectional view of the active matrix substrate, and is a cross-sectional view of the pixel portion 401 and the CMOS circuit. A cross-sectional view of the pixel portion 401 is a cross-sectional view taken along a chain line AA ′ in FIG. 13A, and a cross-sectional view of the CMOS circuit is a cross-sectional view taken along a chain line BB ′ in FIG. .
[0150]
A pixel TFT 406 in the pixel portion 401 is an N-channel TFT. The semiconductor layer 501 is bent in a “U” shape (horse-shoe shape). A scanning line 502 which is a first layer wiring intersects the semiconductor layer 501 with the gate insulating film 510 interposed therebetween.
[0151]
The semiconductor layer 501 includes N ⁺ Mold regions 511 to 513, two channel formation regions 514 and 515, low-concentration impurity regions (N ^- Mold regions) 516 to 519 are formed. N ⁺ The mold regions 511 and 512 are a source region and a drain region.
[0152]
On the other hand, in the CMOS circuit, one gate wiring 601 intersects the two semiconductor layers 602 and 603 with the gate insulating film 610 interposed therebetween. The semiconductor layer 602 includes a source region and a drain region (N ⁺ Mold regions) 611, 612, channel formation region 613, low concentration impurity region (N ^- Mold regions) 614 and 615 are formed. The semiconductor layer 603 includes a source region and a drain region (P ⁺ Mold regions) 621 and 622 and a channel formation region 623 are formed.
[0153]
After the source region and the drain region are formed in the semiconductor layers 501, 602, and 603, an interlayer insulating film 430 is formed over the entire surface of the substrate. On the interlayer insulating film 430, a signal line 503, a drain electrode 504, source electrodes 631 and 632, and a drain electrode 633 are formed as a second layer wiring / electrode.
[0154]
The scan line 502 and the signal line 503 are orthogonal to each other with the interlayer insulating film 430 interposed therebetween as shown in FIG. The drain electrode 504 is an extraction electrode for connecting the drain region 512 to the pixel electrode 505 and is a lower electrode of the storage capacitor 408. In order to increase the capacity of the storage capacitor 408, the drain electrode 504 is made as wide as possible as long as the opening is not lowered.
[0155]
A first planarization film 440 is formed on the second-layer wiring / electrode. In this embodiment, a stacked film of silicon nitride (50 nm) / silicon oxide (25 nm) / acryl (1 μm) is used as the first planarizing film 440. Since organic resin films such as acrylic, polyimide, and benzocyclobutene (BCB) are solution-coated insulating films that can be formed by spin coating, a film thickness of about 1 μm can be formed with high throughput. A flat surface is obtained. Furthermore, since the organic resin film has a lower dielectric constant than silicon nitride or silicon oxide, parasitic capacitance can be reduced.
[0156]
Next, source wirings 641 and 642, a drain wiring 643, and a black mask 520 made of a light-shielding conductive film such as titanium or chromium are formed on the first planarization film 440 as a third-layer wiring. . As shown in FIG. 13A, the black mask 520 is integrated with the pixel portion 401 and overlaps with the periphery of the pixel electrode 505 so as to cover all portions that do not contribute to display. Note that the black mask 520 is arranged as indicated by a dotted line in FIG. Further, the potential of the black mask 520 is fixed to a predetermined value.
[0157]
Prior to the formation of the third-layer wirings 641, 642, 643, and 520, the first planarization film 440 is etched to form a recess 530 on the drain electrode 504 leaving only the lowermost silicon nitride film. Form.
[0158]
In the recess 530, the drain electrode 504 and the black mask 520 are opposed to each other with only the silicon nitride film interposed therebetween. Therefore, in the recess 530, the storage capacitor having the drain electrode 504 and the black mask 520 as electrodes and the silicon nitride film as a dielectric is used. 408 is formed. Silicon nitride has a high relative dielectric constant, and a larger capacity can be secured by reducing the film thickness.
[0159]
A second planarization film 450 is formed on the third-layer wirings 641, 642, and 520. The second planarization film 450 is formed of 1.5 μm thick acrylic. Although a portion where the storage capacitor 408 is formed has a large step, such a step can be sufficiently flattened.
[0160]
Contact holes are formed in the first planarization film 440 and the second planarization film 450, and a pixel electrode 505 made of a transparent conductive film such as ITO or tin oxide is formed. Thus, the active matrix substrate is completed.
[0161]
When the active matrix substrate of this embodiment is used for a liquid crystal display device, an alignment film (not shown) is formed so as to cover the entire surface of the substrate. If necessary, the alignment film is rubbed
[0162]
Note that an active matrix substrate for a reflective AMLCD can be manufactured by using a conductive film having a high reflectance, typically aluminum or a material containing aluminum as a main component, as the pixel electrode 505.
[0163]
In this embodiment, the pixel TFT 406 has a double gate structure, but may have a single gate structure or a multi-gate structure such as a triple gate structure. Further, it can be formed using the inverted staggered TFT shown in Embodiment 1. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. Since the feature of the present invention is the configuration of the gate wiring, the practitioner may determine the other configurations as appropriate.
[0164]
[Embodiment 5] In this embodiment, as an example of an electro-optical device using the active substrate shown in Embodiment 4, an example in which an active matrix liquid crystal display device (referred to as AMLCD) is configured will be described.
[0165]
The appearance of the AMLCD of this example is shown in FIG. 15A, the same reference numerals as those in FIG. 12 denote the same components. The active matrix substrate includes a pixel portion 401, a scanning line driver circuit 402, and a signal line driver circuit 403 formed on the glass substrate 400.
[0166]
The active matrix substrate and the counter substrate 700 are bonded together. Liquid crystal is sealed in the gap between these substrates. However, an external terminal is formed in the TFT manufacturing process on the active matrix substrate, and a portion where the external terminal is formed does not face the counter substrate 700. An FPC (flexible printed circuit) 710 is connected to the external terminal, and external signals and power are transmitted to the circuits 401 to 403 via the FPC 710.
[0167]
In the counter substrate 700, a transparent conductive film such as an ITO film is formed on the entire surface of a glass substrate. The transparent conductive film is a counter electrode with respect to the pixel electrode of the pixel portion 401, and the liquid crystal material is driven by an electric field formed between the pixel electrode and the counter electrode. Further, an alignment film and a color filter are formed on the counter substrate 700 if necessary.
[0168]
IC chips 711 and 712 are attached to the active matrix substrate of this embodiment using the surface to which the FPC 710 is attached. These IC chips are configured by forming circuits such as a video signal processing circuit, a timing pulse generation circuit, a γ correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate. In FIG. 15A, two IC chips are attached, but one IC chip or three or more IC chips may be used.
[0169]
Or the structure of FIG. 15 (B) is also possible. In FIG. 15B, the same components as those in FIG. Here, an example is shown in which the signal processing performed by the IC chip in FIG. 15A is performed by a logic circuit 720 formed using TFTs over the same substrate. In this case, similarly to the drive circuits 402 and 403, the logic circuit 720 is also configured based on a CMOS circuit.
[0170]
In this embodiment, a configuration in which a black mask is provided on an active matrix substrate (BM on TFT) is employed. However, in addition to this, a configuration in which a black mask is provided on the opposite side may be employed.
[0171]
Further, color display may be performed using a color filter, or the liquid crystal may be driven in an ECB (electric field control birefringence) mode, a GH (guest host) mode, or the like, and the color filter may not be used. Further, as described in JP-A-8-15686, a configuration using a microlens array may be used.
[0172]
[Embodiment 6] The TFT shown in Embodiments 1, 2, and 3 can be applied to various other electro-optical devices and semiconductor circuits besides AMLCD.
[0173]
Examples of electro-optical devices other than AMLCDs include EL (electroluminescence) display devices and image sensors.
[0174]
Further, examples of the semiconductor circuit include an arithmetic processing circuit such as a microprocessor constituted by an IC chip, and a high-frequency module (such as MMIC) that handles input / output signals of portable devices.
[0175]
As described above, the present invention can be applied to all semiconductor devices that function by a circuit formed of an insulated gate TFT.
[0176]
Example 7
In addition to the nematic liquid crystal, various liquid crystals can be used for the above-described liquid crystal display device of the present invention. For example, 1998, SID, “Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability” by H. Furue et al., 1997, SID DIGEST, 841, “A Full -Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time ”by T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 671-673," Thresholdless antiferroelectricity in liquid crystals and its application to The liquid crystal disclosed in "displays" by S. Inui et al. or US Pat. No. 5,945,569 can be used.
[0177]
Using a ferroelectric liquid crystal (FLC) exhibiting an isotropic phase-cholesteric phase-chiral smectic C phase transition series, a cholesteric phase-chiral smectic C phase transition is applied while applying a DC voltage, and the cone edge is substantially in the rubbing direction. FIG. 16 shows the electro-optical characteristics of the matched monostable FLC. The display mode using the ferroelectric liquid crystal as shown in FIG. 16 is called “Half-V-shaped switching mode”. The vertical axis of the graph shown in FIG. 16 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. Regarding “Half-V-shaped switching mode”, Terada et al., “Half-V-shaped switching mode FLCD”, Proceedings of the 46th Joint Physics Related Conference, March 1999, p. 1316, and Yoshihara et al. "Time-division full-color LCD using ferroelectric liquid crystal", Liquid Crystal, Vol. 3, No. 3, page 190.
[0178]
As shown in FIG. 16, it can be seen that when such a ferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible. In the liquid crystal display device of the present invention, a ferroelectric liquid crystal exhibiting such electro-optical characteristics can also be used.
[0179]
A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optic response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) is also found. Has been.
[0180]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.
[0181]
In addition, since such a thresholdless antiferroelectric mixed liquid crystal is used for the liquid crystal display device of the present invention, low voltage driving is realized, so that low power consumption is realized.
[0182]
Example 8
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described.
[0183]
FIG. 17A is a top view of an EL display device using the present invention. In FIG. 17A, reference numeral 4010 denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, and 4013 denotes a gate side driver circuit. Each driver circuit reaches an FPC 4017 through wirings 4014 to 4016 and is connected to an external device. The
[0184]
At this time, a cover material 6000, a sealing material (also referred to as a housing material) 7000, and a sealing material (second sealing material) 7001 are provided so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion.
[0185]
FIG. 17B shows a cross-sectional structure of the EL display device of this embodiment. A driving circuit TFT (here, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined) is formed on a substrate 4010 and a base film 4021. 4022 and a pixel portion TFT 4023 (however, only the TFT for controlling the current to the EL element is shown here). These TFTs may have a known structure (top gate structure or bottom gate structure).
[0186]
The present invention can be used for the driving circuit TFT 4022 and the pixel portion TF 4023.
[0187]
When the driver circuit TFT 4022 and the pixel portion TFT 4023 are completed using the present invention, a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on the interlayer insulating film (planarization film) 4026 made of a resin material. A pixel electrode 4027 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (referred to as ITO) or a compound of indium oxide and zinc oxide can be used. Then, after the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.
[0188]
Next, an EL layer 4029 is formed. The EL layer 4029 may have a stacked structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, a vapor deposition method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.
[0189]
In this embodiment, the EL layer is formed by vapor deposition using a shadow mask. Color display is possible by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but either method may be used. Needless to say, an EL display device emitting monochromatic light can also be used.
[0190]
After the EL layer 4029 is formed, a cathode 4030 is formed thereon. It is desirable to remove moisture and oxygen present at the interface between the cathode 4030 and the EL layer 4029 as much as possible. Therefore, it is necessary to devise such that the EL layer 4029 and the cathode 4030 are continuously formed in a vacuum, or the EL layer 4029 is formed in an inert atmosphere and the cathode 4030 is formed without being released to the atmosphere. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0191]
In this embodiment, a stacked structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 4030. Specifically, a 1 nm-thick LiF (lithium fluoride) film is formed on the EL layer 4029 by evaporation, and a 300 nm-thick aluminum film is formed thereon. Of course, you may use the MgAg electrode which is a well-known cathode material. The cathode 4030 is connected to the wiring 4016 in the region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and is connected to the FPC 4017 through a conductive paste material 4032.
[0192]
In order to electrically connect the cathode 4030 and the wiring 4016 in the region indicated by 4031, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These may be formed when the interlayer insulating film 4026 is etched (when the pixel electrode contact hole is formed) or when the insulating film 4028 is etched (when the opening before the EL layer is formed). In addition, when the insulating film 4028 is etched, the interlayer insulating film 4026 may be etched all at once. In this case, if the interlayer insulating film 4026 and the insulating film 4028 are the same resin material, the shape of the contact hole can be improved.
[0193]
A passivation film 6003, a filler 6004, and a cover material 6000 are formed so as to cover the surface of the EL element thus formed.
[0194]
Further, a sealing material is provided inside the cover material 7000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.
[0195]
At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0196]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0197]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0198]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0199]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0200]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 7000 and the sealing material 7001 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are electrically connected to the FPC 4017 through the sealing material 7000 and the sealing material 7001 in the same manner.
[0201]
[Example 9]
In this embodiment, an example of manufacturing an EL display device having a different form from that of Embodiment 8 using the present invention will be described with reference to FIGS. 18A and 18B. The same numbers as those in FIGS. 17A and 17B indicate the same parts, and the description thereof is omitted.
[0202]
FIG. 18A is a top view of the EL display device of this example, and FIG. 18B shows a cross-sectional view taken along line AA ′ of FIG. 18A.
[0203]
According to Example 8, a passivation film 6003 is formed to cover the surface of the EL element.
[0204]
Further, a filler 6004 is provided so as to cover the EL element. The filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0205]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0206]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0207]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0208]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0209]
Next, after the cover material 6000 is bonded using the filler 6004, the frame material 6001 is attached so as to cover the side surface (exposed surface) of the filler 6004. The frame material 6001 is bonded by a sealing material (functioning as an adhesive) 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used if the heat resistance of the EL layer permits. Note that the sealing material 6002 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, a desiccant may be added inside the sealing material 6002.
[0210]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 6002 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.
[0211]
[Example 10]
The present invention can be used in an EL display panel configured as in Embodiments 8 and 9. Here, FIG. 19 shows a more detailed cross-sectional structure of the pixel portion, FIG. 20A shows a top structure, and FIG. 20B shows a circuit diagram. 19, 20 </ b> A, and 20 </ b> B use common reference numerals and may be referred to each other.
[0212]
In FIG. 19, a switching TFT 3502 provided on a substrate 3501 is formed using an NTFT using the present invention. In FIG. 19, the configuration is the same as that of the NTFT of the second embodiment, but the configuration of the first or third embodiment may be used. In this embodiment, a double gate structure is used. However, there is no significant difference in structure and manufacturing process, and thus description thereof is omitted. However, the double gate structure substantially has a structure in which two TFTs are connected in series, and there is an advantage that the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure may be used, and a triple gate structure or a multi-gate structure having more gates may be used. Moreover, you may form using PTFT of this invention.
[0213]
The current control TFT 3503 is formed using an NTFT using the present invention. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current control TFT by the wiring 36. A wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.
[0214]
At this time, it is very important that the current control TFT 3503 has the structure of this embodiment. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and it is also an element with a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current control TFT so as to overlap the gate electrode through the gate insulating film is extremely effective.
[0215]
In this embodiment, the current control TFT 3503 is illustrated as a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.
[0216]
Further, as shown in FIG. 20A, the wiring that becomes the gate electrode 37 of the current control TFT 3503 overlaps the drain wiring 40 of the current control TFT 3503 with an insulating film in the region indicated by 3504. At this time, a capacitor is formed in a region indicated by 3504. This capacitor 3504 functions as a capacitor for holding the voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is always applied.
[0217]
A first passivation film 41 is provided on the switching TFT 3502 and the current control TFT 3503, and a planarizing film 42 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0218]
Reference numeral 43 denotes a pixel electrode (EL element cathode) made of a highly reflective conductive film, which is electrically connected to the drain of the current control TFT 3503. As the pixel electrode 43, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used.
[0219]
A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.
[0220]
There are various types of PPV organic EL materials such as “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,“ Polymers for Light Emitting ”. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and Japanese Patent Laid-Open No. 10-92576 may be used.
[0221]
As a specific light emitting layer, cyanopolyphenylene vinylene may be used for a light emitting layer that emits red light, polyphenylene vinylene may be used for a light emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm).
[0222]
However, the above example is an example of an organic EL material that can be used as a light emitting layer, and is not necessarily limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer.
[0223]
For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0224]
In this embodiment, the EL layer has a laminated structure in which a hole injection layer 46 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light emitting layer 45. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. What can form into a film at low temperature as much as possible is preferable.
[0225]
When the anode 47 is formed, the EL element 3505 is completed. Note that the EL element 3505 here refers to a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. As shown in FIG. 20A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.
[0226]
By the way, in the present embodiment, a second passivation film 48 is further provided on the anode 47. The second passivation film 48 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to cut off the EL element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic EL material and the meaning of suppressing degassing from the organic EL material. This increases the reliability of the EL display device.
[0227]
As described above, the EL display panel of this embodiment has a pixel portion composed of pixels having a structure as shown in FIG. 19, and includes a switching TFT having a sufficiently low off-current value, a current control TFT resistant to hot carrier injection, Have Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.
[0228]
In addition, the structure of a present Example can be implemented in combination freely with Examples 1-3 structure. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 7.
[0229]
Example 11
In this embodiment, a structure in which the structure of the EL element 3505 is inverted in the pixel portion described in Embodiment 10 will be described. FIG. 21 is used for the description. Note that the only difference from the structure of FIG. 19 is the EL element portion and the current control TFT, and other descriptions are omitted.
[0230]
In FIG. 21, a current control TFT 3503 is formed using the PTFT of the present invention. In FIG. 21, the configuration is the same as that of the PTFT of the second embodiment, but the configuration of the first or third embodiment may be used.
[0231]
In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Of course, a conductive film made of a compound of indium oxide and tin oxide may be used.
[0232]
Then, after banks 51a and 51b made of insulating films are formed, a light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.
[0233]
In the case of the present embodiment, the light generated in the light emitting layer 52 is emitted toward the substrate on which the TFT is formed, as indicated by the arrows.
[0234]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-3. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 7.
[0235]
Example 12
In this embodiment, an example in the case of a pixel having a structure different from the circuit diagram shown in FIG. 20B is shown in FIGS. In this embodiment, 3801 is a source wiring of the switching TFT 3802, 3803 is a gate wiring of the switching TFT 3802, 3804 is a current control TFT, 3805 is a capacitor, 3806 and 3808 are current supply lines, and 3807 is an EL element. .
[0236]
FIG. 22A shows an example in which the current supply line 3806 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 3806. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0237]
FIG. 22B shows an example in which the current supply line 3808 is provided in parallel with the gate wiring 3803. In FIG. 22B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they are provided so as to overlap with each other through an insulating film. You can also. In this case, since the exclusive area can be shared by the power supply line 3808 and the gate wiring 3803, the pixel portion can be further refined.
[0238]
Further, FIG. 22C is characterized in that the current supply line 3808 is provided in parallel with the gate wiring 3803 as in the structure of FIG. 22B, and two pixels are formed to be symmetrical with respect to the current supply line 3808. There is. It is also effective to provide the current supply line 3808 so as to overlap with any one of the gate wirings 3803. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0239]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Example 1-3, 8 or 9. In addition, it is effective to use the EL display panel having the pixel structure of this embodiment as the display portion of the electronic device of Embodiment 7.
[0240]
[Example 13]
20A and 20B shown in Embodiment 10, the capacitor 3504 is provided to hold the voltage applied to the gate of the current control TFT 3503. However, the capacitor 3504 can be omitted. In the case of Example 10, since the NTFT having the same configuration as that of Example 2 is used as the current control TFT 3503, the LDD region provided so as to overlap the gate electrode through the gate insulating film is provided. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region, but this embodiment is characterized in that this parasitic capacitance is positively used in place of the capacitor 3504.
[0241]
Since the capacitance of the parasitic capacitance varies depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.
[0242]
Similarly, in the structure of FIGS. 22A, 22B, and 22C shown in the twelfth embodiment, the capacitor 3805 can be omitted.
[0243]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-3, 8-12. In addition, it is effective to use the EL display panel having the pixel structure of this embodiment as the display portion of the electronic device of Embodiment 7.
[0244]
Example 14
The CMOS circuit and the pixel portion formed by implementing the present invention can be used for various display devices (active matrix liquid crystal display devices, active matrix EL display devices, active matrix EC display devices). That is, the present invention can be implemented in all electronic devices in which these display devices are incorporated in the display unit.
[0245]
Such electronic devices include video cameras, digital cameras, projectors (rear or front type), head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones) Or an electronic book). Examples of these are shown in FIGS. 23, 24 and 25. FIG.
[0246]
FIG. 23A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.
[0247]
FIG. 23B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be applied to the display portion 2102 and other signal control circuits.
[0248]
FIG. 23C illustrates a mobile computer, which includes a main body 2201, a camera portion 2202, an image receiving portion 2203, operation switches 2204, a display portion 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.
[0249]
FIG. 23D illustrates a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like. The present invention can be applied to the display portion 2302 and other signal control circuits.
[0250]
FIG. 23E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.
[0251]
FIG. 23F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, an operation switch 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.
[0252]
FIG. 24A illustrates a front type projector that includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 constituting a part of the projection device 2601 and other signal control circuits.
[0253]
FIG. 24B illustrates a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like. The present invention can be applied to the liquid crystal display device 2808 constituting a part of the projection device 2702 and other signal control circuits.
[0254]
Note that FIG. 24C illustrates an example of the structure of the projection devices 2601 and 2702 in FIGS. 24A and 24B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0255]
FIG. 24D shows an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 24D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0256]
However, the projector shown in FIG. 24 shows a case where a transmissive display device is used, and an application example in a reflective display device and an EL display device is not shown.
[0257]
FIG. 25A shows a mobile phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, and the like. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal control circuits.
[0258]
FIG. 25B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003 and other signal circuits.
[0259]
FIG. 25C illustrates a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0260]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic device of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-6 and 8-13.
[0261]
【The invention's effect】
The present invention provides a gettering region in contact with a gettering region when using a technique for crystallizing a semiconductor film using a crystallization promoting element or improving the crystallinity. And the crystallization promoting element removing step can be efficiently performed. In addition, since the process temperature of the crystallization promoting element removing step can be performed at a temperature lower than 600 ° C., it is sufficiently possible to use a glass substrate.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of removing crystallization promoting elements.
FIG. 2 is a schematic diagram of conventional crystallization promoting element removal.
3 is a cross-sectional view showing a manufacturing process of Embodiment 1. FIG.
4 is a cross-sectional view showing a manufacturing process of Embodiment 2. FIG.
5 is a cross-sectional view showing a manufacturing process of Embodiment 3. FIG.
6 is a cross-sectional view showing a manufacturing process of Embodiment 4. FIG.
7 is a plan view of a CMOS circuit according to Embodiment 1. FIG.
8 is a cross-sectional view showing a manufacturing process of the TFT of Example 1. FIG.
9 is a cross-sectional view showing a manufacturing process of the TFT of Example 1. FIG.
10 is a cross-sectional view showing a manufacturing process of the TFT of Example 2. FIG.
11 is a cross-sectional view showing a manufacturing process of the TFT of Example 3. FIG.
12 is a perspective view of an active matrix substrate of Example 4. FIG.
FIG. 13 is a top view of a pixel portion and a CMOS circuit.
FIG. 14 is a cross-sectional view of an active matrix substrate
15 is an external perspective view of a liquid crystal display device of Example 5. FIG.
FIG. 16 is a diagram showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.
17 is a top view and cross-sectional view of an EL display device according to Example 8. FIG.
18 is a top view and cross-sectional view of an EL display device according to Example 9. FIG.
19 is a sectional view of an EL display device according to Example 10. FIG.
20 is a top view and a circuit diagram of an EL display device according to Example 10; FIG.
FIG. 21 is a cross-sectional view of an EL display device according to an eleventh embodiment.
22 is a circuit diagram of an EL display device according to Example 12. FIG.
FIG. 23 is a block diagram of an electronic apparatus according to a fourteenth embodiment.
FIG. 24 is a configuration diagram of an electronic device according to a fourteenth embodiment.
FIG. 25 is a block diagram of an electronic apparatus according to a fourteenth embodiment.
[Explanation of symbols]
100 substrates
102 Amorphous silicon film
104 Ni film
106 crystalline silicon film
108, 109 Semiconductor layer

Claims (5)

Form a base film on the substrate,
Forming a semiconductor film on the base film;
After introducing an element that promotes crystallization into the semiconductor film, a first heat treatment is performed to form a crystalline semiconductor film,
Patterning the crystalline semiconductor film to form an island-shaped semiconductor layer;
Forming a mask insulating film on the island-like semiconductor layer;
After the group 15 element is selectively added to the island-shaped semiconductor layer using the mask insulating film, a second heat treatment is performed on the island-shaped semiconductor layer, and the group 15 element is added to the island-shaped semiconductor layer. Moving the element that promotes crystallization from a region not added to the region to which the group 15 element is added,
Removing the mask insulating film;
Forming a gate insulating film so as to cover the island-shaped semiconductor layer;
A method for manufacturing a semiconductor device, comprising forming a gate electrode through the gate insulating film over a region where the group 15 element is not added in the island-shaped semiconductor layer. A method for manufacturing a semiconductor device having an N-channel thin film transistor and a P-channel thin film transistor,
Form a base film on the substrate,
Forming a semiconductor film on the base film;
After introducing an element that promotes crystallization into the semiconductor film, a first heat treatment is performed to form a crystalline semiconductor film,
Patterning the crystalline semiconductor film to form a first island-like semiconductor layer and a second island-like semiconductor layer;
Forming a first mask insulating film on the first island-shaped semiconductor layer and forming a second mask insulating film on the second island-shaped semiconductor layer;
A source region and a drain region of the N-channel thin film transistor are formed by selectively adding a group 15 element to the first island-like semiconductor layer using the first mask insulating film, and the second mask. The group 15 element is selectively added to the second island-shaped semiconductor layer using an insulating film,
After forming a first resist mask so as to cover the first mask insulating film and the first island-like semiconductor layer, the second resist mask and the second mask insulating film are used to form the second resist mask. A group 13 element is selectively added to the island-shaped semiconductor layer to form a source region and a drain region of the P-channel thin film transistor,
After removing the first resist mask, a second heat treatment is performed on the first island-shaped semiconductor layer and the second island-shaped semiconductor layer, and the group 15 element is formed in the first island-shaped semiconductor layer. The element that promotes crystallization is moved from the region to which the Group 15 element is added to the region to which the Group 15 element is not added, and the region from which the Group 15 element is not added to the second island-shaped semiconductor layer. Moving the element for promoting crystallization to a region to which a group 15 element is added;
Removing the first mask insulating film and the second mask insulating film;
Forming a gate insulating film so as to cover the first island-like semiconductor layer and the second island-like semiconductor layer;
A second resist mask or a third mask insulating film is formed so as to cover the second island-shaped semiconductor layer, and one of the regions where the group 15 element is not added in the first island-shaped semiconductor layer. After forming a third resist mask or a fourth mask insulating film on the portion, the group 15 element is selectively added to the first island-like semiconductor layer to reduce the low concentration impurity of the N-channel thin film transistor Forming a region,
Removing the second resist mask or the third mask insulating film and the third resist mask or the fourth mask insulating film;
After the conductive film is formed on the gate insulating film, the conductive layer is formed so that the first island-shaped semiconductor layer has a region overlapping with a region to which the group 15 element is not added and overlapping with the low-concentration impurity region. A film is patterned to form a first gate electrode on the first island-shaped semiconductor layer via the gate insulating film, and the group 15 element and the group 13 element in the second island-shaped semiconductor layer A second gate electrode is formed on the second island-shaped semiconductor layer through the gate insulating film by patterning the conductive film so as to overlap with a region to which no dopant is added. Manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of the first heat treatment is 450 to 650 ° C.   4. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of the second heat treatment is set to 500 to 850 ° C. 5.   5. The element according to claim 1, wherein the element that promotes crystallization is selected from Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, and Ge. Alternatively, a method for manufacturing a semiconductor device, wherein a plurality of elements are used.

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