JP4357672B2 - Exposure apparatus, exposure method, and manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an exposure apparatus and an exposure method. The present invention also relates to a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as TFT) using the exposure method and a manufacturing method thereof. The semiconductor device of the present invention includes not only an element such as a thin film transistor (TFT) and a MOS transistor but also an electro-optical device such as a display device and an image sensor having a semiconductor circuit composed of these insulated gate transistors. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic apparatus in which such an electro-optical device is mounted as a component.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.
[0003]
[Prior art]
An active matrix liquid crystal display in which a pixel circuit and a drive circuit are formed by thin film transistors (TFTs) formed over an insulating substrate has attracted attention. Liquid crystal displays of up to about 0.5 to 20 inches are used as display displays.
[0004]
At present, in order to realize a liquid crystal display capable of high-definition display, a TFT using a crystalline semiconductor film typified by a polysilicon film as an active layer is attracting attention.
[0005]
However, a TFT using a crystalline semiconductor film as an active layer has a problem that the operation speed and driving capability are higher than a TFT using an amorphous semiconductor film as an active layer, but a leakage current is large.
[0006]
As a technique for suppressing this leakage current, it is known to form an LDD region between a channel formation region and a drain region of a TFT. The LDD region relaxes the strength of the electric field formed between the channel formation region and the drain region, and plays a role in reducing the OFF current of the TFT and preventing deterioration.
[0007]
In order to form an LDD region between the channel formation region and the drain region of the TFT, impurity ions imparting conductivity type are added to the region that becomes the drain region at a high concentration, and the conductivity type is imparted to the region that becomes the LDD region. A mask to which impurity ions are added at a low concentration is used. As a conventional means for forming a mask for selectively forming regions having different impurity concentrations, a patterning method {circle around (1)} (non-self-alignment method) using a photomask, or wiring from a back surface as a mask is used. There is a patterning method (2) (self-alignment method) for performing exposure.
[0008]
A conventional patterning method (1) using a photomask will be briefly described below. In general, when an LDD structure is formed, a mask by a photolithography method is used. Here, as an example, a manufacturing process of a bottom gate TFT will be described.
[0009]
First, a gate wiring is formed on an insulating substrate. At this stage, the first photomask is used. Next, a semiconductor film having a gate insulating film and an amorphous region is stacked over the gate wiring, and the semiconductor film having the amorphous region is heated or crystallized by laser light or the like to be crystallized. A high-quality semiconductor film.
[0010]
Next, a mask pattern is formed using the patterning method (1). The patterning method {circle around (1)} here includes a step of forming an insulating film for a mask pattern, a step of applying a photoresist film on the insulating film for the mask pattern, and exposure using a second photomask. A step of forming a photoresist pattern by development, a step of etching a mask pattern insulating film using the photoresist pattern as a mask to form a mask pattern, and a step of removing the photoresist pattern Pointing to do. Such a method using a photomask is called a non-self-alignment method. After that, impurity ions imparting conductivity to the crystalline semiconductor film are selectively added using a mask pattern to form a source region, a drain region, an LDD region, or the like.
[0011]
The problem with this method is that the characteristics of the TFT vary because the photomask alignment varies within a certain range. In particular, since the width of the channel formation region is determined by the mask pattern, high patterning accuracy is required.
[0012]
Further, a patterning method (2) for performing exposure from the back surface using a wiring as a mask will be described with reference to FIG. Patterning by exposure from the back surface can be performed with higher accuracy than the patterning method (1). However, in the conventional patterning by exposure from the back surface, since the light wraps around, the pattern is slightly narrower than the wiring width.
[0013]
First, the gate wiring 11 is formed on the insulating substrate 10. At this stage, the first photomask is used. Next, a gate insulating film 12 and a semiconductor film having an amorphous region are stacked over the gate wiring, and the semiconductor film having the amorphous region is heated or crystallized by laser light or the like. The crystalline semiconductor film 13 is used.
[0014]
Next, a patterning method (2) for forming a mask pattern is used. The patterning method {circle around (2)} here is a step of forming an insulating thin film 14 for a mask pattern and a step of applying a photoresist film 15 on the insulating thin film for a mask pattern (FIG. 14A). And a step of forming a resist pattern 16 by performing exposure / development from the back surface using the gate wiring as a mask (FIG. 14B), and etching the insulating film for the mask pattern using the resist pattern as a mask. The step of forming the mask pattern 17 and the step of removing the resist pattern 16 (FIG. 14C) are performed. By exposure from the back surface, a mask pattern 17 having almost the same dimensions as the gate wiring is formed. In FIG. 14, the end portion of the resist pattern and the end portion of the wiring are coincident with each other. However, light actually circulates and the mask pattern 17 is smaller than the end portion by about 0.3 to 0.5 μm from the gate wiring.
[0015]
Such a method that does not use a photomask is called a self-alignment method. Thereafter, impurity ions imparting conductivity to the crystalline semiconductor film are selectively added using a mask pattern to form a source region, a drain region, or an LDD region.
[0016]
The problem with this method {circle around (2)} is that only a resist pattern having substantially the same dimensions as the gate wiring used as a mask can be produced, and it is difficult to form a desired resist pattern. It is also possible to change the exposure conditions, for example, the exposure time, and wrap around the light to form the resist pattern inside the gate wiring. However, the wraparound of the light reduces the thickness of the resist pattern. . Therefore, in particular, when a fine wiring is used as a mask, it is not suitable because all the resist on the wiring may be exposed. Further, even if light was circulated, the limit was 1 μm from the end. In addition, a sufficient exposure time and exposure light amount are required to circulate light about 1 μm from the end.
[0017]
Therefore, in the manufacturing process of the bottom gate TFT, when forming the LDD region, it is necessary to selectively add impurities using the mask by the patterning method (1) and the mask by the patterning method (2). .
[0018]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION The present invention solves the above-described problems of the prior art and aims to provide a novel exposure apparatus that forms a mask pattern by a self-alignment method.
[0019]
In addition, a configuration of a display device using a TFT in which a mask pattern is formed by a self-alignment method using an exposure method using the exposure apparatus of the present invention and an LDD region is formed on a gate wiring and a manufacturing method thereof are provided. With the goal.
[0020]
[Means for Solving the Problems]
In order to solve the above-mentioned object, a back surface exposure is performed using an exposure apparatus in which a reflector is provided at a distance X (0.1 μm to 1000 μm) from the surface of the photosensitive thin film on the surface side of the substrate, and a mask pattern is formed by a self-alignment method. It is characterized by forming.
[0021]
The configuration of the invention disclosed in this specification is as follows.
A stage on which a translucent substrate provided with a photosensitive thin film is installed;
A light source that irradiates the photosensitive thin film from the back side of the translucent substrate;
An exposure apparatus comprising: a reflecting means provided on the surface side of the translucent substrate.
[0022]
In the above structure, the reflecting means is a substrate provided with a reflective material thin film.
[0023]
In each of the above structures, the photosensitive thin film is a photoresist film.
[0024]
In each of the above structures, the photosensitive thin film is provided on a pattern made of a non-translucent thin film material.
[0025]
In the exposure method of the present invention, the light from the light source passes through the substrate from the back side and is applied to the photosensitive thin film (other than the region on the gate wiring). Further, the light that has passed through the photosensitive thin film from the light source is reflected and scattered by a reflecting plate provided on the surface side of the substrate, and irradiated to the photosensitive thin film (entire surface) from the surface side of the substrate. A mask pattern is formed using a photosensitive thin film in an area where only a small amount of the reflected / scattered light is irradiated. The region where the reflected / scattered light is irradiated only in a minute amount can be determined by appropriately changing the distance X (0.1 μm to 1000 μm) between the photosensitive thin film surface and the reflecting plate. Therefore, a mask pattern having a desired dimension can be formed on the gate wiring by a self-alignment method.
[0026]
Moreover, the structure of the exposure method of the present invention using the above exposure apparatus is as follows:
Forming a pattern made of a non-translucent thin film material on a translucent substrate;
Forming a photosensitive thin film on the pattern;
Using the pattern as a mask, light from a light source is irradiated from the back side of the substrate to expose the photosensitive thin film, and light from the light source that has passed through the photosensitive thin film is provided on the surface side of the substrate. Reflecting or scattering by the reflecting means, and irradiating from the surface side of the substrate to expose the photosensitive thin film; and
It is an exposure method characterized by having.
[0027]
Further, in the above configuration, the shape of the pattern made of the photosensitive thin film is obtained by reducing the shape of the pattern made of the non-translucent thin film material.
[0028]
By using a mask pattern formed by the exposure method of the present invention or a doping mask made of an insulating film formed using the mask pattern as a mask, impurity ions imparting conductivity are selectively added to form LDD. Form a region.
[0029]
In this specification, the surface of the substrate on which the TFT is manufactured is the front surface, and the surface facing the front surface is the back surface.
[0030]
In this specification, a substrate having a transmittance of 60% or more, preferably 80% or more, for light from a light source of an exposure apparatus is referred to as a light-transmitting substrate.
[0031]
Further, as a reflecting means, a substrate (reflecting plate) on which a reflectivity with respect to the wavelength of light from the light source of the exposure apparatus is 80% or more and a metal film such as an aluminum film or silver having high light reflectivity is formed. Can be used.
[0032]
In this specification, unless otherwise specified, “impurities” refer to elements belonging to Group 13 or Group 15. In addition, although the size (area) of each impurity region changes in the course of the manufacturing process, the same reference numerals are used in this specification as long as the concentration does not change even if the area changes. .
[0033]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
Hereinafter, an example of the embodiment of the present invention will be described in detail with reference to FIG.
[0034]
As shown in FIG. 6, the exposure apparatus of the present invention includes a stage on which a translucent substrate provided with a photosensitive thin film, a light source for exposing the photosensitive thin film, and a surface side of the translucent substrate. Reflection means. As the reflecting means 602, a substrate (reflecting plate) on which a reflective metal thin film is formed, a mirror, a light scattering plate, or the like is used and provided in parallel with the substrate surface. Note that the wraparound distance Y can be controlled by adjusting the distance X between the reflecting means and the photosensitive thin film surface within a range of 0.1 μm to 1000 μm.
[0035]
In the exposure method of the present invention, the light 601 from the light source that has passed through the photosensitive thin film is reflected and scattered by the reflecting means 602 provided on the surface side of the substrate, and selectively from the surface side of the substrate. To expose. By doing so, it is possible to form a mask with good controllability by allowing light to enter the pattern 600 made of a non-transmissive material.
[0036]
The exposure method of the present invention will be briefly described.
[0037]
Here, in the case where the photosensitive resin formed above the pattern 600 made of a non-transparent material is exposed except for the region indicated by 606 (having a pattern separated from the end of the pattern 600 by a distance Y). explain.
[0038]
First, light 601 from the light source exposes the photosensitive thin film from the back surface using the pattern 600 as a mask, and an area indicated by 605a is exposed. Next, the light transmitted through the area indicated by 605a is reflected or scattered by the reflecting means 602, and the photosensitive thin film is exposed again to expose the areas indicated by 605a and 605b. Therefore, the area indicated by 605a is exposed twice. Therefore, when it is desired to expose only the region indicated by 605a, the exposure can be performed in a short time, and the throughput can be improved.
[0039]
Thereafter, the exposed regions 605a and 605b are removed, and only the region indicated by 606 that is not exposed remains. Thus, a mask 606 (having a pattern separated from the end of the pattern 600 by a distance Y) can be formed.
[0040]
The thin film 604 can be selectively etched by using the region indicated by 606 formed through the above steps as a mask. Further, when this 606 is used as a mask, the semiconductor film 607 can be through-doped. Note that reference numeral 608 in FIG. 6 denotes an insulating film.
[0041]
The exposure method of the present invention can be applied without particular limitation when a mask is formed on the pattern 600 made of a non-transmissive material. Note that the pattern 600 may be a material film having a sufficient film thickness to have a light shielding property.
[0042]
(Embodiment 2)
Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to FIGS. Note that a manufacturing method using an N-channel TFT is described for simplicity.
[0043]
First, a substrate is prepared. As the substrate 100, a light-transmitting substrate such as a glass substrate, a quartz substrate, an insulating substrate such as crystalline glass, or a plastic substrate (polyethylene terephthalate substrate) can be used.
[0044]
Next, a base insulating film (hereinafter referred to as a base film) 101 is formed over the substrate, and heat treatment is performed. As the base film 101, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOxNy), or a laminated film thereof can be used in a thickness range of 100 to 500 nm. As a method for forming the base film, a formation method such as a thermal CVD method, a plasma CVD method, a sputtering method, a vapor deposition method, or a low pressure thermal CVD method can be used. This base film has an effect of preventing diffusion of impurities from the substrate. This base film is for improving the electrical characteristics of the TFT and need not be provided.
[0045]
Next, a conductive film (gate wiring forming material layer) made of a non-transmissive conductive material is formed over the insulating film 101, and the gate wiring 102 is formed by a known patterning method.
[0046]
As the conductive film, a conductive material or a semiconductor material such as tantalum (Ta), tantalum nitride (TaN), aluminum (Al), copper (Cu), niobium (Nb), hafnium (Hf), zirconium (Zr), A single metal layer composed of a layer mainly composed of titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), silicon (Si), or the like, or a stacked structure in which these are combined can be used. Typical examples of the laminated structure include a laminated structure of Ta / Al, Ti / Al, Cu / W, Al / W or W / Mo. Alternatively, a structure provided with a metal silicide (specifically, a structure in which conductive silicon such as Si x, Si / TiSix, Si / CoSix, or Si / MoSix is combined with metal silicide) may be used. . In addition, as a film thickness of an electrically conductive film, it can use in the range of 10-500 nm.
[0047]
Next, an insulating film 103 for protecting the surface of the gate wiring, for example, an anodic oxide film formed by anodizing the gate wiring, or a thin silicon nitride film covering the gate wiring may be formed on the entire surface. preferable.
[0048]
Next, a gate insulating film 104 ′ is formed. As the gate insulating film 104 ′, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOxNy), an organic resin film (BCB (benzocyclobutene) film or the like), or a stacked film of these can be used. As a means for forming the gate insulating film, known means such as a thermal CVD method, a plasma CVD method, a low pressure thermal CVD method, a sputtering method, a vapor deposition method, a coating method, etc. can be used, and it can be used in a film thickness range of 10 to 400 nm.
[0049]
Next, a semiconductor film is stacked over the gate insulating film 104 ′. As the semiconductor film, an amorphous silicon film, an amorphous semiconductor film having microcrystals, a microcrystalline semiconductor film, an amorphous germanium film, Si _X Ge _1-X An amorphous silicon germanium film represented by (0 <X <1) or a stacked film thereof can be used in a thickness range of 20 to 70 nm (typically 40 to 50 nm). Further, as a means for forming the semiconductor film, a thermal CVD method, a plasma CVD method, a low pressure thermal CVD method, a sputtering method, or the like can be used.
[0050]
Next, the semiconductor film having an amorphous region is subjected to crystallization treatment, so that the crystalline semiconductor film 105 is formed. (Fig. 1 (A))
[0051]
The crystallization treatment of the present invention may be any known means, for example, crystallization treatment by irradiation with infrared light or ultraviolet light (hereinafter referred to as laser crystallization), laser crystallization using a catalytic element, thermal crystallization. Further, thermal crystallization using a catalyst element can be used. These crystallization treatments may be combined.
[0052]
In particular, laser crystallization is effective because it applies less stress to the substrate and can be processed in a short time. When ultraviolet light is used for the crystallization treatment, excimer laser light or strong light generated from an ultraviolet lamp may be used. When infrared light is used, infrared light or strong light generated from an infrared lamp may be used. The laser beam is linear (several millimeters × several tens of centimeters), rectangular or square using a pulsed laser using XeCl, ArF, KrF or the like as a laser gas, or a continuous wave laser such as an Ar laser. The beam can be formed and irradiated.
[0053]
Laser crystallization conditions (laser beam shape, laser beam wavelength, overlap rate, irradiation intensity, pulse width, repetition frequency, irradiation time, etc.) take into consideration the film thickness of the semiconductor film, the substrate temperature, etc. The practitioner may determine as appropriate. Also, depending on the laser crystallization conditions, the semiconductor film may be crystallized after passing through a molten state, or the semiconductor film may be crystallized in a solid state or an intermediate state between a solid phase and a liquid phase without melting. There is. Alternatively, a semiconductor film formation, an insulating film formation, and laser crystallization of the semiconductor film may be performed in the same chamber without exposure to the air.
[0054]
Further, thermal crystallization in which a catalyst element (nickel) for promoting crystallization is added is described in detail in JP-A Nos. 7-130652 and 9-312260. As the metal element that promotes crystallization, one or more elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au are used. Further, Ge or Pb whose diffusion in the amorphous silicon film is substitutional diffusion can also be used.
[0055]
However, in laser crystallization using a catalytic element or thermal crystallization using a catalytic element, the semiconductor film is stacked after adding the catalytic element to the base film and then crystallizing the semiconductor film. Note that, when crystallization is performed using a catalyst element, the catalyst element remains at a high concentration in the semiconductor film. Therefore, a step of reducing the concentration of the catalyst element in the semiconductor film after the crystallization process, for example, a gettering process It is preferable to apply.
[0056]
Next, a mask pattern is formed using the patterning method of the present invention described below.
[0057]
First, the insulating thin film 106 is formed over the semiconductor film 105. As the insulating thin film 106, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film (SiOxNy), an organic resin film (BCB (benzocyclobutene) film or the like), or a laminated film of these can be used. As a means for forming the insulating thin film 106, a known means such as a thermal CVD method, a plasma CVD method, a low pressure thermal CVD method, a sputtering method, or a vapor deposition method can be used, and it can be used in a film thickness range of 10 to 200 nm. The insulating thin film 106 improves the adhesion with a photosensitive thin film to be laminated in a later step, and protects the semiconductor film, particularly a region to be a channel formation region from contamination.
[0058]
Next, a photosensitive thin film 107 is formed on the insulating thin film. (FIG. 1B) As the photosensitive thin film 107, a positive photoresist, a negative photoresist, a photosensitive polyimide, or the like can be used. As a means for forming the photosensitive thin film 107, a known means such as a coating method is used. Further, the film thickness is not particularly limited as long as it is an ultraviolet light transmission thickness of the photosensitive thin film, but it is used in a film thickness range of 0.25 μm to 4 μm, preferably 1 to 2 μm.
[0059]
Next, the reflector 108 (distance X with respect to the photosensitive thin film surface X) is parallel to the substrate surface. ₁ (X ₁ = 0.1 to 1000 μm)) is used to perform exposure. In the exposure method of the present invention, the light from the light source that has passed through the photosensitive thin film is reflected and scattered by the reflecting plate 108 provided on the surface side of the substrate, and is uneven from the surface side of the substrate to the entire surface of the photosensitive thin film. It is characterized by performing irradiation. Note that light from the light source passes through the substrate from the back side and is irradiated to the photosensitive thin film (other than the region on the gate wiring).
[0060]
That is, the first photosensitive thin film pattern 109 having a size smaller than the size of the gate wiring is obtained using a region where only a small amount of light reflected and scattered by the reflecting plate 108 is irradiated. (FIG. 1C) Note that the reduction ratio of the photosensitive thin film pattern 109 compared to the dimension of the gate wiring 102 is the distance X ₁ It can be appropriately adjusted by changing (the distance between the photosensitive thin film surface and the reflecting plate), the exposure amount, the exposure time, and the like. Using the first photosensitive thin film pattern 109 as an etching mask, the insulating thin film 106 is selectively etched to form an insulating thin film pattern 110 on a region to be a channel formation region. (FIG. 1D) Thereafter, the first photosensitive thin film pattern 109 is removed. (Figure 1 (E))
[0061]
Through the above steps, a pattern can be formed on the gate wiring by the self-alignment method.
[0062]
Next, a photosensitive thin film is formed using the same self-aligned method as the exposure from the back surface, and the exposure from the back surface is performed again. In the second exposure from the back surface, the distance X is smaller than the dimension of the gate wiring pattern and larger than the first photosensitive thin film pattern 109. ₂ The second photosensitive thin film pattern is formed by adjusting the exposure amount, the exposure time, and the like.
[0063]
Next, an impurity imparting P-type or N-type conductivity is added at a high concentration using the second photosensitive thin film pattern and the insulating thin film pattern as a mask. Thus, a region to which an impurity imparting conductivity is selectively added becomes a source region or a drain region.
[0064]
Next, after removing the second photosensitive thin film pattern, an impurity imparting a P-type or N-type conductivity is added at a low concentration using the insulating thin film pattern as a mask. Thus, a low concentration impurity region (LDD region) is formed between the high concentration impurity region (source region / drain region) and the channel formation region.
[0065]
Therefore, the dimension of the channel formation region is determined by the first photosensitive thin film pattern, and the dimension of the LDD region is determined by the second photosensitive thin film pattern. Since the photosensitive thin film pattern formed by the patterning method of the present invention is formed only on the gate wiring, the LDD region and the gate electrode overlap with each other (so-called GOLD structure). Therefore, the deterioration of the on-current of the TFT is suppressed and the reliability is improved.
[0066]
Further, an offset region can be formed instead of the LDD region. Further, the LDD region and the offset region can be formed by performing patterning by the patterning method of the present invention a plurality of times. In addition, by appropriately performing patterning and impurity addition by the patterning method of the present invention a plurality of times, at least three types of impurity regions containing the same impurity at different concentrations can be formed in addition to the channel formation region.
[0067]
Further, it can be used in combination with a patterning method using a known photomask or a known patterning method by exposure from the back surface.
[0068]
Although an example in which the LDD region of the bottom gate type TFT is formed is shown here, there is no particular limitation as long as the mask is patterned on a pattern made of a non-transparent material. Can also be applied to planar structures). For example, the present invention can also be applied to patterning an insulating film having a pattern made of a non-permeable material in the lower layer and patterning an active layer.
[0069]
Further, by using the apparatus of the present invention, backside exposure can be performed even with fine wiring.
[0070]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0071]
【Example】
Examples of the present invention will be described below, but it is needless to say that the present invention is not particularly limited to these examples.
[0072]
[Embodiment 1] In this embodiment, an example in which a CMOS circuit constituting a part of a peripheral driver circuit and a pixel TFT constituting a part of a pixel circuit portion are manufactured on the same substrate using the present invention will be described. To do. The semiconductor device and the manufacturing method thereof according to the present invention will be briefly described below with reference to FIGS. Note that for simplification, in this embodiment, a manufacturing method is described in detail using an N-channel TFT.
[0073]
First, a light-transmitting substrate 100 is prepared. In this example, a glass substrate (Corning 1737; strain point 667 ° C.) was used as the substrate 100. Next, a base insulating film (hereinafter referred to as a base film in this specification) is formed over the substrate 100, and then heat treatment is performed. Further, the heat treatment here is performed at a temperature equal to or lower than the strain point of the substrate, preferably 200 to 700 ° C. In this embodiment, TEOS and oxygen (O ₂ ) Was used as a source gas, and a silicon oxide film having a thickness of 200 nm was formed by a plasma CVD apparatus, followed by heat treatment at 640 ° C. for 4 hours.
[0074]
Next, a conductive film is formed over the base film 101 and patterned to form a gate wiring. In this embodiment, although not shown for simplification, after forming a laminated film of a tantalum nitride film having a thickness of 50 nm and a tantalum film having a thickness of 250 nm, normal patterning using a photomask is performed to form the gate wiring 102. . In this example, the gate wiring protective film 103 was formed by anodizing the gate wiring. By providing this protective film, the crystal grain size formed by crystallization of the semiconductor film, which is a subsequent process, can be made uniform.
[0075]
Next, a gate insulating film 104 ′ is formed so as to cover the gate wiring 102 and its protective film 103. In this embodiment, a plasma CVD method is used as a means for forming the gate insulating film 104 ′, and a silicon oxide film having a thickness of 125 nm is formed.
[0076]
Next, a semiconductor film is formed over the gate insulating film 104 ′. In this embodiment, a plasma CVD method is used as a means for forming a semiconductor film, and an amorphous silicon film having a film thickness of 55 nm is formed.
[0077]
Next, the semiconductor film made of an amorphous silicon film is crystallized. In this embodiment, the crystalline silicon film 105 is formed by irradiation with excimer laser light. (Fig. 1 (A))
[0078]
Next, an insulating thin film 106 is formed over the crystallized semiconductor film 105. In this embodiment, a plasma CVD method is used as means for forming the insulating thin film 106, and a silicon oxide film having a thickness of 200 nm is formed. Although a silicon oxide film is used in this embodiment, it is not particularly limited as long as it is an insulating film.
[0079]
Next, a first photosensitive thin film 107 is formed on the insulating thin film 106. In this example, a positive photoresist film (TSMR 8900, 45 cP, manufactured by Tokyo Ohka Kogyo Co., Ltd.) having a film thickness of 2.3 μm was formed by using a coating method as the first photosensitive thin film forming means. (Fig. 1 (B))
[0080]
Next, the reflecting plate 108 (distance X with the surface of the first photosensitive thin film is parallel to the substrate surface) ₁ ) Was used to perform a first back exposure (here, an exposure light amount of 10 mW) of the self-alignment method. (FIG. 1C) In this embodiment, the distance X between the surface of the first photosensitive thin film shown in FIG. ₁ = 1.0 μm thick Kapton tape is sandwiched between the reflector 108 and the substrate, and ultraviolet light from the light source passes through the substrate from the back side and passes through the first photosensitive thin film (gate The entire surface of the first photosensitive thin film was exposed from the surface side of the substrate by the light that was exposed to a region other than the area on the wiring and reflected / scattered by the reflector provided on the surface side of the substrate. Thereafter, when developed, the first photosensitive thin film exposed to ultraviolet light was selectively removed, and the first photoresist pattern 109 smaller than the dimension of the gate wiring pattern remained.
[0081]
Next, using the first photoresist pattern 109 as an etching mask, the insulating thin film 106 was selectively removed to form an insulating thin film pattern 110. (Figure 1 (D))
[0082]
Next, the first photoresist pattern 109 was removed. (Figure 1 (E))
[0083]
Next, a second photosensitive thin film 111 is formed, and a second backside exposure is performed using a self-aligned method similar to the first backside exposure. In the present embodiment, the same material as the first photosensitive thin film is used as the second second photosensitive thin film 111, and the distance X between the surface of the second photosensitive thin film and the reflecting plate 108 is used. ₂ Was adjusted to 0.5 μm, and a second back exposure (here, an exposure light amount of 10 mW) was performed. (FIG. 2B) In this second backside exposure, the second photoresist pattern 112 smaller than the size of the gate wiring pattern and larger in size than the first photoresist pattern 109 was left.
[0084]
Next, an impurity imparting N-type conductivity is added at a high concentration using the second photoresist pattern 112 and the insulating thin film pattern 110 as a mask. Thus, the region 113 to which an impurity imparting conductivity type is selectively added at a high concentration becomes a source region or a drain region. (Fig. 2 (C))
[0085]
Thereafter, the second photoresist pattern 112 was removed (FIG. 2D) to form a thin silicon oxide film 114 ′ (50 nm). (FIG. 3A) The silicon oxide film 114 ′ is a film for adding impurities at a low concentration with good controllability and does not need to be formed. Note that although a silicon oxide film is used in this embodiment, other insulating material films such as a silicon nitride film and a silicon oxynitride film can also be used.
[0086]
Next, an impurity imparting an N-type conductivity is added through the thin silicon oxide film 114 ′, so that regions 116 and 117 in which impurities are selectively added at a low concentration are formed. The insulating thin film pattern 110 serves as a mask for protecting the channel formation region. Thus, low concentration impurity regions (LDD regions) 116 and 117 were formed between the high concentration impurity regions (source / drain regions) 118 ′ and 119 ′ and the channel formation region 115. In this embodiment, the dimension of the channel formation region is determined by the first resist pattern 109, and the dimension of the LDD region is determined by the second resist pattern 112.
[0087]
In this embodiment, phosphorus element is used as an impurity imparting N-type conductivity, and the phosphorus concentration in the low concentration impurity regions 116 and 117 is 1 × 10 in SIMS analysis. ¹⁵ ~ 1x10 ¹⁷ atoms / cm ^Three , 118 ′, 119 ′, the phosphorus concentration of the high concentration impurity region is 1 × 10 in SIMS analysis. ²⁰ ~ 8x10 ^{twenty one} atoms / cm ^Three The doping conditions, the dose, and the acceleration voltage were adjusted so that (Fig. 3 (B))
[0088]
Thereafter, thermal annealing or laser annealing is performed to activate the impurity imparting N-type conductivity. In this example, activation by laser light was performed. Thereafter, the silicon oxide film 114, the semiconductor films 115 to 119, and the gate insulating film 104 were formed into a desired shape by normal patterning using a photomask. Next, after depositing an interlayer insulating film 120 and forming contact holes exposing the source region and the drain region, a metal film is formed and patterned to form a metal wiring 121 in contact with the source region 118 and the drain region 119. , 122 were formed. In this way, the manufacturing process of the N-channel TFT was completed. (Figure 3 (C))
[0089]
In this embodiment, a method for manufacturing an N-channel TFT is illustrated. However, when a P-channel TFT is manufactured, boron that imparts P-type instead of impurity ions that impart N-type in the impurity addition step is used. Ions may be added. The present invention can also be applied to a CMOS circuit formed by complementary combination of an N-channel TFT and a P-channel TFT or a pixel TFT formed by an N-channel TFT.
[0090]
An example of a structure of a semiconductor device provided with a semiconductor circuit including a semiconductor element (TFT) by using the manufacturing method of this embodiment will be described with reference to FIGS. Note that a semiconductor device according to the present invention includes a peripheral drive circuit section and a pixel circuit section on the same substrate. In the present embodiment, for ease of illustration, a CMOS circuit that forms part of the peripheral drive circuit unit and a pixel TFT (N-channel TFT) that forms part of the pixel circuit unit are shown on the same substrate. ing.
[0091]
5 (A) and 5 (B) are views corresponding to the top view of FIG. 4, and in FIGS. 5 (A) and 5 (B), the portion cut along the dotted line AA ′ is 4 corresponds to the cross-sectional structure of the pixel circuit, and a portion cut along a dotted line BB ′ corresponds to the cross-sectional structure of the CMOS circuit of FIG. Also, the reference numerals used in FIGS. 4 and 5 are the same as those in FIGS.
[0092]
In FIG. 4, any TFT (thin film transistor) is formed on the base film 101 provided on the substrate 100. In the case of a P-channel TFT of a CMOS circuit, a gate wiring 102 is formed on a base film, and a gate insulating film 104 is provided thereon. On the gate insulating film, a high concentration impurity region (p ⁺ Type regions) 418, 419 (source region or drain region), channel formation region 415, and low concentration impurity regions (p− type regions) 416, 417 are formed between the high concentration impurity region and the channel formation region. . The active layer is protected by a protective film 114 made of a silicon oxide film. A contact hole is formed in the first interlayer insulating film 120 covering the protective film 114, wirings 121 and 123 are connected to the high-concentration impurity regions 418 and 419, and a second interlayer insulating film 126 is formed thereon. Then, the lead-out wiring 127 is connected to the wiring 123, and the third interlayer insulating film 130 is formed so as to cover it.
[0093]
On the other hand, an N-channel TFT has a high concentration impurity region (n ⁺ Type regions) 118 and 119 (source region or drain region), a channel formation region 115, and low concentration impurity regions (n− type regions) 116 and 117 are formed between the high concentration impurity region and the channel formation region. . Wirings 121 and 122 are formed in the high concentration impurity regions 118 and 119, and a lead-out wiring 128 is connected to the wiring 122. Portions other than the active layer have substantially the same structure as the P-channel TFT.
[0094]
The N-channel TFT formed in the pixel circuit has the same structure as the N-channel TFT of the CMOS circuit up to the portion where the first interlayer insulating film 120 is formed. Then, wirings 124 and 125 are connected to the high-concentration impurity regions 118 and 119, and a second interlayer insulating film 126 and a black mask 129 are formed thereon. Further, a third interlayer insulating film 130 is formed thereon, and ITO, SnO ₂ A pixel electrode 131 made of a transparent conductive film is connected. The pixel electrode 131 forms a black mask and an auxiliary capacitor.
[0095]
In this embodiment, a transmissive LCD is manufactured as an example, but is not particularly limited. For example, a reflective LCD can be manufactured by using a reflective metal material as a material for the pixel electrode and appropriately changing the patterning of the pixel electrode or adding / deleting some processes as appropriate.
[0096]
In this embodiment, the gate wiring of the pixel TFT of the pixel circuit has a double gate structure, but a multi-gate structure such as a triple gate structure may be used in order to reduce variation in off current. Further, a single gate structure may be used in order to improve the aperture ratio.
[0097]
[Example 2] In Example 1, the back exposure method using a reflector is performed twice, the dimension of the channel formation region is determined by the first resist pattern 109, and the dimension of the LDD region by the second resist pattern 112. An example of determining was shown. In this embodiment, an example is shown in which the dimension of the channel formation region is determined by the first resist pattern 109 by the backside exposure method using a reflector, and the dimension of the LDD region is determined by the pattern by a known exposure method. Since this embodiment is the same as Embodiment 1 up to the step of FIG. 2A, the description up to that step is omitted.
[0098]
In this example, after obtaining the state shown in FIG. 2A in accordance with Example 1, exposure from the known back surface is performed, and a pattern made of a second photosensitive thin film having the same shape as the gate wiring is formed. Formed. The dimension of the LDD region was determined by the pattern made of the second photosensitive thin film. The subsequent steps were in accordance with Example 1 to complete the semiconductor device. Since the known exposure method from the back surface is also a self-alignment method, the number of photomasks used can be reduced as in the first embodiment.
[0099]
In the present embodiment, the first resist pattern 109 is formed by the backside exposure method using the reflector according to the present invention. However, the pattern made of the first photosensitive thin film is formed by using a well-known exposure method. It is good also as a structure which forms the pattern which consists of this photosensitive thin film with the back surface exposure method of this invention. This embodiment can be easily combined with a known exposure method, and the combination is free.
[0100]
Example 3 In this example, an example in which a photosensitive thin film material different from that in Example 1 is used in FIG. 1B will be described. Since this embodiment is the same as Embodiment 1 up to the step of FIG. 1A, description of the step is omitted.
[0101]
In this example, a positive resist material (manufactured by Tokyo Ohka Kogyo Co., Ltd., THMR3300LD) having a higher resolution than that of the photoresist material of Example 1 (manufactured by Tokyo Ohka Kogyo Co., Ltd., TSMR 8900) was used. By carrying out like this, it was able to expose very accurately and a pattern made of a photosensitive thin film could be formed. By increasing the accuracy of the pattern made of the photosensitive thin film, the shape of the channel formation region can be formed accurately, so that variation in electrical characteristics between TFTs can be reduced.
[0102]
The subsequent steps were in accordance with Example 1 to complete the semiconductor device shown in FIG.
[0103]
In addition, the present Example can be easily combined with Example 1 and Example 2, and the combination is free.
[0104]
[Embodiment 4] In Embodiment 1, two types of impurity regions containing the same impurity at different concentrations other than the channel formation region are formed. However, in this embodiment, the same impurity at different concentrations other than the channel formation region is formed. An example of forming at least three or more types of impurity regions will be described. Since this embodiment is the same as Embodiment 1 up to the step of FIG. 3B, the description up to that step is omitted.
[0105]
In this example, after obtaining the state shown in FIG. 3 (B) according to Example 1, a pattern made of a third photosensitive thin film was further formed by the backside exposure method of the present invention or a known method, Impurity doping was performed to form at least three types of impurity regions containing the same impurity at different concentrations in addition to the channel formation region. However, the pattern made of the third photosensitive thin film has a shape larger than the first resist pattern and smaller than the second resist pattern. The subsequent steps were in accordance with Example 1 to complete the semiconductor device.
[0106]
Note that it is preferable to form in multiple stages so that the impurity concentration increases from the channel formation region to the source region (or drain region). By doing so, the electric field relaxation effect is increased and hot carrier resistance is increased. In the semiconductor device formed using this embodiment, since the TFT has excellent reliability, the reliability of the entire semiconductor device is greatly improved.
[0107]
In addition, the present Example can be easily combined with Examples 1 to 3, and the combination is free.
[0108]
[Embodiment 5] In this embodiment, a first mask for forming a channel protective film is patterned using the backside exposure method of the present invention, and a second mask used for forming a source region and a drain region. An example using a normal exposure method (using a photomask) is shown below.
[0109]
In particular, in the bottom gate TFT, the boundary between the LDD region and the channel formation region is located above the gate wiring and at some distance from the end of the gate wiring (for example, the size of the TFT is L / W = 8/8). In some cases, if formed at a position approximately 1 μm away), deterioration of the on-current value (drain current that flows when the TFT is turned on) due to hot carriers can be prevented, so the first exposure using the backside exposure apparatus of the present invention. It is suitable to form a mask.
[0110]
Further, the boundary between the LDD region and the source region (or drain region) is a region other than the region above the gate wiring and a position away from the end of the gate wiring to some extent (for example, the size of the TFT is L / W = 8/8). In this case, since the leakage current of the TFT can be reduced by forming it at a position about 1 μm apart, it is suitable to form the second mask using a known backside exposure method using a photomask.
[0111]
The present embodiment will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel TFT in the display region and a TFT in a driver circuit provided in the periphery of the display region will be described in detail according to the process.
[0112]
(Formation of gate electrode, gate insulating film, crystalline semiconductor film: FIG. 7A)
In FIG. 7A, a low alkali glass substrate or a quartz substrate can be used as the substrate 701. An insulating film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film may be formed on the surface of the substrate 701 on which the TFT is formed (not shown). The gate electrodes 702 to 704 and the capacitor wiring 705 are formed using an element selected from tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), chromium (Cr), and aluminum (Al) or any one of them. A film was formed by using a material as a main component and a known film forming method such as a sputtering method or a vacuum evaporation method, and then an etching process was performed so that the end surface was tapered to form a pattern. In this embodiment, a tantalum nitride (TaN) film with a thickness of 50 nm and a Ta film with a thickness of 250 nm are stacked by sputtering, a resist mask is formed in a predetermined shape, and then CF _Four And O ₂ If the plasma etching process is performed with this mixed gas, it can be processed into a desired shape. Here, for simplification, two layers are not shown. The gate electrode may have a two-layer structure of tungsten nitride (WN) and W. Although not shown here, a gate wiring connected to the gate electrode is also formed at the same time.
[0113]
The gate insulating film 706 is a material containing silicon oxide or silicon nitride as a component, and is formed with a thickness of 10 to 200 nm, preferably 50 to 150 nm. For example, plasma CVD method, SiH _Four , NH _Three , N ₂ A silicon nitride film 706a made from a raw material of 50 nm, SiH _Four And N ₂ A silicon nitride oxide film 706b using O as a raw material may be stacked to a thickness of 75 nm to form a gate insulating film. Of course, a single layer made of a silicon nitride film or a silicon oxide film can be used. In order to obtain a clean surface, performing plasma hydrogen treatment before forming the gate insulating film can be used as an appropriate treatment.
[0114]
Next, a crystalline semiconductor film serving as an active layer of the TFT was formed. Silicon was used as the material of the crystalline semiconductor film. First, an amorphous silicon film having a thickness of 20 to 150 nm was formed in close contact with the gate insulating film 706 by a known film formation method such as a plasma CVD method or a sputtering method. There is no limitation on the conditions for forming the amorphous silicon film, but oxygen and nitrogen impurity elements contained in the film are 5 × 10 5. ¹⁸ cm ^-3 It is desirable to reduce it to the following. Further, since the gate insulating film and the amorphous silicon film can be formed by the same film formation method, they may be formed continuously. After the gate insulating film is formed, it is possible to prevent the surface from being contaminated by not exposing it to the air atmosphere, and it is possible to reduce variations in characteristics and threshold voltage of a TFT to be manufactured. Then, a crystalline silicon film 707 is formed using a known crystallization technique. For example, even if the crystalline silicon film 707 is formed by a laser annealing method, a thermal annealing method (solid phase growth method), or a crystallization method using a catalytic element in accordance with the technique disclosed in Japanese Patent Laid-Open No. 7-130652. good.
[0115]
In the region of the crystalline silicon film 707 where the n-channel TFT is formed, 1 × 10 6 is used for the purpose of controlling the threshold voltage. ¹⁶ ~ 5x10 ¹⁷ cm ^-3 About boron (B) may be added. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film.
[0116]
(Mask formation (backside exposure): FIG. 7B)
Next, in order to form a low-concentration impurity region which becomes an LDD region of the n-channel TFT, a mask for adding an impurity element imparting n-type was formed. First, a mask insulating film 708 made of a silicon oxide film or a silicon nitride film was formed on the surface of the crystalline silicon film 707 to a thickness of 100 to 200 nm, typically 120 nm. After forming a photoresist film on the entire surface, the photoresist film was exposed by the backside exposure method of the present invention using the gate electrodes 702 to 704 as a mask. In this example, the exposure light quantity was 10 mW, and the distance X between the reflector 700 and the photoresist film surface was 500 μm. The reason why the distance X is set to 500 μm is that it is the optimum value when the exposure light quantity is 10 mW. Note that the exposure apparatus of the present invention (shown in FIG. 6) that can be freely adjusted if the distance X is in the range of 0.1 μm to 1000 μm was used. After the back exposure process, if the developed and exposed photoresist is removed, resist masks 709 to 712 can be formed on the gate electrode and inside the gate electrode.
[0117]
(N ^- Region formation: FIG. 7C)
Using the resist masks 709 to 712 obtained by the backside exposure apparatus of the present invention as a mask, an impurity element that imparts n-type to the crystalline silicon film under the mask insulating film 708 is ion-doped (ion implantation method) But it was good). In the semiconductor technical field, phosphorus (P), arsenic (As), antimony (Sb), etc. are applied from the group 15 element of the periodic table as impurity elements imparting n-type. Here, phosphorus (P) is used. Using. The formed low-concentration impurity regions 713 to 718 have a phosphorus (P) concentration of 1 × 10 ¹⁷ ~ 5x10 ¹⁸ cm ^-3 In this case, 5 × 10 ¹⁷ cm ^-3 It was. In this specification, the concentration of an impurity element imparting n-type contained in the impurity regions 713 to 718 is defined as (n ^- ).
[0118]
(Channel protection film formation: FIG. 8A)
Next, the mask insulating film 708 was removed by etching using this resist mask to form channel protective films 719 to 722. In order to etch the mask insulating film 708 with high selectivity with respect to the crystalline silicon film 707 serving as a base, a wet etching method using a hydrofluoric acid-based solution is employed here. Of course, it may be performed by a dry etching method, for example, CHF. _Three The insulating film 708 can be etched with a gas. In this step, channel protection films 719 to 722 may be formed inside the end faces of the resist masks 709 to 712 by over-etching.
[0119]
(N ⁺ Region formation: FIG. 8B)
Next, in the n-channel TFT, a step of forming a high concentration impurity region functioning as a source region or a drain region was performed. Here, resist masks 723 to 725 were formed by a normal exposure method. Then, the channel protective film 722 over the capacitor wiring 705 was removed by etching using this resist mask. Next, high-concentration impurity regions 726 to 730 in which an impurity element imparting n-type conductivity is added to the crystalline silicon film 707 are formed by an ion doping method (or an ion implantation method may be used). The high concentration impurity regions 726 to 730 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} cm ^-3 In this case, 5 × 10 ²⁰ cm ^-3 Impurity elements were included at a concentration of. This concentration is referred to herein as (n ⁺ ).
[0120]
(P ⁺ Region formation: FIG. 8C)
Next, a step of adding an impurity element imparting p-type conductivity was performed in order to form high-concentration impurity regions serving as a source region and a drain region of the p-channel TFT of the driver circuit. In the semiconductor technical field, boron (B), aluminum (Al), gallium (Ga), etc. are applied from the group 13 element of the periodic table to the impurity element imparting p-type, and boron (B) is used here. Using. A mask 731 was formed so as to be positioned on the inner side of the channel protective film 719, and all regions where n-channel TFTs were formed were covered with a resist mask 733. Further, a channel protection insulating film 719b having a new shape is formed by wet etching using a hydrofluoric acid-based solution so that the end portion of the channel protection film 719 substantially matches the end portion of the mask 731. . And diborane (B ₂ H ₆ High-concentration impurity regions 734 to 736 were formed by an ion doping method using () (an ion implantation method may be used). Impurity regions 734 to 736 are doped with an impurity element from the surface of the crystalline silicon film, and the boron (B) concentration in this region is 1.5 × 10 5. ²⁰ ~ 3x10 ^{twenty one} cm ^-3 Where 2 × 10 ^{twenty one} cm ^-3 It was. In this specification, the concentration of the impurity element imparting p-type contained in the impurity regions 734 to 736 formed here is defined as (p ⁺ ). In this way, by providing the end portion in contact with the channel formation region of the high-concentration impurity region of the p-channel TFT on the channel formation region side from the end portions of the low-concentration impurity regions 713 and 714 formed in the previous step, The joining state in this part can be made favorable.
[0121]
As shown in FIGS. 7B to 8A, since phosphorus (P) is added to the impurity regions 735 and 736 in the previous step, boron (B) and phosphorus (P) are mixed. However, by increasing the boron (B) concentration added in this step to 1.5 to 3 times that of the region, p-type conductivity is ensured and the TFT characteristics are not affected at all. It was. In this specification, this region is referred to as a region (A). The impurity region 734 on the channel formation region side of the region (A) is a region containing only boron (B), and this region is referred to as a region (B) in this specification.
[0122]
(Formation of protective insulating film, activation process, hydrogenation process: FIG. 9A)
After each impurity element is selectively added to the crystalline silicon film, the crystalline silicon film is etched to be divided into islands, and a protective insulating film 737 that later becomes a part of the first interlayer insulating film is formed. . The protective insulating film 737 may be formed using a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The film thickness may be 100 to 400 nm.
[0123]
Thereafter, a heat treatment process was performed to activate the impurity element imparting n-type or p-type added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, a rapid thermal annealing method (RTA method), or the like. Further, a process of hydrogenating the active layer was performed by performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step of terminating dangling bonds in the active layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0124]
When the crystalline silicon film 707 to be an active layer is produced from an amorphous silicon film by a crystallization method using a catalytic element, the crystalline silicon film 707 has about 1 × 10 × 10. ¹⁷ ~ 5x10 ¹⁹ cm ^-3 Of catalytic element remained. Of course, there is no problem in completing and operating the TFT even in such a state, but it is more preferable to remove the remaining catalyst element from at least the channel formation region. As one of means for removing the catalyst element, there is a means for utilizing the gettering action by phosphorus (P). The concentration of phosphorus (P) necessary for gettering is the impurity region (n) formed in FIG. ⁺ ) And the catalytic element from the channel formation region of the n-channel TFT and the p-channel TFT to the high-concentration impurity region to which phosphorus (P) is added by the heat treatment in the activation process performed here. Was able to gettering. As a result, the catalyst element concentration in the channel formation region is 5 × 10 5. ¹⁷ cm ^-3 And the impurity region has 1 × 10 10 ¹⁸ ~ 5x10 ²⁰ cm ^-3 The catalyst element segregated.
[0125]
(Formation of interlayer insulating film, formation of source / drain wiring, formation of passivation film, formation of pixel electrode: FIG. 9B)
After the activation step, an interlayer insulating film 738 having a thickness of 500 to 1500 nm was formed on the protective insulating film 737. A laminated film composed of the protective insulating film 737 and the interlayer insulating film 738 was used as a first interlayer insulating film. Thereafter, contact holes reaching the source region or the drain region of each TFT were formed, and source wirings 739 to 741 and drain wirings 742 and 743 were formed. Although not shown, in this embodiment, this electrode is a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film is 150 nm continuously formed by sputtering.
[0126]
The protective insulating film 737 and the interlayer insulating film 738 may be formed of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like, but in any case, it is preferable to set the internal stress of the film as a compressive stress.
[0127]
Next, a passivation film 744 was formed to a thickness of 50 to 500 nm (typically 100 to 300 nm) using a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. Thereafter, when the hydrogenation treatment was performed in this state, a favorable result was obtained for improving the characteristics of the TFT. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 744 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later.
[0128]
Thereafter, a second interlayer insulating film 745 made of an organic resin film was formed to a thickness of about 1 μm. As an applicable organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate. A contact hole reaching the drain wiring 743 was formed in the second interlayer insulating film 745 and the passivation film 744, and a pixel electrode 746 was provided. The pixel electrode 746 may be a transparent conductive film in the case of a transmissive liquid crystal display device, and may be a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by sputtering.
[0129]
Through the above steps, the pixel TFT in the display area and the TFT of the drive circuit provided around the display area can be formed on the same substrate. In the driver circuit, an n-channel TFT 768 and a p-channel TFT 767 are formed, and a logic circuit based on a CMOS circuit can be formed. The pixel TFT 769 is an n-channel TFT, and a storage capacitor 770 is connected to the pixel TFT 769 from a capacitor wiring 705, a semiconductor layer 766, and an insulating film formed therebetween.
[0130]
In addition, a combination with Examples 1-4 is easy for a present Example, The combination method is free.
[0131]
[Embodiment 6] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from a substrate on which a pixel TFT and a drive circuit are formed will be described. As shown in FIG. 10, an alignment film 901 is formed on the substrate in the state of FIG. 9B shown in the fifth embodiment. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A light shielding film 903, a transparent conductive film 904, and an alignment film 905 are formed on the opposite substrate 902. After the alignment film was formed, rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the one substrate on which the pixel TFT and the driving circuit are formed and the counter substrate are bonded to each other through a sealing material (not shown), a columnar spacer 907, and the like by a known cell assembling process. Thereafter, a liquid crystal material 906 was injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. In this way, the active matrix liquid crystal display device shown in FIG. 10 is completed.
[0132]
In addition, a combination with Example 1-5 is easy for a present Example, The combination method is free.
[0133]
Embodiment 7 In this embodiment, an example of a liquid crystal display device manufactured according to the present invention is shown in FIG.
[0134]
11, 800 is a substrate having an insulating surface (plastic substrate provided with a silicon oxide film), 801 is a pixel circuit, 802 is a scanning line driver circuit, 803 is a signal line driver circuit, 830 is a counter substrate, 810 is FPC (flexible) 820 is a logic circuit. As the logic circuit 820, a circuit that performs processing such as a D / A converter, a γ correction circuit, a signal division circuit, or the like that has been substituted for a conventional IC can be formed. Of course, it is also possible to provide an IC chip on the substrate and perform signal processing on the IC chip.
[0135]
Further, in this embodiment, the liquid crystal display device is described as an example, but the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromic) display device as long as it is an active matrix display device. It goes without saying that it is also possible to do.
[0136]
Further, the liquid crystal display device that can be manufactured using the present invention does not matter whether it is a transmissive type or a reflective type. It is up to the practitioner to choose either. Thus, the present invention can be applied to any active matrix type electro-optical device (semiconductor device).
[0137]
Note that when manufacturing the semiconductor device shown in this embodiment, any of the configurations of Embodiments 1 to 6 may be employed, and the embodiments can be used in any combination.
[0138]
[Embodiment 8] The present invention can be applied to all conventional IC technologies. That is, it can be applied to all semiconductor circuits currently on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor integrated on one chip, and is represented by a liquid crystal driver circuit (D / A converter, γ correction circuit, signal dividing circuit, etc.). The present invention may be applied to a signal processing circuit and a high-frequency circuit for a portable device (mobile phone, PHS, mobile computer).
[0139]
A semiconductor circuit such as a microprocessor is mounted on various electronic devices and functions as a central circuit. Typical electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (such as an automobile or a train) may be used. The present invention is applicable to such a semiconductor device.
[0140]
Note that when manufacturing the semiconductor device shown in this embodiment, any of the configurations of Embodiments 1 to 7 may be employed, and the embodiments can be used in any combination.
[0141]
Example 9
A TFT formed by implementing the present invention can be used in various electro-optical devices. That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display units.
[0142]
Examples of such an electronic device include a video camera, a digital camera, a head mounted display (goggles type display), a wearable display, a car navigation system, a personal computer, a personal digital assistant (mobile computer, mobile phone, electronic book, etc.), and the like. . An example of them is shown in FIG.
[0143]
FIG. 12A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.
[0144]
FIG. 12B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display portion 2102, the voice input portion 2103, and other signal control circuits.
[0145]
FIG. 12C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display unit 2205. The present invention can be applied to the display device 2205 and other signal control circuits.
[0146]
FIG. 12D illustrates a goggle type display which includes a main body 2301, a display portion 2302, and an arm portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.
[0147]
FIG. 12E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.
[0148]
FIG. 12F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, an operation switch 2504, and an image receiving portion (not shown). The present invention can be applied to the display portion 2502 and other signal control circuits.
[0149]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-8.
[0150]
[Example 10]
A TFT formed by implementing the present invention can be used in various electro-optical devices. That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display units.
[0151]
Examples of such an electronic device include a projector (rear type or front type). An example of them is shown in FIG.
[0152]
FIG. 13A illustrates a front type projector, which includes a projection device 2601 and a screen 2602. The present invention can be applied to a liquid crystal display device of a projection device and other signal control circuits.
[0153]
FIG. 13B illustrates a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to a projection apparatus and other signal control circuits.
[0154]
FIG. 13C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 13A and 13B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0155]
FIG. 13D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 13D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0156]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-8.
[0157]
[Example 11]
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described.
[0158]
FIG. 15A is a top view of an EL display device manufactured using the present invention. In FIG. 15A, reference numeral 4010 denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, 4013 denotes a gate side driver circuit, and each driver circuit reaches an FPC 4017 through wirings 4014 to 4016 to an external device. Connected.
[0159]
At this time, a cover material 6000, a sealing material (also referred to as a housing material) 7000, and a sealing material (second sealing material) 7001 are provided so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion.
[0160]
FIG. 15B shows a cross-sectional structure of the EL display device of this embodiment. A driver circuit TFT (here, an n-channel TFT and a p-channel TFT are combined on a substrate 4010 and a base film 4021). And the pixel portion TFT 4023 (however, only the TFT for controlling the current to the EL element is shown here).
[0161]
The present invention can be used for manufacturing the driver circuit TFT 4022 and the pixel portion TFT 4023.
[0162]
When the driver circuit TFT 4022 and the pixel portion TFT 4023 are completed using the present invention, a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on the interlayer insulating film (planarization film) 4026 made of a resin material. A pixel electrode 4027 is formed. In the case where the pixel electrode 4027 is a transparent conductive film, it is preferable to use a P-channel TFT as the pixel portion TFT. As the transparent conductive film, a compound of indium oxide and tin oxide (referred to as ITO) or a compound of indium oxide and zinc oxide can be used. Then, after the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.
[0163]
Next, an EL layer 4029 is formed. The EL layer 4029 may have a stacked structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, a vapor deposition method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.
[0164]
In this embodiment, the EL layer is formed by vapor deposition using a shadow mask. Color display is possible by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but either method may be used. Needless to say, an EL display device emitting monochromatic light can also be used.
[0165]
After the EL layer 4029 is formed, a cathode 4030 is formed thereon. It is desirable to remove moisture and oxygen present at the interface between the cathode 4030 and the EL layer 4029 as much as possible. Therefore, it is necessary to devise such that the EL layer 4029 and the cathode 4030 are continuously formed in a vacuum, or the EL layer 4029 is formed in an inert atmosphere and the cathode 4030 is formed without being exposed to the atmosphere. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0166]
In this embodiment, a stacked structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 4030. Specifically, a 1 nm-thick LiF (lithium fluoride) film is formed on the EL layer 4029 by evaporation, and a 300 nm-thick aluminum film is formed thereon. Of course, you may use the MgAg electrode which is a well-known cathode material. The cathode 4030 is connected to the wiring 4016 in the region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and is connected to the FPC 4017 through a conductive paste material 4032.
[0167]
In order to electrically connect the cathode 4030 and the wiring 4016 in the region indicated by 4031, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These may be formed when the interlayer insulating film 4026 is etched (when the pixel electrode contact hole is formed) or when the insulating film 4028 is etched (when the opening before the EL layer is formed). In addition, when the insulating film 4028 is etched, the interlayer insulating film 4026 may be etched all at once. In this case, if the interlayer insulating film 4026 and the insulating film 4028 are the same resin material, the shape of the contact hole can be improved.
[0168]
A passivation film 6003, a filler 6004, and a cover material 6000 are formed so as to cover the surface of the EL element thus formed.
[0169]
Further, a sealing material is provided inside the cover material 6000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.
[0170]
At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0171]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0172]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0173]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0174]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0175]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 7000 and the sealing material 7001 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are electrically connected to the FPC 4017 through the sealing material 7000 and the sealing material 7001 in the same manner.
[0176]
[Example 12]
In this embodiment, an example of manufacturing an EL display device having a different form from that of Embodiment 11 using the present invention will be described with reference to FIGS. Components having the same reference numerals as those in FIGS. 15A and 15B indicate the same parts, and thus description thereof is omitted.
[0177]
FIG. 16A is a top view of the EL display device of this embodiment, and FIG. 16B shows a cross-sectional view taken along line AA ′ of FIG.
[0178]
In accordance with Example 11, a passivation film 6003 is formed to cover the surface of the EL element.
[0179]
Further, a filler 6004 is provided so as to cover the EL element. The filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0180]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0181]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0182]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0183]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0184]
Next, after the cover material 6000 is bonded using the filler 6004, the frame material 6001 is attached so as to cover the side surface (exposed surface) of the filler 6004. The frame material 6001 is bonded by a sealing material (functioning as an adhesive) 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used if the heat resistance of the EL layer permits. Note that the sealing material 6002 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, a desiccant may be added inside the sealing material 6002.
[0185]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 6002 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.
[0186]
[Example 13]
In this embodiment, a more detailed cross-sectional structure of a pixel portion of an EL display panel is shown in FIG. 17, a top structure is shown in FIG. 18A, and a circuit diagram is shown in FIG. In FIG. 17, FIG. 18 (A) and FIG. 18 (B), common reference numerals are used so that they may be referred to each other.
[0187]
In FIG. 17, a switching TFT 3502 provided on a substrate 3501 is formed using the NTFT of the present invention (see Examples 1 to 5). In this embodiment, a double gate structure is used. However, there is no significant difference in structure and manufacturing process, and thus description thereof is omitted. However, the double gate structure substantially has a structure in which two TFTs are connected in series, and there is an advantage that the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure may be used, and a triple gate structure or a multi-gate structure having more gates may be used. Moreover, you may form using PTFT of this invention.
[0188]
The current control TFT 3503 is formed using the NTFT of the present invention. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current control TFT by the wiring 36. A wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.
[0189]
At this time, it is very important that the current control TFT 3503 is manufactured by using the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and it is also an element with a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided so as to overlap the current control TFT is extremely effective.
[0190]
In this embodiment, the current control TFT 3503 is illustrated as a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.
[0191]
As shown in FIG. 18A, the wiring that becomes the gate electrode 37 of the current control TFT 3503 overlaps the drain wiring 40 of the current control TFT 3503 with an insulating film in the region indicated by 3504. At this time, a capacitor is formed in a region indicated by 3504. This capacitor 3504 functions as a capacitor for holding the voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is always applied.
[0192]
A first passivation film 41 is provided on the switching TFT 3502 and the current control TFT 3503, and a planarizing film 42 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0193]
Reference numeral 43 denotes a pixel electrode (EL element cathode) made of a highly reflective conductive film, which is electrically connected to the drain of the current control TFT 3503. In this case, it is preferable to use an N-channel TFT as the current control TFT. As the pixel electrode 43, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used.
[0194]
A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.
[0195]
There are various types of PPV organic EL materials such as “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,“ Polymers for Light Emitting ”. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and Japanese Patent Laid-Open No. 10-92576 may be used.
[0196]
As specific light-emitting layers, cyanopolyphenylene vinylene may be used for a light-emitting layer that emits red light, polyphenylene vinylene may be used for a light-emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light-emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm).
[0197]
However, the above example is an example of an organic EL material that can be used as a light emitting layer, and is not necessarily limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer.
[0198]
For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0199]
In this embodiment, the EL layer has a laminated structure in which a hole injection layer 46 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light emitting layer 45. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. What can form into a film at low temperature as much as possible is preferable.
[0200]
When the anode 47 is formed, the EL element 3505 is completed. Note that the EL element 3505 here refers to a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. As shown in FIG. 18A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.
[0201]
By the way, in the present embodiment, a second passivation film 48 is further provided on the anode 47. The second passivation film 48 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to cut off the EL element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic EL material and the meaning of suppressing degassing from the organic EL material. This increases the reliability of the EL display device.
[0202]
As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 17, and includes a switching TFT having a sufficiently low off-current value and a current control TFT resistant to hot carrier injection. Have. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.
[0203]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-5. In addition, it is effective to use the EL display panel of this embodiment as the display unit of the electronic devices of Embodiments 9 and 10.
[0204]
Example 14
In this embodiment, a structure in which the structure of the EL element 3505 is inverted in the pixel portion described in Embodiment 13 will be described. FIG. 19 is used for the description. Note that the only difference from the structure of FIG. 17 is the EL element portion and the current control TFT, and other descriptions are omitted.
[0205]
In FIG. 17, a current control TFT 3503 is formed using a PTFT manufactured using the present invention. The manufacturing process may refer to Examples 1 to 5.
[0206]
In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Of course, a conductive film made of a compound of indium oxide and tin oxide may be used.
[0207]
Then, after banks 51a and 51b made of insulating films are formed, a light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.
[0208]
In the case of the present embodiment, the light generated in the light emitting layer 52 is emitted toward the substrate on which the TFT is formed, as indicated by the arrows.
[0209]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-5. In addition, it is effective to use the EL display panel of this embodiment as the display unit of the electronic devices of Embodiments 9 and 10.
[0210]
Example 15
In this embodiment, an example in which the pixel has a structure different from the circuit diagram shown in FIG. 18B is shown in FIGS. In this embodiment, 3801 is a source wiring of the switching TFT 3802, 3803 is a gate wiring of the switching TFT 3802, 3804 is a current control TFT, 3805 is a capacitor, 3806 and 3808 are current supply lines, and 3807 is an EL element. .
[0211]
FIG. 20A shows an example in which the current supply line 3806 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 3806. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0212]
FIG. 20B illustrates an example in which the current supply line 3808 is provided in parallel with the gate wiring 3803. In FIG. 20B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, since the exclusive area can be shared by the power supply line 3808 and the gate wiring 3803, the pixel portion can be further refined.
[0213]
20C, the current supply line 3808 is provided in parallel with the gate wiring 3803 similarly to the structure of FIG. 20B, and two pixels are symmetrical with respect to the current supply line 3808. It is characterized in that it is formed. It is also effective to provide the current supply line 3808 so as to overlap with any one of the gate wirings 3803. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0214]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Example 1-5, 11 or 12. In addition, it is effective to use the EL display panel having the pixel structure of this embodiment as the display portion of the electronic devices of Embodiments 9 and 10.
[0215]
[Example 16]
18A and 18B shown in Embodiment 13, the capacitor 3504 is provided to hold the voltage applied to the gate of the current control TFT 3503. However, the capacitor 3504 can be omitted. is there. In the case of Example 13, since the NTFT manufactured using the present invention as shown in Examples 1 to 5 is used as the current control TFT 3503, the LDD provided so as to overlap the gate electrode through the gate insulating film. Has an area. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region, but this embodiment is characterized in that this parasitic capacitance is positively used in place of the capacitor 3504.
[0216]
Since the capacitance of the parasitic capacitance varies depending on the area where the gate electrode and the LDD region overlap, the capacitance of the parasitic capacitance is determined by the length of the LDD region included in the overlapping region.
[0217]
Similarly, the capacitor 3805 can be omitted in the structures of FIGS. 20A, 20B, and 20C shown in the fifteenth embodiment.
[0218]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-5, 11-15. In addition, it is effective to use the EL display panel having the pixel structure of this embodiment as the display portion of the electronic devices of Embodiments 9 and 10.
[0219]
【The invention's effect】
By utilizing the present invention, a pattern can be formed by a self-alignment method without using an exposure apparatus using a photomask. Therefore, variation due to alignment of the photomask does not occur, and variation in TFT characteristics can be reduced. In particular, by using the self-aligned pattern forming method of the present invention as a method for manufacturing a bottom gate TFT, an LDD region or an offset region having a desired dimension can be formed on the gate wiring.
[0220]
Further, by utilizing the present invention, since light can be circulated in a short time, a pattern can be formed on the inner side above the wiring even if the wiring is fine.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a manufacturing process of the present invention (Example 1)
FIG. 2 is a diagram showing an example of a manufacturing process of the present invention (Example 1)
FIG. 3 is a diagram showing an example of a manufacturing process of the present invention (Example 1).
FIG. 4 is a sectional structural view showing an example of the configuration of the present invention (Example 1).
FIG. 5 is a top view showing an example of the configuration of the present invention (Example 1).
FIG. 6 shows an exposure apparatus according to the present invention.
FIG. 7 is a diagram showing an example of a manufacturing process of the present invention (Example 5).
FIG. 8 is a diagram showing an example of a manufacturing process of the present invention (Example 5).
FIG. 9 is a diagram showing an example of a manufacturing process of the present invention (Example 5).
FIG. 10 is a diagram showing a cross-sectional structure of a liquid crystal display device (Example 6).
FIG. 11 shows an active matrix display device (Example 7)
FIG. 12 is a diagram illustrating an example of an electronic device (Example 9)
FIG. 13 is a diagram illustrating an example of an electronic device (Example 10)
FIG. 14 shows an example of a conventional manufacturing process.
FIG 15 illustrates an EL display device. Example 11
FIG 16 illustrates an EL display device. Example 12
FIG 17 illustrates an EL display device. (Example 13)
FIG 18 illustrates an EL display device. (Example 13)
FIG 19 illustrates an EL display device. (Example 14)
FIG. 20 illustrates an EL display device. (Example 15)
[Explanation of symbols]
100 substrates
101 Base film
102 Gate wiring
103 Protective film
104 Gate insulation film
105 Semiconductor film
106 Insulating thin film
107 Photosensitive thin film
108 reflector
109 First resist pattern
110 Mask pattern
111 Photosensitive thin film
112 Second resist pattern
113 High concentration impurity region
115 channel formation region
116, 117 LDD region
118 Source region
119 drain region
120 Interlayer insulation film
121, 122 wiring

Claims (8)

Forming a pattern of non-translucent thin film material on a transparent substrate,
Forming a photosensitive thin film on the pattern;
The light from the light source that has passed through the photosensitive thin film is reflected or scattered by the reflecting means provided on the surface side of the substrate, and the photosensitive thin film is exposed by irradiating from the surface side of the substrate,
The method for manufacturing a semiconductor device comprising the Turkey to developing the exposed photosensitive film. Forming a pattern of non-translucent thin film material on a transparent substrate,
Forming a photosensitive thin film on the pattern;
Using the pattern as a mask, light from a light source is irradiated from the back side of the substrate to expose the photosensitive thin film, and light from the light source that has passed through the photosensitive thin film is provided on the surface side of the substrate. is reflected or scattered by the reflecting means is, by irradiating the surface of the substrate by exposing the photosensitive film,
The method for manufacturing a semiconductor device comprising the Turkey to developing the exposed photosensitive film. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the dimension of the developed photosensitive thin film is smaller than the dimension of the pattern made of the non-light-transmitting thin film material. Form a gate wiring on the translucent substrate,
Forming a gate insulating film on the gate wiring;
Forming a semiconductor film on the gate insulating film;
Forming a photosensitive thin film on the semiconductor film;
Using the gate wiring as a mask, light from a light source is irradiated from the back side of the substrate to expose the photosensitive thin film, and light from the light source that has passed through the photosensitive thin film is provided on the surface side of the substrate. is is reflected or scattered by the reflection means and, exposing the photosensitive film by irradiating the surface of the substrate,
Removing the exposed portion to form a pattern consisting of a photosensitive thin film;
The method for manufacturing a semiconductor device comprising a benzalkonium be added with an impurity which imparts the semiconductor film conductivity type a pattern of the photosensitive film as a mask. Form a gate wiring on the translucent substrate,
Forming a gate insulating film on the gate wiring;
Forming a semiconductor film on the gate insulating film;
Forming an insulating thin film on the semiconductor film;
Forming a photosensitive thin film on the insulating thin film;
Using the gate wiring as a mask, light from a light source is irradiated from the back side of the substrate to expose the photosensitive thin film, and light from the light source that has passed through the photosensitive thin film is provided on the surface side of the substrate. is is reflected or scattered by the reflection means and, exposing the photosensitive film by irradiating the surface of the substrate,
Removing the exposed portion to form a pattern consisting of a photosensitive thin film;
Selectively removing the insulating thin film using the pattern as a mask, forming a pattern comprising the insulating thin film;
Removing the pattern made of the photosensitive thin film,
The method for manufacturing a semiconductor device comprising a benzalkonium be added with an impurity which imparts the semiconductor film conductivity type a pattern of the insulating film as a mask. 6. The semiconductor according to claim 4 , wherein the insulating thin film is a single layer film selected from a silicon nitride film, a silicon oxynitride film, a silicon oxide film, and an organic resin film, or a laminated film thereof. Device fabrication method. In any one of claims 4 to 6, wherein the dimension of a pattern made of a photosensitive thin film, a method for manufacturing a semiconductor device, wherein the dimension smaller than the gate line. In any one of claims 1 to 7, wherein the reflecting means, a method for manufacturing a semiconductor device, wherein the material film having light reflectivity is a reflective plate provided.

Images