JP2000252474A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently remove elements for accelerating crystallization from a crystalline semiconductor film. SOLUTION: An Ni film 13 is formed in contact with a semiconductor film 12 that is made of an amorphous silicon film, a microcrystalline silicon film, or the like. The semiconductor film 12 is heated at 45-650 deg.C for moving Ni to form a crystalline semiconductor film 15. Then, a region that becomes a source region and a region that becomes a drain region of the crystalline semiconductor film 15 are selectively doped with a crystallization acceleration element, thus forming a group 15 element doped region 15a. After that, it is heated at 500-850 deg.C, thus allowing the crystallization acceleration element remaining at a region 15b to be subjected to gettering to be sucked by the 15-family element doped region 15a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device using a crystalline semiconductor film. Note that the semiconductor device of the present invention includes not only elements such as thin film transistors and MOS transistors, but also electronic equipment having a semiconductor circuit composed of these insulated gate semiconductor elements, and electro-optical display devices (typically, an active matrix substrate). Also, electronic equipment such as a personal computer or a digital camera having a liquid crystal display device is included in the category.

[0002]

2. Description of the Related Art At present, a thin film transistor (TFT) is known as a semiconductor element using a semiconductor film. TF
Although T is used in various integrated circuits, it is particularly used as a switching element of a matrix circuit of an active matrix type liquid crystal display device. Further, in recent years, the mobility of the TFT has been increased, and the TFT is used as an element of a driver circuit for driving a matrix circuit.
For use in a driver circuit, it is necessary to use a crystalline silicon film having higher mobility than an amorphous silicon film as a semiconductor layer. This crystalline silicon film (also referred to as a crystalline silicon film) is called polycrystalline silicon, polysilicon, microcrystalline silicon, or the like.

Conventionally, to form a crystalline silicon film,
A method of forming a crystalline silicon film directly, and a method of forming an amorphous silicon film by a CVD method at a temperature of 600 to 1100 ° C.
A method of crystallizing amorphous silicon by heat treatment for 0 to 48 hours is known. The crystalline silicon film formed by the latter method has larger crystal grains and has better characteristics of the manufactured semiconductor element.

When a crystalline silicon film is formed on a glass substrate by the latter method, the upper limit of the crystallization process temperature is about 600 ° C., and the crystallization step requires a long time. Further, the temperature of 600 ° C. is close to the lowest temperature for crystallizing silicon, and if it is lower than 500 ° C., it is impossible to crystallize in an industrial time.

In order to shorten the crystallization time, a crystallization temperature may be raised to about 1000 ° C. by using a quartz substrate having a high strain point, but the quartz substrate is very expensive compared to a glass substrate. It is difficult to increase the area. For example, Corning 7 widely used in active-type liquid crystal display devices
059 glass has a glass strain point of 593 ° C. and 600 ° C.
Heating at the above temperature for several hours causes shrinkage or bending of the substrate. For this reason, there is a demand for a lower temperature and a shorter crystallization process so that a glass substrate such as Corning 7059 glass can be used.

[0006] The crystallization technique using an excimer laser is one of the techniques that has made it possible to reduce the temperature and time of the process.
Excimer laser light can give energy comparable to thermal annealing at about 1000 ° C. to a semiconductor film in a short time with almost no thermal influence on the substrate, and can form a highly crystalline semiconductor film. it can. However,
Since the energy distribution of the irradiation surface of the excimer laser varies, the crystallinity of the obtained crystalline semiconductor film also varies, and the device characteristics of each TFT also vary.

Accordingly, the present applicant has disclosed a technique in which the crystallization temperature is lowered while using a heat treatment as disclosed in Japanese Patent Laid-Open No. Hei 6-2320.
No. 59, JP-A-7-321339 and the like. According to the technique disclosed in the above publication, a crystalline silicon film is obtained by introducing a small amount of an element that promotes crystallization (for convenience, called a crystallization promoting element) as a catalyst into an amorphous silicon film and then performing a heat treatment. Things. The elements that promote and promote crystallization include Ni, Fe, Co, and R.
u, Rh, Pd, Os, Ir, Pt, Cu, Au, Ge
Use an element selected from

In the crystallization of the above publication, heat treatment
The crystallization promoting element moves (also called diffusion) into the amorphous silicon film, and crystallization of the amorphous silicon proceeds. By using the crystallization technique of the above publication, 450 to 600
Crystalline silicon can be formed by heat treatment at 4 [deg.] C. for 4 to 24 hours, and a glass substrate can be used.

However, the crystallization disclosed in the above publication has a problem that the crystallization promoting element remains in the crystalline silicon film. Such a crystallization promoting element impairs the semiconductor characteristics of the silicon film, and impairs the stability and reliability of the element to be manufactured.

In order to solve this problem, the present applicant has studied a method of removing (gettering) a crystallization promoting element from a crystalline silicon film. One way is
This is a method of performing heat treatment in an atmosphere containing a halogen element such as chlorine. In this method, the crystallization promoting element in the film is vaporized as a halide.

The second method is a method in which phosphorus is selectively added to a crystalline silicon film to perform a heat treatment. By performing the heat treatment, the crystallization promoting element moves to the phosphorus-added region and is captured in this region.

However, in the first method, the heat treatment temperature needs to be 800 ° C. or higher to obtain the effect of gettering, and a glass substrate cannot be used. On the other hand, in the second method, the heating temperature can be set to 600 ° C. or less,
There is a drawback that the processing time takes over ten hours.

[0013]

SUMMARY OF THE INVENTION The present invention provides a method for removing a crystallization promoting element according to the second method.
An object of the present invention is to provide a method for efficiently performing a step of removing a crystallization promoting element.

It is a further object of the present invention to reduce the process temperature to 600 ° C. or less and to form a high-performance semiconductor device on a glass substrate.

[0015]

The reason why it takes time to remove the crystallization-promoting element is that the crystallization-promoting element is reduced in a region 70 (referred to as a gettered region for convenience) as shown in FIG. Phosphorus-added region 7 for absorbing and capturing the element
1 (gettering region).

Therefore, when the gettering region is formed in contact with the gettering region, the moving distance to the region where the crystallization-promoting element is captured is shortened, so that the step of removing the crystallization-promoting element is shortened, and the temperature is reduced. Can be achieved.

Here, the region 70 (gettering region) in which the crystallization promoting element is reduced is a region including a region where a good or bad characteristic is a channel forming region that most affects semiconductor characteristics. Switching characteristics and mobility values are greatly affected by characteristics of the channel formation region. If the crystallization promoting element remains irregularly in the channel formation region, semiconductor characteristics such as switching characteristics and mobility are impaired, and the stability and reliability of the device are impaired. Therefore, reducing the crystallization promoting element remaining in the channel formation region is indispensable for producing a stable and reliable element.

Furthermore, it is preferable that the gettering region 70 includes, in addition to the region to be a channel forming region, a region to be a low-concentration impurity region adjacent to the region. The low-concentration impurity region is a region for reducing a leak current at the time of OFF. Therefore, by reducing the amount of the crystallization promoting element remaining in the low-concentration impurity region, it is possible to obtain a stable and reliable element with respect to a reduction in leakage current.

The low-concentration impurity region is a high-resistance region whose impurity concentration is lower than those of the source region and the drain region. The impurity concentration is 10 ¹⁶ to 10 ¹⁹ atoms / cm ³ . However, the low concentration impurity region does not necessarily have to have a lower impurity concentration than the source region and the drain region. It is sufficient that the low concentration impurity region has a higher resistance than the source region and the drain region. Therefore, instead of lowering the impurity concentration of the low-concentration impurity region, ion implantation or laser irradiation is performed on the low-concentration impurity region to make the resistance region higher than that of the source region or the drain region. It does not matter.

The gettering region for capturing the crystallization promoting element is in contact with the gettering region, has a size capable of capturing the crystallization promoting element contained in the gettering region, and reduces the number of steps. Considering,
It is necessary that the region includes at least a region to be a source region and a region to be a drain region. By adding a Group 15 element such as phosphorus to a region including a region serving as a source region and a region serving as a drain region, an impurity element for simultaneously reducing the resistance of the region serving as a source region and the region serving as a drain region can be obtained. The introduction can be performed, and the step of introducing the impurity element can be omitted.

Therefore, in the present invention, as shown in FIG.
A hatched region including at least a source region 81 and a drain region 82 in contact with a gettering region 80 including a region to be a channel formation region or a region to be a channel formation region and a low-concentration impurity region. A group 15 element is added to 83, and the crystallization promoting element in the to-be-gettered region 80 is moved to the gettering region 83 as shown by an arrow 85 to be captured.
The main configuration is to remove the crystallization promoting element from.

In FIG. 1A, a region 8 serving as a source region is shown.
The region 82 serving as the first and drain regions is used as a gettering region 83, and a group 15 element is added to remove the crystallization promoting element in the gettering region 80. FIG. 1 (A)
Since the area of the gettering region 83 for capturing the crystallization promoting element is the minimum size, the gettering region 8
3, the concentration of the crystallization promoting element can be increased, and the resistance of the source region 81 and the drain region 82 can be reduced.

FIG. 1B shows a case where phosphorus is added in a band shape, and it is not necessary to align the phosphorus-added region 83 and the island-shaped semiconductor layer 86 in the horizontal direction (the length direction of the band). Furthermore,
FIG. 1B shows that the area of the gettering region 83 is smaller than that of FIG.
Since it is larger than (A), the time required for removing the crystallization promoting element can be reduced and the temperature can be reduced. At the same time, FIG.
(B) shows that the width of the band of the phosphorus added region 83 is changed to the source region 81.
And the width of the drain region 82, so that the phosphorus-added region 83 is strip-shaped and its area is minimized, so that the source region 81 and the drain region 82 are the most trapped among those which do not require lateral alignment. Thus, the concentration of the crystallization promoting element can be increased, and the resistance of the source region 81 and the drain region 82 can be reduced.

FIG. 1C shows a case where phosphorus is added in a belt-like manner as in FIG. 1B, and the same effect as in FIG. 1B is obtained. FIG. 1C shows that the width of the phosphorus-added region 83 is smaller than that of FIG.
Since the width of the phosphorus-added region 83 is wider than that of the region 81 serving as the source region and the region 82 serving as the drain region as shown in FIG. 1B, the crystallization is further promoted as compared with FIG. It is possible to reduce the time and temperature for removing elements. Further, since the band-shaped width is wider than the width of the region serving as the source region and the width of the region serving as the drain region, the phosphorus-added region 8
3 and the island-shaped semiconductor layer 86 need not be aligned in the horizontal direction (the length direction of the band), and in addition, the phosphorus-added region 83 and the island-shaped semiconductor layer 86 can be aligned in the vertical direction (width direction of the band). It is not necessary to perform strictly. Therefore, FIG. 1C can improve the reliability most.

FIG. 1D shows the case where phosphorus is added to surround a region 84 serving as a channel formation region (or a region serving as a channel formation region and a low concentration impurity region). And lower temperature can be achieved.

The present invention for solving the above-mentioned problems includes a step A of forming a semiconductor film, a step B of introducing an element for promoting crystallization to the semiconductor film, and a step of introducing the element for promoting crystallization. After that, a step C of crystallizing the semiconductor film
A step D of selectively adding a group 15 element to the crystallized semiconductor film; a step E of heating the semiconductor film after the addition of the group 15 element; and patterning the semiconductor film to form an island. Forming a semiconductor layer, and the patterning is performed such that the region to which the group 15 element is added becomes a source region and a drain region, and the region to which the group 15 element is not added is formed. The main configuration is to be performed so as to be a channel formation region.

In the semiconductor film forming step A, the semiconductor film has no crystallinity, or has
A semiconductor film having almost no crystal grains on the order of 00 nm or more, specifically, an amorphous semiconductor film or a microcrystalline semiconductor film. A microcrystalline semiconductor film is a semiconductor film in which microcrystals including crystal grains having a size of several nm to several tens of nm and amorphous are in a mixed phase.

More specifically, the semiconductor film is an amorphous silicon film, a microcrystalline silicon film, an amorphous germanium film, a microcrystalline germanium film, an amorphous Si ₁ Ge _1-x (0 <x <
1), and these semiconductor films are formed by a chemical vapor method such as a plasma CVD method and a low pressure CVD method.

When the semiconductor film is formed, a semiconductor film and an inorganic insulating film may be continuously formed. By doing so, attachment of impurities to the surface of the semiconductor film can be prevented. Further, the continuously formed inorganic insulating film may be used as a gate insulating film or a part of the gate insulating film. Impurities at the interface between the semiconductor film and the gate insulating film may impair semiconductor characteristics.However, when the semiconductor film and the gate insulating film are continuously formed, adhesion of the impurity to the interface between the semiconductor film and the gate insulating film is prevented. Can be.

In the introduction step B, the element that promotes crystallization (crystallization promoting element) is an element having a function of promoting and promoting crystallization of a semiconductor, particularly silicon.
i, Fe, Co, Ru, Rh, Pd, Os, Ir, P
One or more elements selected from t, Cu, Au, and Ge can be used.

As the method for introducing the crystallization promoting element, a method of adding a crystallization promoting element to a semiconductor film and a method of forming a film containing the crystallization promoting element in contact with the upper or lower surface of the semiconductor film are used. Can be.

In the former method, a method in which after forming a semiconductor film, a crystallization promoting element is added to the semiconductor film by an ion implantation method, a plasma doping method or the like can be used.

In the latter method, a film containing a crystallization promoting element is formed by a deposition method such as a CVD method or a sputtering method, or a coating method of applying a solution containing a crystallization promoting element using a spinner. No. Either the formation of the film containing the crystallization promoting element or the formation of the semiconductor film may be performed first. If the semiconductor film is formed first, the film containing the crystallization promoting element is in close contact with the upper surface of the semiconductor film. Formed,
If the formation order is reversed, the film containing the crystallization promoting element will be formed close to the lower surface of the semiconductor film. In the present invention, close contact means not only that the semiconductor film and the crystallization promoting element are literally in close contact with each other, but also that if the crystallization promoting element can move into the semiconductor film, an oxide film having a thickness of about This includes a configuration in which a film or the like exists.

For example, when nickel (Ni) is used as a crystallization promoting element in the introduction step, a Ni film or a Ni silicide film may be formed by a deposition method.

When the coating method is used, nickel bromide, nickel acetate, nickel oxalate, nickel carbonate,
Nickel salts such as nickel chloride, nickel iodide, nickel nitrate and nickel sulfate are used as solutes, and water, alcohol, acid,
A solution using ammonia as a solvent or a solution using nickel as a solute and using benzene, toluene, xylene, carbon tetrachloride, chloroform, or ether as a solvent can be used. Alternatively, even if nickel is not completely dissolved, a material such as an emulsion in which nickel is dispersed in a medium may be used.

Alternatively, nickel alone or a nickel compound may be dispersed in a solution for forming an oxide film to form an oxide film containing nickel. As such a solution, OCD (Ohka Diffusio) of Tokyo Ohka Kogyo Co., Ltd.
n Source) can be used. With the use of this OCD solution, a silicon oxide film can be easily formed by applying it on the surface to be formed and baking it at about 200 ° C. The same applies to other crystallization promoting elements.

As a method of introducing the crystallization promoting element, a doping method or a method of forming a Ni film by a sputtering method is used.
The coating method can most easily adjust the concentration of the crystallization promoting element in the semiconductor film, and the process can be simplified.

The crystallization step C is performed while moving (also called diffusion) the crystallization promoting element into the semiconductor film. When the semiconductor film into which the crystallization promoting element is introduced is heat-treated, the crystallization promoting element immediately moves into the semiconductor film. Then, the crystallization-promoting element moves and exerts a catalytic action on the molecular chains in the amorphous state to crystallize the semiconductor film.

Regarding the action of accelerating the crystallization,
The present applicant has disclosed in Japanese Patent Application Laid-Open Nos. 06-244103 and 06-244104. Silicon in contact with the crystallization promoting element combines with the crystallization promoting element to form silicide. Then, it was found that the silicide reacts with the amorphous silicon bond, and crystallization proceeds. This is because the interatomic distance between the crystallization promoting element and silicon is very close to the interatomic distance of single crystal silicon, and the Ni—Si distance is closest to the single crystal Si—Si distance, and 0.6% As short.

When a reaction for crystallizing an amorphous silicon film using Ni as a crystallization promoting element is modeled, Si [a] -Ni (silicide) + Si [b] -Si [c] (amorphous) → Si [a] -Si [b] (crystalline) + Ni-Si [c] (silicide)

In the above reaction formula, [a],
The indices [b] and [c] indicate Si atom positions.

In the above reaction formula, the distance between Si [a] and Si [b] is almost the same as that of the single crystal because the Ni atom in the silicide replaces the Si [b] atom of the amorphous silicon. Indicates that In addition, it shows that Ni grows crystal while diffusing in the semiconductor film. Further, at the time when the crystallization reaction is completed, it is shown that Ni is localized at the moved end (or the tip of crystal growth) in a state of being bonded to Si. That can be assumed to be randomly distributed within the film after crystallization of silicide state represented by NiSi _x. The presence of this silicide can be confirmed as a hole by subjecting the film after crystallization to FPM treatment.

The FPM treatment is an FPM (50% HF and 50% H ₂ O _{2) that} can remove nickel silicide in a short time.
(Etchant mixed with 1: 1), which is etched by FPM for about 30 seconds, and the presence of nickel silicide can be confirmed by the presence or absence of a hole by the etching.

Holes due to FPM were irregularly formed in the silicon film crystallized by the FPM treatment. This indicates that nickel is localized in the crystallized region, and silicide is formed by bonding with silicon at the localized portion.

It is known that in order to provide energy for causing the crystallization reaction to proceed, heating at 450 ° C. or higher in a heating furnace is sufficient. The upper limit of the heating temperature is 650 ° C. This is to prevent crystallization of the amorphous semiconductor film from progressing in a portion that does not react with the crystallization promoting element. If crystallization occurs in a portion that does not react with the crystallization promoting element, the crystallization promoting element cannot diffuse into that portion, so that the crystal grains cannot be made large and the particle size varies.

In the crystallization step, the semiconductor film crystallized by the heat treatment may contain defects in crystal grains, or may have an amorphous portion.
Therefore, it is preferable to perform heat treatment again in order to crystallize the amorphous portion and eliminate defects in the grains. This heating temperature is higher than the heat treatment during crystallization,
Specifically, the temperature is set to 500 to 1100 ° C, more preferably to 600 to 1100 ° C. Needless to say, the upper limit of the actual temperature is determined by the heat resistant temperature of the substrate.

In this step, excimer laser light can be applied instead of the heat treatment. However, as described above, since the excimer laser has unavoidable irradiation energy variation, the crystallization of the amorphous portion may vary. In particular, in the case where the distribution of the amorphous portion varies from one film to another, not only the characteristics among the elements in one semiconductor device vary, but also the characteristics between the semiconductor devices may vary.

Therefore, when excimer laser light is irradiated after the crystallization step, it is desirable to always perform a heat treatment to crystallize the amorphous portion and reduce defects. Therefore, when an excimer laser is used in the next optical annealing step, it is important to perform a process for improving crystallinity by heat treatment.

As a heating method equivalent to the heat treatment in the heating furnace, the wavelength is 0.6 to 4 μm, and more preferably the wavelength is 0.6 to 4 μm.
The RTA method of irradiating infrared light having a peak at 8 to 1.4 μm for several tens to several hundreds of seconds is known. Since the absorption coefficient of infrared light is high, the semiconductor film is 800
Heat to ~ 1100 ° C in a short time. However, since the RTA method has a longer irradiation time than the excimer laser beam, heat is easily absorbed by the substrate, and when a glass substrate is used, attention must be paid to the occurrence of warpage.

As another method, a pulse oscillation type YA
There is a method using a G laser or a YVO ₄ laser.
In particular, when a laser device of a laser diode pumping type is used, a high output and a high pulse oscillation frequency can be obtained. The second harmonic (532 nm) and the third harmonic (354.7n)
m) or the fourth harmonic (266 nm), for example, a laser pulse oscillation frequency of 1 to 20,000 Hz (preferably 10 to 10000 Hz), and a laser energy density of 200 to 600 mJ / cm ² (typically 300 to 50
0 mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 80 to 90%. When the second harmonic is used, heat is evenly transmitted to the inside of the semiconductor layer, and crystallization can be performed even when the irradiation energy range is slightly varied. As a result, a processing margin can be secured, and crystallization variation is reduced. Further, since the pulse frequency is high, the throughput is improved.

An object of the present invention is to remove (gettering) a crystallization promoting element localized in a crystallized semiconductor film. In the present invention, a group 15 element is used to getter the crystallization promoting element. Here, the Group 15 elements are P, As, N, Sb, and Bi. P has the highest gettering ability, followed by Sb.

In the present invention, the crystallization promoting element is removed by
A group 15 element is selectively added to the crystallized crystalline semiconductor film to form a region containing a group 15 element, and heat treatment is performed to move a crystallization promoting element to a region containing a group 15 element. This is done by capturing. 15 for crystalline semiconductor film
In the step D of adding a group element, a gas phase method such as a plasma doping method or an ion implantation method may be used as in the method of introducing a crystallization promoting element into a semiconductor film.

The region to which the group XV element is added (gettering region) does not include a region to be a channel formation region of the crystallized semiconductor film or a region to be a channel formation region and a region to be a low-concentration impurity region. A region that is to be in contact with the region to be formed or the channel formation region and the region to be the low-concentration impurity region, specifically, a region that includes a region to be a source region and a region to be a drain region. By adding a Group 15 element to the region serving as a source region and the region serving as a drain region, a step of introducing an impurity element for reducing resistance can be performed at the same time, and the process can be simplified.

It is preferable that an inorganic insulating film such as a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like be used as a mask when the Group 15 element is added.

The size of the region (gettering region) to which the Group 15 element is added is sufficient for removing the crystallization promoting element if at least the size of the source region and the drain region is large. It is. However, it is preferable that the region to which the group 15 element is added be large, because the time required for the removal step is reduced and the temperature is reduced. Therefore, performing the step of patterning the semiconductor film to form the island-shaped semiconductor layer after the step of removing the element that promotes crystallization requires that the region to which the group 15 element is added be larger than the source region and the drain region. It is preferable because it is possible.

The group 15 element concentration in the region where the group 15 element is added is 1% of the concentration of the crystallization promoting element remaining in the semiconductor film.
Make it 0 times. In the crystallization method of the present invention, 10 ¹⁸ to 10 ²⁰
Since the crystallization promoting element remains in the order of atoms / cm ³ ,
The group 15 element concentration is 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ .

Removal of crystallization promoting element (gettering)
Is performed in the step E of performing a heat treatment. By the heat treatment, the crystallization promoting element moves to a region (gettering region) to which the group XV element is added and is captured (gettered). This removal step of the crystallization promoting element can be regarded as a step of absorbing (gettering) the crystallization promoting element in the region to which the group 15 element is added.

This heat treatment is performed before forming the gate electrode and the gate wiring (the gate wiring and the gate electrode are often formed integrally). The temperatures at the time of crystallization of the semiconductor film and at the time of removal of the crystallization promoting element must be raised to the highest temperatures in manufacturing a semiconductor device. Therefore, by forming the gate electrode after these steps, a conductive material with low heat resistance can be used as the gate electrode.
The characteristic of the gate electrode material required when using the semiconductor device is low resistance, but the characteristic of the gate electrode material required when manufacturing the semiconductor device is that it has heat resistance. Heat resistance is an important characteristic required so as not to impair the reliability of the semiconductor device. A conductive material having low heat resistance could not be used as a gate electrode material, no matter how low the resistance, but by using the present invention,
The gate electrode can be formed using a conductive material with low heat resistance.

In the present invention, in order to lower the temperature and shorten the time for removing the crystallization promoting element,
It is preferable to irradiate the crystallized crystalline semiconductor film with laser light or strong light. By this light irradiation (light annealing), it is possible to make the crystallization promoting element localized in the crystalline semiconductor film easy to move.

[0060] crystallization promoter element as NiSi _x, remain attached to the semiconductor molecules, although distributed semiconductor film, by the energy of light annealing, is cut off the NiSi bond, crystallization accelerating element Is changed to an atomic state, or the Ni-Si bond energy is reduced, so that the remaining crystallization promoting element is easily moved in the crystalline semiconductor film.

Since the energy required for moving the crystallization promoting element can be reduced by the above-described light annealing, the crystallization promoting element can be moved by heating at 500 ° C. or more. The time can be shortened. Further, since the gettering region is formed in the element formation region, it is not necessary to newly provide a gettering region, and the portion where the element can be formed can be enlarged. Note that the upper limit of the heating temperature in the step of removing the crystallization promoting element is a temperature at which the group 15 element included in the gettering region does not move, and is 800 ° C to 850 ° C.

In the light annealing step, the portion to be irradiated with light may be irradiated to a portion of the semiconductor film to be a semiconductor layer constituting a semiconductor element, and at least a region where a depletion layer of the semiconductor layer is formed. Region).

An excimer laser can be used as a light source for light annealing. For example, KrF excimer laser (wavelength 248 nm), XeCl excimer laser (wavelength 308 nm), XeF excimer laser (wavelength 3
51, 353 nm), ArF excimer laser (wavelength 1
93 nm), XeF excimer laser (wavelength 483 n)
m) and the like can be used. Further, an ultraviolet lamp can be used. Alternatively, an infrared lamp such as a xenon lamp or an arc lamp can be used. Excimer laser light of a pulse oscillation method can be used.

As another method, a pulse oscillation type YA
There is a method using a G laser or a YVO ₄ laser.
In particular, when a laser device of a laser diode pumping type is used, a high output and a high pulse oscillation frequency can be obtained. The fundamental wave (1064 nm), the second harmonic (532 nm), the third harmonic (354.7 nm), and the fourth harmonic (266n)
m), for example, a laser pulse oscillation frequency of 1 to 20,000 Hz (preferably 10 to 10,000)
Hz), laser energy density of 200-600mJ / c
m ² (typically 300 to 500 mJ / cm ² ). Then, the linear beam is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is 80 to
Perform as 90%. Further, since the pulse frequency is high, the throughput is improved.

In the island-shaped semiconductor layer forming step F, the patterning is performed so that the region to which the group 15 element is added becomes a source region and a drain region, and the region to which the group 15 element is not added forms a channel. This is performed so as to be a region or a channel formation region and a low concentration impurity region.

Thereafter, a gate electrode is formed via a gate insulating film provided in contact with the semiconductor layer, and the semiconductor layer facing the gate electrode is used as a channel formation region. The gate electrode is formed on a region (a region to be gettered) of the island-shaped semiconductor layer to which the group 15 element is not added via the gate insulating film.

The present invention does not form a source region and a drain region in self-alignment with the gate electrode. Therefore, only by changing the size of the gate electrode, the structure in which the region (source region and drain region) to which the Group 15 element is added and the gate electrode overlap each other when viewed from the top can be used. The region to which the group 15 element is added (the source region and the drain region) may be formed so as to be almost in contact with the gate electrode, or the region to which the group 15 element is added (the source region and the drain region) and the gate electrode may be formed. It is also possible to adopt a structure in which the distance between the two is constant.

Further, after the region to which the group 15 element is added (the source region and the drain region) and the gate electrode are formed so as to have a fixed distance, that is, the region 15 of the island-like semiconductor layer is formed.
Forming a gate electrode over a part of a region to which a group element is not added (a region to be a channel formation region among regions to be a channel formation region and a low-concentration impurity region) via the gate insulating film; , A low-concentration impurity region can be formed between the source and drain regions and the gate electrode when viewed from above.

Further, after forming the low-concentration impurity region, a second conductive film is formed as a part of the gate electrode on the first conductive film already formed as the gate electrode, and the low-concentration impurity region and the second conductive film are formed. By patterning the second conductive film so that the two conductive films overlap, a gate overlapped LDD (GOLD) structure including a region where the gate electrode and the low-concentration impurity region overlap with each other can be obtained. The GOLD structure can prevent deterioration of a semiconductor device due to hot electron injection. Further, the case where the gate electrode has two layers has been described as an example, but a multilayer structure having three or more layers may be used.

As described above, according to the present invention, an element having a different structure can be manufactured only by changing the size of the gate electrode. Therefore, for example, the element structures of the matrix circuit and the driver circuit on the same panel can be easily different. Similarly, the N-channel type TF of the matrix circuit
The T and P-channel TFTs can easily have different structures.

By adding not only the Group 15 element but also the Group 13 element to the region for capturing the crystallization promoting element,
It has been found that a removal effect higher than that of the Group 15 element alone can be obtained. In this case, the group 13 element concentration is set to 1.3 to 2 times the group 15 element concentration. Group 13 elements are B and A
1, Ga, In, and Ti.

The removal step of the crystallization promoting element of the present invention
The crystallization promoting element concentration is 5 × 10 ¹⁷atoms / cm^ThreeLess than
(Preferably 2 × 10¹⁷atoms / cm^ThreeBelow)
The obtained crystalline semiconductor region is obtained.

At present, SIMS (mass secondary ion)
Analysis) lower limit of detection 2 × 10¹⁷atoms / cm^ThreeAbout
Therefore, it is not possible to determine the concentration below that. Only
However, by performing the removal process described in this specification,
At least 1 × 10¹⁴~ 1 × 10 ^Fifteenatoms / cm^ThreeTo the extent,
It is presumed that the crystallization promoting element is reduced.

[0074]

Embodiments of the present invention will be described with reference to FIGS. Note that the Group 15 element is an element that imparts N-type conductivity to a semiconductor, and the embodiment of the present invention uses a region serving as an N-type source region and a region serving as a drain region as a gettering region.

Embodiment 1 This embodiment will be described with reference to FIG. As shown in FIG. 3A, a substrate 10 is prepared, and a base film 11 is formed on the surface of the substrate 10. The substrate 10 includes an insulating substrate such as a glass substrate, a quartz substrate, and a ceramic substrate, a single crystal silicon substrate, a stainless substrate, a Cu substrate, a high melting point metal material such as Ta, W, Mo, Ti, and Cr, or an alloy thereof ( For example, a conductive substrate such as a substrate made of a nitrogen-based alloy) can be used.

The base film 11 has a function of preventing impurities from diffusing from the substrate into the semiconductor device, a function of increasing the adhesion of the semiconductor film and the metal film formed on the substrate 10 and a function of preventing peeling. As the base film 11, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film formed by a CVD method or the like can be used. For example, when a silicon substrate is used, its surface can be oxidized by thermal oxidation to form a base film. When a heat-resistant substrate such as a quartz substrate or a stainless steel substrate is used, an amorphous silicon film may be formed, and the silicon film may be thermally oxidized.

Further, as the base film 11, tungsten,
A laminated film in which a high-melting-point metal film such as chromium or tantalum or a film having high conductivity such as an aluminum nitride film is formed as a lower layer and the above-described inorganic insulating film is formed as an upper layer may be used. In this case, since the heat generated in the semiconductor device is radiated from the film under the base film 11, the operation of the semiconductor device can be stabilized.

Plasma CVD, reduced pressure C
The semiconductor film 12 is formed by a vapor phase method such as a VD method or thermal CVD. Here, an amorphous silicon film is formed by low pressure CVD
The film is formed to a thickness of 150 nm. Although the plasma CVD method has higher productivity than the low pressure CVD method, the low pressure CVD method requires more time for film formation, but has an advantage that a denser film can be formed than the plasma CVD method. (FIG. 3 (A))

Next, a crystallization promoting element is introduced into the semiconductor film 12. Here, a method of forming a film 13 containing a crystallization promoting element on the surface of the semiconductor film 12 is used. For example, in a spinner, a Ni acetate solution is applied, and this state is maintained for several minutes. By drying using a spinner, a Ni film is formed as the film 13. The solution is practical if the concentration of nickel in the solution is 1 ppm or more, preferably 10 ppm or more. The Ni film is not always in the form of a film, but may be used without being in the form of a film. (FIG. 3
(B))

Then, in a heating furnace, the semiconductor film 12 into which the crystallization promoting element is introduced is heat-treated to form a crystalline semiconductor film 15. The heat treatment is performed under an inert atmosphere such as nitrogen, at a temperature of 450 ° C. to 650 ° C., preferably 5 ° C.
00 ° C to 650 ° C, time 4 to 24 hours. In this embodiment, since the nickel element is in contact with the entire surface of the semiconductor film, the moving direction of nickel moves from the surface of the semiconductor film toward the base film, that is, a direction substantially perpendicular to the substrate surface, and crystallization proceeds in that direction. . (FIG. 3 (C))

Next, a group 15 element is selectively added to a region of the crystalline semiconductor film 15 including a region to be a source region and a drain region. First, a mask insulating film 16 is formed over a region of the semiconductor film 15 which is to be a channel formation region or a region including a channel formation region and a region to be a low concentration impurity region.
As the mask insulating film 16, a resist, silicon oxide, or the like can be used, but an inorganic insulating film is preferable. Here 10
A silicon oxide film having a thickness of 0 nm is formed and patterned to form a mask insulating film 16. Then, a group 15 element is selectively added by a plasma doping method, a coating method, or the like to form a group 15 added region 15 a in the semiconductor film 15. The region 15b to which the group 15 element is not added is referred to as a gettered region for convenience. (FIG. 3 (D))

The group 15 element concentration in the region 15a is set to be 10 times the crystallization promoting element concentration in the gettering region 15b.
In the method of the present embodiment, the area 15b has 10 ¹⁹ to 10 ²⁰
Since the crystallization promoting element remains in the order of atoms / cm ³ ,
The concentration of the Group 15 element in the region 15a is 1 × 10 ²⁰ to 1 × 10
²¹ atoms / cm ³ .

Next, at 500-850 ° C., more preferably
550 to 650 ° C for 4 to 8 hours,
The crystallization promoting element remaining in the
15 which is a region including a region serving as a region and a drain region
Moved to the group element addition region 15a and absorbed there
You. When the connection reaches the source and drain regions
The crystallization promoting element combines with the Group 15 element. For example, promoting crystallization
When the hexadecimal element is Ni and the group 15 element is P, the source region
And NiP in a region to be a drain region.₁, NiP _TwoNi
_Two.. Exist in a coupled state. This combined state
Very stable and has little effect on TFT operation
No. (FIG. 3E) By this heat treatment, the crystallization promoting element (N
i) The concentration is 2 × 10¹⁷atoms / cm^ThreeIs reduced to: Ma
A source region and a drain region
Activate the Group 15 element added to the source region and
Region and the drain region
Can also be.

Then, after the step of removing the crystallization promoting element,
The region 15 is patterned into an island shape so that all or a part of the region 15a becomes a source region and a drain region, thereby forming an island-shaped semiconductor layer 17. A semiconductor element such as a TFT may be manufactured using the semiconductor layer 17.

According to the present invention, before the step of removing the crystallization-promoting element, the region which becomes the source region and the drain region which is in contact with the gettering region from which the crystallization-promoting element is removed,
Since the group V element is added, the time required for the removal step can be reduced. In the present embodiment, the regions that become the source region and the drain region are used as the group 15 additive region that is the gettering region, that is, the group 15 additive region that is the gettering region is formed in the element forming portion, so that the device can be integrated. .

Embodiment 2 This embodiment will be described with reference to FIG. This embodiment is a modification of the catalyst introduction method of the first embodiment. In addition, a method for forming a gate insulating film after formation of a semiconductor layer is described. The rest is the same as in the first embodiment.

The substrate described in Embodiment 1 was prepared, and
A base film 21 is formed on the zero surface. Next, the semiconductor film 22
To form an amorphous silicon film by low pressure thermal CVD. The thickness of the amorphous silicon film is 20 to 100 nm (preferably 40 to 75 nm). Here, the film thickness is 65 nm. Note that a plasma CVD method may be used as long as film quality equivalent to that of an amorphous silicon film formed by a low-pressure thermal CVD method can be obtained.

Next, the semiconductor film 2 made of an amorphous silicon film
A mask insulating film 23 is formed on 2. Mask insulating film 23
Is provided with an opening 23a by patterning.
The opening 23a defines a region to which the crystallization promoting element is added. As the mask insulating film 23, a resist or a silicon oxide film can be used. Here, a 120-nm-thick silicon oxide film is used.

Next, a solution prepared by dissolving nickel acetate containing 5 to 10 ppm by weight of nickel in ethanol is applied by a spin coating method and dried, and a Ni film is masked as a film 24 containing a crystallization promoting element. It is formed on the insulating film 23. In this state, the nickel comes into contact with the semiconductor film 22 at the opening 23 a provided in the mask insulating film 23. (FIG. 4 (A))

Next, after dehydrating at 450 ° C. for about one hour in a heating furnace, nickel is transferred from the nickel-added region 22a to the semiconductor film 22 in an inert atmosphere and a hydrogen atmosphere in the heating furnace. Alternatively, heat treatment is performed in an oxygen atmosphere at a temperature of 450 to 650 ° C. for a heating time of 4 to 24 hours. By heating, nickel is crystallized while moving in the semiconductor film 22 as schematically shown by arrows. Here, heat treatment is performed at 570 ° C. for 8 hours to form a crystalline semiconductor film 25 containing nickel. (FIG. 4 (B))

In this step, the nickel-added region 2
A crystal region (referred to as a lateral growth region) 25b which proceeds preferentially from the nickel silicide reacted in 2a and grows substantially parallel to the substrate surface of the substrate 20 is formed. Since the individual crystal grains are aggregated in a relatively uniform state in the lateral growth region 25b, there is an advantage that the overall crystallinity is excellent. Note that the region 25a is a region into which the crystallization promoting element is introduced, and is unsuitable for an element because it is crystallized but the crystallization promoting element remains at a high concentration. The non-crystallized region 25c is a region where the crystallization promoting element has not moved,
This is a region where crystallization has not progressed. Therefore, only the lateral growth region 25b is suitable for forming a high-performance device.

According to TEM (transmission electron microscopy) observation, in the crystalline semiconductor film, the crystal grains in the lateral growth region 25b are rod-shaped or flat rod-shaped, and the orientations of these crystal grains are almost aligned. Almost all of these crystal grains are roughly $ 11
The crystal orientation is 0 °, and the directions of the <100> axis and the <111> axis are the same for each crystal grain, and the <110> axis slightly fluctuates by about 2 ° between the crystal grains. As described above, since the orientation of the crystal axis is uniform in the lateral growth region 26b, the bonding of atoms at the crystal grain boundaries becomes smooth, and the number of dangling bonds becomes small.

On the other hand, in the conventional polycrystalline silicon, since the direction of the crystal axis is irregular for each crystal grain, there are many atoms that cannot be bonded at the grain boundary. In this regard, the crystal structures of the lateral growth region 25b of the present embodiment and the conventional polycrystalline silicon film are completely different. In the lateral growth region 25b, most of the atoms are not broken at the crystal grain boundaries, and the two crystal grains are bonded with extremely high consistency. This makes it very difficult to create trap levels caused by such factors.

Next, as in the first embodiment, a mask insulating film 27 made of a silicon oxide film is formed. Lateral growth area 25
b is a channel formation region or a gettering region 26a which is a region to be a channel formation region and a low concentration impurity region.
To be included. And P as a Group 15 element
(Phosphorus) is added to form a group 15 element addition region 26c. The nickel concentration remaining in the lateral growth region 25a is about 1/10 of that in the first embodiment, that is, 10 ¹⁸ to 10 ¹⁹ atom.
s / cm ³ , the concentration of phosphorus in the region 26c is 1 × 10
¹⁹ to 1 × 10 ²⁰ atoms / cm ³ . (FIG. 4 (C))

Since the Group 15 element is added to the underlying film 21 and the substrate 20 through the region 26c film, the underlying film 2
Only one or a specific region in the substrate 22 contains a high concentration of a Group 15 element. However, such a group 15 element is TF
There is no adverse effect on the T characteristics.

After the formation of the additional region 26c,
A heat treatment is performed at 00 to 850 ° C. for 2 to 24 hours to move the crystallization promoting element in the gettering region 26 a to the group 15 element-added region 26 c and to absorb it in the region 26 c (the moving direction is indicated by an arrow. Shown). Thus, the crystallization promoting element is 5 × 10 ¹⁷ atoms / cm ³ or less, 1 × 10 ¹⁴ to 1 × 10
A lateral growth region reduced to ¹⁵ atoms / cm ³ is obtained. (FIG. 4 (D))

After the crystallization accelerating element removing step is completed, after removing the mask insulating film 27, the region 26a is changed to a channel forming region or a channel forming region so that all or a part of the region 26c becomes a source region and a drain region. The island-shaped semiconductor layer 28 is formed by patterning into an island shape so as to be a channel formation region and a low concentration impurity region.

Next, the plasma CVD method or the reduced pressure CV
By a method D, an insulating film 30 made of silicon nitride oxide is formed to cover the semiconductor layer 28. The insulating film 30 constitutes a gate insulating film and has a thickness of 50 to 150 n.
m.

Next, a gate electrode 31 is formed on the insulating film 30. For example, P-added silicon, Al, T
High melting point metals such as a, W, Mo, Ti, and Cr and alloys thereof (for example, alloys of high melting point metals and alloys of high melting point metal and nitrogen) can be used.

A TFT can be manufactured using the semiconductor layer 28, the insulating film 30, and the gate electrode 31 obtained in the above steps.

[Embodiment 3] This embodiment will be described with reference to FIG. In this embodiment, the crystallization promoting element is removed after the island-shaped semiconductor layer is formed (after patterning). Others are the same as the first or second embodiment. First, according to the steps described in the first or second embodiment, crystallization of the semiconductor film is performed, and the obtained crystalline semiconductor film is patterned to form the island-shaped semiconductor layer 35. (FIG. 5 (A))

Next, as in Embodiments 1 and 2, a mask insulating film 37 made of a silicon oxide film is formed. And 1
P (phosphorus) as a Group V element is added to the source region and the drain region to form a Group 15 element added region 36c.
(FIG. 5 (B)

After forming the additional region 36c,
A heat treatment is performed at 00 to 850 ° C. for 2 to 24 hours to move the crystallization promoting element in the gettering region 36 d to the group 15 element added region 36 c and suck it (the moving direction is indicated by an arrow). Thus, the catalyst was 5 × 10 ¹⁷ atoms / cm ³
Hereinafter, a region reduced to 1 × 10 ¹⁴ to 1 × 10 ¹⁵ atoms / cm ³ is obtained. (FIG. 5 (C))

Since the source region and the drain region of the semiconductor layer obtained in the above steps have a high nickel element concentration, the resistance of the source region and the drain region can be reduced as compared with the first and second embodiments.

Embodiment 4 This embodiment will be described with reference to FIG. In this embodiment, a low-concentration impurity region is formed by using a gettering region as a channel formation region and a low-concentration impurity region. This embodiment can be applied to the first to third embodiments. First, according to the steps described in the first to third embodiments, the island-shaped semiconductor layer 4 from which the crystallization promoting element in the gettered region 46d has been removed is provided.
8, and a gate insulating film 50 is formed thereon. (FIG. 6 (A))

Next, a gate electrode 51 is formed. For example, P-added silicon, Al, Ta, W, Mo,
Refractory metals such as Ti and Cr and their alloys (eg, alloys of refractory metals, alloys of refractory metals and nitrogen, etc.)
It is formed using. The gate electrode 51 is formed over a part of the gettering region 46d (a region that becomes a channel formation region among regions that become a channel formation region and a low-concentration impurity region). (FIG. 6 (B))

Next, an impurity is added using the gate electrode as a mask to form a low concentration impurity region 52. As for the addition of the impurity, doping was performed at a high acceleration and a low dose, and phosphorus was added to the semiconductor layer through the gate insulating film. The conditions are as follows: acceleration voltage 80 kV, set dose 6 × 10
¹³ atoms / cm ³ and the addition amount is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ ato
ms / cm ³ .

Through the above steps, a low-concentration impurity region can be formed without using a new mask.

After the low-concentration impurity region is further formed by using this embodiment, a second conductive film is formed as a part of the gate electrode on the first conductive film already formed as the gate electrode. By patterning the second conductive film so that the impurity region and the second conductive film overlap, a gate overlapped LDD (GOLD) structure having a region where the gate electrode and the low concentration impurity region overlap is formed. It is also possible to get. The GOLD structure can prevent deterioration of a semiconductor device due to hot electron injection. The gate electrode may have a multilayer structure of three or more layers instead of two layers.

[0110]

Embodiment An embodiment of the present invention will be described with reference to FIGS. Embodiments 1 to 4 may be applied to the embodiment.

[Embodiment 1] In this embodiment, the present invention is applied to a TFT.
In this example, an N-channel TFT and a P-channel TFT are formed over the same substrate to form a CMOS circuit. 7 to 9 are used for the description.

FIG. 7 shows a schematic top view of a CMOS circuit. In FIG. 7, 111 denotes a gate wiring, 108 denotes a semiconductor layer of an N-channel TFT, and 109 denotes a P-channel TF.
T is a semiconductor layer. 161 and 162 are the semiconductor layers 10
8, 109 and contact portions of the source wiring, 16
Reference numerals 3 and 164 denote contact portions between the semiconductor layers 108 and 109 and the drain wiring. Reference numeral 165 denotes a contact portion (gate contact portion) between the gate wiring 111 and the extraction wiring.

A manufacturing process of the TFT will be described with reference to FIGS. 8 and 9, the left side shows a cross-sectional view of an N-channel TFT, and the right side shows a cross-sectional view of a P-channel TFT. The cross-sectional view of each TFT is shown by a chain line AA ′ in FIG.
This corresponds to a cross-sectional view taken along a chain line BB ′.

First, a 1737 glass substrate manufactured by Corning Incorporated is used as the substrate 100. A 300-nm-thick silicon oxide film 101 is formed over a glass substrate 100 as a base film.

When the substrate having the insulating surface is thus prepared, an amorphous silicon film 102 is formed by a low pressure thermal CVD method using disilane as a source gas as a semiconductor film. The thickness of the amorphous silicon film 102 is 55 nm. Next, a mask insulating film 103 made of a 120-nm-thick silicon oxide film is formed over the amorphous silicon film 102. Openings 103a, 10a are formed in the mask insulating film 103 by patterning.
3b is provided.

Next, a solution obtained by dissolving nickel acetate containing 10 ppm by weight of nickel in ethanol is applied by a spin coater and dried to form a Ni film 104. The Ni film 104 is formed in the openings 103 a and 103 b provided in the mask insulating film 103.
Contact 2 Note that since the amorphous silicon film 102 has poor infiltration property, U
If an oxide film of about several nm is formed by V irradiation or the like, it becomes easy to form the Ni film 104 in a state where the Ni film 104 is in contact with the openings 103a and 103b. (FIG. 8A)

When the state shown in FIG. 8A is obtained,
After performing heat treatment at 450 ° C. for about 1 hour in a heating furnace to release hydrogen from the amorphous silicon film 102,
Heat treatment is performed at 570 ° C. for 14 hours in a nitrogen atmosphere. N
Ni moves from the i-film 104 into the amorphous silicon film 102, crystallization proceeds, and the lateral growth regions 106a, 106
The crystalline silicon film 106 having b is formed. (FIG. 8 (B))

When the crystallization step is completed,
It is preferable to heat-treat the crystalline silicon film 106 for 4 hours to crystallize an amorphous portion and improve crystallinity. Further, it is preferable to irradiate the crystalline silicon film 106 with KrF excimer laser light so that Ni localized in the film is easily moved. The excimer laser is processed by an optical system into a linear laser beam having a width of 0.5 mm and a length of 12 cm, and the substrate is scanned in one direction relative to the linear laser beam so that the entire surface of the substrate is irradiated with the laser beam. I do. Alternatively, a laser beam is applied on a side of 5 to 10
Irradiation can also be carried out by processing on a rectangle of about cm.

Next, a channel forming region or a channel of the semiconductor film is formed.
A region including a channel forming region and a region serving as a low-concentration impurity region.
A mask insulating film 118 is formed on the gettering region,
By adding a Group 15 element to the conductor film, an N-channel TFT
A region to be a source region and a drain region is formed. Do
Phosphine diluted to 5% with hydrogen
And add P (phosphorus). With low acceleration and high dose
Doping, doping condition is P concentration semiconductor film
106 times the Ni concentration remaining at 106 and an accelerating voltage of 80
kV, set dose 6 × 10¹³atoms / cm^ThreeAnd add
Addition is 1 × 10 ¹⁹~ 1 × 10^{twenty two}atoms / cm^ThreeAnd (Figure
8 (C))

The semiconductor film 106 has N⁺Mold region 107 is formed
Is done. Here, N of the semiconductor film 106 ⁺One of the mold regions 107
The portion becomes the source and drain regions, and the region 123 is the channel.
This becomes a tunnel formation region and a low concentration impurity region.

By performing a heat treatment in this state, regions 123 and 133 where phosphorus is not added to N ⁺ type region 107 are formed.
Nickel can be absorbed. Ni, which is intentionally added for the crystallization of the amorphous silicon film, has a channel forming region or a region 12 including a channel forming region and a low concentration impurity region, as schematically shown by arrows in FIG.
3 and 133 to the respective regions that become the source and drain regions. As a result, the amount of Ni in the channel formation region and the region serving as the low-concentration impurity region decreases, while the concentration of Ni in the source region and the drain region used for the gettering sink is reduced.
3, 133.

Next, semiconductor layers 108 and 109 are formed by patterning the crystalline silicon film 106 into an island shape.
Note that the above excimer laser irradiation is performed for the semiconductor layer 108,
109 may be formed. (FIG. 8 (D))

Next, SiH _{4 was formed} by plasma CVD.
And N ₂ O as source gas, silicon nitride oxide film 110
Is formed to a thickness of 120 nm. Next, a 40-nm-thick tantalum film (Ta film) is formed over the silicon nitride oxide film 110 by a sputtering device and patterned to form a gate electrode 111. The gate electrode is provided over part of a region to which phosphorus is not added (a region to be a channel formation region of a region to be a channel formation region and a low-concentration impurity region of an N-channel TFT). The irradiation with the excimer laser light may be performed before the Ta film is formed. In this embodiment, at least a region to be a channel formation region may be irradiated with laser light. (FIG. 8 (E))

Using the gate electrode 111 as a mask, impurities are added to form low-concentration impurity regions 124 and 125. As for the addition of the impurity, doping was performed at a high acceleration and a low dose, and phosphorus was added to the semiconductor layer through the gate insulating film. The conditions were an acceleration voltage of 80 kV, a set dose of 6 × 10 ¹³ atoms / cm ³ , and an addition amount of 1 × 10
¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ . (FIG. 9A)

Next, the semiconductor layer 10 of the P-channel type TFT is formed.
9 is added with B (boron) which is a group 13 element. After the N-channel TFT is covered with the resist mask 140, B is added to the semiconductor layer 109. Diborane diluted to 5% with hydrogen is used as a doping gas to form regions 141 and 142 to be P ⁺ -type source and drain regions. (FIG. 9 (B))

After the regions to be the source region and the drain region are formed, the resist mask 140 is removed, and heat treatment is performed at 350 ° C. to 550 ° C., here 450 ° C., for 2 hours in an electric furnace. By this heat treatment, phosphorus and boron added to the source and drain regions 121, 122, 141, and 142 and the low-concentration impurity regions 124 and 125 are activated.

Next, an interlayer insulating film 1 made of a silicon oxide film
Form 50. After forming a contact hole in the interlayer insulating film 150, a laminated film made of titanium / aluminum / titanium is formed as an electrode material, and patterned to form a wiring 15.
1 to 153 are formed. Here, an N-channel TFT and a P-channel TFT are connected by a wiring 153 to form a CMOS circuit. Further, an extraction wiring for a gate wiring connected to the gate electrode 111 (not shown) is also formed. Finally, a hydrogenation process is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to perform a hydrogen termination process on the entire TFT. (FIG. 9 (C))

[Embodiment 2] This embodiment will be described with reference to FIG. This embodiment is an example in which the GOLD structure is formed by modifying the first embodiment. The GOLD structure of this embodiment may be applied to the first embodiment.

The process is performed in the same manner as in Example 1 until an island-shaped semiconductor region in which the crystallization promoting element is reduced is formed. Next, as a gate insulating film, a 20-nm-thick silicon nitride film / 100
A silicon nitride oxide film 210 having a thickness of nm is formed.

Next, a gate electrode and a low concentration impurity region are formed. A first conductive film 215 and a second conductive layer 216 are formed over the surface of the silicon nitride oxide film 210.
The first conductive film 215 may be formed of a material selected from Ti, Ta, W, and Mo, or a material made of an alloy thereof. In addition, a conductive material containing the above material as a main component may be used in consideration of electric resistance and heat resistance. The thickness of the first conductive film needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, a Ti film having a thickness of 50 nm was formed by a sputtering method.

For the second conductive layer 216, it is preferable to use a material selected from Al and Cu. This is provided to reduce the electric resistance of the gate electrode.
４００400 nm, preferably 100-200 nm. When Al is used, pure Al may be used, or an element selected from Ti, Si, and Sc may be 0.1 to 5%.
An Al alloy with atom% added may be used. In the case of using copper, although not shown, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 210.

Here, an Al film containing 0.5 atom% of Sc was formed to a thickness of 200 nm by sputtering.
(FIG. 10A) Then, a step of forming a resist mask 314 in a region where a P-channel TFT is to be formed and adding a first impurity element imparting N-type was performed. The impurity element that imparts N-type to the crystalline semiconductor material includes phosphorus (P),
Although arsenic (As), antimony (Sb), and the like are known, here, phosphorus was used and ion doping was performed using phosphine (PH ₃ ). In this step, the accelerating voltage is 80 keV in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 210 and the first conductive film 215.
And set it higher. The concentration of phosphorus added to the semiconductor layer is preferably in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ , and here is set to 1 × 10 ¹⁸ atoms / cm ³ . Then, a region 31 in which phosphorus is added to the semiconductor layer at a low concentration.
5, 316 were formed. (Fig. 10 (B))

After the resist mask 314 was removed, a third conductive film (not shown) was formed in close contact with the first conductive film 215 and the second conductive layer 216. The third conductive film may be formed of a material selected from Ti, Ta, W, and Mo, but may be a compound containing the above material as a main component in consideration of electric resistance and heat resistance. For example, the thickness of the third conductive film is 10 to 100 nm, preferably 20 to 50 nm.
nm. Here, a thickness of 50 nm and T
The film a was formed by a sputtering method. Then, the first conductive film and the third conductive film are simultaneously patterned to form the first conductive layer 217 and the third conductive layer 21 having the same length in the channel length direction.
8 was formed. (FIG. 10C) Next, B (boron), which is a Group 13 element, is added to the semiconductor layer 209 of the P-channel TFT. N-channel type TFT
Is covered with a resist mask 240, and B is added to the semiconductor layer 209. P ⁺ type source and drain regions 241 and 242 are formed by using diborane diluted to 5% with hydrogen as a doping gas. (FIG. 10 (D))

After forming the source region and the drain region, the resist mask 240 is removed, and the resist mask 240 is removed in an electric furnace.
Heat treatment at 0 ° C. for 2 hours. The source region and the drain region 211,
212, 241, 242 and low concentration impurity region 31
The phosphorus and boron added to 5,316 are activated.

Next, an interlayer insulating film 2 made of a silicon oxide film
56 is formed. After forming a contact hole in the interlayer insulating film 256, a laminated film made of titanium / aluminum / titanium is formed as an electrode material, and patterned to form a wiring 25.
1 to 253 are formed. Here, an N-channel TFT and a P-channel TFT are connected by a wiring 253 to form a CMOS circuit. Further, a lead wire for the gate wire 111 (not shown) is also formed. Finally, a hydrogenation treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to obtain TF
A hydrogen termination process is performed on the entire T. (FIG. 10E)

[Embodiment 3] This embodiment will be described with reference to FIG. In the present embodiment, the gate electrode is formed after the activation step, and a decrease in reliability due to poor heat resistance of the gate electrode can be further prevented than in the first and second embodiments. This embodiment may be applied to the first embodiment or the second embodiment.

The procedure is the same as in Example 1 up to the addition of the Group 15 element. By performing heat treatment in this state, the N ⁺ type region 31 is formed.
Region 32 where phosphorus was not added to 1, 312 and 313
3,333 nickel can be absorbed,
In this embodiment, after adding B (boron), which is a Group 13 element, to a region to be a P-channel TFT, a step of removing a crystallization promoting element is performed.

Therefore, after the N-channel TFT is covered with the resist mask 340, B is added to the semiconductor film to be the P-channel TFT. Diborane diluted to 5% with hydrogen is used as a doping gas to form P ⁺ -type source and drain regions 341 and 342 and a region 343 to be a channel formation region. (FIG. 11B)

In order to cause the P-channel source and drain regions 341 and 342 to absorb the crystallization promoting element, the concentration of boron ions should be about 1.3 to 2 times the concentration of phosphorus ions added to the regions. .

After adding impurities to the source region and the drain region, heat treatment is performed at 500 ° C. for 2 hours in an electric furnace. As a result of this heat treatment, Ni intentionally added for crystallization of the amorphous silicon film is removed, as schematically shown by arrows in FIG.
3 to the respective source and drain regions 321,
Move to 322, 341 and 342. As a result, Ni in the gettering regions 323 and 343 decreases, while
The Ni concentration in the source and drain regions 321, 322, 341, and 342 used for the gettering sink is higher than in the gettering regions 323 and 343. (Figure 1
1 (C))

Further, simultaneously with gettering by this heat treatment, the source and drain regions 321, 322, and 34 are obtained.
The phosphorus and boron added to 1,342 are activated. Next, SiH ₄ and N ₂ O are formed by plasma CVD.
Is used as a source gas, and the silicon nitride oxide film 310 is
A film is formed to a thickness of nm. Next, the silicon nitride oxide film 31
After covering the P-channel TFT on 0 with a resist mask or a mask insulating film 350 and forming a resist mask or a mask insulating film 351 on a channel formation region of the N-channel TFT, phosphorus is added as a Group 15 element. The concentration of phosphorus added to the semiconductor layer is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atom
s / cm ³ , preferably 1 × 10 ¹⁸
atoms / cm ³ . Thus, low-concentration impurity regions 355 and 356 of the N-channel TFT are formed. (FIG. 11
(D))

Thereafter, it is preferable to perform heat treatment at 450 ° C. for 2 hours in an electric furnace. By this heat treatment, the source and drain regions 321, 322, 341, 34
2 and the phosphorus and boron added to the low concentration impurity regions 355 and 356 are activated.

Next, a conductive film for forming the gate wiring 360 is formed. Here, three layers of tantalum nitride (TaN _x ) / tantalum (Ta) / tantalum nitride (TaN _x ) were formed by a sputtering method. The thickness of the TaN _x film is 50 nm, and the thickness of the Ta film is 250 nm. Then, the three-layer film is patterned to form a gate wiring 360. In this embodiment, the N-channel TFT has a GOLD structure,
The P-channel TFT has a structure without a low concentration impurity region. (FIG. 11E)

Next, an interlayer insulating film 3 made of a silicon oxide film
70 is formed. After forming a contact hole in the interlayer insulating film 370, a laminated film made of titanium / aluminum / titanium is formed as an electrode material, and patterned to form a wiring 37.
1 to 373 are formed. Here, an N-channel TFT and a P-channel TFT are connected by a wiring 373 to form a CMOS circuit. Further, an extraction wiring for the gate wiring 360 (not shown) is also formed. Finally, a hydrogenation treatment is performed at 350 ° C. for about 2 hours in a hydrogen atmosphere to obtain TF
A hydrogen termination process is performed on the entire T. (FIG. 11 (F))

[Embodiment 4] In this embodiment, the TFT described in Embodiment 1 is applied to an active matrix substrate. The active matrix substrate of this embodiment is used for a flat-type electro-optical device such as a liquid crystal display device and an EL display device. This embodiment may be applied to the second embodiment or the third embodiment.

This embodiment will be described with reference to FIGS. 12 to 14, the same reference numerals indicate the same components. FIG. 12 is a schematic perspective view of the active matrix substrate of this embodiment. The active matrix substrate includes a pixel portion 401, a scan line driver circuit 402, and a signal line driver circuit 403 formed over a glass substrate 400. The scanning line driving circuit 402 and the signal line driving circuit 403 are connected to the pixel portion 401 by a scanning line 502 and a signal line 503, respectively, and these driving circuits 402 and 403 are mainly configured by CMOS circuits.

The scanning lines 502 are formed for each row of the pixel portion 401, and the signal lines 503 are formed for each column. Near the intersection of the scanning line 502 and the signal line 503, each wiring 50
The pixel TFT 406 connected to 2,503 is formed. A pixel electrode 407 and a storage capacitor 408 are connected to the pixel TFT 406.

First, according to the manufacturing process of the TFT of the first embodiment, the N-channel TFTs of the driving circuits 402 and 403
The channel type TFT and the pixel TFT 406 of the pixel portion 401 are completed.

FIG. 13A is a top view of the pixel portion 401, and is a top view of substantially one pixel. FIG. 13B is a top view of a CMOS circuit included in the driver circuits 402 and 403. FIG. 14 is a cross-sectional view of the active matrix substrate, which is a cross-sectional view of the pixel portion 401 and the CMOS circuit. A cross-sectional view of the pixel portion 401 is a cross-sectional view taken along a chain line AA ′ in FIG. 13A, and a cross-sectional view of the CMOS circuit is FIG.
FIG. 7 is a cross-sectional view taken along a chain line BB ′ of FIG.

The pixel TFT 406 of the pixel portion 401 is an N-channel TFT. The semiconductor layer 501 has a “U” shape (horse-shoe shape). A scan line 502 as a first-layer wiring crosses the semiconductor layer 501 with the gate insulating film 510 interposed therebetween.

The semiconductor layer 501 includes N ⁺ -type regions 511 to 511.
513, two channel formation regions 514 and 515, and low-concentration impurity regions (N ⁻ -type regions) 516 to 519 are formed. The N ⁺ -type regions 511 and 512 are a source region and a drain region.

On the other hand, in a CMOS circuit, one gate wiring 601 crosses two semiconductor layers 602 and 603 with a gate insulating film 610 interposed therebetween. In the semiconductor layer 602,
Source region and drain region (N ⁺ type region) 611, 6
12, a channel formation region 613, a low concentration impurity region (N
^- type region) 614 and 615 are formed. In the semiconductor layer 603, source and drain regions (P ⁺ -type regions) 621 and 622 and a channel formation region 623 are formed.

After forming the source region and the drain region in the semiconductor layers 501, 602, and 603, an interlayer insulating film 430 is formed on the entire surface of the substrate. On the interlayer insulating film 430, the second
As the wiring / electrode of the layer, the signal line 503, the drain electrode 504, the source electrodes 631, 632, the drain electrode 63
3 is formed.

The scanning lines 502 and the signal lines 503 are orthogonal to each other with the interlayer insulating film 430 interposed therebetween as shown in FIG. The drain electrode 504 is an extraction electrode for connecting the drain region 512 to the pixel electrode 505, and is a lower electrode of the storage capacitor 408. In order to increase the capacity of the storage capacitor 408, the drain electrode 504 is made as wide as possible as long as the opening is not reduced.

A first flattening film 440 is formed on the second layer wiring / electrode. In this embodiment, a stacked film of silicon nitride (50 nm) / silicon oxide (25 nm) / acryl (1 μm) is used as the first planarization film 440. Acrylic, polyimide, benzocyclobutene (B
Since the organic resin film such as CB) is a solution-coated insulating film that can be formed by a spin coating method, a film thickness of about 1 μm can be formed with high throughput, and a good flat surface can be obtained. Furthermore, since the organic resin film has a lower dielectric constant than silicon nitride or silicon oxide, the parasitic capacitance can be reduced.

Next, source wirings 641 and 642, a drain wiring 643, and a black mask 520 made of a light-shielding conductive film such as titanium or chromium are formed as third-layer wirings on the first planarization film 440. Have been. As shown in FIG. 13A, the black mask 520 is integrated in the pixel portion 401 and overlaps with the periphery of the pixel electrode 505,
It is formed so as to cover all portions that do not contribute to display. Note that the black mask 520 is arranged as shown by a dotted line in FIG. Black mask 52
The potential of 0 is fixed to a predetermined value.

These third-layer wirings 641, 642, 6
Prior to the formation of 43, 520, the first planarization film 440
Is etched to form a recess 530 on the drain electrode 504 leaving only the lowermost silicon nitride film.

In the recess 530, the drain electrode 504 and the black mask 520 face each other with only the silicon nitride film interposed therebetween.
4. A storage capacitor 408 is formed using the black mask 520 as an electrode and a silicon nitride film as a dielectric. Silicon nitride has a high relative dielectric constant, and a larger capacitance can be ensured by reducing the film thickness.

A second flattening film 450 is formed on the third-layer wirings 641, 642, and 520. The second flattening film 450 is formed of 1.5 μm thick acrylic. The portion where the storage capacitor 408 is formed has a large step,
Such a step can be sufficiently flattened.

A contact hole is formed in the first planarization film 440 and the second planarization film 450, and a pixel electrode 505 made of a transparent conductive film such as ITO or tin oxide is formed.
Thus, an active matrix substrate is completed.

When the active matrix substrate of this embodiment is used for a liquid crystal display device, an alignment film (not shown) is formed to cover the entire surface of the substrate. Rubbing treatment is applied to the alignment film if necessary

When a conductive film having high reflectance, typically aluminum or a material containing aluminum as a main component, is used for the pixel electrode 505, an active matrix substrate for a reflective AMLCD can be manufactured.

Although the pixel TFT 406 has a double gate structure in this embodiment, it may have a single gate structure or a multi-gate structure such as a triple gate structure. In addition, the inverted staggered TF shown in Embodiment 1
It can also be formed of T. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. Since the feature of the present invention lies in the configuration of the gate wiring,
Other configurations may be determined by the practitioner as appropriate.

Embodiment 5 In this embodiment, as an example of an electro-optical device using the active substrate shown in Embodiment 4, an active matrix type liquid crystal display device (AML)
A description will be given of an example in which a CD is described.

FIG. 15 shows the appearance of the AMLCD of this embodiment. In FIG. 15A, the same reference numerals as those in FIG. 12 indicate the same components. The active matrix substrate includes a pixel portion 401 formed over a glass substrate 400, a scanning line driving circuit 4,
02, a signal line driver circuit 403.

Active matrix substrate and counter substrate 70
0 is pasted. Liquid crystal is sealed in the gap between these substrates. Note that external terminals are formed in the active matrix substrate in a manufacturing process of the TFT, and a portion where the external terminals are formed does not face the counter substrate 700. An FPC (flexible print circuit) 710 is connected to the external terminal, and an external signal and power are transmitted to the circuits 401 to 403 via the FPC 710.

The opposing substrate 700 has an I
A transparent conductive film such as a TO film is formed. The transparent conductive film is a counter electrode to the pixel electrode of the pixel portion 401, and the liquid crystal material is driven by an electric field formed between the pixel electrode and the counter electrode. Further, an alignment film and a color filter are formed on the counter substrate 700 if necessary.

On the active matrix substrate of this embodiment, IC chips 711 and 712 are attached using the surface on which the FPC 710 is attached. These IC chips are configured by forming circuits such as a video signal processing circuit, a timing pulse generating circuit, a gamma correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate. In FIG. 15A, two IC chips are attached, but may be one, or three or more.

Alternatively, the configuration shown in FIG. 15B is also possible. In FIG. 15B, the same components as those in FIG. 15A are denoted by the same reference numerals. Here, FIG. 15A illustrates an example in which signal processing performed by an IC chip is performed by a logic circuit 720 formed using TFTs over the same substrate. In this case, the logic circuit 720 is also the driving circuit 4
It is configured on the basis of a CMOS circuit as in the case of 02 and 403.

In this embodiment, a configuration in which a black mask is provided on an active matrix substrate (BMon TFT) is employed. In addition, a configuration in which a black mask is provided on the opposite side may be employed.

A color display may be performed using a color filter, or a liquid crystal may be driven in an ECB (electric field control birefringence) mode, a GH (guest host) mode, or the like.
It is good also as composition not using a color filter. Also,
As described in JP-A-8-15686, a configuration using a microlens array may be adopted.

[Embodiment 6] The TFTs described in Embodiments 1, 2, and 3 can be applied to various other electro-optical devices and semiconductor circuits other than AMLCD.

As an electro-optical device other than AMLCD, E
Examples include an L (electroluminescence) display device and an image sensor.

As the semiconductor circuit, an arithmetic processing circuit such as a microprocessor constituted by an IC chip, and a high-frequency module (MMIC) for handling input / output signals of a portable device are used.
Etc.).

As described above, the present invention can be applied to all semiconductor devices functioning with circuits constituted by insulating gate type TFTs.

[Embodiment 7] In the above-mentioned liquid crystal display device of the present invention, various liquid crystals other than the nematic liquid crystal can be used. For example, 1998, SID, “Characteristics a
nd Driving Scheme of Polymer-Stabilized Monostable
FLCD Exhibiting Fast Response Time and High Contr
ast Ratio with Gray-Scale Capability ”by H. Furue
et al., 1997, SID DIGEST, 841, “A Full-Color T
hresholdless AntiferroelectricLCD Exhibiting Wide
Viewing Angle with Fast Response Time ”by T. Yosh
ida et al., 1996, J. Mater. Chem. 6 (4), 671-673,
"Thresholdless antiferroelectricity in liquid cry
stals and its application to displays "by S. Inui
et al., and the liquid crystal disclosed in US Pat. No. 5,594,569 can be used.

Ferroelectric liquid crystal (FLC) showing isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 16 shows the electro-optical characteristics of a monostable FLC in which a cholesteric phase-chiral smectic C phase transition is performed while applying a DC voltage, and the cone edge is made substantially coincident with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 16 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 16 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For the fV-shaped switching mode, see Terada et al.
Half-V switching mode FLCD ", 46th
Proceedings of the JSCE Lecture Meeting, March 1999
Tsuki, p. 1316, and Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol.
See page 0 for details.

As shown in FIG. 16, it can be seen that the use of such a ferroelectric mixed liquid crystal enables low-voltage driving and gradation display. A ferroelectric liquid crystal having such electro-optical characteristics can be used in the liquid crystal display device of the present invention.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

Since low-voltage driving is realized by using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low power consumption is realized.

[Embodiment 8] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 17A is a top view of an EL display device using the present invention. 17A, reference numeral 4010 denotes a substrate;
4011 is a pixel portion, 4012 is a source side driver circuit, 40
Reference numeral 13 denotes a gate-side drive circuit, and each drive circuit reaches an FPC 4017 via wirings 4014 to 4016.
Connected to an external device.

At this time, the cover member 600 is formed so as to surround at least the pixel portion, preferably the driving circuit and the pixel portion.
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 17B shows a cross-sectional structure of the EL display device of this embodiment, in which a TFT for a driving circuit (here, an n-channel type TF) is formed on a substrate 4010 and a base film 4021.
1 illustrates a CMOS circuit combining a T and a p-channel TFT. ) 4022 and TFT 4023 for pixel portion
(However, here, only the TFT for controlling the current to the EL element is shown). These TFTs
A known structure (a top gate structure or a bottom gate structure) may be used.

The present invention relates to a TFT 4022 for a driving circuit,
It can be used for the pixel portion TF4023.

The TFT 402 for a driving circuit is manufactured by using the present invention.
2. When the pixel portion TFT 4023 is completed, the pixel portion TFT is formed on an interlayer insulating film (flattening film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the FT 4023 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

[0189] In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, the cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 4030 is
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region indicated by 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Furthermore, a sealing material is provided inside the cover member 7000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0196] A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Fiber)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

[Embodiment 9] In this embodiment, an example in which an EL display device having a mode different from that of Embodiment 8 is manufactured using the present invention will be described with reference to FIGS. 18A and 18B. FIG.
Elements having the same numbers as 7A and 17B indicate the same parts, and thus description thereof will be omitted.

FIG. 18A is a top view of the EL display device of this embodiment, and FIG. 18A is a cross-sectional view taken along the line AA ′ of FIG.
B.

According to Embodiment 8, a passivation film 6003 is formed to cover the surface of the EL element.

Further, the filling material 6 is covered so as to cover the EL element.
004 is provided. This filler 6004 is used for the cover material 60.
It also functions as an adhesive for bonding 00. As the filler 6004, PVC (polyvinyl chloride),
Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0205] A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or mylar films.

However, depending on the light emitting direction (light emitting direction) from the EL element, the cover material 6000 needs to have a light transmitting property.

[0209] Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of the sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

[Embodiment 10] The present invention can be applied to an EL display panel having the structure as in Embodiments 8 and 9. Here, a more detailed sectional structure of the pixel portion is shown in FIG. 19, an upper surface structure is shown in FIG. 20A, and a circuit diagram is shown in FIG.
Shown in In FIGS. 19, 20A and 20B, a common reference numeral is used, so that they may be referred to each other.

In FIG. 19, a switching TFT 3502 provided on a substrate 3501 is formed by using an NTFT according to the present invention. In FIG. 19, the configuration is the same as that of the NTFT of the second embodiment. However, the configuration of the first or third embodiment may be adopted. In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. Further, it may be formed using the PTFT of the present invention.

The current controlling TFT 3503 is formed using NTFT using the present invention. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. The wiring indicated by 38 is the gate electrodes 39a and 39b of the switching TFT 3502.
Are electrically connected to each other.

At this time, it is very important that the current control TFT 3503 has the structure of this embodiment. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current controlling TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

In this embodiment, the current controlling TFT 35 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 20A, the wiring which becomes the gate electrode 37 of the current controlling TFT 3503 is 3504
In the region indicated by, it overlaps with the drain wiring 40 of the current controlling TFT 3503 via an insulating film. At this time, 350
A capacitor is formed in a region indicated by reference numeral 4. This capacitor 3504 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is a current supply line (power supply line) 3
506, and a constant voltage is always applied.

The first passivation film 4 is formed on the switching TFT 3502 and the current control TFT 3503.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, light emission failure may occur due to the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
503 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.

Note that there are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As specific light-emitting layers, cyanopolyphenylenevinylene is used for a red light-emitting layer, polyphenylenevinylene is used for a green light-emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light-emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
The EL layer has a laminated structure in which a hole injection layer 46 made of (polythiophene) or PAni (polyaniline) is provided. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, the formation is possible after forming a light-emitting layer or a hole-injection layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 3
505 is completed. Note that the EL element 3505 mentioned here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore,
The utilization efficiency of light emission is very high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of this embodiment has a pixel portion composed of pixels having a structure as shown in FIG. 19, a switching TFT having a sufficiently low off-state current value, and a current control resistant to hot carrier injection. TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

The structure of this embodiment can be implemented by freely combining with the structures of Embodiments 1 to 3. In addition, the display unit of the electronic device according to the seventh embodiment has
It is effective to use a display panel.

[Embodiment 11] In this embodiment, the tenth embodiment will be described.
A structure in which the structure of the EL element 3505 is inverted in the pixel portion shown in FIG. FIG. 21 is used for the description. The structure of FIG. 19 differs from that of FIG. 19 only in the EL element and the current controlling TFT.

In FIG. 21, a current controlling TFT 350
3 is formed using the PTFT of the present invention. In FIG. 21, the configuration is the same as that of the PTFT of the second embodiment. However, the configuration of the first or third embodiment may be adopted.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, the banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed as indicated by the arrow.

The structure of this embodiment can be implemented by freely combining with the structures of Embodiments 1 to 3.
In addition, the display unit of the electronic device of the seventh embodiment serves as the display unit of the present embodiment.
It is effective to use the L display panel.

[Embodiment 12] In this embodiment, FIGS. 22A to 22C show examples in which a pixel having a structure different from that of the circuit diagram shown in FIG. 20B is used. In this embodiment, 3
801 is a source wiring of the switching TFT 3802,
Reference numeral 3803 denotes a gate wiring of a switching TFT 3802, 3804 denotes a current control TFT, 3805 denotes a capacitor, 3806, 3808 denotes a current supply line, and 3807 denotes an EL.
Element.

FIG. 22A shows current supply line 3 between two pixels.
This is an example in the case where 806 is common. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 22B shows an example in which the current supply line 3808 is provided in parallel with the gate wiring 3803. 22B, the current supply line 3808 and the gate wiring 38
03 is provided so as not to overlap,
If the wirings are formed in different layers, they can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

In FIG. 22C, similarly to the structure of FIG. 22B, a current supply line 3808 is provided in parallel with the gate wiring 3803, and two pixels are formed so as to be line-symmetric with respect to the current supply line 3808. There is a feature in the point. It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of this embodiment is similar to those of Embodiments 1 to 3,
It can be implemented in any combination with the configuration of 8 or 9. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 7.

[Embodiment 13] FIG. 20 shown in Embodiment 10
In A and 20B, the capacitor 3504 is provided to hold the voltage applied to the gate of the current controlling TFT 3503, but the capacitor 3504 may be omitted. In the case of Embodiment 10, the current controlling TFT 3
Since an NTFT having the same configuration as that of the second embodiment is used as the reference numeral 503, an LDD region provided so as to overlap the gate electrode via the gate insulating film is provided. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

In addition, FIGS.
Similarly, in the structure of C, the capacitor 3805 can be omitted.

The structure of this embodiment is similar to those of Embodiments 1 to 3,
The present invention can be implemented by freely combining with the configurations of 8 to 12. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 7.

[Embodiment 14] A CMOS circuit and a pixel portion formed by carrying out the present invention can be applied to various display devices (an active matrix type liquid crystal display device, an active matrix type EL display device, an active matrix type EC display). Device). That is, the invention of the present application can be applied to all electronic devices in which these display devices are incorporated in the display unit.

Such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 23, 24 and 25.

FIG. 23A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.

FIG. 23B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102 and other signal control circuits.

FIG. 23C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.

FIG. 23D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302 and other signal control circuits.

FIG. 23E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 23F shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.

FIG. 24A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 24B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 24C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 24A and 24B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 24D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 24D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 24, a case where a transmissive display device is used is shown, and examples of application to a reflective display device and an EL display device are not shown.

FIG. 25A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal control circuits.

FIG. 25B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 25C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. In addition, the electronic apparatus according to the present embodiment includes the first to sixth and eighth to
The present invention can be realized by using any combination of the thirteen combinations.

[0261]

According to the present invention, when a semiconductor film is crystallized by using a crystallization promoting element or a technique for improving crystallinity is used, a gettering region is provided in contact with a gettering region. The element removal step can be shortened, and the crystallization promoting element removal step can be performed efficiently. Further, since the process temperature of the crystallization accelerating element removing step can be performed at a temperature lower than 600 ° C., it is sufficiently possible to use a glass substrate.

[Brief description of the drawings]

FIG. 1 is a schematic view of removing a crystallization promoting element.

FIG. 2 is a schematic view of conventional removal of a crystallization promoting element.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of Embodiment 1.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of Embodiment 2.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of Embodiment 3.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of Embodiment 4.

FIG. 7 is a plan view of the CMOS circuit according to the first embodiment.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of the TFT of Example 1.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of the TFT of Example 1.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of the TFT of Example 2.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of the TFT of Example 3.

FIG. 12 is a perspective view of an active matrix substrate according to a fourth embodiment.

FIG. 13 is a top view of a pixel portion and a CMOS circuit.

FIG. 14 is a cross-sectional view of an active matrix substrate.

FIG. 15 is an external perspective view of a liquid crystal display device according to a fifth embodiment.

FIG. 16 is a diagram showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.

FIG. 17 is a top view and a cross-sectional view of an EL display device according to an eighth embodiment.

FIG. 18 is a top view and a cross-sectional view of an EL display device according to a ninth embodiment.

FIG. 19 is a sectional view of an EL display device according to a tenth embodiment.

FIG. 20 is a top view and a circuit diagram of an EL display device according to a tenth embodiment.

FIG. 21 is a sectional view of an EL display device according to an eleventh embodiment.

FIG. 22 is a circuit diagram of an EL display device according to a twelfth embodiment.

FIG. 23 is a configuration diagram of an electronic apparatus according to a fourteenth embodiment.

FIG. 24 is a configuration diagram of an electronic apparatus according to a fourteenth embodiment.

FIG. 25 is a configuration diagram of an electronic apparatus according to a fourteenth embodiment.

[Explanation of symbols]

 Reference Signs List 100 substrate 102 amorphous silicon film 104 Ni film 106 crystalline silicon film 108, 109 semiconductor layer

Claims (13)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: a step A of forming a semiconductor film; a step B of introducing an element that promotes crystallization into the semiconductor film; and a step of introducing the element that promotes crystallization. Thereafter, a step C of crystallizing the semiconductor film, a step D of selectively adding a group 15 element to the crystallized semiconductor film, and a step of heat-treating the semiconductor film after adding the group 15 element E, and a step F of patterning the semiconductor film to form an island-shaped semiconductor layer, wherein the patterning is performed such that the region to which the group 15 element is added becomes a source region and a drain region, and A method for manufacturing a semiconductor device, which is performed so that a region to which the Group 15 element is not added becomes a channel formation region or a channel formation region and a low-concentration impurity region. 2. A method for manufacturing a semiconductor device, comprising: a step A of forming a semiconductor film; a step B of introducing an element that promotes crystallization into the semiconductor film; and a step of introducing the element that promotes crystallization. Thereafter, a step C of crystallizing the semiconductor film, a step D of selectively adding a group 15 element to the crystallized semiconductor film, and a step of heat-treating the semiconductor film after adding the group 15 element E, a step F of patterning the semiconductor film to form an island-like semiconductor layer, a step G of forming a gate insulating film in contact with the island-like semiconductor layer, and a step 15 of the island-like semiconductor layer. Step H of forming a gate electrode on the non-added region via the gate insulating film
And a method for manufacturing a semiconductor device. 3. A method for manufacturing a semiconductor device, comprising: a step A of forming a semiconductor film; a step B of introducing an element that promotes crystallization into the semiconductor film; and a step of introducing the element that promotes crystallization. Then, a step C of crystallizing the semiconductor film, and a region including a region serving as a source region and a region serving as a drain region of the crystallized semiconductor film, and a region forming a channel formation region or a low concentration impurity Step D of adding a Group 15 element to a region not including a region to be a region
A step E of gettering the crystallization-promoting element in a region to which the group 15 element is added, a step F of patterning the semiconductor film to form an island-like semiconductor layer, Step G of contacting and forming a gate insulating film
And a step H of forming a gate electrode over a region of the island-shaped semiconductor layer to be the channel formation region with the gate insulating film interposed therebetween. 4. A method for manufacturing a semiconductor device, comprising: a step A of forming a semiconductor film; a step B of introducing an element that promotes crystallization to the semiconductor film; and a step of introducing the element that promotes crystallization. Thereafter, a step C of crystallizing the semiconductor film, a step D of selectively adding a Group 15 element to the crystallized semiconductor film, and a heat treatment of the semiconductor film after the addition of the Group 15 element A step E, a step F of patterning the semiconductor film to form an island-shaped semiconductor layer, a step G of forming a gate insulating film in contact with the island-shaped semiconductor layer, and a group 15 element of the island-shaped semiconductor layer A step H of forming a gate electrode on a part of the region where no is added via the gate insulating film, and a step I of adding an impurity element using the gate electrode as a mask. A method for manufacturing a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 1, wherein a group 13 element is added in addition to the group 15 element in the step D according to claim 1. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor film is heated to 450 to 650 ° C. in the step C according to claim 1. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor film is heated to 500 to 850 ° C. in the step E according to claim 1. 8. The semiconductor device according to claim 1, wherein in the step A, the semiconductor film is an amorphous silicon film formed by a low-pressure CVD method. Production method. 9. The process B according to claim 1, wherein N is used as the element for promoting crystallization.
i, Fe, Co, Ru, Rh, Pd, Os, Ir, P
A method for manufacturing a semiconductor device, comprising using one or more kinds of elements selected from t, Cu, Au, and Ge. 10. An active matrix display device manufactured by using the manufacturing method according to claim 1. 11. An electronic apparatus comprising the active matrix display device according to claim 10. 12. An EL display device manufactured by using the manufacturing method according to claim 1. 13. An electronic apparatus comprising the EL display device according to claim 12.