JP2005167056A - Thin film transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid OFF current failure caused by segregation of nickel as a crystallization catalyst element in a thin film transistor. <P>SOLUTION: An outer edge part of a gate electrode is spaced at least about 0.5 μm apart from a source-drain region or the like wherein phosphorus as a gettering element is implanted for preventing segregation of nickel in an area near an outer edge part of the gate electrode. This is realized by controlling the position of phosphorus implantation and by reducing right and left sizes of the gate electrode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a thin film transistor (TFT) having a non-single-crystal crystalline silicon film, and particularly when a crystallization catalyst element (Ni or the like) is used as a catalyst when crystallizing a silicon film. The present invention relates to a manufacturing method in which such an element is removed by gettering to improve the performance of the manufactured transistor.

  Recently, research has been conducted on an insulated gate semiconductor device having a thin-film active layer (also referred to as an active region) on an insulating substrate. In particular, thin-film insulated gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. Thin film transistors are classified as amorphous silicon thin film transistors and crystalline silicon thin film transistors depending on the material and crystal state of the semiconductor used. However, even though crystalline silicon is a non-single crystal that is not a single crystal. Therefore, these are collectively called non-single crystal silicon thin film transistors.

  In thin film transistors, many applications of thin film transistors such as active matrix LCDs require that the data retention time be sufficiently long. The current needs to be minimized. One cause of the OFF current is electric field concentration. Such electric field concentration can be considerably reduced by adopting an LDD structure in which a relatively lightly doped region (LDD region) is provided between the gate and the drain.

  In such a transistor, an amorphous silicon film is usually formed on a glass substrate, and the amorphous silicon is crystallized by heat treatment (thermal annealing) and / or laser irradiation (photo annealing) to form a crystalline silicon film. However, crystallization is promoted by adding a crystallization catalyst element such as Ni. However, in order to obtain a desired effect, it is necessary to add at a certain high concentration. If a crystallization catalyst element such as Ni remains in the silicon film at such a concentration, an electric field is produced in the manufactured transistor. Although the mobility is large, the OFF current tends to be excessively high. In particular, when a large number of the semiconductor devices are formed on the same substrate, there is a problem that not only the OFF current is high, but also the value of the OFF current greatly varies between the semiconductor devices. Such problems are especially fatal defects in TFTs constituting the pixel portion of the liquid crystal display.

Therefore, the source / drain regions are doped with a gettering material such as phosphorus, and by performing thermal annealing and / or optical annealing, the source / drain regions are activated, and at the same time, a solid solution of the gettering material and the catalytic element is formed, It is known that the adverse effects of residual catalyst elements can be eliminated. However, in practice, gettering may be insufficient and an expected result may not be obtained. This is due to the segregation of Ni at the junction (drain end) of the LDD and the channel, which again causes the OFF current failure. In liquid crystal displays, multiple gates such as double gates are connected in series so that they do not become defective unless segregation occurs at the drain end of one of the gates. I can't say that.
JP-A-8-330602

  In view of such problems of the prior art, the main object of the present invention is to add a catalytic element such as nickel that promotes crystallization to an amorphous silicon film formed on a substrate having an insulating surface, and to perform thermal annealing. In a method for manufacturing a thin film transistor having an LDD structure in which a crystalline silicon film is obtained by light annealing, gettering such as phosphorus is performed so that the performance of the manufactured thin film transistor is not impaired by the residual catalyst element. An object of the present invention is to provide a manufacturing method capable of suitably gettering nickel using a material.

  A second object of the present invention is to provide a method for manufacturing a thin film transistor having an LDD structure suitable for realizing stable off-current characteristics.

  A third object of the present invention is to provide a method of manufacturing a thin film transistor having an LDD structure suitable for a liquid crystal display with few pixels.

  According to the present invention, such an object is a method of manufacturing a thin film transistor using a non-single crystalline crystalline silicon film formed on a substrate having an insulating surface, wherein the amorphous silicon film is formed on the substrate. A process of forming a crystalline silicon film on the substrate by adding a catalyst element for promoting crystallization to the amorphous silicon film and crystallizing the amorphous silicon film by thermal annealing and / or optical annealing A process of forming the crystalline silicon film into an island region, a process of forming an insulating film on the island region crystalline silicon film, a process of forming a gate electrode on the insulating film, and the island shape In the region of the crystalline silicon film, phosphorus is doped into a region set to be separated slightly outward from the region immediately below the gate electrode. A process of forming a drain region, a process of performing thermal annealing and / or optical annealing on the island-shaped region crystalline silicon film, and performing gettering of the catalytic element using the phosphorus, and the gettering process And a process of forming an LDD region by relatively lightly doping the outer peripheral region of the gate electrode of the island-shaped region crystalline silicon film after performing Is achieved.

  As a result, segregation of the catalytic element in the vicinity of the gate / drain / junction can be avoided, and OFF current failure can be effectively avoided. Further, by performing relatively mild thermal annealing and / or optical annealing on the region including the LDD region again, the impurities in the LDD region can be activated. In addition to the above, avoiding segregation of the catalytic element directly below and in the vicinity of the gate electrode can be achieved by reducing the lateral dimension of the gate electrode prior to or subsequent to gettering of the catalytic element. Can also be achieved.

In the thin film transistor manufactured by such a method, for example, when nickel is used as the catalyst element, the nickel concentration is 2 × over a range of at least about 0.5 μm from the position directly below the outer edge of the gate electrode to the drain side. It is preferable to set it to 10 ¹⁷ / cm ³ or less. In that case, an LDD region is provided between the gate and the drain, and the LDD region extends over a range of at least about 0.5 μm from a position immediately below the outer edge of the gate electrode, or immediately below the outer edge of the gate electrode. It extends from the position at least about 0.5 μm away from the position toward the drain side.

  In the case of a double gate type thin film transistor, an extended portion is provided between two gate electrodes, and after doping with phosphorus, the catalyst element is gettered to reduce the concentration of the catalyst element over the entire channel region. The same effect can be achieved also by making it.

  Hereinafter, embodiments of the present invention will be described in detail based on specific examples shown in the accompanying drawings.

There are nickel, iron, cobalt, platinum, etc. as catalyst elements that promote the crystallization of the amorphous silicon film. In this example, a transistor in the process of fabrication was formed on a crystalline silicon film into which nickel was introduced as the catalyst element. Improve the crystallinity of the silicon film by implanting ions containing phosphorus in the source / drain regions by a known ion doping method (also called plasma doping method) and then thermal annealing or optical annealing (or both). A method for obtaining an N-type semiconductor device having high characteristics by activating impurities will be described. Hereinafter, a high-performance semiconductor device refers to a device having an OFF current of about 1.0 × 10 ⁻¹² A or less and a small variation in characteristics between elements. FIG. 1 shows a manufacturing process of the thin film transistor of this embodiment.

  First, a base silicon oxide film 101 is provided on a glass substrate 100, and an amorphous silicon film is continuously formed thereon by a plasma CVD method. A nickel acetate aqueous solution is applied to the silicon surface, and a nickel acetate layer (not shown) is formed by spin coating. It is better to add a surfactant to the nickel acetate aqueous solution. Then, the amorphous silicon film is crystallized by thermal annealing at 550 ° C. for 4 hours to obtain a crystalline silicon film. At this time, nickel plays a role of crystal nucleus, and crystallization of the amorphous silicon film is promoted. In order to further improve the crystallinity of the crystalline silicon film thus obtained, the film is irradiated with an excimer laser which is a high-power pulse laser at 200 ° C. The fact that crystallization can be performed at a relatively low temperature and in a short time is due to the action of nickel.

  Next, the crystalline silicon film is etched into an island shape to form a plurality of island-like silicon regions 102. Further, a silicon oxide film 103 is deposited as a gate insulating film by plasma CVD. Subsequently, an aluminum film (containing 0.1-2% silicon) is deposited by sputtering to form the gate electrode 104 (FIG. 1a). The above process is the same as the conventional process.

  A resist film 105 is applied on the gate electrode 104 so as to extend with a predetermined width from the outer periphery thereof (FIG. 1b). Next, phosphorus ions are doped into the island-like silicon region 102 toward the portion where the source / drain regions are to be formed by ion doping using the gate electrode 104 and the resist film 105 as a mask (FIG. 1c). Then, in order to activate the doped phosphorus and cause the phosphorus to getter nickel, thermal annealing is performed, and optical annealing is performed using a KrF excimer laser (FIG. 1d). In this step, both thermal annealing and optical annealing are performed, but only one of them may be performed.

  By such gettering, not only the source / drain regions 106 and 107 but also the nickel in the channel region 108 moves to the doped region and is absorbed by the doped phosphorus. In particular, the position immediately below the outer edge of the gate electrode 104 is the channel region 108 that is hardly doped, so that nickel does not segregate in that portion. As will be described later, according to the knowledge of the present inventor, if a local defect such as segregated nickel is present immediately below the outer edge of the gate electrode 104, the OFF current of the manufactured thin film transistor becomes high, In this embodiment, even if segregated nickel occurs, it occurs at the drain side end of the channel region away from the position directly below the outer edge of the gate electrode 104, and is associated with the OFF current. The problem can be avoided.

  Further, the resist film 105 is removed in advance (before or after gettering), and relatively light phosphorus ions are implanted using the gate electrode 104 as a mask to activate the doped phosphorus, and immediately below the gate electrode 104. LDD (Lightly Doped Drain) regions 109 and 110 extending from the source region to the source / drain region are formed (FIG. 1e). At this time, activation by thermal annealing and / or optical annealing may be performed under conditions that can avoid further gettering by lightly doped phosphorus. Alternatively, the LDD region may be activated as desired.

  Next, although not shown, a silicon oxide film is formed as an interlayer insulator by a plasma CVD method, and a contact hole is formed in this. Then, a multilayer film of a metal material, for example, titanium and aluminum is formed and patterned to form TFT source and drain electrodes / wirings. Finally, thermal annealing is performed at 200 to 350 ° C. in a hydrogen atmosphere at 1 atm. For the basic manufacturing process of the thin film transistor, see Patent Document 1 and the like.

In the thin film transistor manufactured in this way, the nickel concentration in the channel region 108 and the LDD regions 109 and 110 is lower than the nickel concentration in the source / drain regions 106 and 107, and in particular, the OFF current is reduced. In order to achieve the intended purpose of making uniform, it is desirable that it is 2 × 10 ¹⁷ / cm ³ or less. Further, as will be described later, the distance from the position immediately below the outer edge of the gate electrode 104 to the source / drain regions 106 and 107 is about 0.5 μm or more, that is, from the position immediately below the outer edge of the gate electrode 104 to the drain. Desirably, the nickel concentration is 2 × 10 ¹⁷ / cm ³ or less over a range of at least about 0.5 μm toward the side. If desired, the concentration of phosphorus in the LDD region can be made higher in the source / drain region than in the channel region side. Thereby, even if additional heat treatment is performed, a structure in which back diffusion is difficult, that is, nickel hardly moves to the channel side can be obtained.

  FIG. 2 shows a second embodiment of a method of manufacturing a thin film transistor according to the present invention. Portions corresponding to the above embodiment are given the same numbers, and detailed descriptions thereof are omitted. Similar to the above embodiment, the crystalline silicon film 102 is formed in an island shape, the silicon oxide film 103 is deposited as a gate insulating film by plasma CVD, and an aluminum film (0.1-2% silicon is deposited by sputtering). A gate electrode 104 is formed (FIG. 2a). The island-like silicon region 102 is doped with phosphorus ions toward the portion where the source / drain regions are to be formed by ion doping using the gate electrode 104 as a mask (FIG. 2b). Then, in order to activate the doped phosphorus and to cause the phosphorus to getter nickel, thermal annealing is performed, and optical annealing is performed using a KrF excimer laser (FIG. 2c). In this step, both thermal annealing and optical annealing are performed, but only one of them may be performed.

  Next, as indicated by the arrow 111 in FIG. 2d, the gate electrode 104 is isotropically etched to reduce it by about 0.5 μm. Further, a relatively light phosphorus ion is implanted using the narrowed gate electrode 104 as a mask, and the doped phosphorus is activated, so that an LDD (Lightly Doped Drain) region extending from directly under the gate electrode 104 to the source / drain region. 109 and 110 are formed (FIG. 2e). At this time, activation by thermal annealing and / or optical annealing may be performed under conditions that can avoid further gettering by lightly doped phosphorus. Alternatively, the LDD region may be activated as desired.

  Also in this case, even if segregated nickel is generated, it occurs in the vicinity of the position immediately below the outer edge of the gate electrode 104 before thinning, that is, in the portion between the source / drain regions 106 and 107 and the LDD regions 109 and 110. Since it occurs at the drain side end of the channel region away from the position directly below the outer edge of the final gate electrode 104 after thinning, problems associated with the OFF current can be avoided.

Even in the thin film transistor manufactured in this way, the nickel concentration in the channel region 108 is lower than the nickel concentration in the LDD regions 109 and 110 and the source / drain regions 106 and 107, and the OFF current is made small and uniform. In order to achieve the intended purpose of performing, it is desirable that it is 2 × 10 ¹⁷ / cm ³ or less. As will be described later, the distance from the position immediately below the outer edge of the gate electrode 104 to the LDD region 110 is about 0.5 μm or more, that is, at least about from the position immediately below the outer edge of the gate electrode 104 to the drain side. It is desirable that the nickel concentration is 2 × 10 ¹⁷ / cm ³ or less over a range of 0.5 μm.

  As a modified example of this embodiment, gettering may be performed after the gate electrode 104 is thinned.

  FIG. 3 shows a third embodiment of a method of manufacturing a thin film transistor according to the present invention. Portions corresponding to the above embodiment are given the same numbers, and detailed descriptions thereof are omitted. In the present embodiment, as shown in FIG. 3a, the processes until the island-shaped silicon region 102, the silicon oxide film 103 as the gate insulating film and the gate electrode 104 are formed are the same as those in the embodiment shown in FIG. However, the hard mask 112 of the gate electrode 104 is left as it is. Phosphorus ions are doped into the island-like silicon region 102 by ion doping using the hard mask 112 and the gate electrode 104 as masks (FIG. 3b). Then, in order to activate the doped phosphorus and make the phosphorus getter nickel, thermal annealing is performed, and optical annealing is performed using a KrF excimer laser (FIG. 3c). In this step, both thermal annealing and optical annealing are performed, but only one of them may be performed.

  Next, instead of isotropically etching the gate electrode 104, the gate electrode 104 is narrowed by about 0.5 μm as shown by the arrow 113 while leaving the hard mask 112 of the gate electrode 104 (FIG. 3d). ). Next, the hard mask 112 is removed. Further, a relatively light phosphorus ion is implanted using the narrowed gate electrode 104 as a mask, and the doped phosphorus is activated, so that an LDD (Lightly Doped Drain) region extending from directly under the gate electrode 104 to the source / drain region. 109 and 110 are formed (FIG. 3e). At this time, activation by thermal annealing and / or optical annealing may be performed under conditions that can avoid further gettering by lightly doped phosphorus. Alternatively, the LDD region may be activated as desired.

  According to this embodiment, since the gate electrode 104 is etched only in the left-right direction and the thickness thereof is not reduced, it is possible to reliably avoid a situation in which the gate electrode 104 is excessively thinned to hinder its function. There are benefits that can be done. The thin film transistor obtained by this example is the same as that obtained by the example of FIG. As a modified example of this embodiment, gettering may be performed after the gate electrode 104 is thinned.

  FIG. 4 shows a fourth embodiment of a method of manufacturing a thin film transistor according to the present invention. Portions corresponding to the above embodiment are given the same numbers, and detailed descriptions thereof are omitted. In this embodiment, as shown in FIG. 4a, the processes until the island-shaped silicon region 102, the silicon oxide film 103 as the gate insulating film, and the gate electrode 104 are formed are the same as those in the embodiment shown in FIG. However, in this embodiment, the gate electrode has a hat-shaped two-layer structure including a relatively long lower gate electrode 104a and upper gate electrode 104b. For example, the lower gate electrode 104a may extend about 0.5 μm outward from the upper gate electrode 104b at each end. The lower gate electrode 104a and the upper gate electrode 104b may be made of the same material or different materials.

  In this state, by ion doping, phosphorous is formed on the island-like silicon region 102 toward the portion where the source / drain regions are to be formed using the lower gate electrode 104a and the upper gate electrode 104b having a hat-shaped two-layer structure as a mask. Ions are doped (FIG. 4b). Then, in order to activate the doped phosphorus and make the phosphorus getter nickel, thermal annealing is performed, and optical annealing is performed using a KrF excimer laser (FIG. 4c). In this step, both thermal annealing and optical annealing are performed, but only one of them may be performed.

  Next, the lower gate electrode 104a is thinned by about 0.5 μm and etched so as to have the same shape as the upper gate electrode 104b (FIG. 4d). If the lower gate electrode 104a and the upper gate electrode 104b are made of different materials, this etching process can be suitably performed by appropriately selecting an etchant and using the upper gate electrode 104b as a mask.

  Furthermore, a relatively light phosphorus ion is implanted using the gate electrode 104 (lower layer gate electrode 104a and upper layer gate electrode 104b), which is substantially the same shape and thinned as a whole, as a mask to activate the doped phosphorus, LDD (Lightly Doped Drain) regions 109 and 110 extending from directly under the gate electrode 104 to the source / drain regions are formed (FIG. 4e). At this time, activation by thermal annealing and / or optical annealing may be performed under conditions that can avoid further gettering by lightly doped phosphorus. Alternatively, the LDD region may be activated as desired.

  Also in this case, even if segregated nickel is generated, it occurs in the vicinity of the position immediately below the outer edge of the gate electrode 104 before thinning, that is, in the portion between the source / drain regions 106 and 107 and the LDD regions 109 and 110. Since it occurs at the drain side end of the channel region away from the position directly below the outer edge of the final gate electrode 104 after thinning, problems associated with the OFF current can be avoided. In addition, since the gate electrode 104 is etched only in the left-right direction and the thickness of the gate electrode 104 is not reduced, there is an advantage that the gate electrode 104 is excessively thinned and can reliably avoid a situation that impedes its function. . The thin film transistor obtained by this example is the same as that obtained by the example of FIG. As a modified example of this embodiment, gettering may be performed after the gate electrode 104 is thinned.

Even in the thin film transistor manufactured in this way, the nickel concentration in the channel region 108 is lower than the nickel concentration in the LDD regions 109 and 110 and the source / drain regions 106 and 107, and the OFF current is made small and uniform. In order to achieve the intended purpose of performing, it is desirable that it is 2 × 10 ¹⁷ / cm ³ or less. As will be described later, the distance from the position immediately below the outer edge of the gate electrode 104 to the LDD region 110 is about 0.5 μm or more, that is, at least about from the position immediately below the outer edge of the gate electrode 104 to the drain side. It is desirable that the nickel concentration is 2 × 10 ¹⁷ / cm ³ or less over a range of 0.5 μm.

  FIG. 5 shows a fifth embodiment of a method of manufacturing a thin film transistor according to the present invention. Portions corresponding to the above embodiment are given the same numbers, and detailed descriptions thereof are omitted. In this embodiment, a base silicon oxide film 101 is provided on a glass substrate 100, and a plurality of island-like silicon regions 102 and a silicon film 103 as a gate insulating film are deposited. Subsequently, an aluminum film (containing 0.1 to 2% silicon) is deposited to form the gate electrode 104. Further, the source / drain regions 106 and 107 and the LDD regions 109 and 110 are formed using the gate electrode 104 or a resist film (not shown) (FIG. 5a). The above process can be carried out as described herein above or using conventional techniques.

  Next, thermal annealing is performed to activate the doped phosphorus to form the source / drain regions 106 and 107 and the LDD regions 109 and 110, and to cause the phosphorus to getter nickel, and a KrF excimer laser is used. Is used to perform optical annealing (FIG. 5b). In this step, both thermal annealing and optical annealing are performed, but only one of them may be performed. By such gettering, nickel in the channel region 108 moves to the doped regions (source / drain regions 106 and 107 and LDD regions 109 and 110) and is absorbed by the doped phosphorus.

  Next, as indicated by the arrow 111 in FIG. 5c, the gate electrode 104 is isotropically etched to reduce it by about 0.5 μm.

  Even in this case, even if nickel segregation occurs, it occurs in the LDD regions 109 and 110, and the position immediately below the outer edge of the gate electrode 104 is the channel region 102 which is hardly doped. The segregation of nickel does not occur in the portion, and the problems associated with the OFF current can be avoided.

  In addition, after thinning the gate electrode 104 as desired, by using the gate electrode 104 as a mask, at least the periphery of the gate electrode 104 is phosphorous doped, thereby adding additional LDD regions 119, as shown in FIG. 120 may be provided. Further, additional annealing can be performed as necessary.

  FIG. 6 shows a sixth embodiment of a method of manufacturing a thin film transistor according to the present invention. Portions corresponding to the above embodiment are given the same numbers, and detailed descriptions thereof are omitted. In this embodiment, a base silicon oxide film 101 is provided on a glass substrate 100, and a plurality of island-like silicon regions 102 and a silicon film 103 as a gate insulating film are deposited. Subsequently, an aluminum film (containing 0.1 to 2% silicon) is deposited to form the gate electrode 104. Further, the source / drain regions 106 and 107 and the LDD regions 109 and 110 are formed using the gate electrode 104 or a resist film (not shown) (FIG. 6A). The above process may be the same as the embodiment shown in FIG. However, the hard mask 112 of the gate electrode 104 is left.

  Next, thermal annealing is performed to activate the doped phosphorus to form the source / drain regions 106 and 107 and the LDD regions 109 and 110, and to cause the phosphorus to getter nickel, and a KrF excimer laser is used. Is used to perform optical annealing (FIG. 6b). In this step, both thermal annealing and optical annealing are performed, but only one of them may be performed. By such gettering, nickel in the channel region 108 moves to the doped regions (source / drain regions 106 and 107 and LDD regions 109 and 110) and is absorbed by the doped phosphorus.

  Next, instead of isotropically etching the gate electrode 104, the gate electrode 104 is thinned by about 0.5 μm as shown by the arrow 113 while leaving the hard mask 112 of the gate electrode 104 (FIG. 6c). ). According to this embodiment, since the gate electrode 104 is etched only in the left-right direction and the thickness thereof is not reduced, it is possible to reliably avoid a situation in which the gate electrode 104 is excessively thinned to hinder its function. There are benefits that can be done.

  Even in this case, even if nickel segregation occurs, it occurs in the LDD regions 109 and 110, and the position immediately below the outer edge of the gate electrode 104 is the channel region 102 which is hardly doped. The segregation of nickel does not occur in the portion, and the problems associated with the OFF current can be avoided.

  Further, after thinning the gate electrode 104 as desired, at least the periphery of the gate electrode 104 is phosphorus-doped using the gate electrode 104 as a mask, thereby adding additional LDD regions 119, as shown in FIG. 120 may be provided. Further, additional annealing can be performed as necessary.

  FIG. 7 shows a seventh embodiment of a method for manufacturing a thin film transistor according to the present invention. Portions corresponding to the above embodiment are given the same numbers, and detailed descriptions thereof are omitted. In this embodiment, a base silicon oxide film 101 is provided on a glass substrate 100, and a plurality of island-like silicon regions 102 and a silicon film 103 as a gate insulating film are deposited. Subsequently, an aluminum film (containing 0.1 to 2% silicon) is deposited to form the gate electrode 104. Further, the source / drain regions 106 and 107 and the LDD regions 109 and 110 are formed using the gate electrode 104 or a resist film (not shown) (FIG. 7a). The above process may be the same as the embodiment shown in FIG. However, the gate electrode 104 includes a lower gate electrode 104a and an upper gate electrode 104b having a hat-shaped two-layer structure.

  Next, thermal annealing is performed to activate the doped phosphorus to form the source / drain regions 106 and 107 and the LDD regions 109 and 110, and to cause the phosphorus to getter nickel, and a KrF excimer laser is used. Is used to perform optical annealing (FIG. 7b). In this step, both thermal annealing and optical annealing are performed, but only one of them may be performed. By such gettering, nickel in the channel region 108 moves to the doped regions (source / drain regions 106 and 107 and LDD regions 109 and 110) and is absorbed by the doped phosphorus.

  Next, the lower gate electrode 104a is thinned by about 0.5 μm and etched to have the same shape as the upper gate electrode 104b (FIG. 7c). Also in this embodiment, since the gate electrode 104 is etched only in the left-right direction and the thickness thereof is not reduced, the situation that the gate electrode 104 is excessively thinned and its function is hindered is surely avoided. There are benefits to get.

  Even in this case, even if nickel segregation occurs, it occurs in the LDD regions 109 and 110, and the position immediately below the outer edge of the gate electrode 104 is the channel region 102 which is hardly doped. The segregation of nickel does not occur in the portion, and the problems associated with the OFF current can be avoided.

  Further, after thinning the gate electrode 104 as desired, at least the periphery of the gate electrode 104 is phosphorus-doped using the gate electrode 104 as a mask, thereby adding additional LDD regions 119, as shown in FIG. 120 may be provided. Further, additional annealing can be performed as necessary.

  FIGS. 8a and 8b show plan views of single-gate and double-gate thin film transistors, respectively, but the above embodiments are equally applicable to both single-gate and double-gate thin film transistors. In the case of a double-gate thin film transistor, two gate electrodes 104c and 104d, two pairs of LDD regions 109a, 109b, 110a, and 110b and a channel region between the gate electrodes are provided in the channel region.

  Further, in the double gate type thin film transistor shown in FIG. 8c, an additional source / drain region 115 is formed in a region between two gates. The additional source / drain regions 115 originally extend in a direction perpendicular to the channel region. Further, as shown in FIG. 8c, it is preferable that the extended end is further widened so that the area thereof is relatively large. In this embodiment as well, thermal annealing is performed to activate the doped phosphorus and form the LDD and drain regions and to cause the phosphorus to getter nickel, and a KrF excimer laser as desired. In this case, gettering is performed in the additional source / drain regions 115 in the same manner as in the original source / drain regions 106 and 107, and in the adjacent channel region. Therefore, the nickel concentration in the vicinity of the edges of both gate electrodes 104 can be avoided.

Also in this embodiment, in order to achieve the intended purpose as described above, the nickel concentration is within a range of about 0.5 μm from the position immediately below the outer edge of the gate electrodes 104c and 104d. It is desirable that it is 2 × 10 ¹⁷ / cm ³ or less.

  As shown in FIG. 9, with the edge of the gate electrode 104 as a reference, the drain side is a positive direction and the channel region side is a negative direction, and local defects are provided at different positions every 0.1 μm, The change of the OFF current of the manufactured thin film transistor was verified. FIG. 10 shows the phosphorus concentration distribution in this thin film transistor. It is shown that the phosphorus concentration increases in the order of the channel region, the LDD region, and the source / drain region. FIG. 11 shows the magnitude of the OFF current with respect to the gate voltage when there is no local defect. The OFF current is small and has a constant value regardless of the gate voltage. As shown in FIG. 12 and FIG. 13, when there is a local defect on the channel region side (that is, when the position of the local defect is +0.1 μm or less), in the region of relatively low gate voltage, It has been found that the OFF current is relatively high. When the local defect is in the vicinity of the drain side end of the gate electrode 104 (that is, the position of the local defect is in the range of +0.1 μm to +0.4 μm), the OFF current is not affected regardless of the gate voltage. Overall big. When the local defect is relatively in the portion that has entered the drain region (that is, when the position of the local defect is +0.5 μm or more), it is OFF within the normal operating range of the thin film transistor. It has been found that the current is generally kept small.

Process drawing which shows the main processes of 1st Example of the manufacturing method of the thin-film transistor based on this invention which consists of a, b, c, d, and e. Process drawing which shows the main processes of 2nd Example of the manufacturing method of the thin-film transistor which consists of a, b, c, d, and e based on this invention. Process drawing which shows the main processes of 3rd Example of the manufacturing method of the thin-film transistor based on this invention which consists of a, b, c, d, and e. Process drawing which shows the main processes of 4th Example of the manufacturing method of the thin-film transistor based on this invention which consists of a, b, c, d, and e. Process drawing which shows the main processes of 5th Example of the manufacturing method of the thin-film transistor based on this invention which consists of a, b, c, d. Process drawing which shows the main processes of 6th Example of the manufacturing method of the thin-film transistor which consists of a, b, c, and d based on this invention. Process drawing which shows the main processes of 7th Example of the manufacturing method of the thin-film transistor which consists of a, b, c, and d based on this invention. a and b are schematic plan views showing single-gate and double-gate thin film transistors to which the thin film transistor manufacturing method according to the present invention shown in FIGS. These are typical top views which show 8th Example of the manufacturing method of the thin-film transistor based on this invention. The schematic diagram which shows the coordinate set between the drain region and the channel region on the basis of the edge part of a gate electrode. The graph showing the concentration distribution of phosphorus. The graph which shows the magnitude | size of OFF electric current with respect to gate voltage when there is no local defect. The graph which shows the magnitude | size of the OFF electric current with respect to a gate voltage when a local defect exists in the channel area | region side. The graph which shows the magnitude | size of OFF current with respect to gate voltage when a local defect exists in the drain region side.

Explanation of symbols

100 Glass substrate 101 Underlying silicon oxide film 102 Insular silicon region 103 Silicon oxide film 104 Gate electrode 105 Resist film 106, 107 Source / drain region 108 Channel region 109, 110 LDD region 111, 113 Arrow 112 Hard mask 115 Additional source Drain regions 119, 120 Additional LDD regions

Claims (22)

A method of manufacturing a thin film transistor using a non-single crystalline crystalline silicon film formed on a substrate having an insulating surface,
Forming an amorphous silicon film on the substrate;
A process of forming a crystalline silicon film on the substrate by adding a catalyst element for promoting crystallization to the amorphous silicon film and crystallizing the amorphous silicon film by thermal annealing and / or optical annealing;
Forming the crystalline silicon film into an island region;
Forming an insulating film on the island-shaped region crystalline silicon film;
Forming a gate electrode on the insulating film;
Forming a source / drain region by doping phosphorus into a region set to be slightly separated from a region directly below the gate electrode in the island-shaped region crystalline silicon film;
A process of performing thermal annealing and / or optical annealing on the island-shaped region crystalline silicon film, and performing gettering of the catalytic element using the phosphorus;
A step of forming an LDD region by relatively lightly doping an outer peripheral region of the gate electrode of the island-shaped region crystalline silicon film after performing the gettering step. Production method. The source / drain regions are formed by doping phosphorus in a region set at a distance of at least 0.5 μm from a region immediately below the gate electrode in the island-shaped region crystalline silicon film. The manufacturing method according to claim 1. The manufacturing method according to claim 1, wherein the catalytic element contains nickel. The process of forming the source / drain region in a region set so as to be separated slightly outward from the region immediately below the gate electrode,
Applying a resist film on the gate electrode so as to extend with a predetermined width from the outer periphery thereof;
Doping phosphorus ions toward the portion where the source / drain regions are to be formed using the gate electrode and the resist film as a mask;
The method according to claim 1, further comprising a step of removing the resist film. The process of forming the source / drain region in a region set so as to be separated slightly outward from the region immediately below the gate electrode,
The gate electrode is formed to have a width larger than the final width, and the gate electrode is used as a mask to dope phosphorus ions toward the portion where the source / drain regions are to be formed;
The method according to claim 1, further comprising: adjusting the width to a final width by isotropically etching the gate electrode. The process of forming the source / drain region in a region set so as to be separated slightly outward from the region immediately below the gate electrode,
With the hard mask for forming the gate electrode remaining, the gate electrode is formed to have a width larger than the final width, and the source electrode Doping phosphorus ions toward the portion where the drain region is to be formed;
Etching the gate electrode to adjust its width to a final width;
The method according to claim 1, further comprising: removing the hard mask. The process of forming the source / drain region in a region set so as to be separated slightly outward from the region immediately below the gate electrode,
The gate electrode has a lower layer gate electrode and an upper layer gate electrode on the lower layer gate electrode, the dimension of which is reduced in the horizontal direction relative to the lower layer gate electrode, and the source / drain using the gate electrode as a mask Doping phosphorus ions toward the part where the region is to be formed;
2. The manufacturing method according to claim 1, further comprising: adjusting a width to a final width by etching a portion of the lower gate electrode protruding from the upper gate electrode. 3. 8. The manufacturing method according to claim 5, wherein the width of the gate electrode is adjusted to a final width after performing the gettering process. The manufacturing method according to claim 5, wherein the width of the gate electrode is adjusted to a final width before the gettering process is performed. The manufacturing method according to claim 1, further comprising performing a relatively mild thermal annealing on the region including the LDD region again. A method of manufacturing a thin film transistor using a non-single crystalline crystalline silicon film formed on a substrate having an insulating surface,
Forming an amorphous silicon film on the substrate;
A process of forming a crystalline silicon film on the substrate by adding a catalyst element for promoting crystallization to the amorphous silicon film and crystallizing the amorphous silicon film by thermal annealing and / or optical annealing;
Forming the crystalline silicon film into an island region;
Forming an insulating film on the island-shaped region crystalline silicon film;
Forming a gate electrode on the insulating film;
Forming a source / drain region by doping phosphorus into a region set to be slightly separated from a region directly below the gate electrode in the island-shaped region crystalline silicon film;
Forming an LDD region by relatively lightly doping an outer peripheral region of the gate electrode of the island-shaped region crystalline silicon film;
A process of performing thermal annealing and / or optical annealing on the island-shaped region crystalline silicon film, and performing gettering of the catalytic element using the phosphorus;
And a process of reducing the horizontal dimension of the gate electrode. The method further includes a step of forming an additional LDD region by relatively lightly doping the outer peripheral region of the gate electrode having a reduced size in the island-shaped region crystalline silicon film. The manufacturing method according to claim 11. The method according to claim 11, further comprising performing a relatively mild thermal annealing on the region including the additional LDD region again. 12. The manufacturing method according to claim 11, wherein the process of reducing the horizontal dimension of the gate electrode is performed by isotropic etching. 12. The manufacturing method according to claim 11, wherein the process of reducing the horizontal dimension of the gate electrode is performed by etching the gate electrode with the hard mask for forming the gate electrode left. . The process of reducing the lateral dimension of the gate electrode includes the gate electrode having a lower gate electrode and an upper gate electrode on the lower gate electrode, the lateral dimension of which is reduced relative to the lower gate electrode. The method according to claim 11, wherein a portion of the lower gate electrode that protrudes from the upper gate electrode is removed by etching. 14. The thin film transistor of claim 13, wherein the process of reducing the horizontal dimension of the gate electrode is performed such that an outer edge of the gate electrode is separated from the corresponding LDD region by at least about 0.5 [mu] m. A method of manufacturing a double-gate thin film transistor using a non-single crystalline crystalline silicon film formed on a substrate having an insulating surface,
Forming an amorphous silicon film on the substrate;
A process of forming a crystalline silicon film on the substrate by adding nickel to the amorphous silicon film as a catalyst element for promoting crystallization, and crystallizing the amorphous silicon film by thermal annealing and / or optical annealing; ,
The crystalline silicon film is made into an island-like region, each having a portion where a source / drain region is to be formed, a channel region set between these portions, and a portion extending in the width direction from an intermediate portion of the channel region. And the process of
Forming an insulating film on at least the channel region;
Forming at least two gate electrodes on the insulating film so as to sandwich the extended portion;
A source / drain region and an additional source / drain region are formed by doping phosphorus in the portion where the source / drain region is to be formed and the extension portion, respectively, and a region immediately below and around the gate electrode. Forming an LDD region by relatively lightly doping the layer;
And a step of performing thermal annealing and / or optical annealing on the island-shaped region crystalline silicon film, and performing gettering of the nickel using the phosphorus. A non-single crystalline crystalline silicon film formed on a substrate having an insulating surface is used as an island-shaped region, and a source / drain region, a channel region set between both regions, and an insulating film on the channel region are interposed. A thin film transistor having a gate disposed thereon,
The nickel concentration in the source / drain region is 2 × 10 ¹⁷ / cm ³ or more, and the nickel concentration is 2 × 10 ¹⁷ over a range of at least about 0.5 μm from the position immediately below the outer edge of the gate electrode to the drain side. A thin film transistor characterized by having a / cm ³ or less. The LDD region is provided between the gate and the drain, and the LDD region extends over a range of at least about 0.5 μm from a position immediately below the outer edge of the gate electrode. Thin film transistor. An LDD region is provided between the gate and the drain. The LDD region includes a first LDD region having a relatively high phosphorus concentration provided on the drain side and a relatively phosphorus concentration provided on the gate side. The thin film transistor according to claim 19, further comprising a low second LDD region. A non-single crystalline crystalline silicon film formed on a substrate having an insulating surface is used as an island-shaped region, and a source / drain region, a channel region set between both regions, and an insulating film on the channel region are interposed. A double-gate thin film transistor having at least two gate electrodes arranged in series,
A thin film transistor, wherein an extension portion doped with phosphorus is provided between two adjacent gate electrodes.

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