JPH04362616A - Active matrix panel - Google Patents
Active matrix panelInfo
- Publication number
- JPH04362616A JPH04362616A JP3165185A JP16518591A JPH04362616A JP H04362616 A JPH04362616 A JP H04362616A JP 3165185 A JP3165185 A JP 3165185A JP 16518591 A JP16518591 A JP 16518591A JP H04362616 A JPH04362616 A JP H04362616A
- Authority
- JP
- Japan
- Prior art keywords
- active matrix
- film
- base
- tft
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 title claims abstract description 60
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 39
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 34
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 33
- 229920005591 polysilicon Polymers 0.000 abstract description 33
- 239000010408 film Substances 0.000 description 94
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は駆動回路部を備えたア
クティブマトリクスパネルに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix panel equipped with a drive circuit section.
【０００２】0002
【従来の技術】例えばアクティブマトリクス型の液晶デ
ィスプレイ装置には、ガラス等からなる透明基板上にア
クティブマトリクス部用ＴＦＴ（薄膜トランジスタ）の
ほかに駆動回路部用ＴＦＴを形成してなるアクティブマ
トリクスパネルを備えたものがある。図８は従来のこの
ようなアクティブマトリクスパネルの回路構成の一例を
示したものである。このアクティブマトリクスパネルで
は、行方向に走査電極１が列方向に表示電極２がそれぞ
れ設けられ、走査電極１と表示電極２との各交点に対応
する各画素（液晶）３ごとにアクティブマトリクス部用
ＴＦＴ４が設けられ、走査電極１の一端部にゲート駆動
回路部用ＴＦＴ５が設けられ、１本おきの表示電極２の
一端部および残りの表示電極２の他端部にデータ駆動回
路部用ＴＦＴ６、７がそれぞれ設けられ、そしてアクテ
ィブマトリクス部用ＴＦＴ４がオンになると、画素３の
静電容量部に表示データが電荷の形で書き込まれ、アク
ティブマトリクス部用ＴＦＴ４がオフになると、書き込
まれた電荷により画素３が駆動されるようになっている
。ところで、アクティブマトリクス部用ＴＦＴ４および
駆動回路部用ＴＦＴ５〜７は、半導体層を構成するポリ
シリコンの下地として酸化シリコンが設けられている。[Prior Art] For example, an active matrix type liquid crystal display device includes an active matrix panel in which TFTs (thin film transistors) for the active matrix section and TFTs for the drive circuit section are formed on a transparent substrate made of glass or the like. There is something. FIG. 8 shows an example of the circuit configuration of such a conventional active matrix panel. In this active matrix panel, scanning electrodes 1 are provided in the row direction and display electrodes 2 are provided in the column direction, and each pixel (liquid crystal) 3 corresponding to each intersection of the scanning electrode 1 and the display electrode 2 is provided with an active matrix portion. A TFT 4 is provided, a TFT 5 for a gate drive circuit section is provided at one end of the scanning electrode 1, and a TFT 6 for a data drive circuit section is provided at one end of every other display electrode 2 and the other end of the remaining display electrodes 2. When the TFT 4 for the active matrix section is turned on, display data is written in the form of charges in the capacitance section of the pixel 3, and when the TFT 4 for the active matrix section is turned off, the written charge causes the display data to be written in the form of charges. Pixel 3 is now driven. Incidentally, the active matrix portion TFT 4 and the drive circuit portion TFTs 5 to 7 are provided with silicon oxide as a base for polysilicon forming the semiconductor layer.
【０００３】0003
【発明が解決しようとする課題】しかるに、従来のこの
ようなアクティブマトリクスパネルでは、アクティブマ
トリクス部用ＴＦＴ４と駆動回路部用ＴＦＴ５〜７とで
要求される特性に違いがあり、駆動回路部用ＴＦＴ５〜
７の場合、移動度を高めるためにオン電流を十分高くし
なければならないが、カットオフ電流についてはアクテ
ィブマトリクス部用ＴＦＴ４ほど低くする必要はなく、
一方、アクティブマトリクス部用ＴＦＴ４の場合、リー
ク電流を小さくするためにカットオフ電流を十分低くし
なければならないが、オン電流については駆動回路部用
ＴＦＴ５〜７ほど高くする必要はない。しかしながら、
ＴＦＴの半導体層がポリシリコンでその下地が酸化シリ
コンであると、駆動回路部用ＴＦＴ５〜７のオン電流を
十分に高くすることができるが、アクティブマトリクス
部用ＴＦＴ４のカットオフ電流を十分に低くすることが
できず、このため表示品質が低下するという問題があっ
た。この発明の目的は、駆動回路部用ＴＦＴのオン電流
を低下させることなく、アクティブマトリクス部用ＴＦ
Ｔのカットオフ電流を十分に低くすることのできるアク
ティブマトリクスパネルを提供することにある。However, in such a conventional active matrix panel, there are differences in required characteristics between the TFT 4 for the active matrix section and the TFTs 5 to 7 for the drive circuit section. ~
In the case of 7, the on-current must be sufficiently high to increase the mobility, but the cut-off current does not need to be as low as the active matrix TFT 4.
On the other hand, in the case of the TFT 4 for the active matrix section, the cutoff current must be made sufficiently low to reduce leakage current, but the on-current does not need to be as high as the TFTs 5 to 7 for the drive circuit section. however,
If the semiconductor layer of the TFT is polysilicon and its base is silicon oxide, the on-current of TFTs 5 to 7 for the drive circuit section can be made sufficiently high, but the cut-off current of TFT 4 for the active matrix section can be made sufficiently low. Therefore, there was a problem that the display quality deteriorated. An object of the present invention is to provide a TFT for an active matrix section without reducing the on-current of the TFT for a drive circuit section.
An object of the present invention is to provide an active matrix panel in which the cutoff current of T can be made sufficiently low.
【０００４】0004
【課題を解決するための手段】この発明は、ＴＦＴのオ
ン電流およびカットオフ電流が共に下地が酸化シリコン
の場合よりも窒化シリコンの場合の方が低くなることに
着目し、アクティブマトリクス部用ＴＦＴの下地を窒化
シリコン膜とし、且つ駆動回路部用ＴＦＴの下地を酸化
シリコン膜としたものである。[Means for Solving the Problems] The present invention focuses on the fact that both the on-current and cut-off current of a TFT are lower when the base is made of silicon nitride than when the base is silicon oxide. The base of the TFT is a silicon nitride film, and the base of the TFT for the drive circuit portion is a silicon oxide film.
【０００５】[0005]
【作用】この発明によれば、アクティブマトリクス部用
ＴＦＴの下地を窒化シリコン膜としているので、アクテ
ィブマトリクス部用ＴＦＴのカットオフ電流を下地が酸
化シリコン膜の場合と比較して十分に低くすることがで
き、しかも駆動回路部用ＴＦＴの下地を酸化シリコン膜
としているので、駆動回路部用ＴＦＴのオン電流が低下
しないようにすることができる。[Operation] According to the present invention, since the base of the TFT for the active matrix section is a silicon nitride film, the cutoff current of the TFT for the active matrix section can be made sufficiently lower than when the base is a silicon oxide film. Moreover, since the base of the TFT for the drive circuit section is a silicon oxide film, it is possible to prevent the on-state current of the TFT for the drive circuit section from decreasing.
【０００６】[0006]
【実施例】図１〜図６はそれぞれこの発明の一実施例に
おけるアクティブマトリクスパネルの各製造工程を示し
たものである。そこで、これらの図を順に参照しながら
、アクティブマトリクスパネルの構造についてその製造
方法と併せ説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 6 each show the manufacturing process of an active matrix panel according to an embodiment of the present invention. Therefore, referring to these figures in order, the structure of the active matrix panel will be explained along with its manufacturing method.
【０００７】まず、図１に示すように、ガラス等からな
る透明基板１１の上面にスパッタリング装置を用いて下
地用酸化シリコン膜１２を１０００Å程度の厚さに形成
する。次に、下地用酸化シリコン膜１２の上面にプラズ
マＣＶＤ法により下地用窒化シリコン膜１３を１０００
Å程度の厚さに形成する。First, as shown in FIG. 1, a base silicon oxide film 12 is formed to a thickness of about 1000 Å on the upper surface of a transparent substrate 11 made of glass or the like using a sputtering device. Next, on the upper surface of the silicon oxide film 12 for the base, a silicon nitride film 13 for the base is formed with a thickness of 1000 nm by plasma CVD.
It is formed to a thickness of about 100 Å.
【０００８】次に、図２に示すように、フォトリソグラ
フィ技術により、アクティブマトリクス部用ＴＦＴ形成
領域に対応する部分以外の不要な部分の下地用窒化シリ
コン膜１３をエッチングして除去する。次に、全表面に
プラズマＣＶＤ法によりアモルファスシリコン膜１４を
１０００Å程度の厚さに形成する。次に、ＸｅＣｌエキ
シマレーザを照射することによりアモルファスシリコン
膜１４を結晶化してポリシリコン膜１５とする。この場
合、高いエネルギ密度でいきなりレーザ照射すると膜破
壊が生じるので、これを避けるために、３段階に分けて
、すなわちまず１８０ｍＪ／ｃｍ２のエネルギ密度で、
次いで２２０ｍＪ／ｃｍ２のエネルギ密度で、最後に２
７０ｍＪ／ｃｍ２のエネルギ密度でレーザ照射を行う。Next, as shown in FIG. 2, unnecessary portions of the underlying silicon nitride film 13 other than the portion corresponding to the active matrix TFT forming region are etched and removed by photolithography. Next, an amorphous silicon film 14 with a thickness of about 1000 Å is formed on the entire surface by plasma CVD. Next, the amorphous silicon film 14 is crystallized into a polysilicon film 15 by irradiation with XeCl excimer laser. In this case, sudden laser irradiation at a high energy density will cause film destruction, so in order to avoid this, we divided it into three stages: first, at an energy density of 180 mJ/cm2;
Then, at an energy density of 220 mJ/cm2, finally 2
Laser irradiation is performed at an energy density of 70 mJ/cm2.
【０００９】次に、図３に示すように、フォトリソグラ
フィ技術により、駆動回路部用の各ＴＦＴのチャネル領
域２１およびアクティブマトリクス部用の各ＴＦＴのチ
ャネル領域２２に対応する部分のポリシリコン膜１５の
上面にフォトレジスト膜２３、２４をパターン形成する
。次に、フォトレジスト膜２３、２４をマスクとしてイ
オンインプラ装置またはイオンシャワ装置によりリンイ
オンを注入し、各チャネル領域２１、２２に対応する部
分以外のポリシリコン膜１５を不純物領域化する。次に
、フォトレジスト膜２３、２４を剥離し、この後ＸｅＣ
ｌエキシマレーザを２２０ｍＪ／ｃｍ２のエネルギ密度
で照射し、活性化を行う。Next, as shown in FIG. 3, a portion of the polysilicon film 15 corresponding to the channel region 21 of each TFT for the drive circuit section and the channel region 22 of each TFT for the active matrix section is etched by photolithography. Photoresist films 23 and 24 are patterned on the upper surface of the photoresist film. Next, using the photoresist films 23 and 24 as masks, phosphorus ions are implanted using an ion implantation device or an ion shower device to convert the polysilicon film 15 other than the portions corresponding to the channel regions 21 and 22 into impurity regions. Next, the photoresist films 23 and 24 are peeled off, and then the XeC
Activation is performed by irradiating with an excimer laser at an energy density of 220 mJ/cm2.
【００１０】次に、フォトリソグラフィ技術により、駆
動回路部用ＴＦＴ形成領域およびアクティブマトリクス
部用ＴＦＴ形成領域に対応する部分以外の不要な部分の
ポリシリコン膜１５をエッチングして除去し、図４に示
すように、下地用酸化シリコン膜１２の上面に駆動回路
部用ポリシリコン膜３１を形成すると共に、下地用窒化
シリコン膜１３の上面にアクティブマトリクス部用ポリ
シリコン膜３２を形成する。この状態では、既に説明し
たように、図３に示す工程においてリンイオンを注入し
ているので、駆動回路部用ポリシリコン膜３１のチャネ
ル領域２１の両側にソース・ドレイン領域３４が形成さ
れ、またアクティブマトリクス部用ポリシリコン膜３２
のチャネル領域２２の両側にソース・ドレイン領域３５
が形成されている。Next, using photolithography, unnecessary portions of the polysilicon film 15 other than those corresponding to the TFT formation region for the drive circuit section and the TFT formation region for the active matrix section are etched and removed, as shown in FIG. As shown, a polysilicon film 31 for the drive circuit portion is formed on the upper surface of the silicon oxide film 12 for the base, and a polysilicon film 32 for the active matrix portion is formed on the upper surface of the silicon nitride film 13 for the base. In this state, as already explained, since phosphorus ions are implanted in the step shown in FIG. Polysilicon film 32 for matrix section
Source/drain regions 35 are provided on both sides of the channel region 22 of the
is formed.
【００１１】次に、図５に示すように、全表面にスパッ
タリング装置を用いて酸化シリコンからなるゲート絶縁
膜４１を１０００Å程度の厚さに形成する。次に、駆動
回路部用ポリシリコン膜３１のチャネル領域２１に対応
する部分のゲート絶縁膜４１の上面およびアクティブマ
トリクス部用ポリシリコン膜３２のチャネル領域２２に
対応する部分のゲート絶縁膜４１の上面にスパッタリン
グ装置を用いてアルミニウムからなるゲート電極４２、
４３を２０００Å程度の厚さにパターン形成する。Next, as shown in FIG. 5, a gate insulating film 41 made of silicon oxide is formed on the entire surface using a sputtering device to a thickness of about 1000 Å. Next, the upper surface of the gate insulating film 41 in the portion corresponding to the channel region 21 of the polysilicon film 31 for the drive circuit portion and the upper surface of the gate insulating film 41 in the portion corresponding to the channel region 22 of the polysilicon film 32 for the active matrix portion. gate electrode 42 made of aluminum using a sputtering device,
43 is patterned to a thickness of about 2000 Å.
【００１２】次に、図６に示すように、全表面にプラズ
マＣＶＤ法により窒化シリコンからなる層間絶縁膜５１
を５０００Å程度の厚さに形成する。次に、層間絶縁膜
５１の上面にスパッタリング装置を用いてＩＴＯからな
る透明電極（走査電極および表示電極）５２を１０００
Å程度の厚さにパターン形成する。次に、駆動回路部用
ポリシリコン膜３１のソース・ドレイン領域３４に対応
する部分の層間絶縁膜５１およびゲート絶縁膜４１にコ
ンタクトホール５３を形成すると共に、アクティブマト
リクス部用ポリシリコン膜３２のソース・ドレイン領域
３５に対応する部分の層間絶縁膜５１およびゲート絶縁
膜４１にコンタクトホール５４を形成する。次に、コン
タクトホール５３を通して駆動回路部用ポリシリコン膜
３１のソース・ドレイン領域３４と接続されるアルミニ
ウムからなるソース・ドレイン電極５５を層間絶縁膜５
１等の上面に６０００Å程度の厚さにパターン形成する
と共に、コンタクトホール５４を通してアクティブマト
リクス部用ポリシリコン膜３２のソース・ドレイン領域
３５と接続される同じくアルミニウムからなるソース・
ドレイン電極５６を層間絶縁膜５１等の上面に６０００
Å程度の厚さにパターン形成する。かくして、駆動回路
部を備えたアクティブマトリクスパネルが製造される。Next, as shown in FIG. 6, an interlayer insulating film 51 made of silicon nitride is formed on the entire surface by plasma CVD.
is formed to a thickness of about 5000 Å. Next, transparent electrodes (scanning electrodes and display electrodes) 52 made of ITO are formed on the upper surface of the interlayer insulating film 51 using a sputtering device in a thickness of 1000 nm.
A pattern is formed to a thickness of about Å. Next, a contact hole 53 is formed in the interlayer insulating film 51 and the gate insulating film 41 in a portion corresponding to the source/drain region 34 of the polysilicon film 31 for the drive circuit part, and the source of the polysilicon film 32 for the active matrix part is formed. - A contact hole 54 is formed in the interlayer insulating film 51 and gate insulating film 41 in a portion corresponding to the drain region 35. Next, a source/drain electrode 55 made of aluminum that is connected to the source/drain region 34 of the polysilicon film 31 for the drive circuit section through the contact hole 53 is connected to the interlayer insulating film 55.
A source/drain region made of aluminum is formed on the top surface of the first layer to a thickness of approximately 6000 Å, and is connected to the source/drain region 35 of the polysilicon film 32 for the active matrix portion through the contact hole 54.
The drain electrode 56 is placed on the upper surface of the interlayer insulating film 51, etc.
A pattern is formed to a thickness of about Å. In this way, an active matrix panel including a drive circuit section is manufactured.
【００１３】ところで、アモルファスシリコンを結晶化
してなるポリシリコンを用いたＴＦＴにおいては、オン
電流およびカットオフ電流は共に下地が酸化シリコンの
場合よりも窒化シリコンの場合の方が低くなる。しかる
に、このアクティブマトリクスパネルでは、駆動回路部
用ポリシリコン膜３１の下地を酸化シリコン膜１２とし
ているので、駆動回路部用ＴＦＴのオン電流を下地が窒
化シリコン膜の場合と比較して十分に高くすることがで
き、一方、アクティブマトリクス部用ポリシリコン膜３
２の下地を窒化シリコン膜１３としているので、アクテ
ィブマトリクス部用ＴＦＴのカットオフ電流を下地が酸
化シリコン膜の場合と比較して十分に低くすることがで
きる。By the way, in a TFT using polysilicon made by crystallizing amorphous silicon, both the on-current and the cut-off current are lower when the base is silicon nitride than when the base is silicon oxide. However, in this active matrix panel, since the base of the polysilicon film 31 for the drive circuit section is the silicon oxide film 12, the on-current of the TFT for the drive circuit section is sufficiently higher than when the base is a silicon nitride film. On the other hand, the polysilicon film 3 for the active matrix section
Since the base of 2 is the silicon nitride film 13, the cutoff current of the TFT for the active matrix portion can be made sufficiently lower than when the base is a silicon oxide film.
【００１４】ちなみに、透明基板の上面に酸化シリコン
膜を形成し、この酸化シリコン膜の上面にＴＦＴを形成
した下地酸化シリコンＴＦＴと、透明基板の上面に窒化
シリコン膜を形成し、この窒化シリコン膜の上面にＴＦ
Ｔを形成した下地窒化シリコンＴＦＴとをそれぞれ数十
個用意し、オン電流およびカットオフ電流を測定したと
ころ、次のような結果が得られた。なお、ＴＦＴのチャ
ネルの幅および長さをそれぞれ１００μｍ、１０μｍと
した。まず、オン電流については、ゲート電圧が２０Ｖ
でドレイン電圧が５Ｖのときのドレイン電流を測定した
ところ、下地酸化シリコンＴＦＴのオン電流の平均値が
１６６μＡであり、下地窒化シリコンＴＦＴのオン電流
の平均値が１１９μＡであった。したがって、駆動回路
部用ポリシリコン膜３１の下地を酸化シリコン膜１２と
すると、駆動回路部用ＴＦＴのオン電流を下地が窒化シ
リコン膜の場合と比較して十分に高くすることができる
。次に、カットオフ電流については、２種類の測定を行
った。第１のカットオフ電流については、ゲート電圧が
０Ｖでドレイン電圧が１０Ｖのときのドレイン電流を測
定したところ、下地酸化シリコンＴＦＴのオン電流の平
均値が４５９ｐＡであり、下地窒化シリコンＴＦＴのオ
ン電流の平均値が９３．１ｐＡであった。第２のカット
オフ電流については、ゲート電圧が０Ｖでドレイン電圧
が２０Ｖのときのドレイン電流を測定したところ、下地
酸化シリコンＴＦＴのオン電流の平均値が３０．８ｎＡ
であり、下地窒化シリコンＴＦＴのオン電流の平均値が
３．２４ｎＡであった。したがって、アクティブマトリ
クス部用ポリシリコン膜３２の下地を窒化シリコン膜１
３とすると、アクティブマトリクス部用ＴＦＴのカット
オフ電流を下地が酸化シリコン膜の場合と比較して十分
に低くすることができる。Incidentally, a silicon oxide film is formed on the upper surface of a transparent substrate, a base silicon oxide TFT is formed with a TFT formed on the upper surface of the silicon oxide film, and a silicon nitride film is formed on the upper surface of the transparent substrate. TF on the top surface of
Several tens of silicon nitride TFTs each having a T-formed base were prepared, and the on-current and cut-off current were measured, and the following results were obtained. Note that the width and length of the TFT channel were 100 μm and 10 μm, respectively. First, regarding the on-current, the gate voltage is 20V.
When the drain current was measured when the drain voltage was 5 V, the average on-current value of the base silicon oxide TFT was 166 μA, and the average value of the on-current value of the base silicon nitride TFT was 119 μA. Therefore, when the base of the polysilicon film 31 for the drive circuit section is the silicon oxide film 12, the on-current of the TFT for the drive circuit section can be made sufficiently higher than when the base is a silicon nitride film. Next, two types of measurements were performed regarding the cutoff current. Regarding the first cutoff current, when the drain current was measured when the gate voltage was 0 V and the drain voltage was 10 V, the average value of the on-current of the base silicon oxide TFT was 459 pA, and the on-current value of the base silicon nitride TFT was 459 pA. The average value was 93.1 pA. Regarding the second cutoff current, when the drain current was measured when the gate voltage was 0V and the drain voltage was 20V, the average value of the on-current of the underlying silicon oxide TFT was 30.8nA.
The average value of the on-current of the underlying silicon nitride TFT was 3.24 nA. Therefore, the base of the polysilicon film 32 for the active matrix portion is the silicon nitride film 1.
3, the cutoff current of the TFT for the active matrix portion can be made sufficiently lower than when the base is a silicon oxide film.
【００１５】なお、上記実施例では、例えば図４に示す
ように、透明基板１１の上面に下地用酸化シリコン膜１
２を設け、この下地用酸化シリコン膜１２の上面の必要
な部分に下地用窒化シリコン膜１３を設け、そして下地
用酸化シリコン膜１２の上面に駆動回路部用ポリシリコ
ン膜３１を設けると共に、下地用窒化シリコン膜１３の
上面にアクティブマトリクス部用ポリシリコン膜３２を
設けているが、これに限定されるものではない。例えば
、図７に示すように、透明基板１１の上面に下地用窒化
シリコン膜１３を設け、この下地用窒化シリコン膜１３
の上面の必要な部分に下地用酸化シリコン膜１２を設け
、そして下地用酸化シリコン膜１２の上面に駆動回路部
用ポリシリコン膜３１を設けると共に、下地用窒化シリ
コン膜１３の上面にアクティブマトリクス部用ポリシリ
コン膜３２を設けるようにしてもよい。また、図示して
いないが、透明基板の上面の駆動回路部用ＴＦＴ形成領
域に下地用酸化シリコン膜を設けると共に、透明基板の
上面のアクティブマトリクス部用ＴＦＴ形成領域に下地
用窒化シリコン膜を設け、そして下地用酸化シリコン膜
の上面に駆動回路部用ポリシリコン膜を設けると共に、
下地用窒化シリコン膜の上面にアクティブマトリクス部
用ポリシリコン膜を設けるようにしてもよい。また、こ
の発明は液晶表示パネルに限らず、ＴＦＴメモリやイメ
ージセンサ等のマトリクスパネルに幅広く適用できるも
のである。Note that in the above embodiment, as shown in FIG.
2, a silicon nitride film 13 for the base is provided on the upper surface of the silicon oxide film 12 for the base, and a polysilicon film 31 for the drive circuit section is provided on the upper surface of the silicon oxide film 12 for the base. Although the active matrix portion polysilicon film 32 is provided on the upper surface of the silicon nitride film 13, the present invention is not limited thereto. For example, as shown in FIG. 7, a silicon nitride film 13 for the base is provided on the upper surface of the transparent substrate 11, and the silicon nitride film 13 for the base
A base silicon oxide film 12 is provided on the necessary portions of the upper surface, a polysilicon film 31 for the drive circuit section is provided on the upper surface of the base silicon oxide film 12, and an active matrix section is provided on the upper surface of the base silicon nitride film 13. A polysilicon film 32 may also be provided. Although not shown, a silicon oxide film for the base is provided in the TFT formation region for the drive circuit section on the upper surface of the transparent substrate, and a silicon nitride film for the base is provided in the TFT formation region for the active matrix section on the upper surface of the transparent substrate. , and a polysilicon film for a drive circuit section is provided on the upper surface of the underlying silicon oxide film, and
A polysilicon film for the active matrix portion may be provided on the upper surface of the silicon nitride film for the base. Further, the present invention is not limited to liquid crystal display panels, but can be widely applied to matrix panels such as TFT memories and image sensors.
【００１６】[0016]
【発明の効果】以上説明したように、この発明によれば
、アクティブマトリクス部用ＴＦＴの下地を窒化シリコ
ン膜としているので、アクティブマトリクス部用ＴＦＴ
のカットオフ電流を下地が酸化シリコン膜の場合と比較
して十分に低くすることができ、しかも駆動回路部用Ｔ
ＦＴの下地を酸化シリコン膜としているので、駆動回路
部用ＴＦＴのオン電流が低下しないようにすることがで
き、ひいては表示品質を向上させることができる。As explained above, according to the present invention, since the base of the TFT for the active matrix section is a silicon nitride film, the TFT for the active matrix section
The cutoff current can be made sufficiently lower than that when the base is a silicon oxide film.
Since the base of the FT is a silicon oxide film, it is possible to prevent the on-state current of the TFT for the drive circuit portion from decreasing, and as a result, the display quality can be improved.
【図１】この発明の一実施例におけるアクティブマトリ
クスパネルの製造に際し、透明基板の上面に下地用酸化
シリコン膜および下地用窒化シリコン膜を形成した状態
の断面図。FIG. 1 is a cross-sectional view of a state where a base silicon oxide film and a base silicon nitride film are formed on the upper surface of a transparent substrate in manufacturing an active matrix panel in an embodiment of the present invention.
【図２】同アクティブマトリクスパネルの製造に際し、
不要な部分の下地用窒化シリコン膜を除去し、次いでア
モルファスシリコン膜を形成した後このアモルファスシ
リコン膜をレーザ照射によりポリシリコン膜化した状態
の断面図。[Figure 2] When manufacturing the same active matrix panel,
FIG. 3 is a cross-sectional view of a state in which unnecessary portions of the base silicon nitride film are removed, an amorphous silicon film is formed, and the amorphous silicon film is turned into a polysilicon film by laser irradiation.
【図３】同アクティブマトリクスパネルの製造に際し、
イオン注入マスク用のフォトレジスト膜を形成した後リ
ンイオン注入により不純物領域を形成した状態の断面図
。[Figure 3] When manufacturing the same active matrix panel,
FIG. 3 is a cross-sectional view of a state in which an impurity region is formed by phosphorus ion implantation after forming a photoresist film for an ion implantation mask.
【図４】同アクティブマトリクスパネルの製造に際し、
不要な部分のポリシリコン膜を除去して駆動回路部用ポ
リシリコン膜とアクティブマトリクス部用ポリシリコン
膜を形成した状態の断面図。[Figure 4] When manufacturing the same active matrix panel,
FIG. 3 is a cross-sectional view of a state in which unnecessary portions of the polysilicon film are removed to form a polysilicon film for a drive circuit section and a polysilicon film for an active matrix section.
【図５】同アクティブマトリクスパネルの製造に際し、
ゲート絶縁膜およびゲート電極を形成した状態の断面図
。[Figure 5] When manufacturing the same active matrix panel,
FIG. 3 is a cross-sectional view of a state in which a gate insulating film and a gate electrode are formed.
【図６】同アクティブマトリクスパネルの製造に際し、
層間絶縁膜、透明電極およびコンタクトホールを形成し
た後ソース・ドレイン電極を形成した状態の断面図。[Figure 6] When manufacturing the same active matrix panel,
FIG. 3 is a cross-sectional view of a state in which source/drain electrodes are formed after forming an interlayer insulating film, a transparent electrode, and a contact hole.
【図７】この発明の他の実施例におけるアクティブマト
リクスパネルの図４同様の状態の断面図。FIG. 7 is a cross-sectional view of an active matrix panel in a state similar to FIG. 4 in another embodiment of the invention.
【図８】従来のアクティブマトリクスパネルの回路構成
の一例を示す図。FIG. 8 is a diagram showing an example of a circuit configuration of a conventional active matrix panel.
１１ 透明基板 １２ 下地用酸化シリコン膜 １３ 下地用窒化シリコン膜 ２１ 駆動回路部用ポリシリコン膜 11 Transparent substrate 12 Base silicon oxide film 13 Base silicon nitride film 21 Polysilicon film for drive circuit section
Claims (3)
動回路部とを設けたアクティブマトリクスパネルにおい
て、前記アクティブマトリクス部をＴＦＴで構成すると
共にその下地を窒化シリコン膜とし、且つ前記駆動回路
部をＴＦＴで構成すると共にその下地を酸化シリコン膜
としたことを特徴とするアクティブマトリクスパネル。1. An active matrix panel including an active matrix section and a drive circuit section provided on a substrate, wherein the active matrix section is composed of TFTs, the base thereof is a silicon nitride film, and the drive circuit section is composed of TFTs. An active matrix panel characterized in that it is composed of a silicon oxide film and its base is a silicon oxide film.
ン膜上に形成されていることを特徴とする請求項１記載
のアクティブマトリクスパネル。2. The active matrix panel according to claim 1, wherein the silicon nitride film is formed on the silicon oxide film.
ン膜上に形成されていることを特徴とする請求項１記載
のアクティブマトリクスパネル。3. The active matrix panel according to claim 1, wherein the silicon oxide film is formed on the silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16518591A JP3005918B2 (en) | 1991-06-11 | 1991-06-11 | Active matrix panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16518591A JP3005918B2 (en) | 1991-06-11 | 1991-06-11 | Active matrix panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04362616A true JPH04362616A (en) | 1992-12-15 |
| JP3005918B2 JP3005918B2 (en) | 2000-02-07 |
Family
ID=15807459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16518591A Expired - Lifetime JP3005918B2 (en) | 1991-06-11 | 1991-06-11 | Active matrix panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3005918B2 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07111334A (en) * | 1993-08-20 | 1995-04-25 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
| JPH07135323A (en) * | 1993-10-20 | 1995-05-23 | Semiconductor Energy Lab Co Ltd | Thin film semiconductor integrated circuit and its fabrication |
| US5434433A (en) * | 1992-08-19 | 1995-07-18 | Seiko Instruments Inc. | Semiconductor device for a light wave |
| US5585647A (en) * | 1993-06-29 | 1996-12-17 | Kabushiki Kaisha Toshiba | Integrated circuit device having an insulating substrate, and a liquid crystal display device having an insulating substrate |
| US5633176A (en) * | 1992-08-19 | 1997-05-27 | Seiko Instruments Inc. | Method of producing a semiconductor device for a light valve |
| WO1998013811A1 (en) * | 1996-09-26 | 1998-04-02 | Seiko Epson Corporation | Display device |
| US5962897A (en) * | 1992-06-18 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6479331B1 (en) * | 1993-06-30 | 2002-11-12 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2007148446A (en) * | 1996-09-26 | 2007-06-14 | Seiko Epson Corp | Display apparatus |
-
1991
- 1991-06-11 JP JP16518591A patent/JP3005918B2/en not_active Expired - Lifetime
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5962897A (en) * | 1992-06-18 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US5633176A (en) * | 1992-08-19 | 1997-05-27 | Seiko Instruments Inc. | Method of producing a semiconductor device for a light valve |
| US6187605B1 (en) | 1992-08-19 | 2001-02-13 | Seiko Instruments Inc. | Method of forming a semiconductor device for a light valve |
| US5434433A (en) * | 1992-08-19 | 1995-07-18 | Seiko Instruments Inc. | Semiconductor device for a light wave |
| US6455875B2 (en) | 1992-10-09 | 2002-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having enhanced field mobility |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6790749B2 (en) | 1992-10-09 | 2004-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US5585647A (en) * | 1993-06-29 | 1996-12-17 | Kabushiki Kaisha Toshiba | Integrated circuit device having an insulating substrate, and a liquid crystal display device having an insulating substrate |
| US6479331B1 (en) * | 1993-06-30 | 2002-11-12 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device |
| JPH07111334A (en) * | 1993-08-20 | 1995-04-25 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacture thereof |
| JPH07135323A (en) * | 1993-10-20 | 1995-05-23 | Semiconductor Energy Lab Co Ltd | Thin film semiconductor integrated circuit and its fabrication |
| WO1998013811A1 (en) * | 1996-09-26 | 1998-04-02 | Seiko Epson Corporation | Display device |
| US6542137B2 (en) * | 1996-09-26 | 2003-04-01 | Seiko Epson Corporation | Display device |
| EP1465257A1 (en) * | 1996-09-26 | 2004-10-06 | Seiko Epson Corporation | Display apparatus |
| US6862011B2 (en) | 1996-09-26 | 2005-03-01 | Seiko Epson Corporation | Display apparatus |
| US7012278B2 (en) | 1996-09-26 | 2006-03-14 | Seiko Epson Corporation | Light-emitting apparatus driven with thin-film transistor and method of manufacturing light-emitting apparatus |
| JP2007148446A (en) * | 1996-09-26 | 2007-06-14 | Seiko Epson Corp | Display apparatus |
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