JPH07263698A - Thin film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a thin film transistor whose active layer is very thinned, by decreasing the dry etching rate to an N-type semiconductor, and enabling selective etching elimination of an N-type semiconductor on the active layer. CONSTITUTION:On a glass substrate 1 the following are formed; a Cr gate electrode 2, gate insulating silicon nitride 3, an active layer 4 composed of amorphous or polycrystalline silicon, P-type nanocrystalline silicon 5, N-type nanocrystalline silicon 6, and source-drain electrodes 10, 11. An ohmic contact layer 12 is formed by selectively dry-etching the N-type nanocrystalline silicon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device,
In particular, it relates to a structure of a thin film transistor for driving a liquid crystal display and a manufacturing method thereof.

[0002]

2. Description of the Related Art Generally, the structure of an inverted stagger type thin film transistor in which the thickness of the active layer of the thin film transistor is extremely thin to about 200 to 600 Å is described in "Extended Abstracts of the Twenty Second (1990).
International) Conference on Solid State Devices and Materials ”
“Extended Abstracts of the 22nd (1990 Internation
al) Conference on Solid State Devices and Mterial
s: SE-23,1027 ″), a gate electrode, a gate insulating film, an active layer made of a semiconductor on an insulating substrate, an etching stopper layer made of an insulating film on the upper surface thereof, and impurities in the semiconductor. It is composed of an ohmic contact layer formed by doping and source and drain electrodes.

[0003]

The prior art relates to an inverted stagger type thin film transistor, and a dry etching gas is used to achieve thinning of an active layer for the purpose of lowering off current and reducing excitation of electrons by light. On the other hand, an etching stopper layer is partially inserted between the active layer and the ohmic contact layer where the difference in etching rate is not large. Therefore, there is a problem that the number of manufacturing steps is increased to form the etching stopper layer.

On the other hand, the present invention relates to an inverse stagger type thin film transistor, and an object of the present invention is to
An object of the present invention is to provide a high-performance thin film transistor with a low off-current, which has an extremely thin active layer, by increasing the number of manufacturing processes.

[0005]

In order to solve the above problems, a feature of the present invention is that the dry etching rate is higher than that of an ohmic contact layer in at least a partial region of the active layer from the junction surface between the active layer and the ohmic contact layer. Slow p
Type semiconductor.

[0006]

According to the above means, at least a part of the active layer from the junction surface between the active layer and the ohmic contact layer becomes a p-type semiconductor having a slower dry etching rate than the ohmic contact layer, and the p-type semiconductor between the source and drain electrodes The ohmic contact layer can be selectively removed by etching, and therefore the active layer can be made extremely thin.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a manufacturing process of a thin film transistor in one embodiment of the present invention. Figure 1
As shown in (a), 1,200 Cr is deposited on the glass substrate 1.
Å The gate electrode 2 is formed by depositing by sputtering and patterning. Then, the plasma CVD method uses the source gases SiH ₄ , NH ₃ , and N ₂ , respectively, and the silicon nitride film 3, which is a gate insulating film of 3500Å, and SiH ₄ and H ₂ to form an active layer of 200 to 600Å, which is an amorphous layer. Silicon film 4, SiH ₄ , H ₂ , BH ₃ and 100 Å p-type microcrystalline silicon 5, SiH ₄ , H ₂ , PH ₃ 340
Å n-type microcrystalline silicon 6 is continuously deposited. here,
Assuming that BH ₃ is mixed in an amount of 10 to 400 ppm with respect to the total flow rate of the raw material gas as the film forming condition of the p-type microcrystalline silicon 5, as shown in FIG. The etching rate of polycrystalline or amorphous silicon is 0.24Å / s, while it is 0.1
The ratio (selection ratio) to the etching rate of 1.4Å / s of the n-type microcrystalline silicon 6 is 5.8.
It improves from 10 to 14. Therefore, when the n-type microcrystalline silicon 6 is etched, if the underlayer is the p-type microcrystalline silicon 5, it does not affect the underlayer more than the case of the intrinsic polycrystalline or amorphous silicon and is more selective. Can be etched selectively. Then, by sputtering method, Mo
After depositing 600 Å 7, the films 3 to 7 are patterned into islands. Then, using the sputtering method, 28
An ITO (Indium Tin Oxide) 8 of 00Å is deposited. Next, as shown in FIG. 1B, a resist 9 is applied and then formed by photolithography into a predetermined shape for forming source and drain electrodes. Then, as shown in FIG. 1C, ITO8 was wet-etched with bromic acid, and Mo7 was wet-etched with a solution containing phosphoric acid, acetic acid, and nitric acid as main components.
The source and drain electrodes 10 and 11 are formed by sequentially removing them. Then, the n-type microcrystalline silicon 6 is removed by a dry etching method using chlorine gas to remove the ohmic contact layer 1
2 is formed and the thin film transistor is completed.

According to the embodiment, when the ohmic contact layer 12 is formed, since the base of the n-type microcrystalline silicon 6 is the p-type microcrystalline silicon 5 having a smaller etching rate, it affects the base. Therefore, the n-type microcrystalline silicon 6 can be removed more selectively and a thin film transistor having an extremely thin active layer can be manufactured. Then, as shown in FIG. 3, by increasing the resistance of the channel region by thinning, a transistor having an excellent off-state current as compared with a transistor having a normal active layer film thickness of 2200Å is obtained.
Here, the active layer is not limited to the laminated structure of the amorphous silicon 4 and the p-type microcrystalline silicon 5. For example, if the B concentration near the interface with the n-type microcrystalline silicon 6 in the active layer is sufficient, the B concentration may decrease in the film thickness direction. With such a structure, it is sufficient to mix BH ₃ during the film formation of the amorphous silicon in the manufacturing process and increase the mixing ratio, so that the manufacturing throughput is improved. On the other hand, in the case of the laminated structure, B is unlikely to be mixed into the amorphous silicon, so that the characteristics as a transistor are good.

In the embodiment, it is also possible to deposit the amorphous silicon 4 serving as the active layer and then irradiate it with an energy beam to form polycrystalline silicon. For example, after depositing amorphous silicon 4, 220 mJ / cm ² of XeCl ²
Irradiate a laser to polycrystallize the silicon film, and then p
Type microcrystalline silicon 5 and n-type microcrystalline silicon 6 are continuously formed, and the remaining steps are the same as those in the above-described embodiment, so that an active layer excellent in characteristics of high on-current and low off-current is extremely formed. A thin film transistor can be manufactured. At this time,
By laminating the polycrystalline silicon and the p-type microcrystalline silicon, the rough surface of the silicon after laser irradiation can be covered, so that the n-type microcrystalline silicon does not get into the concave surface of the polycrystalline silicon surface, and it is more reliable. Can be easily and selectively removed by etching.

Further, the crystal structure of the p-type semiconductor is not particularly limited to microcrystals as long as a sufficient etching selection ratio with respect to the n-type semiconductor forming the ohmic contact layer can be obtained. For example, in the case of amorphous, the concentration of holes is reduced, so that the off current can be further reduced, and in the case of microcrystalline, the deposition rate is slow and the controllability of the film thickness is improved. Further, the film thickness can be set to a range of 20 to 500 Å as a range not significantly deteriorating the performance of the transistor, but a range of 20 to 200 Å is preferable in view of characteristics and processability.

Further, in the present embodiment, the structure of the transistor is patterned from Mo7 to the silicon nitride film 3 all at once, but the present invention is not particularly limited to this structure. For example, it is of course applicable to a transistor having a structure in which Mo7 to amorphous silicon 4 are collectively patterned on an island.

Next, a second embodiment in which a thin film transistor (hereinafter referred to as TFT) manufactured according to the present invention is used as a drive element of a display pixel of an active matrix type liquid crystal display device will be described.

FIG. 4 shows the configuration of an active matrix type liquid crystal display device which is an embodiment of the present invention. In the figure,
A TFT is provided for each of a plurality of liquid crystal cells (LC) arranged in a matrix, and each liquid crystal cell is driven by the switching operation of the TFT. Here, a gate voltage is sequentially applied to the gate lines G1 to GM, which are electrodes commonly drawn from the gates of the TFTs arranged in the lateral direction on the glass substrate 1, and the gates are turned on for each gate line. Go. On the other hand, the data voltage for each turned-on gate line is sequentially applied to the drain lines D1 to DN, which are electrodes commonly drawn from the drains of the TFTs arranged in the vertical direction, and applied to each liquid crystal cell. FIG. 5 shows a planar structure of one pixel composed of one liquid crystal cell and TFT. Further, FIG. 6 shows a sectional structure taken along a broken line XX ′ in FIG. It is composed of a TFT formed near the intersection of the drain wiring D and the gate wiring G and a liquid crystal cell LC connected thereto via the source electrode 10.
The cross-sectional structure of the TFT is almost the same as that of the first embodiment. This structure can be obtained by the manufacturing method described in the embodiment, but only the changes from the process are as follows. That is, the gate wiring G and the drain wiring D are respectively connected to the gate electrode 2,
The drain electrode 11 was formed at the same time by film formation and etching. In addition, the parts other than the TFT such as the liquid crystal 13 will be described below. The TN type liquid crystal 13 is sealed between a glass substrate (counter substrate) 16 facing the glass substrate on which the TFT is formed. A black matrix 14 and an ITO 15 film for blocking unnecessary light rays are formed on the counter substrate. The liquid crystal is driven by the voltage between the ITO 15 of the counter substrate and the ITO of the TFT substrate, and changes the brightness displayed for each pixel to display an image on the matrix of pixels. A deflection plate 17 for deflecting light on either the glass substrate 1 or 16
Is attached. The deflection axes of these two deflection plates are orthogonal,
Or if they are arranged in parallel, they are normally black,
The display mode is normally white. Although not shown in the figure, the alignment film 18 for aligning the liquid crystal has a protective film 1 on the surface in contact with the liquid crystal, that is, on the glass substrate 1 side.
9 and the surface of the ITO film 10, ITO on the side of the counter substrate 16
It is applied to the surface of the film. The surface of the alignment film is treated by a rubbing method after coating, and is given anisotropy for aligning liquid crystal molecules. As described above, when the TFT manufactured according to the present invention is used as a driving element of a display pixel of an active matrix type liquid crystal display device, a material cost is reduced and a manufacturing throughput is improved because the active layer is an extremely thin film.
Further, since the photoconductivity also decreases, it is possible to avoid deterioration of the image quality due to photoexcited electrons.

Next, a third embodiment in which the crystalline thin film transistor according to the present invention is formed and used on the same substrate as the display portion as a part of the drive circuit of the active matrix type liquid crystal display device will be described.

FIG. 7 shows the structure of an active matrix type liquid crystal display device using the present invention. In this embodiment, part of the function of the driver circuit is formed over the same glass substrate as the thin film transistor of the pixel. In the figure, thin film transistors are provided for a plurality of liquid crystal cells (LC) arranged in a matrix, and the liquid crystal cells are driven by the switching operation of the thin film transistors. Here, a gate voltage is sequentially applied from the gate drive circuit (driver IC) 20 to the gate lines G1 to GM, which are electrodes commonly drawn from the respective gates of the thin film transistors arranged in the lateral direction on the glass substrate 1, The gate is turned on for each gate line. On the other hand, with respect to the drain lines D1 to DN, which are electrodes commonly drawn from the drains of the thin film transistors arranged in the vertical direction,
The data voltage for each turned-on gate line is sequentially applied from the data drive circuit 21 through the sampling circuit 22 and applied to each liquid crystal cell. Further, as shown in FIG. 8, the sampling circuit 22 has a sampling thin film transistor for each drain line, and supplies a plurality of voltages φ1 and φ2 to the gate of the sampling thin film transistor while the pixel thin film transistor gate voltage is on. . The two drain lines are grouped together and connected from the sampling circuit 22 to the data driving circuit 21. Since the sampling circuit 22 is formed on the glass substrate 1 like the thin film transistor of the pixel, the number of connections between the sampling circuit 22 and the data driving circuit 21 is halved. The drain lines D1 and D2 are integrated and connected to the data driving circuit as DK1, and as a result, the number of connections between the data driving circuit 21 and the substrate on which the pixel thin film transistors and the sampling circuit 22 are formed is reduced by half, that is, the data driving circuit is configured. The number of driver ICs used can be halved. Since the sampling circuit 22 can be easily formed in the same process as the pixel thin film transistor, the effect of halving the number of driver ICs has an effect of reducing the liquid crystal display cost. The pixel thin film transistor may have an amorphous active layer, or may be a polycrystalline thin film transistor. As described above, when the crystalline thin film transistor according to the present invention is formed and used on the same substrate as the display unit as a part of the driving circuit of the active matrix type liquid crystal display device,
As in the second embodiment, since the active layer is an ultra-thin film, the material cost is reduced, the manufacturing throughput is improved, and the photoconductivity in the pixel portion is also reduced, so that the deterioration of the image quality due to photoexcited electrons is avoided, and the black Since the width of the matrix 14 can be reduced, the aperture ratio can be increased, which is effective in a high-definition liquid crystal display device.

[0017]

According to the present invention, a thin film transistor having an extremely thin active layer and a low off current can be manufactured by increasing the number of manufacturing processes.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an embodiment in which the present invention is applied to manufacturing a thin film transistor.

FIG. 2 is a characteristic diagram showing the dependence of the etching rate and the selection ratio on the doping ratio of BH ₃ .

FIG. 3 is a characteristic diagram showing a gate voltage-drain current characteristic of a thin film transistor manufactured according to the present invention of a conventional thin film transistor having a thick active layer.

FIG. 4 is an explanatory diagram of an active matrix type liquid crystal display device using a thin film transistor manufactured according to the present invention as a liquid crystal cell driving element.

FIG. 5 is a plan view of one pixel including a liquid crystal cell and a thin film transistor manufactured according to the present invention.

FIG. 6 is a cross-sectional view of one pixel including a liquid crystal cell and a thin film transistor manufactured according to the present invention.

FIG. 7 is an explanatory diagram showing a configuration of an active matrix type liquid crystal display device using the present invention.

FIG. 8 is an explanatory diagram of a sampling circuit using the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 2 ... Gate electrode, 3 ... Silicon nitride film, 4 ... Amorphous silicon film, 5 ... P-type microcrystalline silicon,
6 ... n-type microcrystalline silicon, 7 ... Mo, 8 ... ITO, 9 ...
Resist, 10 ... Source electrode, 11 ... Drain electrode, 1
2 ... Ohmic contact layer.

Claims (14)

[Claims] 1. An inverted staggered type having a gate electrode, a gate insulating film, an active layer made of a semiconductor, an ohmic contact layer formed by doping a semiconductor with an impurity, a source electrode, and a drain electrode formed on an insulating substrate. 2. The thin film transistor according to claim 2, wherein at least a region of the active layer from a junction surface between the active layer and the ohmic contact layer is a p-type semiconductor. 2. An inverted stagger type which is formed on an insulating substrate and has a gate electrode, a gate insulating film, an active layer made of a semiconductor, an ohmic contact layer formed by doping a semiconductor with impurities, a source electrode, and a drain electrode. 3. The thin film transistor according to claim 1, wherein the active layer has a laminated structure of an intrinsic semiconductor and a p-type semiconductor in a film thickness direction from an interface with the gate insulating film. 3. An inverted stagger type having a gate electrode, a gate insulating film, an active layer made of a semiconductor, an ohmic contact layer formed by doping a semiconductor with an impurity, a source electrode, and a drain electrode formed on an insulating substrate. 2. The thin film transistor according to claim 1, wherein the active layer has a laminated structure of a polycrystalline intrinsic semiconductor and a p-type semiconductor in a film thickness direction from an interface with the gate insulating film. 4. An inverted stagger type which is formed on an insulating substrate and has a gate electrode, a gate insulating film, an active layer made of a semiconductor, an ohmic contact layer formed by doping a semiconductor with an impurity, a source electrode, and a drain electrode. 2. The thin film transistor according to claim 1, wherein the active layer has a laminated structure of an amorphous intrinsic semiconductor and a p-type semiconductor in a film thickness direction from an interface with the gate insulating film. 5. An inverted stagger type having a gate electrode, a gate insulating film, an active layer made of a semiconductor, an ohmic contact layer formed by doping a semiconductor with an impurity, a source electrode, and a drain electrode formed on an insulating substrate. 2. The thin film transistor according to claim 1, wherein the active layer has a laminated structure of an intrinsic semiconductor and a microcrystalline p-type semiconductor in a film thickness direction from an interface with the gate insulating film. 6. An inverted stagger type having a gate electrode, a gate insulating film, an active layer made of a semiconductor, an ohmic contact layer formed by doping a semiconductor with an impurity, a source electrode, and a drain electrode formed on an insulating substrate. 2. The thin film transistor according to claim 1, wherein the active layer has a laminated structure of an intrinsic semiconductor and an amorphous p-type semiconductor in a film thickness direction from an interface with the gate insulating film. 7. An inverted staggered type having a gate electrode, a gate insulating film, an active layer made of a semiconductor, an ohmic contact layer formed by doping a semiconductor with an impurity, a source electrode, and a drain electrode formed on an insulating substrate. 2. The method of manufacturing a thin film transistor according to the method, wherein the active layer is formed so that at least a part of a region in a film thickness direction from a bonding surface with the ohmic contact layer is a p-type semiconductor. 8. An inverted stagger type having a gate electrode, a gate insulating film, an active layer made of a semiconductor, an ohmic contact layer formed by doping a semiconductor with an impurity, a source electrode, and a drain electrode formed on an insulating substrate. 2. The method of manufacturing a thin film transistor according to the method, wherein the active layer is formed so as to have a laminated structure of an intrinsic semiconductor and a p-type semiconductor in a film thickness direction from an interface with the front gate insulating film. 9. A liquid crystal display device according to claim 1, 2, 3, 4, 5 or 6, wherein the thin film transistor is used as a liquid crystal cell driving element. 10. A method of manufacturing a thin film transistor for driving a liquid crystal cell of a liquid crystal display device, to which the method of manufacturing the thin film transistor according to claim 7 is applied. 11. A liquid crystal display device according to claim 1, 2, 3, 4, 5 or 6, wherein the thin film transistor is used as a drive circuit element. 12. The method of manufacturing a thin film transistor for driving a liquid crystal display device according to claim 7, wherein the method of manufacturing the thin film transistor is applied. 13. A liquid crystal display device according to claim 1, 2, 3, 5 or 6, wherein the thin film transistor is used as a liquid crystal cell driving element and a display section driving circuit element. 14. A method of manufacturing a thin film transistor for driving a liquid crystal cell and a display unit of a liquid crystal display device, to which the method of manufacturing a thin film transistor according to claim 7 is applied.