JPH06295924A - Manufacture of liquid crystal display device - Google Patents

Manufacture of liquid crystal display device

Info

Publication number
JPH06295924A
JPH06295924A JP34635193A JP34635193A JPH06295924A JP H06295924 A JPH06295924 A JP H06295924A JP 34635193 A JP34635193 A JP 34635193A JP 34635193 A JP34635193 A JP 34635193A JP H06295924 A JPH06295924 A JP H06295924A
Authority
JP
Japan
Prior art keywords
source
liquid crystal
forming
drain
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34635193A
Other languages
Japanese (ja)
Inventor
Myoung S Yang
明 秀 梁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Electronics Inc
Original Assignee
Gold Star Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gold Star Co Ltd filed Critical Gold Star Co Ltd
Publication of JPH06295924A publication Critical patent/JPH06295924A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00Materials and properties
    • G02F2202/10Materials and properties semiconductor
    • G02F2202/104Materials and properties semiconductor poly-Si

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: To avoid the current effect of a transparent electrode and reduce the contact resistance of a source/drain by depositing a heavily doped semicon ductor layer and metal on the entire surface and selectively etching to form data lines and source electrodes connected to source regions. CONSTITUTION: After continuously depositing a heavily doped n-type polycrystalline Si 11 and metal 12 such as Al, a photosensitive film 13 is coated thereon, exposed and developed. When this film 13 is developed, the electrolyte of the developer liq. will lower along the Al bank but never contacts a transparent electrode 9 as the Si 11 acts as a barriers, thus preventing the current effect. The heavily doped n-type polycrystalline Si 11 directly contacts drain/ source regions 6a, 6b to facilitate the contact resistance control. The Si 11 and metal layer 12 are laminated to form a double structure which prevents the short-circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、液晶表示素子に係り、
特に、トップ(top) ゲート多結晶シリコン薄膜トランジ
スタをスイッチング素子として使用する液晶表示素子に
おいて、ソース/ドレイン電極をn+ 多結晶シリコンと
金属とを使用して形成する液晶表示素子の製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, the present invention relates to a method of manufacturing a liquid crystal display element using a top gate polycrystalline silicon thin film transistor as a switching element, in which source / drain electrodes are formed by using n + polycrystalline silicon and a metal.

【0002】[0002]

【従来の技術】一般に、液晶表示素子(Liquid Crystal
Display)は、電極の形成された2枚のガラス基板間に液
晶の注入された構造として、電極に電圧を印加して液晶
分子の配列状態を変化させると、液晶の光学的な性質が
変化することを利用して像(Image) を表示するものであ
る。
2. Description of the Related Art Generally, a liquid crystal display device (Liquid Crystal)
Display) has a structure in which liquid crystal is injected between two glass substrates on which electrodes are formed. When a voltage is applied to the electrodes to change the alignment state of liquid crystal molecules, the optical properties of the liquid crystal change. This is what is used to display an image.

【0003】液晶表示素子は、時分割駆動を利用した操
作電圧とデータ信号電圧との平均化法を使用する単純マ
トリックス(Simple Matrix) 駆動方式と、それぞれの画
素電極に独立な能動素子(Active Element)(スイッチン
グ素子)を取付けてそれぞれの画素を独立的に駆動して
隣接する画素のデータ信号による影響を最少化してコン
トラスト比を高め、かつ、走査線数を増大させるアクテ
ィブマトリックス(Active Matrix) 駆動方式と、に大き
く分けることができる。このようなアクティブマトリッ
クス駆動方式では、能動素子として薄膜トランジスタ
(Thin Film Transistor以下TFT と略記する)を使用し
ており、この薄膜トランジスタは、作られた材料によっ
て非晶質シリコン薄膜トランジスタ(Amorphous Silicon
TFT) と多結晶シリコン薄膜トランジスタ(Poli Silico
n TFT)とに分けられ、形態によってはスタガー(Stagge
r) 型、コプレーナ(Co-planar) 型、自己整列(Self Ali
gned)型、トップゲート(Top gate)型等がある。
The liquid crystal display device includes a simple matrix driving method using an averaging method of an operation voltage and a data signal voltage using time division driving, and an active element independent of each pixel electrode. ) (Switching element) is attached to drive each pixel independently to minimize the influence of the data signal of the adjacent pixel to enhance the contrast ratio and to increase the number of scanning lines Active matrix drive It can be roughly divided into two types. In such an active matrix driving method, a thin film transistor (hereinafter abbreviated as TFT) is used as an active element.
TFT) and polycrystalline silicon thin film transistor (Poli Silico
n TFT), and depending on the form, a stagger (Stagge
r) type, Co-planar type, Self
There are gned type and top gate type.

【0004】このような液晶表示素子のうち、従来のト
ップゲート型多結晶シリコン薄膜トランジスタをスイッ
チング素子として使用した液晶表示素子の画素構造を図
面を参照して説明する。図1乃至図3は従来のトップゲ
ート型多結晶シリコン薄情膜トランジスタの液晶表示素
子の製造方法を示す工程図である。先ず、図1(a) に示
すように、透明ガラス基板(1) に接着力の優れた絶縁膜
としてバッファ層(2) を形成し、バッファ層(2) 上に半
導体層(3) を形成する。
Among such liquid crystal display devices, a pixel structure of a conventional liquid crystal display device using a top gate type polycrystalline silicon thin film transistor as a switching device will be described with reference to the drawings. 1 to 3 are process diagrams showing a conventional method of manufacturing a liquid crystal display element of a top gate type polycrystalline silicon thin film transistor. First, as shown in FIG. 1 (a), a buffer layer (2) is formed on a transparent glass substrate (1) as an insulating film having excellent adhesive strength, and a semiconductor layer (3) is formed on the buffer layer (2). To do.

【0005】次に、図1(b) に示すように、半導体層
(3) をフォトエッチ工程を利用して薄膜トランジスタ形
成領域にのみ残るように選択的に除去して活性層(3a)を
形成する。次に、図1(c) に示すように、全面のゲート
絶縁膜(4) 及び金属層(5) を順次蒸着し、続いて、図2
(a) に示すように、金属層(5) 及びゲート絶縁膜(4) を
選択的に除去して活性層(3a)上にゲート電極(5a)及びゲ
ートライン(5b)を形成する。ここで、ゲートライン(5b)
は他の画素の薄膜トランジスタ駆動用ゲートライン(5b)
である。次に、図2(b) に示すように、ゲート電極(5a)
をマスクとして活性層(3a)に高濃度のn型イオンを注入
し熱処理して薄膜トランジスタのソース/ドレイン領域
(6a),(6b)を形成する。
Next, as shown in FIG. 1B, the semiconductor layer
The active layer (3a) is formed by selectively removing (3) using a photoetching process so that it remains only in the thin film transistor forming region. Next, as shown in FIG. 1 (c), a gate insulating film (4) and a metal layer (5) are sequentially deposited on the entire surface, and then, as shown in FIG.
As shown in (a), the metal layer (5) and the gate insulating film (4) are selectively removed to form a gate electrode (5a) and a gate line (5b) on the active layer (3a). Where the gate line (5b)
Is the gate line (5b) for driving the thin film transistors of other pixels
Is. Next, as shown in FIG. 2 (b), the gate electrode (5a)
The source / drain region of the thin film transistor is formed by implanting high concentration n-type ions into the active layer (3a) using the mask as a mask and performing heat treatment.
Form (6a) and (6b).

【0006】次に、図2(c) に示すように、層間絶縁膜
(7) を蒸着しソース/ドレイン領域(6a),(6b)が露出さ
れるように層間絶縁膜(7) を選択的にエッチングしてコ
ンタクトホール(contact hole)(8) を形成する。次い
で、図3に示すように、薄膜トランジスタの一方の画素
領域に、透明電極(9) を形成した後、全面にアルミニウ
ム等の金属を蒸着し、フォトエッチ工程によりコンタク
トホール(8) 部分にのみ残るように選択的に除去して前
記コンタクトホール(8) を介してドレイン領域(6b)と透
明電極(9) とが連結されるようにし、ソース領域(6a)と
データライン(図示せず)とが連結されるようにソース
/ドレイン電極(10)を形成して従来の液晶表示素子を製
造した。
Next, as shown in FIG. 2C, an interlayer insulating film is formed.
Then, (7) is deposited and the interlayer insulating film (7) is selectively etched so that the source / drain regions (6a) and (6b) are exposed to form contact holes (8). Next, as shown in FIG. 3, a transparent electrode (9) is formed in one pixel area of the thin film transistor, a metal such as aluminum is deposited on the entire surface, and a photoetching process leaves only the contact hole (8). As described above, the drain region (6b) and the transparent electrode (9) are connected to each other through the contact hole (8), and the source region (6a) and the data line (not shown) are connected to each other. A conventional liquid crystal display device was manufactured by forming a source / drain electrode 10 so as to be connected to each other.

【0007】このように製造された従来の液晶表示素子
の動作について説明する。ゲート電極(5a)にしきい値電
圧以上の電圧を印加すると、ゲート絶縁膜(4) と活性層
(3a)との界面にチャネル(channel) が形成され、この時
データライン(data line) に信号電圧が印加されるとソ
ース領域とドレーン領域とが導通せしめられて信号電圧
を透明電極(9) に伝達して表示(ディスプレイ)させ
る。
The operation of the conventional liquid crystal display device manufactured as described above will be described. When a voltage higher than the threshold voltage is applied to the gate electrode (5a), the gate insulating film (4) and the active layer are
A channel is formed at the interface with (3a), and when a signal voltage is applied to the data line at this time, the source region and the drain region are made conductive and the signal voltage is transmitted to the transparent electrode (9). It is transmitted to and displayed (display).

【0008】[0008]

【発明が解決しようとする課題】しかしながら、従来の
液晶表示素子の製造方法には次のような問題がある。 コンタクトホール(8) を介してソース/ドレイン領
域(6a),(6b)にソース/ドレイン電極(10)を連結するの
で、ソース/ドレイン領域(6a),(6b)とソース/ドレイ
ン電極(10)との接触抵抗を制御しにくい。 ソース/ドレイン電極(10)の形成の際、アルミニウ
ムを蒸着し感光膜を塗布して露光及び現像する場合、現
像液の電解質がアルミニウムの塚(hillock)に沿って前
記透明電極(9) と接触して電流効果(Galvanin Effect)
によりアルミニウムのエッチング時の際、透明電極(9)
までも一緒にエッチングされる可能性があるので、断線
及び透明電極パターン形成が不完全になる。 ソース/ドレイン電極(10)を形成する際、データラ
インまでも一緒に、アルミニウムの単層(sigle layer)
で形成するので、データラインが断線される可能性があ
るため、信頼度が低くなる。 本発明の目的は、上記問題点を解決するためのもので、
データライン及びソース/ドレイン電極を高濃度のn型
半導体層及び金属で形成して透明電極の電流効果(Galv
anin Effect)を防止し、ソース/ドレインのコンタクト
抵抗を低減し、かつ、接触抵抗の制御を容易化すると共
に、データラインの短絡防止及びオフセット(Off-Set)
構造が可能となるようにした液晶表示素子を提供するに
ある。
However, the conventional method for manufacturing a liquid crystal display device has the following problems. Since the source / drain electrodes (10) are connected to the source / drain regions (6a) and (6b) through the contact holes (8), the source / drain regions (6a) and (6b) and the source / drain electrodes (10) are connected. ) Is difficult to control the contact resistance with. When the source / drain electrodes (10) are formed, when the aluminum film is vapor-deposited and the photosensitive film is applied for exposure and development, the electrolyte of the developer contacts the transparent electrodes (9) along the aluminum hillocks. And current effect (Galvanin Effect)
When etching aluminum, the transparent electrode (9)
Since it may be etched together, disconnection and transparent electrode pattern formation may be incomplete. When forming the source / drain electrodes (10), a single aluminum layer (sigle layer) is used together with the data lines.
Since it is formed by, there is a possibility that the data line may be broken, resulting in low reliability. An object of the present invention is to solve the above problems,
The data line and the source / drain electrodes are formed of a high concentration n-type semiconductor layer and metal, and the current effect of the transparent electrode (Galv
anin effect), source / drain contact resistance is reduced, contact resistance is easily controlled, and data line short-circuit prevention and offset (Off-Set)
An object of the present invention is to provide a liquid crystal display device that can be structured.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明によれば、透明基板上にバッファ層を形成
し、バッファ層上の薄膜トランジスタ領域に活性層を形
成する工程と、活性層上にゲート絶縁膜、ゲート電極及
びゲートラインを形成する工程と、ゲート電極をマスク
として活性層に不純物イオンを注入することにより、ソ
ース/ドレイン領域を形成する工程と、全面に絶縁膜を
蒸着しソース/ドレイン領域上にコンタクトホールを形
成し、画素領域の絶縁膜上に透明電極を形成する工程
と、全面に高濃度の不純物がドーピングされた半導体層
及び金属を蒸着し、この半導体層及び金属を選択的にエ
ッチングしてソース領域に連結されるようにソース電極
及びデータラインを形成し、ドレイン領域と透明電極と
が連結されるようにドレイン電極を形成する工程と、を
含む。
In order to achieve the above object, according to the present invention, a step of forming a buffer layer on a transparent substrate and forming an active layer in a thin film transistor region on the buffer layer; A step of forming a gate insulating film, a gate electrode and a gate line on the upper surface; a step of forming source / drain regions by implanting impurity ions into the active layer using the gate electrode as a mask; and an insulating film deposited on the entire surface. A step of forming a contact hole on the source / drain region and forming a transparent electrode on the insulating film of the pixel region, and a semiconductor layer and a metal doped with a high concentration of impurities are vapor-deposited on the entire surface. To selectively form a source electrode and a data line to be connected to the source region and to connect a drain region and the transparent electrode. And forming an in-electrode.

【0010】[0010]

【実施例】以下、本発明の液晶表示素子の製造方法を図
面に基づいて詳述する。図4乃至図7は本発明のトップ
ゲート型多結晶シリコン薄膜トランジスタの液晶表示素
子の製造方法を示す工程図である。本発明の液晶表示素
子の製造方法は先ず、図4(a) に示すように、透明ガラ
ス基板(1) に接着力のすぐれたバッファ層(2) を形成
し、バッファ層(2) 上に半導体層(3) を形成する。次
に、図4(b) に示すように、半導体層(3) をフォトエッ
チ工程を利用して薄膜トランジスタ形成領域にのみ残る
ように選択的に除去して活性層(3a)を形成する。次に、
図5(a) に示すように、全面にゲート絶縁膜(4) 及び金
属層(5) を順次蒸着し、続いて、図5(b) に示すよう
に、金属層(5) 及びゲート絶縁膜(4) を選択的に除去し
て活性層(3a)上にゲート電極(5a)及びゲートライン(5b)
を形成する。ここで、ゲートライン(5b)は他の画素の薄
膜トランジスタ駆動用ゲートライン(5b)である。次に、
図5(c) に示すように、ゲート電極(5a)をマスクとして
活性層(3a)に高濃度のn型イオンを注入し熱処理して薄
膜トランジスタのソース/ドレイン領域(6a),(6b)を形
成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a liquid crystal display device of the present invention will be described in detail below with reference to the drawings. 4 to 7 are process diagrams showing a method of manufacturing a liquid crystal display device of a top gate type polycrystalline silicon thin film transistor according to the present invention. In the method for manufacturing a liquid crystal display device of the present invention, first, as shown in FIG. 4 (a), a buffer layer (2) having excellent adhesion is formed on a transparent glass substrate (1), and the buffer layer (2) is formed on the buffer layer (2). A semiconductor layer (3) is formed. Next, as shown in FIG. 4B, the active layer 3a is formed by selectively removing the semiconductor layer 3 so as to remain only in the thin film transistor forming region by using a photoetching process. next,
As shown in FIG. 5 (a), a gate insulating film (4) and a metal layer (5) are sequentially deposited on the entire surface, and then, as shown in FIG. 5 (b), a metal layer (5) and a gate insulating layer are formed. The gate electrode (5a) and gate line (5b) are formed on the active layer (3a) by selectively removing the film (4).
To form. Here, the gate line (5b) is a thin film transistor driving gate line (5b) of another pixel. next,
As shown in FIG. 5 (c), the source / drain regions (6a) and (6b) of the thin film transistor are formed by implanting high-concentration n-type ions into the active layer (3a) using the gate electrode (5a) as a mask and heat-treating. Form.

【0011】次に、図6(a) に示すように、層間絶縁膜
(7) を蒸着し前記ソース/ドレイン領域(6a),(6b)が露
出されるように層間絶縁膜(7) を選択的にエッチングし
てコンタクトホール(8) を形成する。次いで、図6(b)
に示すように、薄膜トランジスタの一方の画素領域に、
透明電極(9) を形成する。
Next, as shown in FIG. 6A, an interlayer insulating film is formed.
Then, (7) is deposited and the interlayer insulating film (7) is selectively etched so that the source / drain regions (6a) and (6b) are exposed to form contact holes (8). Then, FIG. 6 (b)
As shown in, in one pixel area of the thin film transistor,
A transparent electrode (9) is formed.

【0012】次に、図6(c) に示すように、コンタクト
ホール(8) を介して、ソース/ドレイン領域(6a),(6b)
が連結されるように、全面にn型不純物の高濃度でドー
ピングされたポリシリコン(11)とアルミニウム(Al)等の
金属を順次蒸着し、その上に感光膜(13)を塗布した後ソ
ース/ドレイン電極のパターンマスクを利用して露光及
び現像してソース/ドレイン領域を定める(define)。
Next, as shown in FIG. 6 (c), the source / drain regions (6a), (6b) are formed through the contact holes (8).
So that they are connected to each other, a polysilicon (11) doped with a high concentration of n-type impurities and a metal such as aluminum (Al) are sequentially deposited on the entire surface, and then a photosensitive film (13) is applied thereon and then the source is formed. A source / drain region is defined by exposing and developing using a pattern mask of the / drain electrode.

【0013】次に、図7に示すように、定めた感光膜(1
3)をマスクとして前記金属層(12)及びポリシリコン(11)
層を選択的に除去して、前記コンタクトホール(8) を介
して、ソース領域(6a)と連結されるように金属(12a) と
ポリシリコン(11a) とが積層されたソース電極及びデー
タライン(図示せず)を形成し、かつ、コンタクトホー
ル(8) を介して、ドレイン領域(6b)と透明電極(9) とが
連結されるように金属(12b) とポリシリコン(11b) とが
積層されたドレイン電極を形成した後、感光膜(13)を除
去することにより本発明の液晶表示素子を製造する。こ
のようにして製造された本発明の液晶表示素子の動作は
従来と同様である。
Next, as shown in FIG. 7, the photosensitive film (1
The metal layer (12) and polysilicon (11) using 3) as a mask
By selectively removing the layer, the source electrode and the data line in which the metal (12a) and the polysilicon (11a) are laminated so as to be connected to the source region (6a) through the contact hole (8). (Not shown), and the metal (12b) and polysilicon (11b) are connected so that the drain region (6b) and the transparent electrode (9) are connected through the contact hole (8). After forming the stacked drain electrodes, the photosensitive film (13) is removed to manufacture the liquid crystal display device of the present invention. The operation of the liquid crystal display device of the present invention manufactured in this manner is the same as that of the conventional one.

【0014】[0014]

【発明の効果】以上説明したように、本発明の液晶表示
素子の製造方法は、高濃度のn型でドーピングされた多
結晶シリコンとアルミニウム等の金属を連続蒸着した
後、その上に感光膜を塗布し露光及び現像するので、感
光膜を現像する際、現像液の電解質がアルミニウムの塚
に沿って下がっても、前記多結晶シリコンが阻止膜(blo
cking later)の役割をして現像液の電解質が透明電極
(9) と接触することができないので電流効果を防止する
こととなり、ソース/ドレイン領域(6a),(6b)に高濃度
のn型ドーピングされた多結晶シリコンが直接接触され
るので、接触抵抗が低減され、接触抵抗の制御も容易化
される。
As described above, according to the method of manufacturing a liquid crystal display device of the present invention, high-concentration n-type doped polycrystalline silicon and a metal such as aluminum are continuously vapor-deposited, and then a photosensitive film is formed thereon. When the photosensitive film is developed, even if the electrolyte of the developer drops along the aluminum mound, the polycrystalline silicon is blocked by the blocking film.
The electrolyte of the developer plays the role of cking later) and the transparent electrode
Since it cannot contact with (9), the current effect is prevented, and the high-concentration n-type doped polycrystalline silicon is directly contacted with the source / drain regions (6a) and (6b). Is reduced and control of contact resistance is facilitated.

【0015】データラインは金属層のシングルラインで
はなく高濃度のn型ドーピングされた多結晶シリコンと
金属層を積層形成したソース/ドレイン電極及びデータ
ライン(11)の二重構造を採用することにより短絡を防止
し、かつ、セットオフ構造が可能となる効果がある。
The data line is not a single line of a metal layer, but a double structure of a source / drain electrode and a data line (11) in which a high-concentration n-type doped polycrystalline silicon and a metal layer are laminated. There is an effect that a short circuit is prevented and a set-off structure is possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来のトップゲート型多結晶シリコン薄膜トラ
ンジスタの液晶表示素子の製造方法を示す工程図。
FIG. 1 is a process drawing showing a conventional method for manufacturing a liquid crystal display element of a top gate type polycrystalline silicon thin film transistor.

【図2】従来のトップゲート型多結晶シリコン薄膜トラ
ンジスタの液晶表示素子の製造方法を示す工程図。
FIG. 2 is a process drawing showing a method for manufacturing a conventional liquid crystal display device of a top gate type polycrystalline silicon thin film transistor.

【図3】従来のトップゲート型多結晶シリコン薄膜トラ
ンジスタの液晶表示素子の製造方法を示す工程図。
FIG. 3 is a process diagram showing a method of manufacturing a conventional top gate type polycrystalline silicon thin film transistor liquid crystal display element.

【図4】本発明のトップゲート型多結晶シリコン薄膜ト
ランジスタの液晶表示素子の製造方法を示す工程図。
FIG. 4 is a process drawing showing a method of manufacturing a liquid crystal display element of a top gate type polycrystalline silicon thin film transistor of the present invention.

【図5】本発明のトップゲート型多結晶シリコン薄膜ト
ランジスタの液晶表示素子の製造方法を示す工程図。
FIG. 5 is a process drawing showing a method of manufacturing a liquid crystal display element of a top gate type polycrystalline silicon thin film transistor of the present invention.

【図6】本発明のトップゲート型多結晶シリコン薄膜ト
ランジスタの液晶表示素子の製造方法を示す工程図。
FIG. 6 is a process drawing showing a method of manufacturing a liquid crystal display element of a top gate type polycrystalline silicon thin film transistor of the present invention.

【図7】本発明のトップゲート型多結晶シリコン薄膜ト
ランジスタの液晶表示素子の製造方法を示す工程図。
FIG. 7 is a process drawing showing a method of manufacturing a liquid crystal display element of a top gate type polycrystalline silicon thin film transistor of the present invention.

【符号の説明】 1 透明ガラス基板 2 バッファ層 3 半導体層 3a 活性層 4 ゲート絶縁膜 5 金属層 5a ゲート電極 5b ゲートライン 6a ソース領域 6b ドレイン領域 7 層間絶縁膜 8 コンタクトホール 9 透明電極 10 ソース/ドレイン電極 11,11a ポリシリコン 12 金属層 12a 金属 13 感光膜[Description of Reference Signs] 1 transparent glass substrate 2 buffer layer 3 semiconductor layer 3a active layer 4 gate insulating film 5 metal layer 5a gate electrode 5b gate line 6a source region 6b drain region 7 interlayer insulating film 8 contact hole 9 transparent electrode 10 source / Drain electrode 11, 11a Polysilicon 12 Metal layer 12a Metal 13 Photosensitive film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】透明基板(1) 上にバッファ層(2) を形成
し、前記バッファ層(2) 上の薄膜トランジスタ領域に活
性層(3a)を形成する工程と、 前記活性層(3a)上にゲート絶縁膜(4) 、ゲート電極(5a)
及びゲートライン(5b)を形成する工程と、 前記ゲート電極(5a)をマスクとして前記活性層(3a)に不
純物イオンを注入することにより、ソース/ドレイン領
域(6a),(6b)を形成する工程と、 全面に絶縁膜(7) を蒸着し、ソース/ドレイン領域上に
コンタクトホール(8)を形成し、画素領域の前記絶縁膜
(7) 上に透明電極(9) を形成する工程と、 全面に高濃度の不純物がドーピングされた半導体層及び
金属を蒸着し、この半導体層及び金属を選択的にエッチ
ングしてソース領域に連結されるようにソース電極及び
データラインを形成し、前記ドレイン領域(6b)と前記透
明電極(9) とが連結されるようにドレイン電極を形成す
る工程と、 を含むことを特徴とする液晶表示素子の製造方法。
1. A step of forming a buffer layer (2) on a transparent substrate (1) and forming an active layer (3a) in a thin film transistor region on the buffer layer (2), and on the active layer (3a). Gate insulating film (4), gate electrode (5a)
And a step of forming a gate line (5b), and by implanting impurity ions into the active layer (3a) using the gate electrode (5a) as a mask, source / drain regions (6a) and (6b) are formed. Process and insulating film (7) is vapor-deposited on the entire surface, contact holes (8) are formed on the source / drain regions, and the insulating film in the pixel region is formed.
(7) A step of forming a transparent electrode (9) on the upper surface, and a semiconductor layer and a metal doped with a high concentration of impurities are vapor-deposited on the entire surface, and the semiconductor layer and the metal are selectively etched and connected to the source region. Forming a source electrode and a data line as described above, and forming a drain electrode so that the drain region (6b) and the transparent electrode (9) are connected to each other. Device manufacturing method.
【請求項2】前記半導体層を、高濃度のn型不純物がド
ーピングされた多結晶シリコンで形成することを特徴と
する請求項1記載の液晶表示素子の製造方法。
2. The method of manufacturing a liquid crystal display device according to claim 1, wherein the semiconductor layer is formed of polycrystalline silicon doped with a high concentration of n-type impurities.
JP34635193A 1992-12-22 1993-12-22 Manufacture of liquid crystal display device Pending JPH06295924A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019920025127A KR100268007B1 (en) 1992-12-22 1992-12-22 Fabrication method of lcd
KR1992-25127 1992-12-22

Publications (1)

Publication Number Publication Date
JPH06295924A true JPH06295924A (en) 1994-10-21

Family

ID=19346313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34635193A Pending JPH06295924A (en) 1992-12-22 1993-12-22 Manufacture of liquid crystal display device

Country Status (3)

Country Link
US (1) US5429962A (en)
JP (1) JPH06295924A (en)
KR (1) KR100268007B1 (en)

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US5429962A (en) 1995-07-04
KR940015562A (en) 1994-07-21

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