KR0174032B1 - Tft for lcd - Google Patents
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- KR0174032B1 KR0174032B1 KR1019940031943A KR19940031943A KR0174032B1 KR 0174032 B1 KR0174032 B1 KR 0174032B1 KR 1019940031943 A KR1019940031943 A KR 1019940031943A KR 19940031943 A KR19940031943 A KR 19940031943A KR 0174032 B1 KR0174032 B1 KR 0174032B1
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- gate electrode
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- high concentration
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- thin film
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- 239000010408 film Substances 0.000 claims abstract description 40
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 액정표시장치용 박막 트랜지스터 및 그 제조방법에 관한 것으로서, 투명기판상에 하측 게이트전극과 게이트절연막을 형성하고, 그 상부에 비정질실리콘으로된 반도체층 패턴을 형성하며, 상기 반도체층 패턴의 양측에 오옴믹 접촉을 위한 고농도 불순물층을 후면 노광으로 형성되는 감광막패턴을 마스크로 형성한 후, 그 상측에도 게이트절연막과 상측 게이트전극을 형성하여 TFT의 채널폭을 증가시켰으므로, TFT의 크기를 감소시켜 개구율을 향상시키고, 동일한 면적의 TFT에서는 소자동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor for a liquid crystal display device and a method of manufacturing the same, wherein a lower gate electrode and a gate insulating film are formed on a transparent substrate, and a semiconductor layer pattern made of amorphous silicon is formed thereon, Since the photoresist pattern formed by the back exposure is formed with a high concentration impurity layer for ohmic contact on both sides as a mask, a gate insulating film and an upper gate electrode are formed on the upper side to increase the channel width of the TFT. The aperture ratio can be reduced to improve the reliability, and the reliability of device operation can be improved in TFTs having the same area.
Description
제1도는 종래 기술에 따른 액정표시장치용 박막 트랜지스터를 설명하기 위한 레이아웃도.1 is a layout for explaining a thin film transistor for a liquid crystal display device according to the prior art.
제2도는 제1도에서의 선 A-A에 따른 단면도.2 is a cross-sectional view taken along the line A-A in FIG.
제3도는 본 발명에 따른 액정표시장치용 박막 트랜지스터를 설명하기 위한 레이아웃도.3 is a layout for explaining a thin film transistor for a liquid crystal display device according to the present invention.
제4도는 제3도에서의 선 C-C에 따른 단면도.4 is a cross-sectional view taken along the line C-C in FIG.
제5도는 제3도에서의 선 B-B에 따른 단면도.5 is a cross-sectional view taken along the line B-B in FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 투명기판 2 : 게이트전극1 transparent substrate 2 gate electrode
3 : 게이트절연막 4 : 반도체층3: gate insulating film 4: semiconductor layer
5 : 에칭 스토퍼 6 : 고농도 불순물층5: etching stopper 6: high concentration impurity layer
7 : 필드산화막 8 : 콘택홀7: field oxide film 8: contact hole
9 : 소오스전극 10 : 드레인전극9 source electrode 10 drain electrode
11 : 게이트라인 12 : 데이터라인11 gate line 12 data line
13 : 화소전극13: pixel electrode
본 발명은 액정표시장치(Liquid Crystal Display; 이하 LCD라 칭함)용 박막 트랜지스터(thin film transistor; 이하 TFT라 칭함) 및 그 제조방법에 관한 것으로서, 특히 반도체층 패턴의 상하로 게이트 라인과 연결되는 게이트 전극을 이층으로 형성하여 LCD의 개구율을 향상시키고, 고정세화에 유리하며 소자동작의 신뢰성을 향상시킬 수 있는 LCD용 TFT 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor for a liquid crystal display (hereinafter referred to as LCD) and a method of manufacturing the same, and in particular, a gate connected to a gate line above and below a semiconductor layer pattern. The present invention relates to a TFT for an LCD and a method of manufacturing the same, by forming an electrode in two layers to improve the aperture ratio of the LCD, to improve definition, and to improve the reliability of device operation.
평판표시장치(flat pannel display)의 일종인 LCD는 액체의 유동성과 결정의 광학적 성질을 겸비하는 액정에 전계를 가하여 광학적 이방성을 변화시키는 장치로서, 종래 음극선관(Cathode Ray Tube)에 비해 소비전력이 낮고, 부피가 작으며, 대형화 및 고정세화가 가능하여 널리 사용되고 있다.LCD, which is a kind of flat pannel display, is a device that changes the optical anisotropy by applying electric field to liquid crystal that combines liquidity and optical properties of crystal, and consumes more power than conventional cathode ray tube. Its low volume, small size, large size and high definition make it widely used.
일반적으로 LCD는 화소전극이 형성되어 스위칭 소자와 연결되어 있는 하측 액정기판과 공통전극이 형성되어 있는 상측 액정기판의 사이에 액정이 밀봉되어 있는 형태로 구성된다.In general, LCDs are configured in such a manner that liquid crystal is sealed between a lower liquid crystal substrate having pixel electrodes formed therein and connected to a switching element, and an upper liquid crystal substrate having common electrodes formed thereon.
종래 LCD의 제조방법을 살펴보면 다음과 같다.Looking at the manufacturing method of the conventional LCD is as follows.
먼저, 석영재질의 투명기판상에 인듐.틴.옥사이드(indum thin oxide; 이하 ITO라 칭함)로된 화소전극과 투명전극 패턴을 형성하고, 상기 투명전극 패턴의 단락을 방지하기 위한 보호막과 액정을 배열시키기 위한 배향막을 순차적으로 형성한다.First, a pixel electrode made of indium thin oxide (ITO) and a transparent electrode pattern are formed on a transparent substrate made of quartz, and a protective film and a liquid crystal are formed to prevent a short circuit of the transparent electrode pattern. Alignment films for aligning are formed sequentially.
그다음 상기 배향막에 방향성을 주기 위하여 원통형의 코아에 천이 감겨 있는 러빙 롤을 사용하여 배향막에 일정한 방향성을 갖는 골들을 형성하는 러빙을 실시하여 하측 액정기판을 완성한다.Then, a rubbing is performed to form valleys having a certain directionality in the alignment layer by using a rubbing roll wound around a cylindrical core to give the alignment layer a direction, thereby completing the lower liquid crystal substrate.
그후, 공통전극을 갖는 상측 액정기판을 형성한 후, 상기 상.하측 액정기판을 일정한 셀겝을 갖도록 스페이서 및 실패턴을 형성하여 봉합시키고, 셀겝에 액정을 주입한 후, 밀봉하여 LCD를 완성한다.Thereafter, after forming an upper liquid crystal substrate having a common electrode, the upper and lower liquid crystal substrates are sealed by forming spacers and a failure turn so as to have a constant cell height, injecting liquid crystal into the cell cell, and sealing to complete the LCD.
상기와 같은 통상의 LCD는 사용되는 액정의 종류나 구동 방법등에 의해 티.엔(Twisted Nematic), 에스.티.엔(Super Twisted Nematic), 강유전성(Ferroelectric) 및 TEF LCD등으로 구분된다.Conventional LCDs as described above are classified into T. ne (Twisted Nematic), S. T. (Super Twisted Nematic), Ferroelectric, TEF LCD, etc., depending on the type of liquid crystal used and the driving method.
여기서 TFT를 화소 동작의 스위칭 소자로 사용하는 TFT LCD는 다른 종류의 LCD에 비해 응답속도가 빠르고, 넓은 시야각을 가지며, 대화면화, 고정세화 및 고화질화가 가능하여 휴대용 TV나 랩탑 PC등에 널리 사용되고 있다.TFT LCDs using TFTs as switching elements for pixel operation have faster response speed, wider viewing angles, and larger screens, higher definitions, and higher definitions than other types of LCDs.
이러한 TFT의 구조는 크게 반도체층 패턴인 활성층의 위치에 따라 구별할 수 있다. 즉 반도체층을 사이에 두고 게이트 전극과 소오스/드레인 전극이 분리되어 있는 스테거드(staggered)형과 반도체층의 일면에 게이트 전극과 소오스/드레인 전극이 형성되어 있는 코플라나(coplanar)형으로 나눈다.The structure of such a TFT can be largely distinguished according to the position of an active layer which is a semiconductor layer pattern. In other words, the semiconductor layer is divided into a staggered type in which the gate electrode and the source / drain electrode are separated, and a coplanar type in which the gate electrode and the source / drain electrode are formed on one surface of the semiconductor layer.
그러나 상기의 TFT LCD는 화소의 일측에 TFT 소자를 형성하여야하고 소자를 동작시키기 위하여 게이트 버스 및 데이터 버스선을 배치하여야 하므로 화소의 개구율이 떨어지는 문제점이 있다.However, in the TFT LCD, a TFT element must be formed on one side of the pixel, and a gate bus and a data bus line must be disposed to operate the element, thereby causing a problem that the aperture ratio of the pixel is lowered.
특히 비정질 실리콘을 채널로 사용하는 TFT는 다결정실리콘층을 채널로 사용하는 경우 보다 전하 이동도가 떨어지므로 채널폭을 크게 형성하여야 하며, 따라서 개구율은 더욱 나빠진다.In particular, the TFT using amorphous silicon as a channel has a lower charge mobility than the case of using a polysilicon layer as a channel, so that the channel width must be made larger, and thus the aperture ratio becomes worse.
제1도 및 제2도는 종래 기술에 따른 LCD용 TFT를 설명하기 위한 도면들로서, 스테거드형 TFT의 예이며, 서로 연관시켜 설명한다.1 and 2 are diagrams for explaining the TFT for LCD according to the prior art, which is an example of a staggered TFT, and will be described in association with each other.
먼저, 투명기판(1)상에 금속 패턴으로된 게이트전극(2)이 형성되어 있으며, 상기 구조의 전표면에 산화막으로된 게이트절연막(3)이 형성되어 있다. 이때 상기 게이트전극(2)의 일측은 투명기판(1)에 대해 가로 방향으로 연장되어 있는 게이트 라인(11)과 연결되어 있다.First, a gate electrode 2 having a metal pattern is formed on the transparent substrate 1, and a gate insulating film 3 made of an oxide film is formed on the entire surface of the structure. At this time, one side of the gate electrode 2 is connected to the gate line 11 extending in the horizontal direction with respect to the transparent substrate (1).
또한 상기 게이트전극(2) 상부의 게이트절연막(3) 상에 상기 게이트 전극(2)과 중앙부분이 중첩되는 직사각 형상의 반도체층(4) 패턴이 비정질 실리콘으로 형성되어 있으며, 상기 게이트전극(2) 상측의 반도체층(4) 패턴 상에는 산화막 또는 질화막 패턴으로된 에칭 스토퍼(5)가 형성되어 있다.In addition, a rectangular semiconductor layer 4 pattern in which a center portion overlaps with the gate electrode 2 is formed of amorphous silicon on the gate insulating layer 3 on the gate electrode 2, and the gate electrode 2 is formed. On the upper semiconductor layer 4 pattern, an etching stopper 5 formed of an oxide film or a nitride film pattern is formed.
또한 상기 에칭 스토퍼(5)에 의해 노출되어 있는 반도체층(4) 패턴상에는 고농도 불순물층(6)이 형성되어 있으며, 상기 구조의 전표면에 필드산화막(7)이 형성되어 있다.A high concentration impurity layer 6 is formed on the semiconductor layer 4 pattern exposed by the etching stopper 5, and a field oxide film 7 is formed on the entire surface of the structure.
또한 상기 고농도 불순물층(6)들중의 양측 일부를 콘택홀(8)이 노출시키고 있으며, 각측의 고농도 불순물층(6)과 접촉되는 소오스전극(9) 및 드레인전극(10)이 각각 형성되어 있고, 상기 소오스전극(8) 및 드레인전극(10)은 각각 세로 방향으로 연장되어 있는 데이터 라인(12) 및 투명전극으로된 화소전극(13)과 연결된다.In addition, contact holes 8 expose portions of both sides of the high concentration impurity layers 6, and source and drain electrodes 10 and 10 contacting the high concentration impurity layers 6 on each side are formed, respectively. The source electrode 8 and the drain electrode 10 are connected to the data line 12 and the pixel electrode 13 made of a transparent electrode, respectively, extending in the vertical direction.
상기와 같은 종래의 비정질 실리콘층을 채널로 사용하는 LCD용 TFT는 채널을 폭을 감소시키기 어려워 TFT를 크게 형성하여 하므로, LCD의 개구율이 떨어지는 문제점이 있다.The LCD TFT using the conventional amorphous silicon layer as the channel is difficult to reduce the width of the channel to form a large TFT, there is a problem that the aperture ratio of the LCD falls.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 비정질 실리콘층 패턴의 상하 측면에 금속 게이트전극을 형성하여 TFT의 크기를 감소시켜 개구율을 향상시킬 수 있는 LCD용 TFT를 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a TFT for LCD which can improve the aperture ratio by reducing the size of the TFT by forming metal gate electrodes on the upper and lower sides of the amorphous silicon layer pattern. have.
본 발명의 다른 목적은 투명기판상에 하측 게이트전극과 게이트절연막을 형성하고, 상기 하측 게이트전극과 중앙부분이 중첩되는 비정질실리콘층 패턴을 형성하고, 그상측에 다시 게이트 절연막과 상측 게이트전극을 형성하여 채널의 폭을 증가시켜 TFT의 크기를 작게하여 개구율을 향상시킬 수 있는 LCD용 TFT의 제조방법을 제공함에 있다.Another object of the present invention is to form a lower gate electrode and a gate insulating film on a transparent substrate, form an amorphous silicon layer pattern overlapping the lower gate electrode and a center portion, and form a gate insulating film and an upper gate electrode on the upper side again. By increasing the width of the channel to reduce the size of the TFT to provide an LCD manufacturing method that can improve the aperture ratio.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 LCD용 TFT의 특징은, 투명기판상에 형성되어있는 제 1 게이트전극과, 상기 구조의 전표면에 형성되어 있는 제 1 게이트절연막과, 상기 제 1 게이트전극과 중첩되고 양측으로 연장되도록 제 1 게이트절연막상에 형성되어 있는 반도체층 패턴과, 상기 제 1 게이트전극 양측 상부의 반도체층 패턴에 형성되어있는 고농도 불순물층과, 상기 구조의 전표면에 형성되어 있는 제 2 게이트절연막과, 상기 제 1 게이트전극과 중첩되도록 제 2 게이트절연막상에 형성되고 일측이 콘택홀을 통하여 상기 제 1 게이트전극과 연결되는 제 2 게이트전극과, 상기 양측 고농도 불순물층의 일측 상부의 상기 제 2 및 제 1 게이트절연막이 순차적으로 제거되어 상기 고농도 불순물층을 노출시키는 콘택홀들과, 상기 콘택홀을 통하여 상기 고농도 불순물층과 접촉되는 소오스/드레인전극을 구비함에 있다.The LCD TFT according to the present invention for achieving the above object is characterized in that the first gate electrode formed on the transparent substrate, the first gate insulating film formed on the entire surface of the structure, and the first A semiconductor layer pattern formed on the first gate insulating film so as to overlap the gate electrode and extending to both sides, a high concentration impurity layer formed on the semiconductor layer pattern on both sides of the first gate electrode, and the entire surface of the structure A second gate insulating film, a second gate electrode formed on the second gate insulating film so as to overlap the first gate electrode, and having one side connected to the first gate electrode through a contact hole, and the high concentration impurity layers on both sides. Contact holes exposing the high concentration impurity layer by sequentially removing the second and first gate insulating layers on one side and through the contact hole; As is provided with the source / drain electrodes in contact with the high concentration impurity layer.
다른 목적을 달성하기 위한, 본 발명에 따른 LCD용 TFT 제조방법의 특징은 투명기판상에 제 1 게이트전극을 형성하는 공정과, 상기 구조의 전표면에 제 1 게이트절연막을 형성하는 공정과, 상기 제 1 게이트 전극과 중앙부분이 중첩되는 반도체층 패턴을 상기 제 1 게이트절연막상에 형성하는 공정과, 상기 제 1 게이트전극 양측 상부의 반도체층 패턴에 고농도 불순물층을 형성하는 공정과, 상기 구조의 전표면에 제 2 게이트절연막을 형성하는 공정과, 상기 제 1 게이트전극에서 상기 반도체층 패턴과 중첩되지 않는 부분과 상기 양측의 고농도 불순물층의 일측 상부의 제 2 게이트절연막을 제거하여 각각을 노출시키는 콘택들을 형성하는 공정과, 상기 제 1 게이트전극과 중첩되고 콘택홀을 통하여 접촉되는 제 2 게이트전극과 다른 콘택홀을 통하여 고농도 불순물층과 접촉되는 소오스/드레인전극을 형성하는 고정을 구비함에 있다.To achieve another object, a feature of the TFT manufacturing method for an LCD according to the present invention is to form a first gate electrode on a transparent substrate, to form a first gate insulating film on the entire surface of the structure, and Forming a semiconductor layer pattern overlapping a first gate electrode and a central portion on the first gate insulating film, forming a high concentration impurity layer on the semiconductor layer pattern on both sides of the first gate electrode, and Forming a second gate insulating film on an entire surface of the first gate electrode; and removing portions of the first gate electrode not overlapping with the semiconductor layer pattern, and removing the second gate insulating film on one side of the high concentration impurity layer on both sides to expose each of the first gate electrode. Forming a contact and a high concentration through a contact hole different from the second gate electrode overlapping the first gate electrode and contacting through the contact hole; It consists in a fixing to form a source / drain electrode in contact with the impurity layer.
이하, 본 발명에 다른 LCD용 TFT 및 그 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, the TFT for LCD which concerns on this invention, and its manufacturing method are demonstrated in detail with reference to an accompanying drawing.
제3도 내지 제5도는 본 발명에 따른 LCD용 TFT를 설명하기 위한 도면들로서, 서로 연관시켜 구조 및 제조방법을 동시에 설명한다.3 to 5 are diagrams for explaining the TFT for LCD according to the present invention, in which the structure and the manufacturing method are simultaneously described in association with each other.
먼저, 투명재질, 예를들어 석영이나 유리로된 투명기판(1) 상에 가로 방향으로 예정된 폭을 갖고 연장되어 있으며, 일측이 돌출되어 제 1 게이트전극(2A)이 되는 게이트 라인(11)을 Cr, Ti 또는 Al등의 금속패턴으로 형성하고, 상기 구조의 전표면에 산화막 재질의 제 1 게이트절연막(3A)을 형성한다.First, the gate line 11 extending on the transparent substrate 1 made of a transparent material, for example, quartz or glass, has a predetermined width in the horizontal direction, and one side protrudes to become the first gate electrode 2A. It is formed of a metal pattern such as Cr, Ti, or Al, and a first gate insulating film 3A made of an oxide film is formed on the entire surface of the structure.
그다음 상기 제 1 게이트전극(2A)과는 중앙부분에서 중첩되는 반도체층(4) 패턴을 상기 제 1 게이트절연막(3A)상에 직사각 형상의 비정질 실리콘으로 형성하고, 상기 제 1 게이트전극(2A) 양측 상부의 반도체층(4) 패턴에 N 또는 P형 불순물을 이온주입이나 이온 샤워 방법으로 주입하여 고농도 불순물층(6)을 형성한다. 이때 상기 이온주입의 마스크는 상기 제 1 게이트전극(2A)을 마스크로하는 후면 노광방법으로 형성되는 감광막패턴(도시되지 않음)을 사용한다.Subsequently, a pattern of the semiconductor layer 4 overlapping with the first gate electrode 2A at the center portion is formed of amorphous silicon having a rectangular shape on the first gate insulating film 3A, and the first gate electrode 2A is formed. A high concentration impurity layer 6 is formed by implanting N or P-type impurities into the semiconductor layer 4 patterns on both sides by ion implantation or ion showering. In this case, a mask of the ion implantation uses a photoresist pattern (not shown) formed by a backside exposure method using the first gate electrode 2A as a mask.
그후, 상기 구조의 전표면에 산화막 재질의 제 2 게이트절연막(3B)을 형성하고, 상기 제 1 게이트전극(2A)과 접촉되는 게이트라인(11)의 상측과 상기 고농도 불순물층(6)의 양측 상부의 제 2 및 제 1 게이트절연막(3B),(3A)을 순차적으로 제거하여 각각을 노출시키는 콘택홀(8)들을 형성한다. 이때 상기 제 1 및 제 2 게이트절연막(3A),(3B)은 각각 화학기상증착(chemical vapor deposition; 이하 CVD라 칭함) 또는 물리기상증착(physical vapor deposition; 이하 PVD라 칭함) 방법으로 형성된다.Thereafter, a second gate insulating film 3B made of an oxide film is formed on the entire surface of the structure, and an upper side of the gate line 11 in contact with the first gate electrode 2A and both sides of the high concentration impurity layer 6. The upper and second gate insulating layers 3B and 3A are sequentially removed to form contact holes 8 exposing each of them. In this case, the first and second gate insulating films 3A and 3B are formed by chemical vapor deposition (hereinafter referred to as CVD) or physical vapor deposition (hereinafter referred to as PVD).
그다음 상기 제 1 게이트전극(2A)과 중첩되고, 콘택홀(8)에 의해 노출되어 있는 게이트 라인(11)과 접촉되는 제 2 게이트전극(2B)과, 양측의 콘택홀(8)을 통하여 상기 노출되어있는 고농도 불순물층(6)과 접촉되는 소오스전극(9) 및 드레인전극(10)을 Ti, Cr 또는 Al등의 금속 패턴으로 형성한다. 이때 상기 제 2 게이트전극(2B)은 게이트라인(11)과 접촉되지 않고 제 1 게이트전극(2A)의 일측과 접촉될 수도 있으며, 상기 소오스전극(9)은 데이터 라인(12)과 일체로 형성되며, 상기 드레인전극(10)은 투명전극 패턴으로된 화소전극(13)과 접촉된다.Next, the second gate electrode 2B overlaps the first gate electrode 2A and contacts the gate line 11 exposed by the contact hole 8, and the contact hole 8 is formed through both contact holes 8. The source electrode 9 and the drain electrode 10 in contact with the exposed high concentration impurity layer 6 are formed in a metal pattern such as Ti, Cr or Al. In this case, the second gate electrode 2B may not be in contact with the gate line 11 but may be in contact with one side of the first gate electrode 2A, and the source electrode 9 may be integrally formed with the data line 12. The drain electrode 10 is in contact with the pixel electrode 13 having a transparent electrode pattern.
이상에서 설명한 바와 같이, 본 발명에 따른 LCD용 TFT는 투명기판상에 하측 게이트전극과 게이트절연막을 형성하고, 그 상부에 비정질실리콘으로된 반도체층 패턴을 형성하며, 상기 반도체층 패턴의 양측에 오옴믹 접촉을 위한 고농도 불순물층을 후면 노광으로 형성되는 감광막패턴을 마스크로 형성한 후, 그 상측에도 게이트절연막과 상측 게이트전극을 형성하여 TFT의 채널폭을 증가시켰으므로, TFT의 크기를 감소시켜 개구율을 향상시키고, 동일한 면적의 TFT에서는 소자동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the TFT for LCD according to the present invention forms a lower gate electrode and a gate insulating film on a transparent substrate, forms a semiconductor layer pattern of amorphous silicon on the top thereof, and is formed on both sides of the semiconductor layer pattern. After forming a photoresist pattern formed of a high concentration impurity layer for MIC contact by a backside exposure as a mask, a gate insulating film and an upper gate electrode were formed on the upper side thereof to increase the channel width of the TFT. In this case, the TFT having the same area has the advantage of improving the reliability of device operation.
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