KR0146253B1 - Method for manufacturing tft for lcd apparatus - Google Patents
Method for manufacturing tft for lcd apparatusInfo
- Publication number
- KR0146253B1 KR0146253B1 KR1019940031980A KR19940031980A KR0146253B1 KR 0146253 B1 KR0146253 B1 KR 0146253B1 KR 1019940031980 A KR1019940031980 A KR 1019940031980A KR 19940031980 A KR19940031980 A KR 19940031980A KR 0146253 B1 KR0146253 B1 KR 0146253B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000010408 film Substances 0.000 claims abstract description 63
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 액정표시장치용 박막트랜지스터의 제조방법에 관한 것으로서, 투명기판상에 소오스/드레인전극을 형성하고, 상기 소오스/드레인전극을 제외한 투명기판상에 완충막 패턴을 형성하여 상부 표면을 평탄하게 한 후, 소오스/드레인전극 및 그 양측의 완충막 패턴상에 채널이 되는 반도체층 패턴을 형성하고, 후속 공정을 진행하여 스테거드형 TFT를 형성하였으므로, 소오스/드레인전극과 게이트전극의 경계 부분에서 단차가 커지지 않으므로 게이트산화막이나 필드산화막이 얇아져 배선들이 단락되는 것을 방지할 수 있어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor for a liquid crystal display device, wherein a source / drain electrode is formed on a transparent substrate, and a buffer layer pattern is formed on the transparent substrate except for the source / drain electrode to make the top surface flat. After that, a semiconductor layer pattern serving as a channel was formed on the source / drain electrodes and the buffer film patterns on both sides thereof, and a subsequent step was performed to form a staggered TFT. Therefore, at the boundary between the source / drain electrodes and the gate electrode, Since the step difference is not large, the gate oxide film or the field oxide film is thinned to prevent the wirings from being shorted, thereby improving process yield and reliability of device operation.
Description
제1a도 내지 제1c도는 종래 기술의 일실시예에 따른 액정표시장치용 박막트랜지스터의 제조공정도.1A to 1C are manufacturing process diagrams of a thin film transistor for a liquid crystal display according to an embodiment of the prior art.
제2a도 내지 제2c도는 본 발명에 따른 액정표시장치용 박막트랜지스터의 제조공정도.2a to 2c is a manufacturing process diagram of a thin film transistor for a liquid crystal display device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:투명기판 2:절연막1: transparent substrate 2: insulation film
3:소오스/드레인전극 4:반도체층3: source / drain electrode 4: semiconductor layer
5:게이트산화막 6:게이트전극5: gate oxide film 6: gate electrode
7:고농도 불순물 반도체층 8:필드산화막7: High concentration impurity semiconductor layer 8: Field oxide film
9:콘택홀 10:금속배선9: contact hole 10: metal wiring
11:완충막 12:감광막패턴11: buffer film 12: photoresist pattern
본 발명은 액정표시장치(Liquid Crystal Display; 이하 LCD라 칭함)용 박막트랜지스터(thin film transistor; 이하 TFT라 칭함)의 제조방법에 관한 것으로서, 특히 반도체층 패턴의 양측면에 게이트전극과 소오스/드레인전극이 형성되는 스테거드(staggerd)형 TFT에서 소오스/드레인전극을 감싸는 절연막 패턴을 형성하고, 그 상부에 반도체층 패턴과 게이트산화막 및 게이트전극을 형성하여 후속 적층막들의 단차피복성을 향상시키고 배선간의 단락을 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 LCD용 TFT의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor (hereinafter referred to as TFT) for a liquid crystal display (hereinafter referred to as LCD), and in particular, gate electrodes and source / drain electrodes on both sides of a semiconductor layer pattern. An insulating film pattern surrounding the source / drain electrodes is formed in the formed staggered TFT, and a semiconductor layer pattern, a gate oxide film, and a gate electrode are formed thereon to improve step coverage of the subsequent stacked films, and The present invention relates to a manufacturing method of a TFT for an LCD which can prevent a short circuit and improve process yield and device operation reliability.
평판표시장치(flat pannel display)의 일종인 LCD는 액체의 유동성과 결정의 광학적 성질을 겸비하는 액정에 전계를 가하여 광학적 이방성을 변화시키는 장치로서, 종래 음극선관(Cathode Ray Tube)에 비해 소비전력이 낮고, 부피가 작으며, 대형화 및 고정세화가 가능하여 널리 사용되고 있다.LCD, which is a kind of flat pannel display, is a device that changes the optical anisotropy by applying electric field to liquid crystal that combines liquidity and optical properties of crystal, and consumes more power than conventional cathode ray tube. Its low volume, small size, large size and high definition make it widely used.
일반적으로 LCD는 화소전극이 형성되어 스위칭 소자와 연결되어 있는 하측 액정기판과 공통전극이 형성되어 있는 상측 액정기판의 사이에 액정이 밀봉되어 있는 형태로 구성된다.In general, LCDs are configured in such a manner that liquid crystal is sealed between a lower liquid crystal substrate having pixel electrodes formed therein and connected to a switching element, and an upper liquid crystal substrate having common electrodes formed thereon.
종래 LCD의 제조방법을 살펴보면 다음과 같다.Looking at the manufacturing method of the conventional LCD is as follows.
먼저, 석영재질의 투명기판상에 인듐.틴.옥사이드(indum thin oxide; 이하 ITO라 칭함)로된 화소전극과 투명전극 패턴을 형성하고, 상기 투명전극 패턴의 단락을 방지하기 위한 보호막과 액정을 배열시키기 위한 배향막을 순차적으로 형성한다.First, a pixel electrode made of indium thin oxide (ITO) and a transparent electrode pattern are formed on a transparent substrate made of quartz, and a protective film and a liquid crystal are formed to prevent a short circuit of the transparent electrode pattern. Alignment films for aligning are formed sequentially.
그다음 상기 배향막에 방향성을 주기 위하여 원통형의 코아에 천이 감겨있는 러빙 롤을 사용하여 러빙을 실시한 후, 보호막과 칼라필터등을 형성하여 하측 액정기판을 완성한다.Then, after rubbing is carried out using a rubbing roll wound around a cylindrical core to give the alignment layer a direction, a protective film, a color filter, and the like are formed to complete the lower liquid crystal substrate.
그후, 공통전극을 갖는 상측 액정기판을 형성한 후, 상기 상.하측 액정기판을 일정한 셀갭을 갖도록 스페이서 및 실패턴을 형성하여 봉합시키고, 셀갭에 액정을 주입하고, 밀봉하여 LCD를 완성한다.Thereafter, after forming an upper liquid crystal substrate having a common electrode, the upper and lower liquid crystal substrates are sealed by forming a spacer and a failure turn to have a constant cell gap, injecting liquid crystal into the cell gap, and sealing to complete the LCD.
또한 통상의 LCD는 사용되는 액정의 종류나 구동 방법등에 의해 티.엔(Twisted Nematic), 에스.티.엔(Super Twisted Nematic), 강유전성(Ferroelectric) 및 TFT LCD등으로 구분된다.Conventional LCDs are classified into Twisted Nematic, Super Twisted Nematic, Ferroelectric, TFT LCD, etc., depending on the type of liquid crystal used and the driving method.
여기서 TFT를 화소 동작의 스위칭 소자로 사용하는 TFT LCD는 다른 종류의 LCD에 비해 응답속도가 빠르고, 넓은 시야각을 가지며, 고정세화 및 고화질화가 가능하여 휴대용 TV나 랩탑 PC등에 널리 사용되고 있다.TFT LCDs using TFTs as switching elements for pixel operations have a wider response speed, wider viewing angles, and higher definition and higher image quality than other types of LCDs, and are widely used in portable TVs and laptop PCs.
제1a도 내지 제1c도는 종래 기술에 따른 LCD용 TFT의 제조 공정도이다.1A to 1C are manufacturing process diagrams of the TFT for LCD according to the prior art.
먼저, 투명기판(1)상에 산화막 재질의 절연막(2)을 도포한 후, 상기 절연막(2)상에 양측으로 서로 이격되어있는 다결정실리콘층 패턴으로된 소오스/드레인전극(3)을 형성한다. 그다음 상기 소오스/드레인전극(3)의 상부와 그 사이의 절연막(2)상에 채널이 되는 반도체층(4) 패턴을 다결정실리콘으로 형성한다. (제1a도 참조).First, an insulating film 2 made of an oxide film is coated on the transparent substrate 1, and then source / drain electrodes 3 having a polysilicon layer pattern spaced apart from each other on both sides are formed on the insulating film 2. . Next, a pattern of the semiconductor layer 4 serving as a channel is formed of polycrystalline silicon on the top of the source / drain electrode 3 and the insulating film 2 therebetween. (See also Figure 1a).
그다음 상기 소오스/드레인전극(3) 사이의 반도체층(4) 패턴 상에서 서로 중첩되어 있는 게이트전극(6)과 반도체층(4) 패턴상에 저저항 및 오옴믹 접촉을 위한 이온주입을 실시하여 고농도 불순물 반도체층(7)을 형성한다. 이때 상기 게이트전극(6)은 다결정실리콘으로 형성한다. (제 1b도 참조).Then, ion implantation for low resistance and ohmic contact is performed on the gate electrode 6 and the semiconductor layer 4 pattern that overlap each other on the semiconductor layer 4 pattern between the source / drain electrodes 3 to form a high concentration. The impurity semiconductor layer 7 is formed. In this case, the gate electrode 6 is formed of polycrystalline silicon. (See also Figure 1b).
그후, 상기 구조의 전표면에 필드산화막(8)을 형성하고, 상기 게이트전극(6)과 소오스/드레인전극(3) 일측 상부의 필드산화막(8)을 제거하여 고농도 불순물 반도체층(7)을 노출시키는 콘택홀(9)을 형성하고, 상기 콘택홀(9)을 통하여 상기 게이트전극(6) 및 소오스/드레인전극(3)과 접촉되는 금속배선(10)을 형성한다. (제1c도 참조).Thereafter, the field oxide film 8 is formed on the entire surface of the structure, and the high concentration impurity semiconductor layer 7 is removed by removing the field oxide film 8 on one side of the gate electrode 6 and the source / drain electrode 3. A contact hole 9 exposing is formed, and a metal wiring 10 in contact with the gate electrode 6 and the source / drain electrode 3 is formed through the contact hole 9. (See also Figure 1c).
상기와 같은 종래의 기술에 따른 스테거드형 LCD용 TFT 제조방법은 소오스/드레인전극과 게이트전극이 정확하게 정렬되는 경우 소오스/드레인전극과 게이트전극이 경계 부분이 다른 부분에 비해 단차가 많이 지게되고, 따라서 그 부분에서 게이트산화막이나 필드 산화막이 얇게 형성되어, 전압 인가시 소오스/드레인전극과 게이트전극 또는 게이트전극과 금속배선간에 단락이 발생하여 공정수율 및 소자동작의 신뢰성을 떨어뜨리는 문제점이 있다.In the method for manufacturing a staggered LCD TFT according to the related art as described above, when the source / drain electrode and the gate electrode are correctly aligned, the step / drain electrode and the gate electrode have a large step difference compared to the other part of the boundary part. Therefore, the gate oxide film or the field oxide film is thinly formed in the portion, and a short circuit occurs between the source / drain electrode and the gate electrode or the gate electrode and the metal wiring when voltage is applied, thereby degrading process yield and device operation reliability.
본 발명은 상기과 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 스테거드형 LCD용 TFT에서 투명기판상에 소오스/드레인전극을 형성한 후, 상기 소오스/드레인전극의 사방에 절연막 패턴을 형성하여 상기 소오스/드레인전극이 잠기도록하고 후속 공정을 진행하여 스테거드형 TFT를 형성하여 배선간의 단락을 방지할 수 있는 LCD용 TFT의 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to form a source / drain electrode on the transparent substrate in the TFT for staggered LCD, and then form an insulating film pattern on all sides of the source / drain electrode The present invention provides a method for manufacturing a TFT for an LCD that can prevent a short circuit between wirings by forming a staggered TFT by allowing the source / drain electrodes to be locked and performing a subsequent process.
상기과 같은 목적을 달성하기 위한, 본 발명에 따른 LCD용 TFT제조방법의 특징으로 투명기판상에 서로 이격되어 있는 소오스/드레인전극을 형성하는 공정과, 상기 구조의 전표면에 완충막을 형성하는 공정과, 상기 소오스/드레인전극상의 완충막을 노출시키는 감광막패턴을 형성하는 공정과, 상기 감광막패턴에 의해 노출되어 있는 완충막을 제거하여 상기 소오스/드레인전극과 평탄한 면을 갖는 완충막 패턴을 형성하는 공정과, 상기 감광막패턴을 제거하는 공정과, 상기 소오스/드레인전극과 그 사이의 완충막 패턴상에 반도체층 패턴을 형성하는 공정과, 상기 소오스/드레인전극 사이의 반도체층 패턴상에 서로 중첩되어 있는 게이트산화막과 게이트전극을 형성하는 공정과, 상기 게이트전극과 그 양측의 반도체층 패턴에 고농도 불순물 반도체층을 형성하는 공정과, 상기 구조의 전표면에 필드 산화막을 형성하는 공정과, 상기 게이트전극과 소오스/드레인전극 상부의 고농도 불순물 반도체층상의 필드산화막을 제거하여 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 게이트전극 및 소오스/드레인전극상의 고농도 불순물 반도체층과 접촉되는 금속배선을 형성하는 공정을 구비함에 있다.In order to achieve the above object, there is provided a method of manufacturing a TFT for an LCD according to the present invention, comprising: forming a source / drain electrode spaced apart from each other on a transparent substrate; and forming a buffer film on the entire surface of the structure; Forming a buffer film pattern exposing the buffer film on the source / drain electrode, removing the buffer film exposed by the photosensitive film pattern, and forming a buffer film pattern having a flat surface with the source / drain electrode; Removing the photoresist pattern, forming a semiconductor layer pattern on the source / drain electrodes and the buffer layer pattern therebetween, and a gate oxide film overlapping each other on the semiconductor layer pattern between the source / drain electrodes And a gate electrode, and a high concentration impurity semiconductor layer is formed on the gate electrode and the semiconductor layer pattern on both sides thereof. Forming a field oxide film on the entire surface of the structure; forming a contact hole by removing a field oxide film on a high concentration impurity semiconductor layer on the gate electrode and the source / drain electrode; And forming a metal wiring in contact with the highly doped impurity semiconductor layer on the gate electrode and the source / drain electrode.
이하, 본 발명에 따른 LCD용 TFT의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a manufacturing method of the TFT for LCD according to the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2d도는 본 발명에 따른 LCD용 TFT의 제조 공정도이다.2A to 2D are manufacturing process diagrams of the TFT for LCD according to the present invention.
먼저, 투명재질, 예를들어 석영이나 유리로된 투명기판(1) 상에 산화막이나 질화막으로된 절연막(2)을 형성하고, 상기 절연막(2)상에 다결정실리콘층 패턴으로된 소오스/드레인전극(3)을 형성한 후, 상기 구조의 전표면에 화학기상증착(chemical vapor deposition; 이하 CVD)이나 물리기상증착(physical vapor deposition; 이하 PVD라 칭함) 방법으로 절연재질, 예를들어 산화막이나 질화막으로된 완충막(11)을 형성하고, 상기 소오스/드레인전극(3) 상부의 완충막(11)을 노출시키는 감광막패턴(12)을 형성한다. 이때 상기 절연막(3)은 형성하고자하는 소오스/드레인전극(3)의 두께 보다 같거나 두껍게 형성한다. (제2a도 참조).First, an insulating film 2 made of an oxide film or a nitride film is formed on a transparent substrate 1 made of a transparent material such as quartz or glass, and a source / drain electrode having a polysilicon layer pattern on the insulating film 2. (3), and then an insulating material such as an oxide film or a nitride film on the entire surface of the structure by chemical vapor deposition (CVD) or physical vapor deposition (hereinafter referred to as PVD). The buffer film 11 is formed, and the photosensitive film pattern 12 exposing the buffer film 11 on the source / drain electrode 3 is formed. In this case, the insulating layer 3 is formed to be the same or thicker than the thickness of the source / drain electrode 3 to be formed. (See also Figure 2a).
그다음 상기 감광막패턴(12)에 의해 노출되어 있는 완충막(11)을 제거하여 상기 소오스/드레인전극(3)을 노출시키는 완충막(11) 패턴을 형성한 후, 상기 감광막패턴(12)을 제거한다. 이때 상기 완충막(11)을 과식각하여 경계 부분에서의 돌출되는 부분들을 제거할 수도 있다.Thereafter, the buffer layer 11 exposed by the photoresist pattern 12 is removed to form a buffer layer 11 pattern exposing the source / drain electrodes 3, and then the photoresist pattern 12 is removed. do. In this case, the buffer layer 11 may be overetched to remove portions protruding from the boundary portion.
그후, 상기 소오스/드레인전극(3) 상부와 그 양측의 완충막(11) 상에 채널이 되는 반도체층(4) 패턴을 비정질 또는 다결정실리콘으로 형성하고, 상기 소오스/드레인전극(3) 사이의 반도체층(4) 패턴상에 서로 중첩되어 있는 게이트산화막(5)과 게이트전극(6)을 형성한다. (제 2b도 참조).Subsequently, a pattern of the semiconductor layer 4 serving as a channel is formed of amorphous or polysilicon on the source / drain electrodes 3 and the buffer films 11 on both sides thereof, and between the source / drain electrodes 3. The gate oxide film 5 and the gate electrode 6 overlapping each other are formed on the semiconductor layer 4 pattern. (See also part 2b).
그다음 상기 게이트전극(6)과 그 양측의 반도체층(4) 패턴상에 N 또는 P형 불순물을 이온주입하여 저저항 및 오옴믹 접촉을 위한 고농도 불순물 반도체층(7)을 형성한 후, 상기 구조의 전표면에 필드산화막(8)을 형성한다.Next, an N or P-type impurity is ion-implanted on the gate electrode 6 and the pattern of the semiconductor layer 4 on both sides thereof to form a high concentration impurity semiconductor layer 7 for low resistance and ohmic contact. The field oxide film 8 is formed on the entire surface of the film.
그후, 상기 게이트전극(6)과 다결정실리콘층(3) 패턴 일측 상부의 필드산화막(8)을 제거하여 고농도 불순물 반도체층(7)을 노출시키는 콘택홀(9)들을 형성한 후, 상기 콘택홀(9)을 통하여 상기 게이트전극(6) 및 소오스/드레인전극(3)과 접촉되는 금속배선(10)을 형성한다. (제2c도 참조).Thereafter, the contact hole 9 exposing the high concentration impurity semiconductor layer 7 is formed by removing the field oxide layer 8 on one side of the gate electrode 6 and the polysilicon layer 3 pattern, and then forming the contact hole. A metal wiring 10 in contact with the gate electrode 6 and the source / drain electrodes 3 is formed through (9). (See also 2c).
이상에서 설명한 바와 같이, 본 발명에 따른 LCD용 TFT의 제조방법은 투명기판상에 소오스/드레인전극을 형성하고, 상기 소오스/드레인전극을 제외한 투명기판상에 완충막 패턴을 형성하여 상부 표면을 평탄하게 한 후, 소오스/드레인전극 및 그 양측의 완충막 패턴상에 채널이 되는 반도체층 패턴을 형성하고, 후속 공정을 진행하여 스테거드형 TFT를 형성하였으므로, 소오스/드레인전극과 게이트전극의 경계 부분에서 단차가 커지지 않으므로 게이트산화막이나 필드산화막이 얇아져 배선들이 단락되는 것을 방지할 수 있어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing an LCD TFT according to the present invention, a source / drain electrode is formed on a transparent substrate, and a buffer layer pattern is formed on the transparent substrate except for the source / drain electrode to flatten the upper surface. After this, the semiconductor layer pattern serving as a channel was formed on the source / drain electrodes and the buffer film patterns on both sides, and the subsequent process was performed to form a staggered TFT. Thus, the boundary between the source / drain electrodes and the gate electrode was formed. Since the step is not increased, the gate oxide film or the field oxide film is thinned, thereby preventing the wirings from being shorted, thereby improving the process yield and the reliability of device operation.
Claims (7)
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| US9666601B2 (en) | 2000-12-11 | 2017-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| US10665610B2 (en) | 2000-12-11 | 2020-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
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