JP2002164543A - Semiconductor device, electrooptic device and their fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and an electrooptic device comprising a TFT characteristics of which are stabilized by cleaning the interface between a semiconductor film and a gate insulation film, and their fabricating method. SOLUTION: When TFTs 10, 20 and 30 are formed on an active matrix substrate 2, an amorphous silicon semiconductor film 10a is formed on a substrate 100 and subjected to laser annealing. A first thin gate insulation film 131 is then formed on the surface of the semiconductor film 10a by atmospheric pressure plasma oxidation and a resist mask 401 is formed on the surface thereof. Under that state, the first gate insulation film 131 and the semiconductor film 10a are etched collectively and the resist mask 401 is removed thus forming a second gate insulation film 132.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a thin film transistor (hereinafter, referred to as TFT), an electro-optical device, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a semiconductor device having a TFT, for example, there is an active matrix substrate with a built-in drive circuit of a liquid crystal device (electro-optical device) using the TFT as an active element for pixel switching or the like.

In manufacturing this active matrix substrate, conventionally, for example, as shown in FIG. 11A, a base protection film 101 such as a silicon oxide film and a base protection film 101 such as a silicon oxide film are formed on a substrate 100 such as a quartz substrate or a glass substrate. After sequentially forming a semiconductor film 10a such as an amorphous silicon film, the semiconductor film 10a is subjected to laser annealing to polycrystallize the semiconductor film 10a. Next, as shown in FIG. 11B, a resist mask 4 is formed on the surface of the semiconductor film 10a.
After forming the semiconductor film 10a through the resist mask 401 and patterning the semiconductor film 10a into an island shape, the resist mask is removed as shown in FIG. Next, as shown in FIG. 11D, a gate insulating film 13 such as a silicon oxide film is formed on the surface of the semiconductor film 10a.
To form Next, as shown in FIG. 11E, the scanning line 91 and the gate electrode 24 are formed on the surface of the gate insulating film 13.
34, the scanning line 91 and the gate electrode 2 are formed.
4, 34, or a predetermined impurity is introduced into a predetermined region of the semiconductor film 10a through a resist mask for impurity introduction to form the source region 16, 26, 36 and the drain region 1.
7, 27 and 37 are formed.

In this way, the TF for pixel switching is
After forming T10, N-type TFT 20 for the drive circuit and P-type TFT 30 for the drive circuit, the interlayer insulating films 18, 1
9, source electrodes 41 and 43, data lines 90, drain electrodes 11 and 42, pixel electrodes 9, and the like.

[0005]

However, in the conventional method of manufacturing a semiconductor device (active matrix substrate of a liquid crystal device), as shown in FIG.
When patterning Oa, the resist mask 401 is formed directly on the surface of the semiconductor film 10a, so that the interface between the semiconductor film 10a and the gate insulating film 13 is not clean. Therefore, there is a problem that the characteristics of the TFTs 10, 20, and 30 are not stable. That is, although the resist mask 401 is removed after the patterning of the semiconductor film 10a is completed, the semiconductor film 10a is exposed to a stripping solution such as sulfuric acid when removing the resist mask 401. In order to form the resist mask 401 with good adhesion, the semiconductor film 1
0a is exposed to the vapor of hexamethyldisilazane, and when forming the gate insulating film 13, dilute hydrofluoric acid is used to remove the oxide film formed on the surface of the semiconductor film 10a up to that time. Exposure to solution. Therefore, the surface of the semiconductor film 10a is roughened, carbon-based molecules are attached, and the like, so that the interface between the semiconductor film 10a and the gate insulating film 13 is not very clean.

[0006] In view of the above problems, an object of the present invention is to provide:
The interface between the semiconductor film and the gate insulating film is cleaned and high quality MOS (Metal-Oxide-Semicond)
(Uctor) An object of the present invention is to provide a semiconductor device, an electro-optical device, and a method for manufacturing the same, each having a TFT whose characteristics are stabilized by forming an interface.

[0007]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a thin film transistor having a semiconductor film serving as a channel and a gate electrode opposed to the semiconductor film via a gate insulating film. A semiconductor film forming step of forming the semiconductor film; a first gate insulating film forming step of forming a first gate insulating film by oxygen plasma treatment on the surface of the semiconductor film under atmospheric pressure; A mask forming step of forming a resist mask on the surface of the gate insulating film, a patterning step of patterning the first gate insulating film and the semiconductor film via the resist mask, and after removing the resist mask, A second gate insulating film forming step of forming a second gate insulating film on a surface of the first gate insulating film; A gate electrode forming step of forming a gate electrode on the surface of the gate insulating film; and a source / drain region forming step of forming a source / drain region of the TFT by introducing an impurity into the semiconductor film. .

Therefore, in the semiconductor device to which the present invention is applied, the TFT includes, as the gate insulating film, a first gate insulating film formed on the surface of the semiconductor film by oxidation, and the first gate insulating film. The second formed on the surface of
Wherein the first gate insulating film comprises:
It is thinner than the second gate insulating film and is formed in the same pattern as the semiconductor film.

According to the present invention, when a semiconductor film is patterned into an island shape, a thin first gate insulating film is formed on the surface of the semiconductor film instead of forming a resist mask directly on the surface of the semiconductor film. Then, a resist mask is formed on the surface of the first gate insulating film, and the first gate insulating film and the semiconductor film are patterned using the resist mask. Therefore, the surface of the semiconductor film is used for forming a resist mask, sulfuric acid used for removing the resist mask, hexamethyldisilazane vapor used for pretreatment when forming the resist mask, and forming a gate insulating film. There is no contact with a diluted hydrofluoric acid solution used for removing foreign matter from the surface of the semiconductor film. Therefore, the surface of the semiconductor film is not roughened or adhered with carbon-based molecules.
A clean interface can be formed between the semiconductor film and the gate insulating film. Therefore, it is possible to prevent traps and the like from being generated at the interface between the semiconductor film and the gate insulating film.
The electrical characteristics of T are improved.

In the present invention, the thickness of the first gate insulating film is, for example, 20 nm or less, and preferably 10 nm or less.
m or less. With such a film thickness, the semiconductor film and the first gate insulating film can be patterned at one time. In particular, when the film thickness of the first gate insulating film is 10 nm or less, the semiconductor film and the first gate insulating film can be patterned together. It is easier to collectively pattern the first gate insulating film.

In the present invention, in the first gate insulating film forming step, the first gate insulating film is formed by oxidizing a surface of the semiconductor film. For example, in the first gate insulating film forming step, the surface of the semiconductor film is oxidized at atmospheric pressure by plasma formed using a helium gas mixed with oxygen. With such a structure, since the surface of the first gate insulating film is formed by oxidizing the surface of the semiconductor film, the interface between the gate insulating film and the semiconductor film originally exists in the bulk of the semiconductor film and is outside air. There is no exposure. Therefore, a cleaner M
Since an OS interface can be obtained, TF with stable characteristics
T can be manufactured.

In the present invention, in the oxidation using plasma in the first gate insulating film forming step, oxygen is mixed with helium at a ratio of 5% or less.

[0013] Ionization for generating plasma is determined by kinetic energy obtained until molecules accelerated by an electric field collide with nearby molecules. At atmospheric pressure, the mean free path of the molecules is short, and thus the ionization is not sufficient. Energy cannot be obtained. However, since the helium molecule has a small molecular size, a relatively long moving distance until collision and sufficient kinetic energy can be obtained, ionization becomes easy, and plasma is generated. So for helium,
By adding oxygen up to 5% at the maximum, oxygen can also be turned into plasma.

Furthermore, in the generation of plasma in the present invention, it is possible to increase the oxidation rate by mixing carbon tetrafluoride with helium at a ratio of 0.03% or less.

Similarly, in the generation of plasma according to the present invention, it is possible to increase the oxidation rate by mixing krypton with helium at a ratio of 0.03% or less.

Further, in the generation of plasma in the present invention, 13.56, 27.12 to 40.68 MH
By using a high frequency such as z, streamer discharge near the electrode is suppressed, and plasma can be obtained stably. In addition, the generated charge cannot move following the change in the electric field as the frequency increases,
Physical collision with the semiconductor film and the electrode is suppressed. Therefore, problems such as contamination due to electrode sputtering and charge-up due to charge are eliminated.

In the present invention, in the semiconductor film forming step, a crystallization step of forming the semiconductor film as an amorphous silicon film and crystallizing the amorphous silicon film before performing the first gate insulating film forming step is performed. It is preferred to do so. For example, in the crystallization step,
Perform a laser annealing step. With such a method, a TFT can be manufactured by a low-temperature process. Further, since laser annealing is performed on the semiconductor film before the gate insulating film is formed, there is an advantage that the semiconductor film is not adversely affected by the gate insulating film when crystallizing.

In the present invention, the laser annealing step is preferably performed by irradiating a laser beam in a vacuum atmosphere. When irradiation is performed in a vacuum atmosphere, the surface of the polycrystalline silicon does not have irregularities of 10 nm or more, and is relatively smooth. Therefore, even if this surface is subjected to plasma oxidation under atmospheric pressure, only the valleys of the irregularities corresponding to the crystal grain boundaries are not oxidized intensively, and an oxide film having a uniform thickness is formed. can do.

In the present invention, it is preferable that the semiconductor film is kept in a non-oxidizing atmosphere from the semiconductor film forming step to the first gate insulating film forming step. When formed in this manner, the surface of the semiconductor film is oxidized or contaminated by outside air or foreign substances contained in the semiconductor film before the first gate insulating film is formed on the surface of the semiconductor film after the semiconductor film is formed. Can be prevented.

Such a semiconductor device is, for example, an active matrix substrate of an electro-optical device using the TFT as a pixel switching element.

[0021]

Embodiments of the present invention will be described with reference to the drawings. Here, an example in which the present invention is applied to a drive circuit built-in type active matrix substrate as a semiconductor device will be described. This active matrix substrate is used for an active matrix type liquid crystal device (electro-optical device). Note that the active matrix substrate of this embodiment has the same basic configuration as the conventional active matrix substrate described with reference to FIG. 11, and therefore, portions having corresponding functions are denoted by the same reference numerals. .

(Structure of Image Display Area of Electro-Optical Device) FIG. 1 shows a matrix formed in an image display area of an active matrix substrate (semiconductor device) used in an electro-optical device (liquid crystal device) of the present embodiment. Is an equivalent circuit such as various elements and wiring of the pixel.

As shown in FIG. 1, in the electro-optical device 1 according to the present embodiment, a plurality of pixels formed in a matrix to form an image display area 1a have a TFT 10 (for controlling a pixel electrode 9). TFT for pixel switching)
Are formed in a matrix, and a data line 90 to which a pixel signal is supplied is electrically connected to a source of the TFT 10. The image signal S1 to be written to the data line 90,
S2,..., Sn may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 90 for each group. Also, TFT1
The scanning line 91 is electrically connected to the 0 gate,
The scanning signals G1, G2,..., Gm are applied in a pulsed manner to the scanning line 91 in this order at a predetermined timing. The pixel electrode 9 is electrically connected to the drain of the TFT 10, and by closing the switch of the TFT 10, which is a switching element, for a predetermined period, the image signals S 1, S
2, ..., Sn are written at a predetermined timing. The image signal S of a predetermined level written in the liquid crystal through the pixel electrode 9
1, S2,..., Sn are held for a certain period between the counter electrodes formed on the counter substrate. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the incident light cannot pass through the liquid crystal portion according to the applied voltage. In the normally black mode, the incident light passes through the liquid crystal portion according to the applied voltage. Light having a contrast according to the image signal is emitted from the electro-optical device 1 as a whole. Here, in order to prevent the held image signal from leaking, the storage capacitor 4 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the counter electrode by using the capacitor line 92 or the like.
0 is formed.

(Configuration of Pixel and TFT) FIGS. 2 and 3 are a plan view and a sectional view, respectively, of a pixel switching TFT 10 formed in each pixel.
Some of the pixel groups formed on the active matrix substrate are extracted and shown in FIG. 3, and FIG. 3 is a cross-sectional view taken along line AA 'in FIG.

In FIG. 2, an active matrix substrate 2 includes a plurality of transparent ITO (Indium Tin O 2).
The pixel electrodes 9 made of an xide) film are formed in a matrix, and an N-type TFT 10 for pixel switching is connected to each of the pixel electrodes 9. A data line 90, a scanning line 91 and a capacitance line 92 are formed along the vertical and horizontal boundaries of the pixel electrode 9, and the TFT
10 is connected to the data line 90 and the scanning line 91. That is, the data line 90 is electrically connected to the source region 16 of the TFT 10 through the contact hole, and the pixel electrode 9 is electrically connected to the TFT 1 through the contact hole.
0 is electrically connected to the drain region 17. The scanning line 91 extends so as to face the channel forming region 15 of the TFT 10. The storage capacitor 40 is a silicon film 1 for forming the TFT 10 for pixel switching.
A conductive portion of the silicon film 40a (semiconductor film / shaded region in FIG. 2) corresponding to the extended portion of the semiconductor film 40a (semiconductor film / shaded region in FIG. 2) is defined as a lower electrode 41, and The capacitor 41 has a structure in which a capacitance line 92 overlaps with the electrode 41 as an upper electrode.

FIG. 3 shows a cross section taken along line AA 'of the pixel region thus configured. As can be seen from FIG. 3, an insulating base protective film 101 made of a silicon oxide film or the like is formed on the surface of the substrate 100 serving as the base of the active matrix substrate 2.
01, a semiconductor film 1 made of an island-shaped silicon film
0a and 40a are formed. A gate insulating film 13 composed of a first gate insulating film 131 and a second gate insulating film 132, which will be described later, is formed on the surface of the semiconductor film 10a, and a scanning line 91 is formed on the surface of the gate insulating film 13 as a gate electrode. Passing through. In the silicon film 10a, a region facing the scanning line 91 via the gate insulating film 13 is a channel forming region 15. The channel forming region 15 one side with respect to the low concentration source region 161 of the impurity concentration for example of about 1 × 10 ¹⁸ cm ^3, and the impurity concentration of the heavily doped source region 162 of approximately 1 × 10 ²⁰ cm ³ For example a source region 16 provided in the forming, on the other side, a lightly doped drain region 171 of an impurity concentration for example of about 1 × 10 ¹⁸ cm ^3, and the impurity concentration of the heavily doped drain region 172 of approximately 1 × 10 ²⁰ cm ³ for example The provided drain region 17 is formed.

A first interlayer insulating film 18 and a second interlayer insulating film 19 are formed on the surface side of the pixel switching TFT 10 thus configured, and are formed on the surface of the first interlayer insulating film 18. The data line 90 thus formed is electrically connected to the high-concentration source region 162 via a contact hole formed in the first interlayer insulating film 18 and the gate electrode 13. The data line 9 is provided on the surface of the first interlayer insulating film 18.
0 is formed at the same time as the drain electrode 11. The drain electrode 11 is electrically connected to the high-concentration drain region 172 via the contact holes formed in the first interlayer insulating film 18 and the gate electrode 13. ing. Also,
A pixel electrode 9 is formed on the surface of the second interlayer insulating film 19, and the pixel electrode 9 is electrically connected to the drain electrode 11 via a contact hole formed in the second interlayer insulating film 19. I have. Here, the second interlayer insulating film 19 is a lower interlayer insulating film 19 obtained by firing a polysilazane coating film.
1 and an upper-layer interlayer insulating film 192 made of a silicon oxide film formed by a CVD method.
A surface protection film 45 made of a silicon oxide film or an organic film is formed on the surface side of the pixel electrode 9, and an alignment film 46 made of a polyimide film is formed on the surface of the surface protection film 45. The alignment film 46 is a film obtained by performing a rubbing process on a polyimide film.

A lower electrode 41 made of a low-concentration region is formed on the silicon film 40a extending from the high-concentration drain region 172. The storage capacitor 40 is formed because the capacitance line 92 faces the lower electrode 41 via an insulating film (dielectric film) formed simultaneously with the gate insulating film 13.

Here, the TFT 10 preferably has an LDD (Lightly Doped Drain) as described above.
n) Although it has a structure, it may have an offset structure in which impurity ions are not implanted into regions corresponding to the low-concentration source region 161 and the low-concentration drain region 171. Further, the TFT 10 may be a self-aligned TFT in which high concentration source and drain regions are formed in a self-aligned manner by implanting impurity ions at a high concentration using the scanning line 91 as a mask. In this embodiment, the TFT 10
The gate electrode (scanning line 91) has a single gate structure in which only one is disposed between the source and drain regions. However, two or more gate electrodes may be disposed between them. At this time, the same signal is applied to each gate electrode. Thus dual gate (double gate)
Alternatively, if the TFT 10 is formed by a triple gate or more, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-state current can be further reduced and a stable switching element can be obtained.

(Other TFTs on Active Matrix Substrate) FIG. 4 is a cross-sectional view of each TFT and storage capacitor formed on the active matrix substrate 2 (semiconductor device) with a built-in drive circuit. FIG. 4 shows, from right to left, an N-type TFT for pixel switching having an LDD structure, an N-type TFT for a drive circuit having an LDD structure, and a drive circuit having an LDD structure. P-type TFT is shown. These driving circuit TFTs constitute a scanning line driving circuit and a data line driving circuit described later with reference to FIG.

As shown in FIG. 4, in the active matrix substrate 2 with a built-in drive circuit,
N-type TFT 10 for drive circuit, P-type T for drive circuit
FT20 and N-type TFT30 for pixel switching
Are formed. Among these elements, the N-type TFT 10 for pixel switching is as described with reference to FIG. 3, and thus the description is omitted here. Also, an N-type TF for a driving circuit
The basic configuration of the T20 and the P-type TFT 30 is the same as that of the N-type TFT 10 for pixel switching.
These structures will be briefly described.

In the active matrix substrate 2, an underlying protective film 101 made of a silicon oxide film is formed on the surface side of the substrate 100, and a polycrystalline semiconductor patterned in an island shape is formed on the surface of the underlying protective film 101. Membrane 10
a is formed. These semiconductor films 10a are respectively an N-type TFT 10 for pixel switching, an N-type TFT 20 for a drive circuit, and a P-type TFT for a drive circuit.
The gate insulating film 13 including a first gate insulating film 131 and a second gate insulating film 132, which will be described later, is formed on the surface of each semiconductor film 10a.

In the N-type TFT 10 for the drive circuit and the P-type TFT 30 for the drive circuit, the gate insulating film 13
The gate electrodes 24 and 34 are respectively formed on the surface of the substrate. Each semiconductor film 10a has a gate electrode 24, 34
Channel regions 25 and 35 are formed in regions facing each other via gate insulating film 13. Source regions 26 and 36 and drain regions 27 and 37 are formed on both sides of these channel regions 25 and 35, respectively. In this embodiment, the source regions 26 and 36 and the drain regions 27 and 37 have gate electrodes 24 and 3 respectively.
The low-concentration source regions 261, 271 and the low-concentration drain regions 271, 271 having an impurity concentration of, for example, about 1 × 10 ¹⁸ cm ³ , which face the end of the gate electrode 4 via the gate insulating film 13.
371 is formed, and adjacent to the low-concentration source regions 261 and 361 and the low-concentration drain regions 271 and 371, the high-concentration source regions 262 and 362 and the high-concentration drain region 272 having an impurity concentration of about 1 × 10 ²⁰ cm ³ , for example. ,
372 are formed respectively. The source electrodes 41 and 43 and the drain electrode 42 are electrically connected to the high-concentration source regions 262 and 362 via contact holes in the first interlayer insulating film 18, respectively. Also,
The second interlayer insulating film 19 is formed on the surface side of the source electrodes 41 and 43 and the drain electrode 42.

(Structure of Gate Insulating Film 13) In the active matrix substrate 2 thus configured, in any of the TFTs 10, 20, and 30, the gate insulating film 13
Is composed of a thin first gate insulating film 131 formed on the surface of the semiconductor film 10a, and a second gate insulating film 132 formed on the surface side of the first gate insulating film 131. Here, the first gate insulating film 131 has a thickness of 20 nm or less, preferably 10 nm or less. On the other hand, the second gate insulating film 132 is thicker than the first gate insulating film 131, and has a thickness of, for example, 90 nm. Also, as described later, the first gate insulating film 13
Since 1 is patterned together with the semiconductor film 10a, it is formed with the same pattern as each semiconductor film 10a corresponding to its base.

(Method of Manufacturing TFT) A method of manufacturing the active matrix substrate 2 having such a structure will be described with reference to FIGS. 5, 6 and 7.

FIG. 5 shows the formation of an amorphous semiconductor film 10a and the formation of this semiconductor film 10a in the manufacturing method of this embodiment.
FIG. 2 is a configuration diagram of a processing apparatus for performing laser annealing on the substrate and forming various insulating films. 6 and 7
Is a process sectional view illustrating the method for manufacturing the active matrix substrate 2 of the present embodiment.

In the present embodiment, steps to be described later with reference to FIGS. 6A and 6B are performed in the processing apparatus shown in FIG. 5, and therefore, before describing each step, refer to FIG. The configuration of the processing apparatus will be described.

Referring to FIG. 5, a processing apparatus 700 includes a cassette-type loader / unloader 710 for carrying the substrate 100 into and out of the processed substrate 100, and Plasma CVD apparatus 72 for forming base protective film 101 and semiconductor film 10a
0, a laser annealing device 750 for performing laser annealing on the amorphous semiconductor film 10a, and an atmospheric pressure plasma oxidizing device 740 for oxidizing the first gate insulating film 131. The laser annealing apparatus 750 includes a laser annealing chamber 752, a laser optical system 754, a laser light source 756, and the like. In the atmospheric pressure plasma oxidizer 740,
In the case where the processing chamber is connected with a non-oxidizing atmosphere, the process gas may be sealed after the substrate is loaded and the pressure may be set to the atmospheric pressure, or the buffer may be provided to return to the atmospheric pressure and then the substrate may be loaded. . In the former case, it is necessary to have a vacuum pump so as to be able to handle the loading and unloading of the substrate, although it is an atmospheric pressure plasma oxidation apparatus.

The substrate 100 loaded by the loader / unloader 710 is loaded into the processing apparatus 700 by the plasma CVD apparatus 720 and the laser annealing apparatus 75.
And the processed substrate 100 is transferred to the loader / unloader unit 7.
A transport mechanism 760 for returning the substrate 100 and a housing 790 for maintaining the transport path of the substrate 100 in a non-oxidizing atmosphere are provided.

To manufacture the active matrix substrate 2 using such a processing apparatus 700, first, the cleaned substrate 100 is set on the loader / unloader section 710 of the processing apparatus 700. After that, the substrate 100 is processed in this processing apparatus 700 until the first gate insulating film forming step described with reference to FIG. Will be

First, as shown in FIG. 6A, in a chamber of a plasma CVD apparatus 720 of a processing apparatus 700, a substrate 100 made of a glass substrate under a temperature condition of about 150 ° C. to about 450 ° C. Protective film 10 made of a silicon oxide film on the surface of
Form one. As the raw material gas at this time, for example, a mixed gas of monosilane and laughing gas, TEOS and oxygen,
Alternatively, disilane and ammonia can be used.

Next, without exposing the substrate 100 to the outside air,
In the chamber of the plasma CVD apparatus 720 of the same processing apparatus 700, the substrate temperature is about 150 ° C. to about 450 ° C.
Under a temperature condition of 100 ° C., the substrate 100
A semiconductor film 10a made of an amorphous silicon film having a thickness of 40 nm to 70 nm is formed on the entire surface of the substrate. At this time, for example, disilane or monosilane can be used as a source gas (semiconductor film forming step).

Next, without exposing the substrate 100 to the outside air,
In the laser annealing chamber 752 of the laser annealing apparatus 750 of the same processing apparatus 700, the semiconductor film 10
a is irradiated with laser light to form an amorphous semiconductor film 10
a is changed to a polysilicon film (crystallization step). In this crystallization step, the laser light (excimer laser) emitted from the laser light source 756 is irradiated through the optical system 754 toward the substrate 100 mounted on the stage in the laser annealing apparatus 750. At this time, the semiconductor film 10a is irradiated with a line beam whose irradiation region is long in one direction, and the irradiation region is shifted. As a result, the amorphous semiconductor film 10a is once melted and polycrystallized through a cooling and solidification process. At this time, since the irradiation time of the laser beam to each region is very short, and the irradiation region is local to the entire substrate 100, the entire substrate 100 may be heated to a high temperature at the same time. Absent. Therefore, substrate 1
Even if a glass substrate is used as 00, no deformation or cracking due to heat occurs.

Next, as shown in FIG. 6B, the substrate is sandwiched while flowing a helium gas (10000 SCCM) mixed with 200 SCCM of oxygen under the atmospheric pressure in the processing chamber of the atmospheric pressure plasma oxidizing apparatus 740 of the same processing apparatus 700. A plasma is formed by applying an output of 4 W / cm ² between the electrodes by a high frequency power supply having a frequency of 40.68 MHz, and the surface of the semiconductor film 10a is oxidized. (First gate insulating film forming step). The substrate temperature at this time is 200 ° C
The degree is preferred. Further, by adding carbon tetrafluoride or krypton to the gas for forming plasma at 2 SCCM, the oxidation rate can be increased.

FIG. 8 shows the processing conditions and the substrate temperature 20.
0 ° C, helium gas 10000 SCCM, oxygen 200S
CCM, and frequency 40.68MHz, output 4W / c
The oxidation rate when atmospheric pressure plasma oxidation is performed is shown by m ² .

If the thickness of the first gate insulating film is as thin as 20 nm or less, preferably 10 nm or less, the first gate insulating film can be collectively patterned with the semiconductor film 10a in the next step of patterning. In the above, if the oxidation treatment time is set to 20 minutes, preferably about 10 minutes,
A first gate insulating film having such a thickness can be formed.

Next, as shown in FIG. 6C, a resist mask 401 is formed on the surface of the first gate insulating film 131 by photolithography (mask forming step).

Next, dry etching is performed through the resist mask 401 to collectively pattern the first gate insulating film 131 and the semiconductor film 10a.
As shown in (D), N-type TF for pixel switching
T10, storage capacitor 40, N-type TFT 2 for drive circuit
0, and the semiconductor films 10a, 20a, 30a, and 40a are left in an island shape in each formation region of the P-type TFT 30 for the drive circuit (patterning step). During this etching, what is formed on the surface of the semiconductor film 10a is, for example, a thin silicon oxide film having a thickness of 10 nm (the first gate insulating film 1).
31), when dry etching is performed on the semiconductor film 10a, the first gate insulating film 131 is simultaneously etched.

Next, after the resist mask 401 is removed, as shown in FIG.
Silicon film 10 is formed by VD method, plasma CVD method, or the like.
A second gate insulating film 132 made of a silicon oxide film having a thickness of about 15 nm to about 100 nm is formed on the surface a (second gate insulating film forming step). The second gate insulating film 132 forms the gate insulating film 13 together with the first gate insulating film 131.

Next, as shown in FIG. 7A, an N-type TFT 10 for pixel switching and an N-type TF
A low-concentration N-type impurity is introduced into the semiconductor film 40a with the region for forming the T20 and the P-type TFT 30 for the driving circuit covered with the resist mask 402. As a result, the lower electrode 41 of the storage capacitor 40 is formed.

Next, after removing the resist mask 402, the surface of the second gate insulating film 132 is formed on a surface of a gate electrode such as a doped silicon, a silicide film, a metal film such as an aluminum film, a chromium film, or a tantalum film. By forming a conductive film (not shown) and patterning the conductive film for forming a gate electrode, a scanning line 91, a capacitor line 92, and gate electrodes 24 and 34 are formed as shown in FIG. 7B. (Gate electrode forming step). As a result, the capacitance line 9
A storage capacitor 40 having the upper electrode 2 is formed.

Next, an N-type TFT for pixel switching
10 and about 0.1 × 10 ¹³ / c in a state where the side of the N-type TFT 20 for the drive circuit is covered with the resist mask 403.
m ² to about 10 × 10 ¹³ / cm ^{2 at} a dose (low concentration)
Introduce the mold impurities. As a result, the P-type T
On the side of the FT 30, the low concentration source region 361 and the low concentration drain region 3 are self-aligned with the gate electrode 34.
71 are formed.

Next, after the resist mask 403 is removed, as shown in FIG.
A resist mask 404 is formed to cover the side of the type TFT 10 and the N-type TFT 20 for the driving circuit and to cover the gate electrode 34 slightly wider.
P-type impurities are introduced at a dose (high concentration) of 0 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² . As a result, a P-type TFT 30 for a driving circuit is formed.
The high-concentration source region 362 and the high-concentration drain region 372 are left except for the low-concentration source region 361 and the low-concentration drain region 371 at a portion facing the end of the gate electrode 34.
Are formed.

Next, after removing the resist mask 404, as shown in FIG. 7D, a P-type TFT for a drive circuit is used.
With the 30 side covered with a resist mask 405, N-type impurities are introduced at a dose (low concentration) of about 0.1 × 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ² . as a result,
On the side of the N-type TFT 10 for pixel switching and the N-type TFT 30 for the driving circuit, the low concentration source region 16 is self-aligned with the scanning line 91 and the gate electrode 24.
1, 261 and low concentration drain regions 171 and 271 are formed.

Next, after the resist mask 405 is removed, as shown in FIG.
A resist mask 406 is formed to cover the scan line 91 and the gate electrode 24 while covering the scan line 91 and the gate electrode 24 a little wider.
In this state, about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10
N-type impurities are introduced at a dose of ¹⁵ / cm ² (high concentration). As a result, the N-type TFT 1 for pixel switching
0 and an N-type TFT 20 for a driving circuit are formed. In these TFTs 10 and 20, the low-concentration source region 16 is formed in a portion facing the scanning line 91 and the end of the gate electrode 24.
The high-concentration source regions 162 and 262 and the high-concentration drain regions 172 and 272 are formed except for the regions 1 and 261 and the low-concentration drain regions 171 and 271.

Thus, the N for pixel switching is
After the formation of the TFT 10 of the type, the N-type TFT 20 for the driving circuit, and the P-type TFT 30 for the driving circuit, the resist mask 406 is removed. Thereafter, as shown in FIGS. 3 and 4, a silicon oxide film or an NSG A first interlayer insulating film 18 made of a film (a silicate glass film containing neither boron nor phosphorus), a contact hole, source electrodes 41 and 43,
The drain electrodes 11 and 42, the second interlayer insulating film 19, the surface protection film 45, the pixel electrode 9, and the alignment film 46 are sequentially formed.

(Effects of the present embodiment) As described above, in the method of manufacturing the active matrix substrate 2 of the present embodiment, when the semiconductor film 10a is patterned into an island shape, a thin first film is formed on the surface of the semiconductor film 10a. After the gate insulating film 131 is formed by atmospheric pressure plasma oxidation, a resist mask 401 is formed on the surface of the first gate insulating film 131, and the first gate insulating film 131 and the semiconductor film 10a are patterned. For this reason, the surface of the semiconductor film 10a is formed on the resist mask 401, sulfuric acid used for removing the resist mask 401, hexamethyldisilazane vapor used for pretreatment when forming the resist mask 401,
And the semiconductor film 10a when forming the gate insulating film 13.
No exposure to dilute hydrofluoric acid solution used to remove foreign matter from the surface. Therefore, the surface of the semiconductor film 10a is not roughened or adheres with carbon-based molecules.
A clean interface can be formed between the semiconductor film 10a and the gate insulating film 13. Therefore, generation of traps and the like at the interface between the semiconductor film 10a and the gate insulating film 13 can be prevented, and the electrical characteristics such as the threshold voltage of the TFTs 10, 20, and 30 being stabilized are improved.

In this embodiment, the first gate insulating film 1
Since a sufficiently thin insulating film having a thickness of 10 nm or less is formed as the first film 31, the first gate insulating film 131 and the semiconductor film 1 are formed.
0a can be easily dry-etched collectively. Therefore, the patterning step can be simplified.

Further, in this embodiment, in the semiconductor film forming step, the semiconductor film 10a is formed as an amorphous silicon film, and the crystallization step (laser) for crystallizing the amorphous silicon film before performing the first gate insulating film forming step. (Annealing step). Therefore, the TFTs 10, 20, 30 can be manufactured by a low-temperature process. In addition, since laser annealing is performed on the semiconductor film 10a before the gate insulating film 13 is formed, there is an advantage that the semiconductor film 10a is not adversely affected by the gate insulating film 13 during crystallization.

Furthermore, during the period from the semiconductor film forming step to the first gate insulating film forming step, the semiconductor film 10a is kept in a non-oxidizing atmosphere in the processing apparatus 700, so that the surface of the semiconductor film 10a is exposed to the outside air. Do not expose. Therefore,
After the formation of the semiconductor film 10a, the surface of the semiconductor film 10a can be prevented from being contaminated before the first gate insulating film 131 is formed.

(Structure of Electro-Optical Device) FIGS. 9 and 10 show an example in which an electro-optical device (liquid crystal device) is formed using the active matrix substrate 2 formed by such a method.
This will be described with reference to FIG.

FIGS. 9 and 10 are a plan view of the electro-optical device according to the present embodiment as viewed from the counter substrate side, and a cross-sectional view of the electro-optical device taken along the line HH 'in FIG. .

9 and 10, the electro-optical device 1 includes an active matrix substrate 2 on which pixel electrodes 9 are formed in a matrix, a counter electrode 62 and a light-shielding film 63.
And a liquid crystal 69 sealed and sandwiched between these substrates. The active matrix substrate 2 and the opposing substrate 3
Are bonded to each other with a predetermined gap therebetween by a sealing material 52 containing a gap material formed along the outer peripheral edge of the sealing member.
Between the active matrix substrate 2 and the counter substrate 3,
A liquid crystal sealing region 66 is defined by the sealing material 52, and a liquid crystal 69 is sealed in the liquid crystal sealing region 66. Spacers 63 may be scattered between the active matrix substrate 2 and the opposing substrate 3 in the liquid crystal sealing region 66. As the sealing material 52, an epoxy resin, various ultraviolet curable resins, or the like can be used. In addition, as a gap material mixed in the sealing material 52, an inorganic or organic fiber or sphere having a size of about 2 μm to about 10 μm is used.

The opposing substrate 3 is an active matrix substrate 2
The peripheral portion of the active matrix substrate 2 is bonded so as to protrude from the outer peripheral edge of the counter substrate 3. Therefore, the drive circuits (the scan line drive circuit 70 and the data line drive circuit 60) and the input / output terminals 45 of the active matrix substrate 2 are exposed from the counter substrate 3. Here, since the sealing material 52 is partially interrupted, the liquid crystal injection port 58 is formed by the interrupted portion.
For this reason, after the opposing substrate 3 and the active matrix substrate 2 are bonded to each other, if the inner region of the sealing material 52 is set in a reduced pressure state, the liquid crystal 69 can be injected under reduced pressure from the liquid crystal injection port 58. Fill the liquid crystal injection port 58 with the sealant 5
You can close it with 9. The counter substrate 3 includes a sealing material 52.
A light-shielding film 54 for cutting off the image display area 1a is formed on the inner side. In addition, a vertical conductive material 56 for establishing electrical conduction between the active matrix substrate 2 and the counter substrate 3 is formed at a corner of the counter substrate 3.

Here, if the delay of the scanning signal supplied to the scanning line does not matter, it goes without saying that the scanning line driving circuit 70 may be provided on only one side. Further, the data line driving circuits 60 may be arranged on both sides along the side of the image display area 1a. For example, an odd-numbered data line supplies an image signal from a data line driving circuit arranged along one side of the image display area 1a, and an even-numbered data line extends along an opposite side of the image display area 1a. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines are driven in a comb-tooth shape as described above, the formation area of the data line driving circuit 60 can be expanded, so that a complicated circuit can be formed.

On the side of the active matrix substrate 2 facing the data line drive circuit 60, a precharge circuit or an inspection circuit may be provided by utilizing a portion under the light shielding film 54 or the like. The data line driving circuit 6
Instead of forming the scanning line driving circuit 70 and the scanning line driving circuit 70 on the active matrix substrate 2, for example, a driving LSI
May be electrically and mechanically connected to a terminal group formed on the periphery of the active matrix substrate 2 via an anisotropic conductive film. Good. The type of the liquid crystal 69 to be used and the
That is, TN (twisted nematic) mode,
STN (Super TN) mode, D-STN (Double-
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as an STN) mode and a normally white mode / normally black mode.

When the electro-optical device 1 of this embodiment is configured as a transmission type, it can be used, for example, in a projection type electro-optical device (liquid crystal projector). In this case, the three electro-optical devices 1 are used as light valves for RGB, and each of the electro-optical devices 1 receives light of each color separated through a dichroic mirror for RGB color separation as projection light. Respectively. Therefore, no color filter is formed in the electro-optical device 1 of the present embodiment.

Further, by forming an RGB color filter together with its protective film in a region facing each pixel electrode 9 on the opposing substrate 3, it is possible to use not only a projection type liquid crystal display but also a color filter.
A color electro-optical device such as a color liquid crystal television can be configured. Furthermore, a dichroic filter that creates RGB colors by utilizing the interference effect of light may be formed by stacking a number of interference layers having different refractive indexes on the counter substrate 3. According to the counter substrate with the dichroic filter, brighter color display can be performed.

[0069]

As described above, according to the present invention, after forming a thin first gate insulating film on the surface of a semiconductor film by atmospheric pressure plasma oxidation, a resist mask is formed on the surface of the first gate insulating film. Is formed, and the first gate insulating film and the semiconductor film are patterned using the resist mask. Therefore, according to the present invention, since the surface of the semiconductor film is not contaminated by a resist mask or the like, a clean interface can be formed between the semiconductor film and the gate insulating film. Further, since the obtained gate insulating film also has high performance, a high quality interface can be formed. Therefore, traps and the like can be prevented from being generated at the interface between the semiconductor film and the gate insulating film.
The electrical characteristics of the device are improved.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements and wirings of a plurality of pixels formed in a matrix in an image display area of an active matrix substrate (semiconductor device) in an electro-optical device (liquid crystal device) to which the present invention is applied. .

FIG. 2 shows a pixel switching T formed on an active matrix substrate (semiconductor device) to which the present invention is applied.
It is a top view of FT.

FIG. 3 is a cross-sectional view taken along line AA 'of FIG.

FIG. 4 shows TFs formed on an active matrix substrate (semiconductor device) incorporating a drive circuit to which the present invention is applied.
It is sectional drawing of T and storage capacitance.

FIG. 5 is a configuration diagram of a processing apparatus for forming an amorphous semiconductor film, laser annealing the semiconductor film, and forming various insulating films when manufacturing the active matrix substrate shown in FIG. 4;

FIGS. 6A to 6E are process cross-sectional views each showing up to a second gate insulating film forming process in the manufacturing process of the active matrix substrate shown in FIG. 4;

FIGS. 7A to 7E are cross-sectional views showing respective steps performed after the step shown in FIG. 6 in the manufacturing steps of the active matrix substrate shown in FIG.

FIG. 8 shows a method of manufacturing an active matrix substrate to which the present invention is applied.
7 is a graph showing an oxidation rate when forming a gate insulating film of FIG.

FIG. 9 is a plan view of an electro-optical device (liquid crystal device) to which the present invention is applied, as viewed from a counter substrate side.

FIG. 10 is a sectional view taken along line HH ′ in FIG. 9;

FIGS. 11A to 11E are process cross-sectional views illustrating a conventional method for manufacturing an active matrix substrate.

[Explanation of symbols]

 Reference Signs List 1 electro-optical device (liquid crystal device) 1a image display area 2 active matrix substrate (semiconductor device) 3 counter substrate 9 pixel electrode 10 N-type TFT for pixel switching 10a semiconductor film 11, 42 drain electrode 13 gate insulating film 15, 25 , 35 Channel region 16, 26, 36 Source region 17, 27, 37 Drain region 18, 19 Interlayer insulating film 20 N-type TFT for drive circuit 24, 34 Gate electrode 30 P-type TFT for drive circuit 40 Storage capacitance 41, 43 Source electrode 60 Data side drive circuit 62 Counter electrode 70 Scan side drive circuit 90 Data line 91 Scan line 100 Substrate 101 Underlayer protective film 131 First gate insulating film 132 Second gate insulating film

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hiroaki Akiyama 3-3-5 Yamato, Suwa-shi, Nagano F-term (reference) in Seiko Epson Corporation 2H092 JA25 JA29 JA38 JA42 JA44 JA46 JB13 JB23 JB32 JB33 JB38 JB41 JB51 JB57 JB63 JB69 KA04 MA05 MA07 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA30 MA35 MA37 MA41 NA25 NA27 PA07 QA07 RA05 5C094 AA02 AA21 BA03 BA43 CA19 EA04 EA05 EB02 5F058 BA20 BB07 BD01 BD04 BF07 BF23 A02 BF25 A02 BF25 EE04 EE05 EE08 EE28 FF09 FF23 FF25 GG02 GG13 GG25 GG45 HJ04 HM14 HM15 NN02 NN23 NN72 PP03 QQ02 QQ11

Claims (19)

[Claims] 1. A semiconductor device having a thin film transistor including a semiconductor film serving as a channel and a gate electrode opposed to the semiconductor film via a gate insulating film, wherein the thin film transistor is formed on the surface of the semiconductor film as the gate insulating film. A first gate insulating film formed,
A second gate insulating film formed on a surface of the first gate insulating film, wherein the first gate insulating film is thinner than the second gate insulating film, and A semiconductor device characterized by being formed in the same pattern. 2. The method according to claim 1, wherein the first gate insulating film has a thickness of 20.
2. The semiconductor device according to claim 1, wherein the thickness is not more than nm. 3. The first gate insulating film has a thickness of 10
2. The semiconductor device according to claim 1, wherein the thickness is not more than nm. 4. An electro-optical device using the semiconductor device according to claim 1, wherein the thin-film transistor is formed as a pixel switching element. 5. A method for manufacturing a semiconductor device having a thin film transistor including a semiconductor film serving as a channel and a gate electrode opposed to the semiconductor film via a gate insulating film, wherein: a semiconductor film forming step of forming the semiconductor film; A first gate insulating film forming step of forming a first gate insulating film on the surface of the semiconductor film; a mask forming step of forming a resist mask on the surface of the first gate insulating film; A patterning step of patterning the first gate insulating film and the semiconductor film by removing the resist mask, and forming a second gate insulating film on the surface of the first gate insulating film after removing the resist mask. Forming an insulating film, forming a gate electrode on the surface of the second gate insulating film, forming an impurity on the semiconductor film. The method of manufacturing a semiconductor device characterized by having a source-drain region formation step of forming a source and drain regions of the thin film transistor by entering. 6. The method according to claim 5, wherein, in the patterning step, the first gate insulating film and the semiconductor film are collectively etched. 7. The first gate insulating film has a thickness of 20
7. The method for manufacturing a semiconductor device according to claim 5, wherein the thickness is not more than nm. 8. The film thickness of the first gate insulating film is 10
7. The method for manufacturing a semiconductor device according to claim 5, wherein the thickness is not more than nm. 9. In the first gate insulating film forming step,
11. The method according to claim 5, wherein the first gate insulating film is formed by oxidizing a surface of the semiconductor film. 10. The semiconductor device according to claim 9, wherein the oxidation in the first gate insulating film forming step is performed at atmospheric pressure by plasma formed using a helium gas mixed with oxygen. Manufacturing method. 11. The oxidization using plasma in the first gate insulating film forming step, wherein oxygen is mixed with helium at a ratio of 5% or less.
The manufacturing method of the semiconductor device described in the above. 12. The oxidation using plasma in the first gate insulating film forming step includes the step of mixing oxygen at 5% or less and carbon tetrafluoride at a rate of 0.03% or less with respect to helium. The method for manufacturing a semiconductor device according to claim 9, wherein: 13. The oxidation using plasma in the first gate insulating film forming step is characterized in that oxygen is mixed with helium at a ratio of 5% or less and krypton at a ratio of 0.03% or less. A method for manufacturing a semiconductor device according to claim 9. 14. Oxidation using plasma in the first gate insulating film forming step is performed at 13.56, 27.12.
10. The method of manufacturing a semiconductor device according to claim 9, wherein plasma is formed by a high frequency of 40 to 68.68 MHz and oxidation is performed. 15. In the semiconductor film forming step, the semiconductor film is formed as an amorphous silicon film, and
15. The method of manufacturing a semiconductor device according to claim 5, wherein a crystallization step of crystallizing the amorphous silicon film is performed before performing the gate insulating film forming step. 16. The method according to claim 15, wherein the crystallization step is a laser annealing step of irradiating the semiconductor film with laser light. 17. The method according to claim 16, wherein the laser annealing step includes irradiating a laser beam in a vacuum. 18. The semiconductor device according to claim 5, wherein said semiconductor film is kept in a non-oxidizing atmosphere from said semiconductor film forming step to said first gate insulating film forming step.
8. The method for manufacturing a semiconductor device according to item 7. 19. A method of manufacturing an electro-optical device using the method of manufacturing a semiconductor device according to claim 5, wherein the thin film transistor is formed as a pixel switching element. Device manufacturing method.