KR100205867B1 - Active matrix substrate and its fabrication method - Google Patents

Active matrix substrate and its fabrication method Download PDF

Info

Publication number
KR100205867B1
KR100205867B1 KR1019960017119A KR19960017119A KR100205867B1 KR 100205867 B1 KR100205867 B1 KR 100205867B1 KR 1019960017119 A KR1019960017119 A KR 1019960017119A KR 19960017119 A KR19960017119 A KR 19960017119A KR 100205867 B1 KR100205867 B1 KR 100205867B1
Authority
KR
South Korea
Prior art keywords
metal layer
semiconductor layer
substrate
layer
film
Prior art date
Application number
KR1019960017119A
Other languages
Korean (ko)
Other versions
KR970075984A (en
Inventor
류기현
Original Assignee
구자홍
엘지전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, 엘지전자주식회사 filed Critical 구자홍
Priority to KR1019960017119A priority Critical patent/KR100205867B1/en
Publication of KR970075984A publication Critical patent/KR970075984A/en
Application granted granted Critical
Publication of KR100205867B1 publication Critical patent/KR100205867B1/en

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/13439Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136231Active matrix addressed cells for reducing the number of lithographic steps

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 액정표시장치 등에 쓰이는 액티브매트릭스기판의 제조방법 및 그 방법에 의해 제조되는 액티브매트릭스기판에 관한 것으로, 화소전극을 마스크로하여 소스전극과 드레인전극을 형성하여 마스크형성 및 그에 의한 패턴형성의 수를 줄이고, 화소전극 상에 폴리이미드 막을 형성하고 폴리이미드막 상의 소정의 영역에 블랙레진막을 형성하여 양호한 배향상태를 갖는 액티브매트릭스기판을 완성한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an active matrix substrate used in a liquid crystal display device and the like, and to an active matrix substrate manufactured by the method. The number is reduced, a polyimide film is formed on the pixel electrode, and a black resin film is formed in a predetermined region on the polyimide film to complete an active matrix substrate having a good alignment state.

Description

액티브매트릭스기판의 제조방법 및 그 방법에 의해 제조되는 액티브매트릭스기판Method for manufacturing active matrix substrate and active matrix substrate manufactured by the method

제1도는 일반적인 액티브매트릭스기판을 나타내는 평면도이다.1 is a plan view showing a general active matrix substrate.

제2도는 제1도의 Ⅱ-Ⅱ선에 따른 단면도이다.2 is a cross-sectional view taken along the line II-II of FIG.

제3도는 본 발명의 실시예에 따른 액티브매트릭스기판의 제조공정도이다.3 is a manufacturing process diagram of an active matrix substrate according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

111, 311 : 투명유리기판 112, 312 : 게이트 버스 배선111, 311: transparent glass substrates 112, 312: gate bus wiring

113, 313 : 소스버스배선 113a, 313a : 소스전극113, 313: source bus wiring 113a, 313a: source electrode

113b, 313b : 드레인전극 114, 314 : 게이트절연막113b and 313b drain electrodes 114 and 314 gate insulating film

115, 315 : 반도체층 116, 316 : 불순물 반도체층115 and 315: semiconductor layer 116 and 316: impurity semiconductor layer

117, 317 : 화소전극 120 : 보호절연막117, 317: pixel electrode 120: protective insulating film

318 : 폴리이미드막 119, 319 : 블랙레진막318: polyimide film 119, 319: black resin film

본 발명은 액정표시장치 등에 쓰이는 액티브매트릭스기판의 제조방법과 그 방법에 의해 제조되는 액티브매트릭스기판에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an active matrix substrate for use in a liquid crystal display device and the like and an active matrix substrate produced by the method.

일반적으로 액티브매트릭스기판은 각각의 화소를 각기 구동하는 스위칭소자로 주로 박막트랜지스터(Thin Film Transistor; 이하 "TFT"라 칭한다. )를 이용한다. 제1도는 스위칭소자로 박막트랜지스터를 이용하는 일반적인 액티브매트릭스기판을 나타내는 평면도로서, 투명유리기판 상에 게이트버스배선(112)이 수평방향으로 평행하게 형성되고, 상기 게이트버스배선을 포함한 투명유리기판의 전면에 걸쳐 게이트절연막이 형성되고, 이 게이트절연막 상에 각 게이트버스배선(112)과 교차하는 다수의 소스버스배선(113)이 수직방향으로 평행하게 형성되어 있다. 그리고 각 게이트버스배선(112)과 각 소스버스배선(113)의 교점 부근에서 게이트버스배선(112)과 일체로 형성된 게이트전극(112a) 상의 상기 게이트절연막 위에 반도체층이 형성되고, 이 반도체층 상에 드레인전극(113b) 및 소스전극(113a)이 대향하도록 형성되어 능동소자로서의 TFT가 구성된다. 그리고 화소전극(117)은 드레인전극(113b)과 전기적으로 연결되어 있다.In general, an active matrix substrate mainly uses a thin film transistor (“TFT”) as a switching element for driving each pixel. FIG. 1 is a plan view showing a general active matrix substrate using a thin film transistor as a switching element, in which a gate bus wiring 112 is formed in parallel in a horizontal direction on a transparent glass substrate, and a front surface of the transparent glass substrate including the gate bus wiring is formed. A gate insulating film is formed over the gate insulating film, and a plurality of source bus wiring 113 intersecting with the respective gate bus wiring 112 is formed in parallel in the vertical direction. A semiconductor layer is formed on the gate insulating film on the gate electrode 112a formed integrally with the gate bus wiring 112 near the intersection of each gate bus wiring 112 and each source bus wiring 113. The drain electrode 113b and the source electrode 113a are formed to face each other so as to form a TFT as an active element. The pixel electrode 117 is electrically connected to the drain electrode 113b.

제2도는 제1도를 Ⅱ-Ⅱ선을 따라 절단한 구성도인데 이를 참고하여 액티브매트릭스기판을 설명하면 다음과 같다.FIG. 2 is a schematic view of FIG. 1 taken along line II-II. Referring to this, the active matrix substrate is described below.

투명유리기판(111) 위에 위치하는 게이트전극(112a)을 덮는 게이트절연막(114)위에, 반도체층(115)이 형성되고, 그 위에 양쪽으로 분리형성된 불순물 반도체층(116) 상에 드레인전극(113b) 및 소스전극(113a)이 형성되어, 능동소자로서의 TFT가 구성된다. 그리고 반도체층(115), 투명유리기판(111), 드레인전극(113b), 소스전극(113a)은 보호절연막(120)으로 덮히며, 드레인전극(113b)은 보호절연막(120) 상에 형성된 투명화소전극(117)과 전기적으로 연결된다. 보호절연막(120) 상에 형성되어 각 화소의 경계를 나타내는 차광막(119) 상에는, 액정분자를 배향하기 위한 배향막(118)이 형성된다. 이러한 액티브매트릭스기판은 그 제조공정에 있어서 상술한 각각의 막형성 공정 및 이 막들이 소정의 형상으로 패터닝하여 전술한 배선들 및 전극들을 형성하기 위한 포토에칭공정을 반복해서 만들어진다.The semiconductor layer 115 is formed on the gate insulating film 114 covering the gate electrode 112a positioned on the transparent glass substrate 111, and the drain electrode 113b is formed on the impurity semiconductor layer 116 formed on both sides thereof. ) And a source electrode 113a are formed to form a TFT as an active element. The semiconductor layer 115, the transparent glass substrate 111, the drain electrode 113b, and the source electrode 113a are covered with a protective insulating film 120, and the drain electrode 113b is a transparent formed on the protective insulating film 120. It is electrically connected to the pixel electrode 117. On the light shielding film 119 formed on the protective insulating film 120 and showing the boundary of each pixel, an alignment film 118 for orienting liquid crystal molecules is formed. Such an active matrix substrate is repeatedly produced in the manufacturing process of each of the above-described film forming processes, and the films are patterned into a predetermined shape, and the photoetching process for forming the above-mentioned wirings and electrodes is repeated.

이와 같은 종래의 액티브매트릭스기판의 제조방법은 패턴형성을 위한 각각의 마스크공정에 있어서, 마스크 패턴의 형성, 정확한 패턴 묘사를 위한 고도의 마스크 정렬, 레지스트의 도포 및 현상 등의 여러 과정을 거치면서 많은 시간이 소요되고 수율이 낮아진다. 한편, 차광막의 형성으로 인한 단차증가에 의해 배향불량이 심화되며 화질에 나쁜 영향을 주게 된다.Such a method of manufacturing an active matrix substrate in the related art has many processes in various mask processes for pattern formation, such as formation of a mask pattern, advanced mask alignment for accurate pattern description, application and development of resist, and the like. It takes time and yields are low. On the other hand, due to an increase in the level difference due to the formation of the light shielding film, the misalignment worsens and adversely affects the image quality.

본 발명의 목적은 전술한 일반적인 액티브매트릭스기판의 제조에 있어서, 특히 화소전극을 마스크로하여 불순물 반도체층 및 후술하는 제2금속층을 에칭함으로써 소스전극과 드레인전극을 형성하여 제조시간을 단축하고 수율을 향상시킬 수 있는 액티브매트릭스 기판의 제조방법을 제공하는 데 있으며, 또 그러한 방법에 의해 제조되는 액티브매트스기판을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to produce a source electrode and a drain electrode by etching an impurity semiconductor layer and a second metal layer, which will be described later, using the pixel electrode as a mask, in the manufacture of the above-mentioned general active matrix substrate, thereby shortening the manufacturing time and increasing the yield. There is provided a method of manufacturing an active matrix substrate which can be improved, and an active matrix substrate manufactured by such a method.

본 발명의 또 다른 목적은 단차가 감소되어 배향불량을 줄일 수 있는 액티브매트릭스기판 및 그 제조방법을 제공하는데 있다.It is still another object of the present invention to provide an active matrix substrate and a method of manufacturing the same, which can reduce the misalignment by reducing the step difference.

이러한 목적을 달성하기 위한 본 발명에 따른 액티브매트릭스기판의 제조 방법은 기판 상에 제1금속층을 증착한 후 패터닝하여 게이트전극 및 게이트버스배선을 형성하는 단계와; 상기 게이트전극 및 상기 게이트버스배선과 상기 기판 상에 게이트절연막, 반도체층, 불순물 반도체층, 제2금속층을 연속증착하는 단계와; 상기 게이트절연막, 상기 반도체층, 상기 불순물 반도체층 및 상기 제2금속층을 차례로 에칭하여 소정의 패턴을 형성하는 단계와; 상기 제2금속층 및 상기 기판 상에 투명금속층을 증착하는 단계와; 상기 투명금속층을 선택적으로 에칭하는 단계와; 상기 선택적으로 애칭된 투명금속층을 마스크로하여 제2금속층과 상기 불순물 반도체층을 에칭하여 소스 및 드레인전극을 형성하는 단계와; 상기 선택적으로 에칭된 투명금속층 및 상기 반도체층 상에 폴리이미드막을 형성하는 단계와; 상기 폴리이미드막 상의 소정의 영역에 블랙레진막을 형성하는 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of manufacturing an active matrix substrate, the method comprising: forming a gate electrode and a gate bus wiring by depositing and patterning a first metal layer on the substrate; Continuously depositing a gate insulating film, a semiconductor layer, an impurity semiconductor layer, and a second metal layer on the gate electrode, the gate bus wiring, and the substrate; Etching the gate insulating film, the semiconductor layer, the impurity semiconductor layer, and the second metal layer in order to form a predetermined pattern; Depositing a transparent metal layer on the second metal layer and the substrate; Selectively etching the transparent metal layer; Etching the second metal layer and the impurity semiconductor layer using the selectively etched transparent metal layer as a mask to form source and drain electrodes; Forming a polyimide film on the selectively etched transparent metal layer and the semiconductor layer; And forming a black resin film in a predetermined region on the polyimide film.

본 발명의 액티브매트릭스기판의 제조방법에 의해 만들어지는 액티브매트릭스기판은 기판과; 상기 기판 상에 형성되어 게이트버스배선 및 게이트전극을 이루는 제1금속층과, 상기 제1금속층과 기판 상에 형성된 게이트절연층과; 상기 게이트절연층 상에 형성된 반도체층과, 상기 반도체층 상에 형성된 불순물 반도체층과; 상기 불순물 반도체층 상에 형성되어 소스전극 및 소스버스배선과 드레인전극을 이루는 제2금속층과; 상기 제2금속층 및 상기 기판 상의 소정의 영역에 형성된 투명금속층과; 상기 투명금속층과 상기 반도체층 상에 형성된 폴리이미드막과; 상기 폴리이미드막 상의 소정의 영역에 형성된 차광막으로 이루어진 구조를 갖는다.An active matrix substrate made by the method of manufacturing an active matrix substrate of the present invention comprises: a substrate; A first metal layer formed on the substrate to form a gate bus wiring and a gate electrode, and a gate insulating layer formed on the first metal layer and the substrate; A semiconductor layer formed on the gate insulating layer, and an impurity semiconductor layer formed on the semiconductor layer; A second metal layer formed on the impurity semiconductor layer to form a source electrode, a source bus wiring, and a drain electrode; A transparent metal layer formed on the second metal layer and a predetermined region on the substrate; A polyimide film formed on the transparent metal layer and the semiconductor layer; It has a structure which consists of a light shielding film formed in the predetermined area | region on the said polyimide film.

이하, 본 발명에 따른 액티브매트릭스기판의 제조 방법의 실시예를 제3도를 이용하여 설명한다.Hereinafter, an embodiment of a method of manufacturing an active matrix substrate according to the present invention will be described with reference to FIG.

[실시예]EXAMPLE

투명유리기판(311) 상에 Cr, Al, 또는 Al-Ta 등으로 된 제1금속층을 스퍼터링법 등으로 증착한다. 포토처리 후, 에칭용액으로 제1금속층을 선택적으로 에칭하여 게이트버스배선(도면에 도시되지 않았다. )과 게이트버스배선에서 분기하는 게이트전극(312a)을 형성한다. (제3a도)A first metal layer made of Cr, Al, Al-Ta, or the like is deposited on the transparent glass substrate 311 by sputtering or the like. After the photoprocessing, the first metal layer is selectively etched with an etching solution to form a gate bus wiring (not shown in the figure) and a gate electrode 312a branching off from the gate bus wiring. (Figure 3a)

필요하다면, 내화학성 및 내열성, 특히 다음에 형성되는 게이트절연층과의 결합성 등을 높이기 위해 게이트버스배선(312)을 양극산화시켜, 게이트버스배선 상에 양극산화막을 형성할 수 있는데, 이 양극산화막은 뒤에 형성되는 게이트절연층의 질화실리콘층과 2층 절연층으로 되어 게이트버스배선(312)과 신호선(소스버스배선)과의 층간절연을 개선하는 역할을 한다.If necessary, the gate bus wiring 312 may be anodized to increase chemical resistance and heat resistance, in particular, bonding with the gate insulating layer formed next, and an anodizing film may be formed on the gate bus wiring. The oxide film serves as a silicon nitride layer and a two-layer insulating layer of the gate insulating layer formed later, thereby improving the interlayer insulation between the gate bus wiring 312 and the signal line (source bus wiring).

이어서, 투명유리기판(311) 상에 스퍼터링법이나, 프라즈마CVD장치로 암모니아가스, 실란가스, 질소가스, 수소가스 등을 도입하여, 게이트절연층(314), 아몰퍼스 실리콘(a-Si)의 반도체층(315), n+ a-Si의 불순물 반도체층(316), Pd, Al-Si, Al-Si-Ti, Al-Si-Cu 등으 금속으로 된 제2금속층(313)을 연속증착한다. (제3b도)Subsequently, ammonia gas, silane gas, nitrogen gas, hydrogen gas, or the like is introduced onto the transparent glass substrate 311 by a sputtering method or a plasma CVD apparatus to form a gate insulating layer 314 and an amorphous silicon (a-Si) semiconductor. A layer 315, an impurity semiconductor layer 316 of n + a-Si, and a second metal layer 313 made of metal such as Pd, Al-Si, Al-Si-Ti, Al-Si-Cu, etc. are continuously deposited. (Figure 3b)

제2금속층(313) 상에 감광막을 도포하고 노광한 후 제2금속층(313), 불순물 반도체층(316), 반도체층(315) 및 게이트절연층(314)을 차례로 에칭하여 소정의 패턴을 형성한다.(제3c도)After coating and exposing the photoresist on the second metal layer 313, the second metal layer 313, the impurity semiconductor layer 316, the semiconductor layer 315, and the gate insulating layer 314 are sequentially etched to form a predetermined pattern. (Figure 3c)

제2금속층(313)과 투명유리기판(311) 상에 화소전극을 이루는 ITO(Indium Tin Oxide) 등의 투명금속층(317)을 증착하고 이 투명금속층 상에 감광막을 도포하고 노광한 후 에칭을 행하여 투명금속층의 패턴을 형성한다. 상기의 에칭에 의해서 소정의 부분이 제거되고 제2금속층(313)의 전극분리영역은 노출된다. (제3d도)On the second metal layer 313 and the transparent glass substrate 311, a transparent metal layer 317, such as indium tin oxide (ITO), which forms a pixel electrode is deposited, and a photosensitive film is applied on the transparent metal layer, exposed, and then etched. A pattern of the transparent metal layer is formed. By etching, a predetermined portion is removed and the electrode isolation region of the second metal layer 313 is exposed. (Figure 3d)

에칭된 투명금속층을 마스크로하여 에칭을 행하여 노출된 제2금속층의 전극분리영역과 노출부분 밑의 불순물 반도체등을 제거하여 소스전극(313a)과 드레인전극(313b)을 형성한다. (제3e도)Etching is performed using the etched transparent metal layer as a mask to remove the electrode isolation region of the exposed second metal layer and the impurity semiconductor under the exposed portion to form the source electrode 313a and the drain electrode 313b. (Figure 3e)

이어서 폴리이미드막(318)을 도포한다. 폴리이미드막(318)은 보호절연막의 기능 및 배향막의 기능을 한다. (제3f도)Next, the polyimide film 318 is applied. The polyimide film 318 functions as a protective insulating film and as an alignment film. (Figure 3f)

폴리이미드막(318) 상의 소정의 영역에 차광막인 블랙레진막(319)을 형성하여 각 화소간의 경계를 구분한다. (제3g도)A black resin film 319, which is a light shielding film, is formed in a predetermined region on the polyimide film 318 to separate the boundaries between the pixels. (Figure 3g)

폴리이미드막(318) 상에 블랙레진막(319)이 형성되기 때문에 반도체층(315)과 블랙레진막(319)의 직접적인 접촉에 의한 트랜지스터의 특성 열화가 없이 박막트랜지스터를 외부의 빛으로부터 보호할 수 있다. 또한 차광막의 기능을 하는 블랙레진막(319)이 배향막인 폴리이미드막(318) 상에 형성되어 블랙레진막(319) 만큼의 단차가 감소되고 러빙시의 균일성(uniformity)이 보장되어 보다 양호한 배향상태를 얻을 수 있다.Since the black resin film 319 is formed on the polyimide film 318, the thin film transistor can be protected from external light without deterioration of transistor characteristics due to direct contact between the semiconductor layer 315 and the black resin film 319. Can be. In addition, a black resin film 319 functioning as a light shielding film is formed on the polyimide film 318, which is an alignment film, so that the level difference as much as the black resin film 319 is reduced and uniformity during rubbing is ensured. The alignment state can be obtained.

본 발명에 의한 액트브매트릭스기판에 있어서, 소스 및 드레인전극은 투명금속층을 마스크로 하여 형성되며, 이 투명금속층은 소스전극과, 드레인전극을 이루는 제2금속층 상에서 분리형성되고 투명유리기판 상으로 연장되어 화소전극을 형성한다. 그리고 배향막인 블랙레진막의 일부분에는 차광막이 형성되어 화소간의 경계를 나타낸다.In the act matrix matrix according to the present invention, the source and drain electrodes are formed using a transparent metal layer as a mask, and the transparent metal layer is formed on the second metal layer forming the source electrode and the drain electrode and extends onto the transparent glass substrate. To form a pixel electrode. A light shielding film is formed on a portion of the black resin film as the alignment film to show the boundary between the pixels.

본 발명에 의하면, 화소전극을 마스크로 하여 소스전극과 드레인전극을 형성하기 때문에 마스크패턴의 형성 및 그에 의한 패턴형성의 수가 줄어들고, 화소전극 상에 배향막인 블랙레진막을 도포한 후 폴리이미드막 상에 차광막인 블랙레진막을 형성하여 트랜지스터의 특성열화가 없으며 양호한 배향상태를 갖는 액티브매트릭스기판을 보다 짧은 시간에 높은 수율로 얻을 수 있다.According to the present invention, since the source electrode and the drain electrode are formed using the pixel electrode as a mask, the number of mask patterns and the number of pattern formations are reduced, and a black resin film as an alignment film is coated on the pixel electrode, and then on the polyimide film. By forming a black resin film, which is a light shielding film, an active matrix substrate having no good deterioration of a transistor and having a good alignment state can be obtained with a high yield in a shorter time.

Claims (2)

기판 상에 제1금속층을 증착한 후 패터닝하여 게이트전극 및 게이트버스배선을 형성하는 단계와; 상기 게이트전극 및 상기 게이트버스배선과 상기 기판상에 게이트절연막, 반도체층, 불순물반도체층, 제2금속층을 연속증착하는 단계와; 상기 게이트절연막 상기 반도체층, 상기 불순물 반도체층 및 상기 제2금속층을 차례로 에칭하여 소정의 패턴을 형성하는 단계와; 상기 제2금속층 및 상기 기판 상에 투명금속층을 증착하는 단계와; 상기 투명금속층을 선택적으로 에칭하는 단계와;, 상기 선택적으로 에칭된 투명금속층을 마스크로 하여 제2금속층과 상기 불순물 반도체층을 에칭하여 소스 및 드레인 전극을 형성하는 단계와; 상기 투명금속층 및 상기 반도체층 상에 폴리이미드막을 형성하는 단계와; 상기 폴리이미드막 상의 소정의 영역에 블랙레진막을 형성하는 단계를 포함하여 이루어지는 액티브매트릭스기판의 제조방법.Depositing and patterning a first metal layer on the substrate to form a gate electrode and a gate bus wiring; Continuously depositing a gate insulating film, a semiconductor layer, an impurity semiconductor layer, and a second metal layer on the gate electrode, the gate bus wiring, and the substrate; Etching the gate insulating film, the impurity semiconductor layer, and the second metal layer in order to form a predetermined pattern; Depositing a transparent metal layer on the second metal layer and the substrate; Selectively etching the transparent metal layer, etching a second metal layer and the impurity semiconductor layer using the selectively etched transparent metal layer as a mask to form source and drain electrodes; Forming a polyimide film on the transparent metal layer and the semiconductor layer; And forming a black resin film in a predetermined region on the polyimide film. 기판 위에 형성된 게이트전극을 덮도록 게이트절연층, 반도체층, 불순물 반도체층, 소스전극 및 드레인전극이 순차 적층되어 섬 모양을 구성하되, 상기 불순물 반도체층, 상기 소스전극은 상기 반도체층 위에서 양쪽으로 분리되고, 상기 반도체층의 일부 표면이 노출되도록 이루어진 스위칭 소자와; 상기 반도체층의 노출된 표면을 기준으로 소스전극 및 드레인전극을 덮고, 상기 기판 표면까지 연장되어 각각 분리되도록 구성되는 투명금속층과; 상기 투명금속층과 상기 노출된 반도체층의 표면을 덮는 폴리이미드막과; 상기 폴리이미드막 위에 상기 스위칭소자를 가리도록 형성되는 차광막; 를 포함하여 이루어지는 액티브매트릭스기판.A gate insulating layer, a semiconductor layer, an impurity semiconductor layer, a source electrode, and a drain electrode are sequentially stacked to cover the gate electrode formed on the substrate, and form an island shape. The impurity semiconductor layer and the source electrode are separated on both sides of the semiconductor layer. A switching element configured to expose a portion of the surface of the semiconductor layer; A transparent metal layer covering the source electrode and the drain electrode based on the exposed surface of the semiconductor layer and extending to the surface of the substrate to be separated from each other; A polyimide film covering the surfaces of the transparent metal layer and the exposed semiconductor layer; A light shielding film formed on the polyimide film so as to cover the switching device; An active matrix substrate comprising a.
KR1019960017119A 1996-05-21 1996-05-21 Active matrix substrate and its fabrication method KR100205867B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960017119A KR100205867B1 (en) 1996-05-21 1996-05-21 Active matrix substrate and its fabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960017119A KR100205867B1 (en) 1996-05-21 1996-05-21 Active matrix substrate and its fabrication method

Publications (2)

Publication Number Publication Date
KR970075984A KR970075984A (en) 1997-12-10
KR100205867B1 true KR100205867B1 (en) 1999-07-01

Family

ID=19459288

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960017119A KR100205867B1 (en) 1996-05-21 1996-05-21 Active matrix substrate and its fabrication method

Country Status (1)

Country Link
KR (1) KR100205867B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100654777B1 (en) * 2000-02-16 2006-12-08 엘지.필립스 엘시디 주식회사 liquid crystal display device and fabrication method thereof
US7459323B2 (en) 2003-08-28 2008-12-02 Samsung Electronics Co., Ltd. Method of manufacturing a thin film transistor array panel

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6667494B1 (en) 1997-08-19 2003-12-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100654777B1 (en) * 2000-02-16 2006-12-08 엘지.필립스 엘시디 주식회사 liquid crystal display device and fabrication method thereof
US7459323B2 (en) 2003-08-28 2008-12-02 Samsung Electronics Co., Ltd. Method of manufacturing a thin film transistor array panel

Also Published As

Publication number Publication date
KR970075984A (en) 1997-12-10

Similar Documents

Publication Publication Date Title
US6927105B2 (en) Thin film transistor array substrate and manufacturing method thereof
US4958205A (en) Thin film transistor array and method of manufacturing the same
US7129105B2 (en) Method for manufacturing thin film transistor array panel for display device
KR100333180B1 (en) TFT-LCD Manufacturing Method
US7317208B2 (en) Semiconductor device with contact structure and manufacturing method thereof
US5963797A (en) Method of manufacturing semiconductor devices
US5751020A (en) Structure of a liquid crystal display unit having exposed channel region
KR100653467B1 (en) Method for manufacturing tft-lcd
KR20000027509A (en) Method for manufacturing liquid crystal display device with high opening ratio and high transmitting ratio
JP2003517641A (en) Method for manufacturing active matrix device
US6025605A (en) Aligned semiconductor structure
JP2002250934A (en) Method for manufacturing matrix substrate for liquid crystal
KR0171980B1 (en) Method for manufacturing liquid crystal display element
KR100205867B1 (en) Active matrix substrate and its fabrication method
KR100202236B1 (en) Active matrix panel and its making method
US7116389B2 (en) Liquid crystal display device and method of manufacturing the same
KR100623981B1 (en) Thin film transistor array panel for liquid crystal display and manufacturing method of the same
JPH11142879A (en) Active matrix type tft element array
KR100193650B1 (en) Method of manufacturing thin film transistor of liquid crystal display device
JPH08262491A (en) Liquid crystal display element and its production
KR100599958B1 (en) Method of manufacturing lcd having high aperture ratio and high transmittance
JPH0797191B2 (en) Active matrix cell and manufacturing method thereof
KR100471765B1 (en) Thin film transistor substrate with single film gate line and manufacturing method
KR20020028014A (en) Method for fabricating tft-lcd
KR950003942B1 (en) Method of manufacturing thin film transistor for lcd

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120330

Year of fee payment: 14

FPAY Annual fee payment

Payment date: 20130329

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20160329

Year of fee payment: 18

EXPY Expiration of term