KR100867537B1 - top gate type poly silicon TFT and fabrication method of thereof - Google Patents

Abstract

The top gate type polysilicon thin film transistor according to the present invention is a top gate type polysilicon thin film transistor in which an active pattern, a gate insulating film, a gate electrode, a source and a drain electrode are sequentially formed on a substrate. Characterized in that the dummy active pattern is formed at a position spaced a predetermined distance from the end of the active pattern formed in the lower,

In addition, the method of manufacturing a top gate polysilicon thin film transistor according to the present invention includes the steps of forming an active pattern and a dummy active pattern on a substrate, and forming a gate insulating film on a surface on which the active pattern and the dummy active pattern are formed. And forming a gate electrode on the gate insulating layer formed on an area where the active pattern and the dummy active pattern are formed, and sequentially forming an insulating layer, a source, and a drain electrode on a surface on which the gate electrode is formed. .

According to the present invention, by reducing the step difference between the gate insulating film and the gate electrode generated at the active pattern edge (edge) to prevent the concentration of the electric field formed on the gate electrode and the active pattern edge can suppress the hump phenomenon, and further There is an advantage that can suppress the hump phenomenon while using the conventional process as it is without the process.

Description

Top gate type poly silicon TFT and fabrication method

1 is a view schematically showing a liquid crystal panel of a conventional liquid crystal display device.

FIG. 2 schematically illustrates a polysilicon thin film transistor formed on one pixel of a conventional liquid crystal display.

3 is a cross-sectional view of a specific portion (A-A ') of the thin film transistor shown in FIG.

4 is a longitudinal cross-sectional view of a specific portion B-B 'of the thin film transistor shown in FIG.

5 is a graph showing a hump phenomenon.

FIG. 6 schematically illustrates a polysilicon thin film transistor formed on one pixel of a liquid crystal display according to the present invention; FIG.

FIG. 7 is a longitudinal cross-sectional view of a specific portion D-D ′ of the thin film transistor illustrated in FIG. 6.

8 is a diagram illustrating an active pattern and a dummy active pattern of a polysilicon thin film transistor according to the present invention;

9 is a cross-sectional view showing a manufacturing process of a polysilicon thin film transistor according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 10 ': thin film transistor (TFT) 12: source electrode                 

14 drain electrode 16 gate electrode

18: active pattern 20: data line

22 gate line 24 glass substrate

26 gate insulating film 28 source region

30 drain region 32 insulating layer

34 pixel electrode 36 dummy active pattern

38 substrate 40 gate film

42: protective film

The present invention relates to a thin film transistor, and more particularly, to a top gate polysilicon thin film transistor and a method of manufacturing the same.

Thin Film Transistors (TFTs) Liquid crystal displays (LCDs) form thin film transistors as switching elements that are connected to individual pixels that form the screen of the display device, and use the thin film transistors to convert pixel electrode potentials. It is a liquid crystal display device of a control method. The thin film transistor is usually formed on a glass substrate using a semiconductor thin film, and a polysilicon thin film transistor is one in which polysilicon is used as the semiconductor thin film.

The polysilicon has a much higher mobility of carriers than amorphous silicon. Therefore, the transistor element for the driving circuit IC can be formed on the glass substrate together with the switching transistor for the pixel electrode, thereby reducing the cost of the module process in LCD manufacturing and at the same time using the LCD to be completed. Power can also be lowered.

1 is a view schematically showing a liquid crystal panel of a conventional liquid crystal display device.

Referring to FIG. 1, the structure of a liquid crystal panel which is a basic component of a general liquid crystal display device will be described.

The liquid crystal display includes a color filter including a black matrix (BM) and a sub color filter (3) (R, G, and B) and an upper substrate (1) on which a transparent common electrode (4) is formed on the color filter. ) And a lower substrate 5 having an array wiring including a pixel region P and a pixel electrode 8 formed on the pixel region and a thin film transistor as a switching element T. The upper substrate 1 The liquid crystal 9 is filled between the lower substrates 5.

The lower substrate 5 is also referred to as an array substrate. The thin film transistor T, which is a switching element, is disposed in a matrix form, and a gate line 6 and a data line 7 passing through the plurality of thin film transistors are formed.

The pixel region P is a region where the gate line 6 and the data line 7 cross each other. The pixel electrode 8 formed on the pixel region P is made of a transparent conductive metal having relatively high light transmittance, such as indium-tin oxide (ITO).

When the operation of the liquid crystal panel is described, a voltage is applied between the common electrode 4 formed on the upper substrate 1 and the pixel electrode 8 formed on the lower substrate 5, and thus, between the two substrates. The image is displayed by varying the amount of light transmitted according to the arrangement of the liquid crystals 9 to be filled.

FIG. 2 schematically illustrates a polysilicon thin film transistor formed on one pixel of a conventional liquid crystal display. That is, FIG. 2 is a view of the thin film transistor T region in FIG.

Referring to FIG. 2, the thin film transistor 10 is formed in each pixel of the liquid crystal display, and the individual pixels are switched and driven by the thin film transistor 10.

That is, the pixel electrode (not shown) of the pixel is formed in contact with the drain electrode 14 of the thin film transistor 10, and the voltage applied to the pixel electrode is a constant voltage applied to the data line 20. The polysilicon active pattern 18 is applied to the pixel electrode via the drain electrode 14.

However, the predetermined voltage applied to the data line 20 may pass through the polysilicon active pattern 18 only when the voltage applied to the gate line 22 is greater than or equal to a predetermined threshold voltage Vth.

As a result, the thin film transistor 10 serves as a switching element for driving the respective pixels.

3 is a cross-sectional view of a specific portion A-A 'of the thin film transistor shown in FIG.

Referring to FIG. 3, the thin film transistor T includes a gate electrode 16, a source electrode 12, and a drain electrode 14, and a polysilicon active layer between the source electrode 12 and the drain electrode 14. The pattern 18 is constructed.

The gate electrode 16 of the thin film transistor T is individually formed for each pixel, and the gate electrodes 16 are connected to a predetermined gate line (not shown). In addition, a gate insulating layer 26 and a polysilicon active pattern 18 are formed under the gate electrode 16.

In the conventional thin film transistor 10, a polysilicon layer is laminated on the glass substrate 24 through a process of forming a polysilicon pattern constituting the active pattern 18 on the glass substrate 24. After etching, the active pattern 18 is formed, and then the gate insulating layer 26 and the gate electrode 16 are formed.

In addition, high-dose ion implantation is performed outside the gate electrode 16 formation region to form a source region 28 and a drain region 30 of the thin film transistor in the active pattern 18, and the gate electrode 16. ) Deposits an insulating layer 32 on the surface on which the () is formed, and then forms a via hole (not shown) where the source region 28 and the drain region 30 correspond. The source electrode 12 and the drain electrode 14 are formed only in the formed region.

As a result, the thin film transistor T shown in FIG. 2 is formed, and when the pixel electrode 34 electrically contacting the drain electrode 14 is formed, individual pixel regions P of the liquid crystal display are formed. will be.                         

4 is a longitudinal cross-sectional view of a specific portion B-B ′ of the thin film transistor illustrated in FIG. 2.

In particular, FIG. 4 shows only a cross section of a portion where an active pattern, a gate insulating film, and a gate electrode are formed.

Referring to FIG. 4, after the polysilicon active pattern 18 is formed, a gate insulating layer 26 and a gate electrode 16 are formed thereon, wherein the active pattern 18 is formed by the thickness of the active pattern 18. The gate insulating layer 26 and the gate electrode 16 formed longer than the longitudinal length of the pattern 18 may not be formed flat, and the gate electrode 16 may form a step at a position where the active pattern 18 ends. do.

Accordingly, as shown in FIG. 4, the capacitance formed between the active pattern 18 and the gate electrode 16 has a different value depending on its position.

Particularly, the capacitance at the gate edge region is not a flat capacitor but a rounded capacitor due to the formed structure, so that the capacitance is increased relative to the same unit area, and thus the thickness of the gate insulating film felt at the position electrically. Is to be thinned.

That is, the capacitance Cg formed at the center portion of the active pattern 18 and the gate electrode 16, that is, the flat portion, is formed at the portion where the active pattern 18 ends and the step difference between the gate electrode 16 is formed. The capacitances Cp1 and Cp2 have different capacitances compared to the same unit area, and as described above, the values of Cp1 and Cp2 are larger than the values of Cg.

As a result, parasitic transistors are formed in both stepped portions where Cp1 and Cp2 are formed, and electric field crowding occurs in both stepped portions because the values of Cp1 and Cp2 are larger than the values of Cg. As a result, the threshold voltage (Vth) is lower than that of the Cg region, thereby turning on early.

This phenomenon is called a hump phenomenon, and as a threshold voltage is lowered in a specific portion as described above, a voltage is applied to the pixel electrode before a predetermined switching point of the transistor, thereby causing a current to flow.

5 is a graph showing the hump phenomenon. Referring to FIG. 5, FIG. 5 is a graph of the relationship between the gate voltage Vg and the drain current Id, which shows that the Id curve is bent at Vg = 0.1 of the region indicated by the circle. Hump phenomenon described.

The generation of the hump will bring about a shift of the flat band voltage and the threshold voltage (Vth) of the entire thin film transistor, which is likely to cause a different operation from the design characteristics when the first thin film transistor is fabricated.

In addition, the hump characteristics may be generated for each thin film transistor according to the process characteristics of each position in the glass substrate, which adversely affects the uniformity of the flat band voltage and the threshold voltage of the entire thin film transistor. There are disadvantages.                         

In addition, this phenomenon becomes a greater problem in the current thin film transistor manufacturing situation in which the thickness of the active pattern is increased and the thickness of the gate insulating film is reduced.

The present invention forms a dummy active pattern on an active pattern present at a lower end of a gate electrode and a gate insulating layer, thereby reducing a step difference between the gate electrode and the gate insulating layer at an edge of the active pattern, thereby suppressing a hump phenomenon. Its purpose is to provide a type poly silicon thin film transistor and a method of manufacturing the same.

Top gate polysilicon thin film transistor according to the present invention for achieving the above object,

In a top gate type polysilicon thin film transistor in which an active pattern, a gate insulating film, a gate electrode, a source and a drain electrode are sequentially formed on a substrate, the top gate type polysilicon thin film transistor, wherein a predetermined distance is spaced from an end portion of the active pattern formed under the gate electrode and the gate insulating film. The dummy active pattern is formed at a position.

In addition, the dummy active pattern is positioned above and below the active pattern, and the width of the dummy active pattern is equal to or wider than the width of the gate electrode, and unlike the active pattern, the dummy active pattern is not connected to the source and drain electrodes. do.

The dummy active pattern may be formed of the same material as the active pattern, and the active pattern may be made of polysilicon.

In addition, the top gate type polysilicon thin film transistor manufacturing method according to the present invention in order to achieve the above object,

Forming an active pattern and a dummy active pattern on a substrate, forming a gate insulating film on a surface on which the active pattern and the dummy active pattern are formed, and forming the gate on the region where the active pattern and the dummy active pattern are formed. And forming a gate electrode on the insulating layer, and sequentially forming an insulating layer, a source, and a drain electrode on the surface on which the gate electrode is formed.

In addition, the dummy active pattern is positioned above and below the active pattern, and the width of the dummy active pattern is equal to or wider than the width of the gate electrode, and is not connected to the source and drain electrodes.

According to the present invention, by forming a dummy active pattern in the active pattern, it is possible to reduce the step difference between the gate insulating film and the gate electrode generated at the active pattern edge, thereby forming the gate electrode and the active pattern edge. There is an advantage in that the electric field concentration is prevented to suppress the hump phenomenon.

In addition, this has the advantage of suppressing the hump characteristics while using the conventional process as it is without additional process, the thickness of the active pattern, the thickness of the gate insulating film in the realistic manufacturing situation of the thin film transistor of the present invention The effect is further increased.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.                     

FIG. 6 schematically illustrates a polysilicon thin film transistor formed on one pixel of a liquid crystal display according to the present invention.

Referring to FIG. 6, the polysilicon thin film transistor 10 'formed on one pixel of the liquid crystal display according to the present invention is the same as the conventional liquid crystal display shown in FIG. The dummy active pattern 36 is formed above and below the active pattern 18, and the width of the dummy active pattern 36 is equal to or wider than the width of the gate electrode 16.

As a result, the thin film transistor 10 'is formed on each pixel of the liquid crystal display device as in the conventional liquid crystal display device, and the individual pixels are the thin film transistor 10'. It is switched and driven by.

That is, the pixel electrode (not shown) of the pixel is formed in contact with the drain electrode 14 of the thin film transistor 10 ′, and the voltage applied to the pixel electrode is a predetermined voltage applied to the data line 20. A voltage is applied to the pixel electrode through the polysilicon active pattern 18 via the drain electrode 14. However, the predetermined voltage applied to the data line 20 may pass through the polysilicon active pattern 18 only when the voltage applied to the gate line 22 is greater than or equal to a predetermined threshold voltage Vth.

In this case, unlike the active pattern 18, the dummy active pattern 36 is not connected to the source and drain electrodes 12 and 14, and is formed at the same time as the active pattern 18. .                     

The dummy active pattern 36 is further provided to suppress the hump phenomenon occurring in the related art, which will be described in detail below.

In addition, since the polysilicon thin film transistor 10 ′ shown in FIG. 6 has the same structure as that of the conventional polysilicon thin film transistor 10 except that the dummy active pattern 36 is further provided as described above, The cross sectional view for the portion C-C 'is the same as that shown in FIG.

FIG. 7 is a longitudinal cross-sectional view of a specific portion D-D ′ of the thin film transistor illustrated in FIG. 6. In particular, FIG. 7 illustrates only a cross section of a portion where an active pattern, a dummy active pattern, and a gate insulating film / gate electrode are formed.

Referring to FIG. 7, after the polysilicon active pattern 18 and the dummy active pattern 36 are formed, the gate insulating layer 26 and the gate electrode 16 are formed thereon.

At this time, the dummy active pattern 36 is formed by forming the gate insulating layer 26 and the gate electrode 16 that are formed longer than the vertical length of the active pattern 18 by the thickness of the active pattern 18. This is to prevent the formation of a step in the gate electrode 16 at the position where the active pattern 18 ends.

That is, as shown in FIG. 7, the dummy active pattern 36 formed at a predetermined distance from the upper and lower portions of the active pattern 18 is formed between the active pattern 18 and the gate electrode 16 as in the related art. Capacitances Cg ', Cp1', and Cp2 'may have different values than the same unit area according to their positions.

As the dummy active pattern 36 is formed, the gate insulating layer 26 and the gate electrode 16 formed on the active pattern 18 and the dummy active pattern 36 are edges of the active pattern 18. It is possible to suppress the formation of the step in the portion to the maximum, thereby reducing the value of the high capacitance formed in the stepped portion of the gate electrode 16 and the edge portion of the active pattern 18, which has been conventionally generated. do.

In other words, the capacitance Cg ′ formed at the center portion of the active pattern 18 and the gate electrode 16, that is, the flat portion, and the end portion of the active pattern 18, the active pattern 18, and the dummy active pattern 36. The values of capacitances Cp1 'and Cp2' formed at the portion of the gate electrode 16 slightly bent by the grooves between the two sides, although not coincident with each other, do not show a large difference.

Accordingly, the influence of the parasitic transistors formed on both curved portions where Cp1 'and Cp2' are formed can be minimized, and since the values of Cp1 'and Cp2' do not show a large difference from the values of Cg ', both curved portions By preventing the occurrence of electric field crowding phenomenon, the threshold voltage (Vth) is lower than the region where Cg 'is formed, thereby suppressing the hump characteristic that is turned on early. It becomes possible.

8 illustrates an active pattern and a dummy active pattern of a polysilicon thin film transistor according to the present invention.

Referring to FIG. 8, the active pattern 18 is formed to have a constant width because it must be in electrical contact with the source electrode (not shown) and the drain electrode (not shown). In contrast, the dummy active pattern 36 is positioned above and below the active pattern 18 by a predetermined distance, and a width of the dummy active pattern 36 is formed on the active pattern 18 and the dummy active pattern 36. Is equal to or slightly wider than

Here, the predetermined distance is about 0.1 μm or more, and the width of the dummy active pattern 36 should have a width such that the gate insulating film (not shown) and the gate electrode can be supported.

9 is a cross-sectional view showing a manufacturing process of a polysilicon thin film transistor according to the present invention. However, FIG. 9 illustrates a manufacturing process centering on cross sections of C-C 'and D-D' in FIG.

Referring to Figure 9 describes the manufacturing process of the polysilicon thin film transistor according to the present invention.

The active pattern 18 is formed by depositing a silicon layer on the substrate 38 and forming a silicon pattern through nicking with a photoresist.

Here, the silicon layer is composed of polysilicon, which is formed by forming amorphous silicon at a low temperature of 500Å to 800Å by CVD at low temperature, and then crystallizing by annealing with laser immediately, or forming amorphous silicon by CVD at low temperature and forming a gate insulating film thereon. An insulating film such as a silicon oxide film is formed to have a thickness of about 1000 GPa, and then laser annealing is formed. The active pattern 16 and the dummy active pattern 36 are simultaneously formed during the silicon pattern. Therefore, the dummy active pattern 36 is formed of the same material as the active pattern 18.

However, unlike the active pattern 18, the dummy active pattern 36 is not connected to the source and drain electrodes because the dummy active pattern 36 does not serve as a channel for transmitting a signal in the data line to the pixel electrode. (A)

Next, the gate insulating layer 26 and the gate layer 40 are sequentially stacked on the active pattern 18 and the dummy active pattern 36. The gate insulating layer 26 is formed of a silicon oxide film or a silicon nitride film, and the gate film 40 is formed by stacking a metal layer to a predetermined thickness. In this case, aluminum (Al) or aluminum alloy (Al) is used. alloy), chromium (Cr), etc. (B)

Next, a photoresist is applied on the gate layer 40 and exposed using a photomask, and then a constant photoresist pattern is left through development. At this time, the gate electrode 16 is formed by the photoresist pattern, and the source region 28 of the p-type or n-type thin film transistor is formed by performing p-type or n-type high dose ion implantation with the photoresist pattern removed. ) And the drain region 30 are formed. Ion implantation usually proceeds with high energy, typically 80 to 90 keV (C).

Next, an insulating layer 32 is deposited on the surface on which the gate electrode 16 is formed. At this time, the insulating layer 32 uses a silicon oxide film or a silicon nitride film. (D)

Next, via holes (not shown) are formed in the corresponding portions of the source region 28 and the drain region 30 formed above, and a metal layer (not shown) is deposited. After depositing the metal layer (not shown), the source electrode 12 and the drain electrode 14 are formed only in a region in which the via hole (not shown) is formed through a general semiconductor process, and the sour electrode 12 and the drain are formed. When the electrode 14 is formed, a protective film 42 is deposited thereon. (E)

Finally, after forming a contact hole (not shown) above the drain electrode 14, a metal layer (not shown) is deposited and the pixel electrode 34 in contact with the drain electrode 14 through a general semiconductor process. Is formed. (F)

As a result, the method of manufacturing the top gate polysilicon thin film transistor according to the present invention can suppress the hump phenomenon by additionally simultaneously forming the dummy active pattern during the active pattern forming process without any additional process to the conventional thin film transistor manufacturing process. Will be.

As described above, according to the top gate type polysilicon thin film transistor according to the present invention and a method of manufacturing the same, the step difference between the gate insulating layer and the gate electrode generated at the edge of the active pattern can be reduced by adding a dummy active pattern to the active pattern. As a result, the concentration of the electric field formed on the gate electrode and the active pattern edge is prevented, thereby suppressing the hump phenomenon.

In addition, this has the advantage of suppressing the hump phenomenon while using the conventional process as it is without additional process, the thickness of the active pattern, the thickness of the gate insulating film in the realistic manufacturing situation of the thin film transistor of the present invention The effect is further increased.

Claims (8)

In the top gate type polysilicon thin film transistor in which an active pattern, a gate insulating film, a gate electrode, a source and a drain electrode are sequentially formed on a substrate, A dummy active pattern formed at a position spaced a predetermined distance from an end of the active pattern formed under the gate electrode and the gate insulating layer to suppress the formation of a step in the edge region of the active pattern as much as possible; Top gate polysilicon thin film transistor, characterized in that. The method of claim 1, And the dummy active pattern is positioned above and below the active pattern, and the width of the dummy active pattern is equal to or wider than the width of the gate electrode. The method of claim 1, And the dummy active pattern is not connected to the source and drain electrodes. The method of claim 1, And wherein the dummy active pattern is formed of the same material as the active pattern. The method of claim 1, The active pattern is made of polysilicon top gate type polysilicon thin film transistor. Forming a dummy active pattern on a substrate at a position spaced a predetermined distance from both ends of the active pattern; Forming a gate insulating film on a surface on which the active pattern and the dummy active pattern are formed; Forming a gate electrode on the gate insulating layer formed on an area where the active pattern and the dummy active pattern are formed; And forming an insulating layer, a source and a drain electrode sequentially on the surface on which the gate electrode is formed. The method of claim 6, The dummy active pattern may be positioned above and below the active pattern, and the width of the dummy active pattern may be equal to or wider than the width of the gate electrode. The method of claim 6, The dummy active pattern is not connected to the source and drain electrodes, the method of manufacturing a top gate type polysilicon thin film transistor.

Images