JP2010003910A - Display element - Google Patents

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JP2010003910A
JP2010003910A JP2008161894A JP2008161894A JP2010003910A JP 2010003910 A JP2010003910 A JP 2010003910A JP 2008161894 A JP2008161894 A JP 2008161894A JP 2008161894 A JP2008161894 A JP 2008161894A JP 2010003910 A JP2010003910 A JP 2010003910A
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formed
active layer
driving
thin film
circuit
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JP2008161894A
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Arichika Ishida
有親 石田
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Toshiba Mobile Display Co Ltd
東芝モバイルディスプレイ株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal panel which suppresses display unevenness and power consumption and is driven fast. <P>SOLUTION: A display element has a plurality of n-channel type pixel driving TFTs 33 each having an active layer 33c formed of at least an oxide semiconductor. The display element has a plurality of TFTs 45 for driving circuits each having an active layer 45c formed of a non-oxide semiconductor. Sub-pixels are driven by the pixel driving TFTs 33 which suppress variation in defect density among the active layers 33c and are relatively low in threshold voltage, so the display unevenness and power consumption are suppressed. A driver is driven by the TFTs 45 for the driving circuits each having the active layer 45c formed of the non-oxide semiconductor having high field-effect mobility, so high-speed driving becomes possible. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display element including an n-channel thin film transistor including an active layer formed of an oxide semiconductor.

  In recent years, a display device integrated with a drive circuit in which drive circuits such as an interface circuit and a timing generation circuit are integrated on a glass substrate has been developed.

  In a thin film transistor used as such a drive circuit, a polycrystalline silicon thin film melt-crystallized by, for example, an excimer laser is used as an active layer.

  However, a polycrystalline silicon film melt-crystallized with an excimer laser has a variation in the density of defects in the film due to variations in the energy of laser shots. There's a problem.

On the other hand, in recent years, research on thin film transistors using an oxide semiconductor such as InGaZnO as an active layer has been advanced. These oxide semiconductors hardly cause local variations (see, for example, Patent Document 1).
JP 2008-72012 A

  However, since an oxide semiconductor can generally be formed only in an n-channel type, when a thin film transistor in which an active layer is formed using an oxide semiconductor is applied to a driver circuit, if only one channel can be formed, power consumption increases. .

In addition, since the field effect mobility of an oxide semiconductor is approximately 10 cm 2 / Vs, there is a problem that it is not easy to form a high-speed driver circuit.

  The present invention has been made in view of these points, and an object of the present invention is to provide a display element that can suppress display unevenness and power consumption and can be driven at high speed.

  The present invention includes a substrate, a driving active layer formed of at least an oxide semiconductor, a plurality of n-channel pixel driving thin film transistors formed on the substrate, and a circuit formed of a non-oxide semiconductor A plurality of driving circuit thin film transistors formed on the substrate, driven by the pixel driving thin film transistors, and driven by at least the driving circuit thin film transistors, And a driving circuit for driving the driving thin film transistor.

  And an n-channel pixel driving thin film transistor for driving a pixel having a driving active layer formed of at least an oxide semiconductor on a substrate and a circuit active layer formed of a non-oxide semiconductor. A driving circuit thin film transistor for driving the driving circuit is formed.

  According to the present invention, since the pixel is driven by the pixel driving thin film transistor in which variation in the defect density of the driving active layer is suppressed and the threshold voltage is relatively low, display unevenness and power consumption can be suppressed, and the driving circuit Can be driven by a thin film transistor for a driver circuit having a second active layer formed of a non-oxide semiconductor having a high field effect mobility, so that high-speed driving is possible.

  Hereinafter, the structure of the display element of the 1st Embodiment of this invention is demonstrated with reference to drawings.

  In FIG. 3, reference numeral 11 denotes a liquid crystal display element as a display element, that is, a liquid crystal panel which is an LCD (Liquid Crystal Display). The liquid crystal panel 11 is, for example, planar light from a backlight which is a planar light source device (not shown). A transmission type that modulates and transmits the image.

  The liquid crystal panel 11 is, for example, an active matrix type capable of color display, and an array substrate 16 as a first substrate as a substrate device and a counter substrate 17 as a second substrate are illustrated as gap holding members. The liquid crystal layer 18 as a light modulation layer is interposed between the substrates 16 and 17, and a polarizing plate (not shown) is attached to each of the substrates 16 and 17. , 17 are bonded and fixed together by a seal portion 19 as an adhesive portion, and a rectangular display region 20 in which sub-pixels SP, which are pixels for displaying an image, are formed in a matrix is formed in a substantially central portion. In addition, a frame portion 21 that is a frame-like non-display region is formed around the display region 20.

  As shown in FIGS. 1 and 2, the array substrate 16 has a glass substrate 25 as a first substrate body as a light-transmitting substrate, for example, on the main surface of the glass substrate 25 on the liquid crystal layer 18 side. The scanning lines (gate wirings) 31 and the signal lines (source wirings) 32, which are a plurality of wirings formed in a thin film shape by a conductor such as a metal member, are arranged in a lattice shape so as to be substantially orthogonal to each other. In addition, a pixel driving thin film transistor 33 (hereinafter referred to as a pixel driving TFT 33), which is a first thin film transistor for driving a pixel as a switching element, is provided at each crossing position of the scanning line 31 and the signal line 32, An alignment film (not shown) for aligning the liquid crystal molecules of the liquid crystal layer 18 is provided thereon. The scanning line 31 is electrically connected to a gate driver 36 which is a scanning line driving circuit as a driving circuit, and the signal line 32 is electrically connected to a source driver 37 which is a signal line driving circuit as a driving circuit. It is connected to the.

  The pixel driving TFT 33 is a bottom-gate n-channel thin film transistor, and is formed on an interlayer insulating film 41 which is a first insulating film such as a silicon oxide film or a silicon nitride film formed on the glass substrate 25. A gate insulating film 42 which is a second insulating film such as a silicon oxide film or a silicon nitride film is formed on the gate electrode 33g, and an active layer which is a driving active layer as a first active layer is formed on the gate insulating film 42. A layer 33c is formed, and a source electrode 33s and a drain electrode 33d are formed on the active layer 33c, and an etching stopper layer 43 that is a channel protective film such as a silicon nitride film self-aligned with the gate electrode 33g is formed. Covering the source electrode 33s, the drain electrode 33d, and the etching stopper layer 43, the protective film is a third insulating film such as a silicon oxide film or a silicon nitride film. Film 44 is formed.

  The gate electrode 33g is formed by protruding a part of the scanning line 31. Therefore, the gate electrode 33g is electrically connected to the scanning line 31. The source electrode 33s is electrically connected to the signal line 32. Further, the drain electrode 33d is electrically connected to a pixel electrode (not shown) formed of a transparent conductive material such as ITO on the protective insulating film 44 and the auxiliary capacitor Cs. The source electrode 33s and the drain electrode 33d are simultaneously formed by the same material and the same process.

The active layer 33c is formed in an oxide semiconductor, for example, an island shape the InGaZnO 4 by sputtering and etching.

  The pixel driving TFT 33 is switched by applying a signal from the gate driver 36 to the gate electrode 33g via the scanning line 31, and corresponds to a signal input from the source driver 37 via the signal line 32. By applying a voltage to the pixel electrode, the subpixels SP can be turned on / off independently.

  The gate driver 36 and the source driver 37 are electrically connected to a controller (not shown) that is formed on the glass substrate 25 and includes a data processing circuit, a clock generation circuit, and the like. Here, the data processing circuit processes RGB data input from an external device and outputs it to the source driver 37 as a video signal, and the clock generation circuit operates in each of the drivers 36 and 37. A clock signal for controlling the timing is generated and output. The gate driver 36 and the source driver 37 are composed of a driving circuit thin film transistor 45 (hereinafter referred to as driving circuit TFT 45) as a second thin film transistor forming a pair for driving circuit and a circuit driving thin film transistor 46 (hereinafter referred to as driving circuit thin film transistor 46). Circuit driving TFT 46).

  The drive circuit TFT 45 is a top-gate p-channel thin film transistor, and an active layer 45c, which is a circuit active layer as a second active layer, is formed on the glass substrate 25. The active layer 45c is an interlayer insulating film. The gate electrode 45g is formed on the interlayer insulating film 41, and the source electrode 45s and the drain electrode 45d are formed on the gate insulating film 42 covering the gate electrode 45g. The source electrode 45s and the drain electrode 45d Are electrically connected to the active layer 45c through the contact holes 48 and 49, respectively, and the source electrode 45s and the drain electrode 45d are covered with the protective insulating film 44.

  The active layer 45c is formed in an island shape from polycrystalline silicon which is a non-oxide semiconductor, that is, polysilicon (p-Si). In the active layer 45c, a source region 45cs electrically connected to the source electrode 45s is formed on one side, and a drain region 45cd electrically connected to the drain electrode 45d is formed on the other side. .

  The gate electrode 45g is formed simultaneously with the same material and in the same process as the gate electrode 33g of the pixel driving TFT 33.

  The source electrode 45s and the drain electrode 45d are simultaneously formed in the same material and in the same process as the source electrode 33s and the drain electrode 33d of the pixel driving TFT 33, respectively.

  The circuit driving TFT 46 is a bottom-gate n-channel thin film transistor having the same configuration as the pixel driving TFT 33. Therefore, in the circuit driving TFT 46, a gate electrode 46g is formed on the interlayer insulating film 41, and an active layer 46c which is a circuit driving active layer as a third active layer is formed on the gate insulating film 42 covering the gate electrode 46g. A source electrode 46s and a drain electrode 46d are formed on the active layer 46c, and an etching stopper layer 50 that is a channel protective film such as a silicon nitride film self-aligned with the gate electrode 46g is formed on the active layer 46c. The drain electrode 46d and the etching stopper layer 50 are covered with the protective insulating film 44.

  The gate electrode 46g is formed simultaneously with the same material and in the same process as the gate electrode 33g of the pixel driving TFT 33. Further, the source electrode 46s and the drain electrode 46d are simultaneously formed in the same material and in the same process as the source electrode 33s and the drain electrode 33d of the pixel driving TFT 33.

The active layer 46c is formed in an island shape by sputtering and etching an oxide semiconductor such as InGaZnO 4 . The active layer 46c is formed simultaneously with the same material and the same process as the active layer 33c of the pixel driving TFT 33.

  In the TFTs 45 and 46, for example, the gate electrodes 45g and 46g are electrically connected to each other, and the drain electrode 45d and the source electrode 46s or the drain electrode 46d and the source electrode 45s are electrically connected to each other. Complementary switching circuits are formed.

  The contact holes 48 and 49 are formed through the gate insulating film 42 and the interlayer insulating film 41 by etching or the like, for example.

  The auxiliary capacitor Cs is electrically in parallel with the liquid crystal capacitor of the liquid crystal layer 18, and is used to redistribute the potential and determine the voltage applied to the pixel electrode. The same electrode and the same material as the gate electrode 33g are simultaneously formed in the same process, and the other electrode is simultaneously formed in the same process and the same material as the drain electrode 33d of the pixel driving TFT 33. It is electrically connected to the drain electrode 33d of the driving TFT 33.

  As shown in FIG. 3, the counter substrate 17 has a glass substrate 55 which is a second substrate body having translucency. On the glass substrate 55, a color filter layer, a counter electrode and an alignment film (not shown) are provided. Etc. are sequentially laminated.

  The color filter layer is formed in a thin film shape for each sub-pixel SP, for example, with a synthetic resin corresponding to the three primary colors of RGB, and has, for example, a stripe shape in plan view. The color filter layer may be formed on the array substrate 16 side.

  The counter electrode is formed by a sputtering method or the like with a transparent conductive material such as ITO at a position corresponding to the pixel electrode in the display region 20.

  The liquid crystal layer 18 is a light modulation layer formed of a predetermined liquid crystal material.

  Further, the seal portion 19 is formed in a frame shape (frame shape) surrounding the display region 20 with a predetermined adhesive or the like.

  Next, the manufacturing method of the first embodiment will be described.

  In manufacturing the array substrate 16, first, an amorphous silicon (a-Si) film is formed on a glass substrate 25 on which an unillustrated undercoat layer or the like is formed, for example, by a CVD (Chemical Vapor Deposition) method as shown in FIG. (Amorphous silicon film forming step) After annealing for a predetermined time at a predetermined temperature (annealing step), this amorphous silicon film is melt crystallized by, for example, excimer laser annealing (ELA) method to form a polysilicon film PS, Patterning into a predetermined shape by photoetching or the like (polysilicon film forming step). At this time, one electrode of the auxiliary capacitor Cs is simultaneously formed of the same material.

  Next, as shown in FIG. 5, an interlayer insulating film 41 is formed so as to cover the polysilicon film PS by, eg, CVD (interlayer insulating film forming step).

  Thereafter, as shown in FIG. 6, a single layer of tantalum, chromium, aluminum, molybdenum, tungsten, copper, or the like, or a laminated film thereof, an alloy film or the like (not shown) is deposited on the interlayer insulating film 41, and a photoetching method or the like. The gate electrodes 33g, 45g, and 46g are formed together with the scanning lines 31 and the like (gate electrode forming step) by patterning them into a predetermined shape by using a resist that has been coated so that impurities are not implanted. For example, a source region 45cs and a drain region 45cd are formed in the active layer 45c by doping boron, for example (doping step).

  Further, as shown in FIG. 7, the gate insulating film 42 covering the gate electrodes 33g, 45g, 46g is formed by using, for example, PECVD (Plasma Enhanced CVD) (gate insulating film forming step).

Alternatively, for example, oxygen is used as a sputtering gas, a metal that does not contain oxygen as a target, or an oxide semiconductor having a lower oxygen concentration than the stoichiometric composition, and a DC sputtering method that is a reactive sputtering method, InGaZnO is used. Active layers 33c and 46c are formed from oxide semiconductors such as 4 (active layer forming step), and etching stopper layers 43 and 50 are further formed (etching stopper layer forming step).

  Then, as shown in FIG. 8, contact holes 48 and 49 are formed in the gate insulating film 42 and the interlayer insulating film 41 by, eg, photoetching (first contact hole forming step), and further, tantalum, chromium, aluminum Each electrode 33s, 33d, 45s, 45d, 46s, and 46d is formed by depositing a single layer of molybdenum, tungsten, copper, etc., or a laminated film or alloy film thereof, and patterning it into a predetermined shape by a photoetching method or the like. Then, the TFTs 33, 45, and 46 are completed (electrode formation process).

  Thereafter, as shown in FIG. 1, a protective insulating film 44 is formed by PECVD or the like so as to cover the electrodes 33s, 33d, 45s, 45d, 46s, and 46d (protective insulating film forming step). Then, a contact hole is formed (second contact hole forming step), for example, an ITO film is formed by sputtering or the like, and then patterned into a predetermined shape by a photoetching method or the like to form a pixel electrode (pixel electrode forming step) Further, an alignment film and spacers are formed to complete the array substrate 16.

  As described above, in the first embodiment, the n-channel pixel driving TFT 33 that has the active layer 33c formed of at least an oxide semiconductor and drives the sub-pixel SP and the non-oxide semiconductor are formed. A driving circuit TFT 45 that has the active layer 45c formed and drives the gate driver 36 and the source driver 37 is formed.

  For this reason, for example, compared with the case where a thin film transistor having an active layer formed by melting and crystallizing an amorphous silicon film to form a polysilicon film is used for pixel driving, the pixel driving TFT 33 suppresses variation in the defect density of the active layer 33c. In addition, since the threshold voltage is low, it is possible to suppress visible display unevenness and power consumption, and each of the drivers 36 and 37 includes an active layer 45c formed of a non-oxide semiconductor having high field effect mobility. Since it is driven by the TFT 45 for use, high-speed driving becomes possible.

  In addition, by driving each driver 36, 37 with a driving circuit TFT 45 and a circuit driving TFT 46, a complementary switching circuit can be configured by these TFTs 45, 46, and power consumption can be further suppressed. Since the driving TFT 46 has fewer manufacturing steps than an n-channel type thin film transistor in which an active layer is formed of a non-oxide semiconductor, for example, an increase in manufacturing steps can be suppressed.

  Furthermore, each TFT 33, 45, 46 can be formed simultaneously with the same material and the same process as the gate electrodes 33g, 45g, 46g, etc., so the increase in man-hours is suppressed and the cost is increased more than necessary while ensuring manufacturability Can be prevented.

  Further, by forming the auxiliary capacitor Cs at the same time using the same material and the same process as a part of the TFTs 33, 45, and 46, the number of steps can be reduced as compared with the case where a process for forming the auxiliary capacitor is separately required.

  Next, a second embodiment will be described with reference to the drawings. In addition, about the structure and effect | action similar to the said 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  In the second embodiment, instead of the circuit driving TFT 46 of the first embodiment, as shown in FIG. 9, a driving circuit thin film transistor 58 as a fourth thin film transistor for the driving circuit (hereinafter referred to as the other TFT). The other driving circuit TFT 58 is paired with one driving circuit TFT 45.

  The other drive circuit TFT 58 is a top-gate n-channel thin film transistor, and an active layer 58c, which is a circuit active layer as a fourth active layer, is formed on the glass substrate 25. This active layer 58c is an interlayer. A gate electrode 58g is formed on the interlayer insulating film 41 and is covered with the insulating film 41. A source electrode 58s and a drain electrode 58d are formed on the gate insulating film 42 covering the gate electrode 58g, and the source electrode 58s and the drain are formed. The electrode 58d is electrically connected to the active layer 58c through the contact holes 61 and 62, respectively, and the source electrode 58s and the drain electrode 58d are covered with the protective insulating film 44.

  The active layer 58c is formed in an island shape from polycrystalline silicon which is a non-oxide semiconductor, that is, polysilicon (p-Si). In the active layer 58c, a source region 58cs electrically connected to the source electrode 58s is formed on one side, and a drain region 58cd electrically connected to the drain electrode 58d is formed on the other side. In addition, an LDD (Lightly Doped Drain) region (not shown) is formed adjacent to the source region 58cs and the drain region 58cd.

  The gate electrode 58g is formed simultaneously with the same material and the same process as the gate electrode 33g of the pixel driving TFT 33.

  The source electrode 58s and the drain electrode 58d are simultaneously formed by the same material and the same process as the source electrode 33s and the drain electrode 33d of the pixel driving TFT 33, respectively.

  When the array substrate 16 is manufactured, as shown in FIG. 10, an amorphous silicon (a-Si) film is formed on the glass substrate 25 on which an undercoat layer (not shown) is formed by, for example, the CVD method. After film formation (amorphous silicon film forming step) and annealing at a predetermined temperature for a predetermined time, this amorphous silicon film is melt-crystallized by, for example, excimer laser annealing to form a polysilicon film PS (annealing step), and predetermined by photoetching or the like (Polysilicon film forming step). At this time, one electrode of the auxiliary capacitor Cs is simultaneously formed of the same material.

  Next, as shown in FIG. 11, for example, an interlayer insulating film 41 is formed by covering the polysilicon film PS by the CVD method (interlayer insulating film forming step), and the resist is applied so that impurities are not implanted. A source region 58cs and a drain region 58cd are formed in the active layer 58c (first doping step) by doping, for example, phosphorus by ion implantation or ion doping method, etc. with the masking of the portion (first doping step), and further LDD in the active layer 58c. Impurities are activated by implanting impurities to form regions and annealing them (LDD region forming step).

  Thereafter, as shown in FIG. 12, a single layer of tantalum, chromium, aluminum, molybdenum, tungsten, copper, or the like, or a laminated film or an alloy film thereof, not shown, is deposited on the interlayer insulating film 41, and a photoetching method or the like. The gate electrodes 33g, 45g, and 58g are formed together with the scanning lines 31 and the like by patterning into a predetermined shape (gate electrode formation step), and a part is masked with a resist that is applied so that impurities are not implanted. For example, a source region 45cs and a drain region 45cd are formed in the active layer 45c by doping boron, for example (second doping step).

  Further, as shown in FIG. 13, the gate insulating film 42 covering the gate electrodes 33g, 45g, 58g is formed by using, for example, PECVD (gate insulating film forming step).

Alternatively, for example, oxygen is used as a sputtering gas, a metal that does not contain oxygen as a target, or an oxide semiconductor having a lower oxygen concentration than the stoichiometric composition, and a DC sputtering method that is a reactive sputtering method, InGaZnO is used. Each of the active layers 33c is formed of an oxide semiconductor such as 4 (active layer forming step), and further, an etching stopper layer 43 is formed (etching stopper layer forming step).

  Then, as shown in FIG. 14, contact holes 48, 49, 61, 62 are formed in the gate insulating film 42 and the interlayer insulating film 41 by, eg, photoetching (first contact hole forming step), and further tantalum. Each electrode 33s, 33d, 45s, 45d, 58s is formed by depositing a single layer of chromium, aluminum, molybdenum, tungsten, copper, etc., or a laminated film or alloy film thereof, and patterning it into a predetermined shape by a photoetching method or the like. , 58d are formed (electrode forming step), and the TFTs 33, 45, 58 are completed.

  Thereafter, as shown in FIG. 9, a protective insulating film 44 is formed by PECVD or the like so as to cover these electrodes 33s, 33d, 45s, 45d, 58s and 58d (for example, a photo-etching method). Then, a contact hole is formed (second contact hole forming step), for example, an ITO film is formed by sputtering or the like, and then patterned into a predetermined shape by a photoetching method or the like to form a pixel electrode (pixel electrode forming step) Further, an alignment film and spacers are formed to complete the array substrate 16.

  As described above, the gate driver includes the n-channel pixel driving TFT 33 that has at least the active layer 33c formed of the oxide semiconductor and drives the subpixel SP, and the active layer 45c formed of the non-oxide semiconductor. By having the same configuration as in the first embodiment, such as forming the drive circuit TFT 45 for driving 36 and the source driver 37, the same effects as the first embodiment can be obtained. it can.

  In addition, the gate driver 36 and the source driver 37 include not only the p-channel type driving circuit TFT 45 in which the active layer 45c is formed of a non-oxide semiconductor, but also the n-channel type driving in which the active layer 58c is formed of a non-oxide semiconductor. By using the circuit TFT 58, it is possible to further suppress power consumption by configuring a complementary switching circuit with the TFTs 45 and 58, and the TFTs 45 and 58 have high field-effect mobility. Can be driven at higher speed.

  In the second embodiment, for example, as in the third embodiment shown in FIG. 15, the thin film transistors constituting the gate driver 36 and the source driver 37 may be only the driving circuit TFT 45. In this case, the manufacturing man-hours of the drivers 36 and 37 can be further suppressed.

  Further, for example, as in the fourth embodiment shown in FIG. 16, the thin film transistors constituting the gate driver 36 and the source driver 37 may be only the driving circuit TFT 58. In this case, manufacturing man-hours can be suppressed while suppressing a decrease in the driving speed of each of the drivers 36 and 37.

  Further, in each of the above embodiments, each sub-pixel SP (pixel) is driven by a thin film transistor, and if the thin film transistor is driven by another thin film transistor, not only the liquid crystal panel 11 but also an organic EL, for example, It can be applied to any other display element.

It is a longitudinal cross-sectional view which shows the principal part of the display element of the 1st Embodiment of this invention. It is a circuit diagram which shows a display element same as the above. It is a description side view which shows a display element same as the above. It is explanatory sectional drawing which shows the amorphous silicon film formation process of the manufacturing method of a display element same as the above, an annealing process, and a polysilicon film formation process. It is explanatory sectional drawing which shows the interlayer insulation film formation process of the manufacturing method of a display element same as the above. It is explanatory sectional drawing which shows the gate electrode formation process and doping process of the manufacturing method of a display element same as the above. It is explanatory sectional drawing which shows the gate insulating film formation process, active layer formation process, and etching stopper layer formation process of the manufacturing method of a display element same as the above. It is explanatory sectional drawing which shows the 1st contact hole formation process and electrode formation process of the manufacturing method of a display element same as the above. It is a longitudinal cross-sectional view which shows the principal part of the display element of the 2nd Embodiment of this invention. It is explanatory sectional drawing which shows the amorphous silicon film formation process of the manufacturing method of a display element same as the above, an annealing process, and a polysilicon film formation process. It is explanatory sectional drawing which shows the interlayer insulation film formation process, 1st doping process, and LDD area | region formation process of the manufacturing method of a display element same as the above. It is explanatory sectional drawing which shows the gate electrode formation process and 2nd doping process of the manufacturing method of a display element same as the above. It is explanatory sectional drawing which shows the gate insulating film formation process, active layer formation process, and etching stopper layer formation process of the manufacturing method of a display element same as the above. It is explanatory sectional drawing which shows the 1st contact hole formation process and electrode formation process of the manufacturing method of a display element same as the above. It is a longitudinal cross-sectional view which shows the principal part of the display element of the 3rd Embodiment of this invention. It is a longitudinal cross-sectional view which shows the principal part of the display element of the 4th Embodiment of this invention.

Explanation of symbols

11 Liquid crystal panels as display elements
25 Glass substrate as substrate
33 Thin film transistor for pixel drive
33c Active layer for driving
36 Gate driver as drive circuit
37 Source driver as drive circuit
45, 58 Thin film transistor for drive circuit
Active layer that is an active layer for 45c and 58c circuits
46 Thin film transistor for circuit drive
46c Active layer as an active layer for circuit drive
Sub pixel that is SP pixel

Claims (3)

  1. A substrate,
    A plurality of n-channel pixel driving thin film transistors each including an active layer for driving formed of an oxide semiconductor and formed on the substrate;
    A plurality of driving circuit thin film transistors formed on the substrate, comprising a circuit active layer formed of a non-oxide semiconductor;
    A plurality of pixels respectively driven by the pixel driving thin film transistors;
    A display element comprising: a driving circuit that is driven by at least the driving circuit thin film transistor and drives each pixel driving thin film transistor.
  2. An active layer for circuit driving formed of at least an oxide semiconductor, and an n-channel type circuit driving thin film transistor formed on the substrate,
    The display device according to claim 1, wherein the driving circuit is driven by the driving circuit thin film transistor and the circuit driving thin film transistor.
  3. The display element according to claim 1, wherein the driving circuit thin film transistor is at least one of a top-gate p-channel thin film transistor and a top-gate n-channel thin film transistor.
JP2008161894A 2008-06-20 2008-06-20 Display element Pending JP2010003910A (en)

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