JP2001196590A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a large number of unpaired bonding hands are formed at crystal grain boundaries, when a crystalline semiconductor film composed of crystal grains is low in orientation properties, and the crystal semiconductor film is deteriorated in carrier (electron, hole) transfer properties. SOLUTION: This manufacturing method comprises a first process in which the surface of a substrate is exposed to a plasma atmosphere that contains halogen, a second process in which an amorphous semiconductor film is formed on the substrate, a third process in which a layer that contains a catalytic element which promotes the crystallization of the amorphous semiconductor film is formed on the amorphous semiconductor film, a fourth process in which the amorphous semiconductor film is turned into a crystalline semiconductor film through a first thermal treatment, a fifth process in which the crystalline semiconductor film is selectively removed into inland-like crystalline semiconductor films, a sixth process in which a gate insulating film is formed on the island- like crystalline semiconductor films, and a seventh process in which the substrate is subjected to a second thermal treatment in an oxidizing atmosphere after the sixth process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter, referred to as TFT) on a substrate having an insulating surface and a method for manufacturing the same. In particular, the present invention relates to an electro-optical device typified by a liquid crystal display device in which a pixel circuit and a control circuit provided therearound are provided on the same substrate, and an electronic apparatus equipped with the electro-optical device.

[0002]

2. Description of the Related Art A thin film transistor (hereinafter, referred to as TFT) can be manufactured using a semiconductor film formed on a substrate. TFTs can form various integrated circuits as active elements. In particular, a switching element provided in a pixel portion of an active matrix type liquid crystal display device,
Alternatively, it can be used as an element for forming a driving circuit provided around the pixel portion.

A TFT using an amorphous silicon film as a semiconductor film has a low process temperature and is easy to produce, but has a drawback of low electrical characteristics. Therefore, it can be used as a switching element provided in each pixel, but it has not been possible to form a drive circuit. However, a semiconductor film having a crystalline structure (hereinafter, referred to as a crystalline semiconductor film) has a TF
It is known that the electrical characteristics can be enhanced by forming T. A silicon film having a crystal structure as a typical example of a crystalline semiconductor film is also known as a polycrystalline silicon film, a polysilicon film, a microcrystalline silicon film, or the like.
In the technical field of FT, a crystalline silicon film obtained by crystallizing an amorphous silicon film by light or thermal energy is used in many cases.

However, the thermal crystallization method using thermal energy requires a heat treatment at a temperature of 600 ° C. or higher, and requires a processing time of about 10 hours. Therefore, there is a problem that productivity is reduced. On the other hand, as a crystallization technique using light energy, a laser crystallization method using an excimer laser beam or a YAG laser beam is known, but the electrical characteristics are inferior to those of a TFT manufactured by a thermal crystallization method. There is.

Further, a technique for forming a crystalline semiconductor film by a thermal crystallization method using a catalytic element is known. For example, JP-A-7-130652, JP-A-8-783
The technology disclosed in Japanese Patent Publication No. 29 and the like can be used. According to the thermal crystallization method using a catalytic element, a catalytic element such as nickel is introduced into an amorphous silicon film, and a temperature of 550 ° C.
A crystalline silicon film can be formed by heat treatment for a long time.

[0006]

A base film made of silicon oxide, silicon nitride, silicon oxynitride or the like is formed on a substrate such as glass, and an amorphous semiconductor film deposited thereon is subjected to a thermal crystallization method or a laser. The crystalline semiconductor film obtained by crystallization by the crystallization method is preferentially oriented to <111> according to the magnitude relationship of the interface energy between the base film and the semiconductor film, and has a random orientation in other directions. It is known from analysis of electron diffraction that many crystal grains exist. On the other hand, in a crystalline semiconductor film formed by a thermal crystallization method using a catalyst element such as nickel, most of the crystal grains are oriented in <110>. However, as described above, other orientations such as <111> are slightly mixed depending on the interface energy between the base film and the semiconductor film.

[0007] In a crystalline semiconductor film composed of a plurality of crystal grains, if the orientation is low, many dangling bonds are formed at the crystal grain boundaries, and the carrier (electron / hole) transport characteristics in the crystalline semiconductor film are degraded. . That is, since a carrier is scattered or trapped, a TFT having a high field-effect mobility even when a TFT is manufactured using such a crystalline semiconductor film.
Cannot be produced. In addition, since the crystal grain boundaries are present at random, they may cause variations in the electrical characteristics of individual TFTs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a means for solving the above-mentioned problems, and to provide an orientation of a crystalline semiconductor film formed by using an amorphous semiconductor film by a thermal crystallization method or a laser crystallization method. The purpose is to enhance the nature. Further, it is another object of the present invention to improve the characteristics of the TFT by using such a crystalline semiconductor film and reduce the variation in the characteristics.

[0009]

According to the present invention, a first step of exposing a surface of a substrate to a plasma atmosphere containing a halogen element, a second step of forming an amorphous semiconductor film on the substrate, A third step of forming a layer containing a catalytic element that promotes crystallization of the amorphous semiconductor film on the amorphous semiconductor film, and forming the crystalline semiconductor film by performing a first heat treatment on the amorphous semiconductor film. Forming a crystalline semiconductor film, selectively removing the crystalline semiconductor film to form an island-shaped crystalline semiconductor film, and forming a gate insulating film on the island-shaped crystalline semiconductor film. And a seventh step of performing a second heat treatment in an oxidizing atmosphere containing halogen after the sixth step.

A first step of exposing the surface of the substrate to a plasma atmosphere containing a halogen element; a second step of forming an amorphous semiconductor film on the substrate; A third step of forming a first insulating film, a fourth step of forming a layer containing a catalytic element that promotes crystallization of the amorphous semiconductor film on the amorphous semiconductor film, A fifth step of forming a crystalline semiconductor film by performing a first heat treatment on the amorphous semiconductor film, a sixth step of removing the first insulating film, and selectively removing the crystalline semiconductor film. A seventh step of forming an island-shaped crystalline semiconductor film by removing, and an eighth step of forming a gate insulating film on the island-shaped crystalline semiconductor film.
And a ninth step of performing a second heat treatment in an oxidizing atmosphere containing halogen after the eighth step.

[0011]

[Embodiment 1] As shown in FIG. 11A, a base film formed on a quartz substrate 1101 or on its surface contains a halogen atom (fluorine in this embodiment) 1103. To fluorinate the surface of the substrate. Specifically, the surface is exposed to an atmosphere of fluorine or fluorine radicals, and the surface is coated with fluorine.
As the halogen element, chlorine, bromine, and the like can be used.

For example, silicon tetrafluoride (SiF ₄ ) or nitrogen trifluoride (NF ₃ ) is introduced and turned into plasma to generate fluorine atoms or fluorine radicals. As the means, for example, a plasma CVD apparatus can be applied. Plasma CVD devices include capacitively coupled or inductively coupled plasma CVD devices and ECR (Electron Cycloton Resonance).
Any type of device such as a plasma CVD device or a microwave CVD device may be applied. In particular, since ECR plasma and microwave plasma have high gas decomposition efficiency, fluorine radicals can be efficiently generated.

The surface of the fluorinated substrate 1102 is
A semiconductor film 1104 having an amorphous structure with a thickness of 0 to 100 nm (preferably 40 to 80 nm) is formed by a low pressure thermal CVD method.
It is formed by a plasma CVD method or a sputtering method (FIG. 11).
(B)). The semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film. For example, an amorphous silicon film made of SiH ₄ or SiH ₄ and H ₂ by plasma CVD
It is formed with a thickness of 5 nm. Alternatively, Si ₂
An amorphous silicon film may be formed with a thickness of 55 nm from H ₆ . Further, it is also effective to continuously form a base film and an amorphous silicon film on a substrate without exposing them to the atmosphere.

Then, as shown in FIG. 11C, a layer 1105 containing the catalyst element is formed by spin coating in which an aqueous solution containing 10 ppm by weight of the catalyst element is applied by rotating the substrate with a spinner. Catalyst elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), and gold. (Au). The layer 1104 containing the catalyst element can be formed by a printing method, a spray method, a bar coater method,
Alternatively, the catalyst element layer may be formed to a thickness of 1 to 5 nm by a sputtering method or a vacuum evaporation method.

In the crystallization step shown in FIG. 11D, a heat treatment is first performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atom% or less. If the hydrogen content of the amorphous silicon film has this value from the beginning after film formation, this heat treatment is not always necessary.
Then, thermal crystallization is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours using a furnace annealing furnace. Preferably, heat treatment is performed at 550 ° C. for 4 hours. Thus, a crystalline semiconductor film 1106 made of a crystalline silicon film can be obtained.

A predetermined region of the crystalline semiconductor film 1106 thus manufactured is etched to form the island-like semiconductor film 1.
107 is formed. Then, the gate insulating film 11 is formed thereon.
08 is formed of an insulating film containing silicon as a component to a thickness of 20 to 200 nm. For example, SiH _{4 is formed by} a plasma CVD method.
70nm silicon oxynitride film from a mixed gas of the N ₂ O
Formed to a thickness of

Then, a heat treatment at 700 to 1100 ° C. in an oxidizing atmosphere containing halogen (typically chlorine) is performed for 0.1 hour.
Perform for ~ 8 hours. By this heat treatment, the gate insulating film 110
A new oxide film is formed at the interface between the gate insulating film 8 and the island-shaped semiconductor film 1107, and the thickness of the gate insulating film 1108 becomes 120 nm.
In addition, the gate insulating film 1 is oxidized in a halogen atmosphere.
The metal impurity element and the like contained in the semiconductor film 108 and the island-shaped semiconductor film 1107 form a compound with halogen and can be removed in the gas phase. Further, the gate insulating film 1108 has a high withstand voltage and can reduce the interface state density with the island-shaped semiconductor film (FIG. 11E).

[Embodiment 2] An example of manufacturing a TFT using an island-shaped semiconductor film and a gate insulating film manufactured according to Embodiment 1 will be described. FIG. 12 shows n formed on the substrate 301.
2 shows a cross-sectional structure of a channel type and a p-channel type TFT. The gate electrodes of the n-channel TFT and the p-channel TFT are formed of first conductive layers 311 and 313 provided in contact with the gate insulating film 310 and 312 and 314 provided in contact with the first conductive layer. Consists of

The first conductive layers 311 and 313 are formed of an element such as titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), or a material containing these elements as components. In addition, the second conductive layers 312, 314
May be made of aluminum (Al) or copper (Cu) having low resistivity. Depending on the application, the conductive layer may be formed using only the first conductive layer, or another conductive layer may be stacked on the second conductive layer.

The semiconductor layer of the p-channel TFT includes a source region 303 and a drain region 304.

The channel forming region 302 may be doped with boron in advance. This boron is added to control the threshold voltage, and another element can be used as long as the same effect can be obtained.

When the n-channel TFT and the p-channel TFT are completed in this way, the first interlayer insulating film 315,
The source regions 303 and 30 are covered with a second interlayer insulating film 316.
9, source wirings 317 and 319 that are in contact with the drain regions 304 and 308 and drain wirings 318 are provided. FIG.
In the second structure, a silicon nitride film is provided as the passivation film 320 after these are provided. Further, a third interlayer insulating film 321 made of a resin material is provided. The third interlayer insulating film does not need to be limited to a resin material. For example, when applied to a liquid crystal display device, it is preferable to use a resin material in order to ensure flatness of the surface.

[Third Embodiment] Similar to the first embodiment, the surface of a base film formed on a quartz substrate 1201 or on a substrate surface is treated with a plasma 1202 containing fluorine (FIG. 13).
After (A)), an amorphous semiconductor film 1204 is formed on the treated surface 1203 by 30 to 100 nm, preferably 50 to 100 nm.
It is formed with a thickness of 60 nm. For example, an amorphous silicon film made of SiH ₄ or SiH ₄ and H ₂ is formed with a thickness of 55 nm by a plasma CVD method (FIG. 13B). Alternatively, an amorphous silicon film may be formed with a thickness of 55 nm from Si ₂ H ₆ by a low pressure CVD method. Amorphous semiconductor film 120
4 a mask film 1 made of an insulating film containing silicon (silicon)
205 is formed with a thickness of 150 nm, and an opening 1206 is formed by patterning (FIG. 13C).

A layer holding a catalyst element is formed on the surface of a semiconductor film having an amorphous structure, and heat treatment is performed. In the present embodiment, nickel is used as a catalyst element,
Heat treatment for 4 hours is performed. As a result, the crystallization proceeds from the opening 1206 as a starting point in a direction substantially parallel to the substrate (the direction indicated by the arrow), and a semiconductor film having a crystal structure in which macroscopic crystal growth directions are aligned (in this embodiment, Quality silicon film) is formed. (FIG. 13D)

Next, a gettering step of removing nickel used in the crystallization step from the crystalline silicon film is performed.
Using the mask film 1205 formed earlier as it is as a mask, a step of adding an element belonging to Group 15 (phosphorus in this embodiment) is performed, and 1 × 10 ¹⁹ to 1 × 10 9 A phosphorus-added region (hereinafter referred to as a gettering region) 1207 containing phosphorus at a concentration of ²⁰ atoms / cm ³ is formed.

Next, at 450 to 650 ° C. in a nitrogen atmosphere.
(Preferably 500 to 550 ° C.) and a heat treatment step for 4 to 24 hours (preferably 6 to 12 hours) are performed. By this heat treatment step, nickel in the crystalline silicon film moves in the direction of the arrow, and is captured in the gettering region 107 by the gettering action of phosphorus. That is, since nickel is removed from the crystalline silicon film, the concentration of nickel contained in the crystalline silicon film after gettering is 1 × 10 ¹⁷ at.
ms / cm ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ (FIG. 13E).

Thereafter, the mask 1205 is removed, and an island-like semiconductor film 1208 is formed from the obtained crystalline semiconductor film in the same manner as in the first embodiment. Further, by forming a gate insulating film and performing a heat treatment in an oxidizing atmosphere containing halogen, a gate insulating film having a high withstand voltage can be formed as in the first embodiment, and an interface state with the island-shaped semiconductor film can be formed. Density can be reduced. Then, the TFT described in Embodiment 2 can be formed.

[Embodiment 4] In Embodiments 1 and 3, a semiconductor film having an amorphous structure is formed by plasma CVD or low-pressure CVD.
The method of manufacturing from SiH ₄ or Si ₂ H _{6 by the} D method was described. In this embodiment mode, a case of manufacturing using another gas is described.

A feature of the manufacturing method of this embodiment is that the semiconductor film having an amorphous structure is formed by using a reaction gas containing a halogen element and hydrogen. Specifically, a halogen element and hydrogen are mixed when, for example, an amorphous silicon film is formed as a semiconductor film having an amorphous structure. It is particularly preferable to use fluorine as the halogen element, and fluorine has an effect of etching silicon, and a portion having a weak bond can be preferentially etched in a film deposition process. Further, by supplying hydrogen, the concentration of fluorine remaining in the film can be reduced. Then, a dense amorphous silicon film with few voids and vacancies can be manufactured by utilizing the action of fluorine and hydrogen. Such an effect can be obtained by an amorphous silicon-germanium (a-SiGe) film, an amorphous silicon carbide (a
-SiC) film, amorphous silicon tin (a-SiSn)
It can be applied to a film and the like.

The method of supplying fluorine and hydrogen is as follows. When an amorphous silicon film is formed as an amorphous semiconductor film, silicon tetrafluoride (SiF ₄ ) and hydrogen (H ₂ ) or SiF ₄ are used as reaction gases. And SiH ₄ , or a combination of SiF ₄ , SiH ₄ and H ₂ can be selected. Instead of SiF ₄ , trifluorosilane (SiHF ₃ ), difluorosilane (SiH ₂ F ₂ ), or monofluorosilane (SiH ₃ F) can also be used. Further, SiH ₄ and F ₂ may be directly reacted. Further, germanium (GeH ₄ ) or germanium tetrafluoride (GeF ₄ ) is used for forming an amorphous silicon-germanium film, and methane (CH ₄ ) or tetrafluoride is used for forming an amorphous silicon carbide film. Methane (C
For forming an amorphous silicon / tin film such as F ₄ ), tin hydride (SnH ₄ ) may be appropriately added.

The thickness of the semiconductor film having an amorphous structure is 25
It is formed with a thickness of about 100 nm. In the initial stage of film deposition, the surface of the base can be fluorinated by the effect of fluorine.

As described above, the semiconductor film 1103 having an amorphous structure manufactured by using a reaction gas containing fluorine and hydrogen contains 0.1% of hydrogen in the film depending on the substrate temperature at the time of film formation. It is formed so as to contain ２０20 atomic% and 0.1０．１10 atomic% of fluorine. Fluorine and hydrogen remaining in the film are released from the film in the subsequent thermal crystallization step and the concentration remaining in the film further decreases, but the dense amorphous semiconductor film and the outermost surface are made of fluorine. Interaction with the terminated base film can further enhance the orientation of <110>.

[Embodiment 5] As a method of fluorinating the surface of the base or the interface between the base and the amorphous semiconductor film, FIG.
As shown in FIG. 1 or FIG. 13, after an amorphous semiconductor film is formed on a quartz substrate as it is, fluorine may be implanted from the surface of the amorphous semiconductor film. As the technique, an ion doping method or an ion implantation method is used.

In the ion doping method, SiF is used as an ion source.
Ionization is performed using F ₄ or F ₂ diluted with helium (He), and the ions are implanted from the surface of the amorphous semiconductor film. The acceleration voltage is set high so that the peak of the concentration distribution of the injected fluorine exists at or near the interface between the amorphous semiconductor film 1103 and the base film 1102. In that case, the peak concentration is 1 ×
It is set to 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ . In the ion doping method, elements other than fluorine are implanted at the same time because they are not separated by mass, but are suitable for processing a large-area substrate such as a liquid crystal display device. Also, fluorine can be implanted at a similar concentration at the interface between the amorphous semiconductor film and the base or in the vicinity thereof by an ion implantation method. Further, by implanting fluorine ions from the surface of the amorphous semiconductor film,
The effect of destroying microcrystalline nuclei that may exist in the amorphous semiconductor film can be obtained at the same time, and the nucleation density in thermal crystallization can be reduced.

When a layer containing a catalytic element is provided in contact with the amorphous semiconductor film 1103 and crystallized in the same manner as in Embodiment 1 in a state in which fluorine is implanted, the same effect can be obtained.

[Embodiment 6] The crystalline semiconductor film manufactured as shown in this embodiment has a low interfacial energy between a quartz substrate and silicon formed thereon. It is known from electron diffraction analysis that when a crystalline silicon film is crystallized by a thermal crystallization method, it is preferentially oriented to <111>, and there are many other crystal grains having random orientations. On the other hand, crystalline silicon films produced by a thermal crystallization method using a catalyst element such as nickel
Microscopically, it has a structure in which a plurality of needle-like or rod-like crystals are aggregated. However, it is expected that the continuity of adjacent crystal grains is high and dangling bonds are hardly formed. Most of the crystal grains are oriented in <110>. One of the reasons is
The crystal growth process in the case of using a catalyst element such as nickel is considered to involve silicide of the catalyst element. Since the thickness of the semiconductor film is as thin as 25 to 100 nm, (111) It is considered that the orientation substantially perpendicular to the substrate surface grows preferentially, so that the orientation of <110> substantially increases. However, as described above, since the interface energy between the quartz substrate and silicon is low, <11
1> It is possible to take other plane orientations included in the crystal zone. Therefore, other orientations are slightly mixed.

However, in the thermal crystallization method using a catalytic element, the surface of the quartz substrate is fluorinated,
The effect of the interface with the quartz substrate can be reduced, and the effect can be substantially ignored. As a result, the orientation of the crystal is affected only by the surface energy, but the orientation of <110> is increased by the crystal growth using the catalytic element. Such an effect can be realized by a normal thermal crystallization method, a laser crystallization method, or the like, but can be more remarkably obtained by a thermal crystallization method using a catalytic element. The crystalline semiconductor film manufactured in this manner can be suitably used as a semiconductor film for manufacturing a TFT as described in Embodiment Mode 2.

[0038]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel circuit and a control circuit for controlling the pixel circuit over the same substrate will be described. However, for the sake of simplicity, the control circuit shows a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

In FIG. 1A, a quartz substrate or a silicon substrate is desirably used as the substrate 100. In this embodiment, a quartz substrate was used. Alternatively, a substrate obtained by forming an insulating film on the surface of a metal substrate or a stainless steel substrate may be used as the substrate. In the case of this embodiment, since heat resistance that can withstand a temperature of 800 ° C. or more is required, any substrate may be used as long as it meets the requirement.

Then, the surface of the substrate 100 on which TFTs are to be formed is treated with the plasma 101a, and the treated substrate surface 101b is treated with 20 to 100 nm (preferably 40 to 100 nm).
A semiconductor film 102 having an amorphous structure with a thickness of 80 nm is formed by a low pressure thermal CVD method, a plasma CVD method, or a sputtering method. In this embodiment, an amorphous silicon film having a thickness of 60 nm is formed, but since a thermal oxidation step is performed later, this film thickness does not necessarily become the final film thickness of the active layer of the TFT.)

The semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film. . Further, it is also effective to continuously form a base film and an amorphous silicon film on a substrate without exposing them to the atmosphere. By doing so, it becomes possible to prevent contamination of the substrate surface from affecting the amorphous silicon film, and it is possible to reduce the variation in characteristics of the TFT to be manufactured.

Next, a mask film 103 made of an insulating film containing silicon (silicon) is formed on the amorphous silicon film 102, and openings 104a and 104b are formed by patterning. The opening serves as an addition region for adding a catalyst element that promotes crystallization in the next crystallization step.
(FIG. 1 (B))

Note that as the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The silicon nitride oxide film is an insulating film containing silicon, nitrogen, and oxygen in predetermined amounts, and is an insulating film represented by SiOxNy. Silicon nitride oxide film is SiH
4. N2O and NH3 can be produced as source gas, and the nitrogen concentration is 25 atomic% or more and 50 atom
It is good to be less than mic%.

At the same time as the patterning of the mask film 103 is performed, a marker pattern serving as a reference for a subsequent patterning step is formed. When the mask film 103 is etched, the amorphous silicon film 102 is also slightly etched. However, this step can be used as a marker pattern at the time of mask alignment later.

Next, a semiconductor film having a crystal structure is formed according to the technique described in Japanese Patent Application Laid-Open No. Hei 10-247735 (corresponding to US Application No. 09 / 034,041). The technology described in the publication discloses a catalyst element (nickel, cobalt, germanium, tin, lead, palladium, etc.) that promotes crystallization during crystallization of a semiconductor film having an amorphous structure.
Crystallization means using one or more elements selected from iron and copper).

Specifically, heat treatment is performed with the catalyst element held on the surface of the semiconductor film having an amorphous structure, and the semiconductor film having an amorphous structure is changed to a semiconductor film having a crystalline structure. It is to let. As the crystallization means, the technique described in Example 1 of JP-A-7-130652 may be used. In addition, a semiconductor film including a crystalline structure includes a so-called single crystal semiconductor film and a polycrystalline semiconductor film, and a semiconductor film including a crystal structure formed in the publication has a crystal grain boundary.

In this publication, a spin-coating method is used when a layer containing a catalytic element is formed on a mask film.
Means for forming a thin film containing a catalytic element by a gas phase method such as a sputtering method or an evaporation method may be employed.

Although it depends on the hydrogen content, the amorphous silicon film is preferably subjected to a heat treatment at 400 to 550 ° C. for about 1 hour to sufficiently desorb the hydrogen before crystallization. . In this case, the hydrogen content is preferably set to 5 atom% or less.

The crystallization step is first performed at 400 to 500 ° C. for 1 hour.
After performing a heat treatment process for about an hour to desorb hydrogen from the film, the heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600 ° C.).
C.) for 6 to 16 hours (preferably 8 to 14 hours).

In this embodiment, nickel is used as a catalyst element, and a heat treatment is performed at 570 ° C. for 14 hours. as a result,
From the openings 104a and 104b as starting points, crystallization proceeds in a direction substantially parallel to the substrate (direction indicated by an arrow), and a semiconductor film having a crystal structure in which macroscopic crystal growth directions are aligned (in this embodiment, a crystalline film). Silicon films) 105a to 105d are formed. (Fig. 1 (C))

Next, a gettering step of removing nickel used in the crystallization step from the crystalline silicon film is performed.
In this embodiment, a step of adding an element belonging to Group XV (phosphorus in this embodiment) using the previously formed mask film 103 as a mask is performed, and the crystalline silicon film exposed in the openings 104a and 104b is added to the 1 × 10 4 ¹⁹ to 1 × 10 ²⁰ at
Phosphorus-added regions (hereinafter, referred to as gettering regions) 106a and 106b containing phosphorus at a concentration of oms / cm ³ are formed.
(Fig. 1 (D))

Next, at 450 to 650 ° C. in a nitrogen atmosphere.
(Preferably 500 to 550 ° C.) and a heat treatment step for 4 to 24 hours (preferably 6 to 12 hours) are performed. By this heat treatment step, nickel in the crystalline silicon film moves in the direction of the arrow, and is captured in the gettering regions 106a and 106b by the gettering action of phosphorus. That is, since nickel is removed from the crystalline silicon film, the concentration of nickel contained in the crystalline silicon films 107a to 107d after gettering is 1 × 10 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁷ atms / cm ³ or less.
It can be reduced to × 10 ¹⁶ atms / cm ³ .

Next, the mask film 103 is removed, and a protective film 108 is formed on the crystalline silicon films 107a to 107d for the later addition of impurities. The protective film 108 is 100 to 2
It is preferable to use a silicon nitride oxide film or a silicon oxide film with a thickness of 00 nm (preferably 130 to 170 nm). This protective film 108 has a meaning to prevent the crystalline silicon film from being directly exposed to plasma at the time of adding an impurity and to enable fine concentration control.

Then, a resist mask 109 is formed thereon, and an impurity element imparting p-type (hereinafter, referred to as a p-type impurity element) is added via the protective film 108. As the p-type impurity element, an element belonging to Group 13 typically, typically, boron or gallium can be used.
This step (called a channel doping step) is a step for controlling the threshold voltage of the TFT. Here, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.

By this step, 1 × 10 ¹⁵ to 1 × 10 ¹⁸ at
oms / cm ³ (typically 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / c
Impurity regions 110a and 110b containing a p-type impurity element (boron in this embodiment) at a concentration of m ³ ) are formed. Note that in this specification, an impurity region containing a p-type impurity element within the above concentration range (a region not containing phosphorus) is defined as a p-type impurity region (b). (FIG. 1 (E))

Next, the resist mask 109 is removed, and the crystalline silicon film is patterned to form island-shaped semiconductor layers (hereinafter, referred to as active layers) 111 to 114. In addition,
The active layers 111 to 114 are formed of a crystalline silicon film having extremely good crystallinity by selectively adding nickel and crystallizing. Specifically, it has a crystal structure in which rod-shaped or columnar crystals are arranged with a specific direction. Further, after crystallization, nickel is removed or reduced by the gettering action of phosphorus.
The concentration of the catalyst element remaining in 14 is 1 × 10 ¹⁷ atms / c
m ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ . (Figure 1
(F))

The active layer 111 of the p-channel TFT
Is a region not containing an impurity element intentionally added, and the active layers 112 to 114 of the n-channel TFT are p-type impurity regions (b). In this specification, the active layers 111 to 114 in this state are all defined as being intrinsic or substantially intrinsic. That is, a region to which an impurity element is intentionally added to such an extent that the operation of the TFT is not hindered may be considered as a substantially intrinsic region.

Next, an insulating film containing silicon having a thickness of 10 to 100 nm is formed by a plasma CVD method or a sputtering method. In this embodiment, a 30-nm-thick silicon nitride oxide film is formed. As the insulating film containing silicon, another insulating film containing silicon may be used as a single layer or a stacked layer.

Next, at 800-1150 ° C. (preferably 9 ° C.)
A heat treatment step at a temperature of (00 to 1000 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment step is performed at 950 ° C. for 80 minutes in an atmosphere in which 3% by volume of hydrogen chloride is added in an oxygen atmosphere. Note that boron added in the step of FIG. 1E is activated during this thermal oxidation step. (Figure 2
(A))

The oxidizing atmosphere may be a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer.
Further, in this embodiment, an atmosphere in which a halogen element is included in an oxygen atmosphere is used, but the atmosphere may be performed in a 100% oxygen atmosphere.

During this thermal oxidation step, an oxidation reaction also proceeds at the interface between the insulating film containing silicon and the active layers 111 to 114 thereunder. In the present invention, in consideration of this, the thickness of the gate insulating film 115 finally formed is 50 to 200 nm.
(Preferably 100 to 150 nm). In the thermal oxidation step of this embodiment, 25 nm of the active layer having a thickness of 60 nm is oxidized, and the thickness of the active layers 111 to 114 becomes 45 nm. Further, since a 50-nm-thick thermal oxide film is added to the 30-nm-thick silicon-containing insulating film, the final gate insulating film 115 has a thickness of 110 nm.

Next, resist masks 116 to 11 are newly added.
9 is formed. Then, an impurity element imparting n-type (hereinafter referred to as an n-type impurity element) is added to form impurity regions 120 to 122 exhibiting n-type. Note that as the n-type impurity element, an element belonging to Group XV, typically, phosphorus or arsenic can be used. (Figure 2
(B))

The impurity regions 120 to 122 will be
N-channel type TF of MOS circuit and sampling circuit
T is an impurity region for functioning as an LDD region. The impurity region formed here has n
The type impurity element is contained at a concentration of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ (typically, 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ ). In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).

Here, phosphorus is added at a concentration of 1 × 10 ¹⁸ atoms / cm ³ by an ion doping method in which phosphine (PH ₃ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the crystalline silicon film via the gate film 115.

Next, at 600 to 1000 ° C. (preferably 7 ° C.)
Heat treatment is performed in an inert atmosphere (at 00 to 800 ° C.) to activate the phosphorus added in the step of FIG. In this embodiment, the heat treatment at 800 ° C. for 1 hour is performed in a nitrogen atmosphere.
(Fig. 2 (C))

At this time, it is possible to repair the active layer damaged at the time of adding phosphorus and the interface between the active layer and the gate insulating film. In this activation step, furnace annealing using an electric heating furnace is preferable, but optical annealing such as lamp annealing or laser annealing may be used together.

By this step, n-type impurity region (b) 12
The boundary portion between 0 and 122, that is, the junction with the intrinsic or substantially intrinsic region (including the p-type impurity region (b)) existing around the n-type impurity region (b) becomes clear. . This means that when the TFT is completed later, LDD
This means that the region and the channel forming region can form a very good junction.

Next, a conductive film to be a gate wiring is formed. Note that the gate wiring may be formed using a single-layer conductive film, but is preferably a stacked film such as two layers or three layers as necessary. In this embodiment, a stacked film including the first conductive film 123 and the second conductive film 124 is formed. (FIG. 2 (D))

Here, the first conductive film 123 and the second conductive film 12
4 include tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (C
r), an element selected from silicon (Si), or a conductive film containing the above element as a main component (typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film combining the above elements ( Typically, a Mo-W alloy film, a Mo-Ta alloy film, a tungsten silicide film, etc.)
Can be used.

The first conductive film 123 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm) and the second conductive film 124
Is 200 to 400 nm (preferably 250 to 350 n
m). In this embodiment, a 50 nm thick tungsten nitride (WN) film is used as the first conductive film 123, and a 350 nm thick tungsten film is used as the second conductive film 124. Although not shown, it is effective to form a silicon film under the first conductive film 123 with a thickness of about 2 to 20 nm. This can improve the adhesion of the conductive film formed thereon and prevent oxidation.

It is also effective to use a tantalum nitride film as the first conductive film 123 and a tantalum film as the second conductive film.

Next, the first conductive film 123 and the second conductive film 12
4 are collectively etched to form gate wirings 125 to 128 having a thickness of 400 nm. At this time, gate wirings 126 and 127 formed in the control circuit are n-type impurity regions (b).
The gate insulating film 115 is formed so as to overlap with a part of the gate insulating films 120 to 122. This overlapping portion will later become a Lov region. Although the gate wirings 128a and 128b appear to be two in cross section, they are actually formed from one continuous pattern. (FIG. 2 (E))

Next, a resist mask 129 is formed, and p
The impurity regions 130 and 131 containing boron at a high concentration are formed by adding a type impurity element (boron in this embodiment).
In this embodiment, 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically, 5 × 10 ^{21 to} 3 × 10 ²¹ atoms / cm ³ ) by an ion doping method (of course, an ion implantation method) using diborane (B ₂ H ₆ ).
Boron is added at a concentration of (× 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ). In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (FIG. 3 (A))

Next, the resist mask 129 is removed, and resist masks 132 to 134 are formed so as to cover the gate wiring and the region to be the p-channel TFT. And n
The impurity regions 135 to 141 containing phosphorus at a high concentration are formed by adding a type impurity element (phosphorus in this embodiment). Also in this case, the ion doping method using phosphine (PH ₃ ) (of course, the ion implantation method may be used), and the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ at.
oms / cm ³ (typically ^{2 × 10 20 ~5 × 10 2} 1 atoms / c
m ³ ). (FIG. 3 (B))

In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). The region where the impurity regions 135 to 141 are formed contains phosphorus or boron already added in the previous step, but phosphorus is added at a sufficiently high concentration. You do not need to consider the effect of phosphorus or boron. Therefore, in this specification, the impurity regions 135 to 141 may be referred to as n-type impurity regions (a).

Next, the resist masks 132 to 134 are removed, and an n-type impurity element (phosphorus in this embodiment) is added in a self-aligned manner using the gate wirings 125 to 128 as a mask. The impurity regions 143 to 146 thus formed have a concentration of の to 1/10 (typically ３ to ４) of the n-type impurity region (b) (however, the channel doping step described above). 5 to 10 times higher than the boron concentration added in the step (1), typically 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ,
Typically, adjustment is performed so that phosphorus is added at 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ³ ). Note that, in this specification, an impurity region containing an n-type impurity element (excluding the p-type impurity region (a)) in the above concentration range is defined as an n-type impurity region (c). (FIG. 3 (C))

In this step, 1 × 10 ^{16 to} 5 × 1 is applied to all the impurity regions except for the portion hidden by the gate wiring.
Although phosphorus is added at a concentration of 0 ¹⁸ atoms / cm ³ , the function is extremely low and does not affect the function of each impurity region. The n-type impurity regions (b) 142 to 147 have already been formed in the channel doping step at 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms.
Although boron is added at a concentration of s / cm ³ , phosphorus is added at a concentration of 5 to 10 times that of boron contained in the p-type impurity region (b) in this step.
It may be considered that the function of the type impurity region (b) is not affected.

Next, a first interlayer insulating film 148 is formed.
The first interlayer insulating film 148 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. Further, the film thickness may be 100 to 400 nm. In the present embodiment, SiH ₄ , N
_A silicon nitride oxide film having a thickness of 200 nm (nitrogen concentration: 25 to 50 atomic%) is used with ₂ O and NH ₃ as source gases.

Thereafter, a heat treatment step was performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by furnace annealing, laser annealing, lamp annealing, or a combination thereof. When performing the furnace annealing method,
The heat treatment may be performed at 500 to 800C, preferably 550 to 600C in an inert atmosphere. In this embodiment, 600
A heat treatment is performed at 4 ° C. for 4 hours to activate the impurity element.
(FIG. 3 (D))

In this embodiment, tungsten is used as a wiring material, but it is known that a tungsten film is very susceptible to oxidation. That is, even if it is covered with the protective film and oxidized, if the pinhole exists in the protective film, it is immediately oxidized. However, in this embodiment, a very effective silicon nitride film is used as an antioxidant film, and a silicon nitride oxide film is laminated on the silicon nitride film. It is possible to carry out the activation step at a high temperature without having to do so.

Next, after the activation step, heat treatment is performed at 300 to 450 ° C. for 1 to 4 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the active layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

After the activation step, the first interlayer insulating film 1
A second interlayer insulating film 149 having a thickness of 500 nm to 1.5 μm is formed on the gate insulating film 48. In this embodiment, the second interlayer insulating film 149 is used.
800nm thick silicon oxide film as plasma CVD
It is formed by a method. Thus, a 1 μm-thick interlayer insulating film composed of a stacked film of the first interlayer insulating film (silicon nitride oxide film) 148 and the second interlayer insulating film (silicon oxide film) 149 is formed.

If heat resistance is allowed in a later step, an organic resin film such as polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene) can be used as the second interlayer insulating film 149. .

Thereafter, contact holes reaching the source region or the drain region of each TFT are formed, and the source wirings 150 to 153 and the drain wiring 154 are formed.
To 156 are formed. In order to form a CMOS circuit, the drain wiring 154 is shared between the p-channel TFT and the n-channel TFT. Although not shown, in the present embodiment, this wiring is
nm, Ti-containing aluminum film 500 nm, Ti film 1
A three-layer laminated film having a thickness of 00 nm formed continuously by a sputtering method. (FIG. 4 (A))

Next, as a passivation film 157,
A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film having a thickness of 50 to 500 nm (typically, 200 to 300 nm);
(nm). At this time, in this embodiment, a plasma treatment is performed using a gas containing hydrogen such as H ₂ and NH ₃ before forming the film, and a heat treatment is performed after the film is formed. Hydrogen excited by this pretreatment is supplied into the first and second interlayer insulating films. By performing the heat treatment in this state, the film quality of the passivation film 157 is improved, and the hydrogen added to the first and second interlayer insulating films diffuses to the lower layer side, so that the active layer is effectively hydrogenated. be able to.

After the passivation film 157 is formed, a hydrogenation step may be further performed. For example, 3
300 to 450 ° C. in an atmosphere containing １００100% hydrogen
The heat treatment is preferably performed for 1 to 12 hours, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening (not shown) may be formed in the passivation film 157 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed after the hydrogenation step.

Then, a third interlayer insulating film 158 made of an organic resin is formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film or an organic SiO compound other than those described above can also be used. Here, it is formed by baking at 300 ° C. using a type of polyimide which is thermally polymerized after being applied to the substrate.

Next, in a region to be a pixel circuit, the third
A shielding film 159 is formed over the interlayer insulating film 158. In addition,
In this specification, the term shielding film is used to mean that light and electromagnetic waves are shielded. The shielding film 159 is made of aluminum (A
1) A film made of an element selected from titanium (Ti) and tantalum (Ta) or a film containing any one of the elements as a main component and having a thickness of 100 to 300 nm. In this embodiment, 1w
An aluminum film containing t% titanium is formed to a thickness of 125 nm.

When an insulating film such as a silicon oxide film is formed on the third interlayer insulating film 158 in a thickness of 5 to 50 nm, the adhesion of the shielding film formed thereon can be improved. In addition, when plasma treatment using CF ₄ gas is performed on the surface of the third interlayer insulating film 158 formed of an organic resin, adhesion of a shielding film formed on the film can be improved by surface modification.

It is also possible to form not only a shielding film but also other connection wirings by using the aluminum film containing titanium. For example, connection wiring for connecting the circuits in the control circuit can be formed. However, in that case, before forming the material for forming the shielding film or the connection wiring, the third
It is necessary to form a contact hole in the interlayer insulating film.

Next, an oxide 160 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the shielding film 159 by anodic oxidation or plasma oxidation (in this embodiment, anodic oxidation). In this embodiment, the shielding film 159 is used.
Is used, an aluminum oxide film (alumina film) is formed as the anodic oxide 160.

In this anodizing treatment, first, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration is prepared. This is a solution obtained by mixing a 15% aqueous solution of ammonium tartrate and ethylene glycol at a ratio of 2: 8, and ammonia water is added thereto to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, and the substrate on which the shielding film 159 is formed is immersed in the solution.
A DC current of several tens mA) is passed.

The voltage between the cathode and the anode in the solution changes with time according to the growth of the anodic oxide, but the voltage is increased at a constant current of 100 V / min at a boosting rate to reach the ultimate voltage of 45 V. By the way, the anodizing treatment is terminated. In this way, the surface of the shielding film 159 has a thickness of about 50
nm anodic oxide 160 can be formed. As a result, the thickness of the shielding film 159 becomes 90 nm.
It is to be noted that the numerical values relating to the anodic oxidation method shown here are merely examples, and the optimum values can naturally vary depending on the size of the element to be manufactured.

Although the insulating film is provided only on the surface of the shielding film by using the anodic oxidation method here, the insulating film may be formed by a gas phase method such as a plasma CVD method, a thermal CVD method or a sputtering method. good. In this case, the film thickness is 20 to 1
It is preferably set to 00 nm (preferably 30 to 50 nm). In addition, silicon oxide film, silicon nitride film, silicon nitride oxide film, DLC (Diamond like carbon)
A film, a tantalum oxide film, or an organic resin film may be used.
Further, a stacked film combining these may be used.

Next, a contact hole reaching the drain wiring 156 is formed in the third interlayer insulating film 158 and the passivation film 157, and a pixel electrode 161 is formed. In addition,
The pixel electrode 162 is a pixel electrode of another adjacent pixel.
The pixel electrodes 161 and 162 may be formed using a transparent conductive film when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is formed. Here, in order to obtain a transmissive liquid crystal display device, indium tin oxide (IT
O) A film is formed to a thickness of 110 nm by a sputtering method.

At this time, the pixel electrode 161 and the shielding film 1
59 overlap with each other via the anodic oxide 160 to form a storage capacitance (capacity striation) 163. Note that in this case, it is desirable that the shielding film 159 be set to a floating state (an electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal transmitted as data).

Thus, an active matrix substrate having a control circuit and a pixel circuit on the same substrate was completed. In FIG. 4B, a p-channel TFT 1301 and n-channel TFTs 1302 and 130 are included in the control circuit.
3 is formed, and a pixel TFT 1304 formed of an n-channel TFT is formed in the pixel circuit.

In the p-channel TFT 1301 of the control circuit, a channel forming region 201, a source region 202, and a drain region 203 are each formed of a p-type impurity region (a). However, strictly speaking, the source 202 region and the drain region 203 contain phosphorus at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ .

The n-channel type TFT 1302 includes:
The channel formation region 204, the source region 205, the drain region 206, and a region between the channel formation region and the drain region which overlaps with the gate wiring with a gate insulating film interposed therebetween (in this specification, such a region is referred to as a Lov region That.
In addition, ov is attached with the meaning of overlap. ) 207 is formed. At this time, the Lov area 207 is 2 × 10 ^{16 to} 5 × 10
It is formed so as to contain phosphorus at a concentration of ¹⁹ atoms / cm ³ and to completely overlap with the gate wiring.

The n-channel TFT 1303 includes:
LDD regions 211 and 212 are formed so as to sandwich the channel formation region 208, the source region 209, the drain region 210, and the channel formation region. That is, an LDD region is formed between the source region and the channel formation region and between the drain region and the channel formation region.

In this structure, the LDD regions 211, 2
12 are arranged so as to overlap with the gate wiring, a region (Lov region) that overlaps with the gate wiring via the gate insulating film and a region that does not overlap with the gate wiring (such a region is referred to as Loff region, where off is
Affixed in the meaning of offset. ) Has been realized.

Here, the cross-sectional view shown in FIG. 6 is an enlarged view showing a state in which the n-channel TFT 1303 shown in FIG. 4B is manufactured up to the step of FIG. As shown here, the LDD region 211 is further divided into Lov regions 211a and Loff regions.
It can be distinguished into the area 211b. Also, the Lov region 21 described above is used.
Although 1a contains phosphorus at a concentration of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , the Loff region 211b has a concentration of 1 to 2 times (typically, 1.2 to 1.5 times). Contains phosphorus.

The pixel TFT 1304 includes channel forming regions 213 and 214, a source region 215, a drain region 216, Loff regions 217 to 220, and an Loff region 21.
8, 219 are formed in contact with n-type impurity regions (a) 221. At this time, the source region 215 and the drain region 21
6 are each formed of an n-type impurity region (a),
Regions 217 to 220 are formed by n-type impurity regions (c).

In the present embodiment, the structure of the TFT forming each circuit can be optimized according to the circuit specifications required by the pixel circuit and the control circuit, and the operation performance and reliability of the semiconductor device can be improved. Specifically, n-channel type TF
T makes the arrangement of the LDD region different according to the circuit specifications,
By properly using the ov region or the Loff region, a TFT structure emphasizing high-speed operation or measures against hot carriers and a TFT structure emphasizing low off-current operation can be realized on the same substrate.

For example, in the case of an active matrix type liquid crystal display device, the n-channel type TFT 1302 is suitable for a control circuit such as a shift register circuit, a frequency dividing circuit, a signal dividing circuit, a level shifter circuit, and a buffer circuit which emphasizes high-speed operation. That is, the Lov region is formed only between the channel formation region and the drain region, so that the resistance component is reduced as much as possible and the hot carrier measures are emphasized. This is because, in the case of the above-described circuit group, the functions of the source region and the drain region do not change and the direction in which carriers (electrons) move is constant.

However, an Lov region can be formed with a channel forming region interposed therebetween, if necessary. That is, it can be formed between the source region and the channel formation region and between the drain region and the channel formation region.

Further, the n-channel type TFT 1303 is suitable for a sampling circuit (sample-and-hold circuit) which emphasizes both hot carrier measures and low off-current operation.
That is, the hot carrier is prevented by forming the Lov region, and a low off-current operation is realized by forming the Loff region. In the sampling circuit, the functions of the source region and the drain region are reversed, and the carrier moving direction is 18
Since the angle is changed by 0 °, the structure must be line-symmetric with respect to the gate wiring. In some cases, L
There may be only the ov region.

Further, the n-channel TFT 1304 is suitable for a pixel circuit and a sampling circuit (sample-hold circuit) which place importance on low off-current operation. That is, the Lov region, which can be a factor for increasing the off-current value, is not arranged, and
By arranging the f region and the offset region, low off-current operation is realized. Further, by using an LDD region having a lower concentration than the LDD region of the control circuit as the Loff region, a measure is taken to thoroughly reduce the off-current value even if the on-current value is slightly reduced. Further, it has been confirmed that the n-type impurity region (a) 221 is very effective in reducing the off-current value.

The length (width) of the Lov region 207 of the n-channel TFT 1302 for the channel length of 3 to 7 μm.
Is 0.3 to 3.0 μm, typically 0.5 to 1.5 μm
It is good. Also, the Lov of the n-channel TFT 303
The length (width) of the regions 211a and 212a is 0.3 to 3.0 μm.
m, typically 0.5 to 1.5 μm, Loff region 211
The length (width) of b, 212b may be 1.0 to 3.5 μm, typically 1.5 to 2.0 μm. The pixel TF
The length (width) of the Loff regions 217 to 220 provided in T1304 is 0.5 to 3.5 μm, typically 2.0 to 3.5 μm.
It may be 2.5 μm.

Further, the p-channel TFT 1301 is formed in a self-aligned (self-aligned) manner, and the n-channel TFTs 1302 to 1304 are formed in a non-self-aligned (non-self-aligned) manner. One.

In this embodiment, an alumina film having a relative dielectric constant as high as 7 to 9 is used as the dielectric of the storage capacitor.
The area occupied by the storage capacitor required to form the required capacitance can be reduced. Further, by using the shielding film formed on the pixel TFT as one electrode of the storage capacitor as in this embodiment, the aperture ratio of the image display section of the active matrix type liquid crystal display device can be improved.

The present invention need not be limited to the structure of the storage capacitor shown in this embodiment. For example, the present applicant has filed Japanese Patent Application No. 9-316567 and Japanese Patent Application No. 9-2732.
A storage capacitor having a structure described in Japanese Patent Application No. 44 or Japanese Patent Application No. 10-254097 can also be used.

Here, a process of manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 5, an alignment film 501 is formed on the substrate in the state shown in FIG. In this embodiment, a polyimide film is used as an alignment film. Further, a transparent conductive film 503 and an alignment film 504 are formed over the counter substrate 502.
Note that a color filter and a shielding film may be formed on the counter substrate as needed.

Next, after forming the alignment film, a rubbing treatment is performed to adjust the liquid crystal molecules so as to be aligned with a certain pretilt angle. Then, the pixel circuit, the active matrix substrate on which the control circuit is formed, and the counter substrate are bonded together by a known cell assembling process via a sealing material, a spacer (both not shown), or the like. afterwards,
Liquid crystal 505 is injected between both substrates, and a sealing agent (not shown)
Complete sealing. A known liquid crystal material may be used for the liquid crystal. Thus, the active matrix type liquid crystal display device shown in FIG. 5 is completed.

[Example 2]

Here, a method of manufacturing a pixel TFT of a pixel portion and a circuit TFT of a driver circuit (a source signal line driver circuit, a gate signal line driver circuit, and the like) provided around the pixel portion on the same substrate is described in detail according to steps. Will be described. However, a CMOS circuit and an n-channel TFT will be illustrated for the sake of simplicity.

In FIG. 5A, reference numeral 6000 denotes a substrate having heat resistance, which may be a quartz substrate, a silicon substrate, a ceramic substrate, or a metal substrate (typically, a stainless steel substrate). Regardless of which substrate is used, a base film (preferably, an insulating film containing silicon as a main component) as necessary.
May be provided.

Next, a plasma 60 containing fluorine is applied to the substrate surface.
After the treatment with 01a, a semiconductor film having an amorphous structure with a thickness of 20 to 6050 nm (preferably 30 to 80 nm) is formed on the treated surface 6001b by a known method such as a plasma CVD method or a sputtering method. I do. In this embodiment, an amorphous silicon film is formed to a thickness of 53 nm by a plasma CVD method. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. In the case of forming a base film, the base film and the amorphous silicon film can be formed by the same film formation method, and thus both may be formed continuously.
After forming the base film, it is possible to prevent the surface from being contaminated by not once exposing it to the air atmosphere.
Variations in the characteristics of T and fluctuations in the threshold voltage can be reduced.

Then, a crystalline silicon film 6002 is formed from the amorphous silicon film by using a known crystallization technique. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied.
According to the technique disclosed in Japanese Patent No. 0652, a crystalline silicon film 6002 was formed by a crystallization method using a catalytic element.

[0120] A solution containing nickel (Ni) as a catalyst element for promoting crystallization of the amorphous silicon film was applied by spin coating to form a Ni-containing layer. Also,
As a catalyst element, in addition to nickel, cobalt (C
o), iron (Fe), palladium (Pd), platinum (P
t), copper (Cu), gold (Au) or the like can be used.

In the step of adding the catalyst element, an ion implantation method using a resist mask or a plasma doping method can be used. In this case, the reduction of the occupied area of the addition region and the control of the growth distance of the lateral growth region are facilitated, so that this is an effective technique when configuring a miniaturized circuit.

Prior to the crystallization step, depending on the amount of hydrogen contained in the amorphous silicon film, a temperature of 400 to 500 ° C.
It is desirable to perform heat treatment for about an hour to reduce the content of hydrogen to 5 atom% or less before crystallization. After the step of adding the catalyst element is completed, hydrogen is removed at 450 ° C. for about 1 hour, and then 500 to 700 ° C. (typically 550 to 650) in an inert atmosphere, a hydrogen atmosphere, or an oxygen atmosphere.
C.) for 4 to 24 hours to crystallize the amorphous silicon film. In the present embodiment, 6
A heat treatment was performed at 00 ° C. for 12 hours to crystallize the amorphous silicon film.

When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the film becomes denser. Therefore, the thickness of the crystalline silicon film to be formed is equal to the initial thickness of the amorphous silicon film (in this embodiment, 53 nm). (FIG. 5 (A)).

A 130 nm-thick protective oxide film 6003 made of a silicon oxide film is formed on the crystalline silicon film 6002.
Was formed. Then, an opening 6004 was formed in the protective oxide film 6003 in order to form a gettering region in the crystalline silicon film 6002. (FIG. 5 (B))

After removing the resist mask 6005, phosphorus is doped to remove nickel in the crystalline silicon film 6002. Then, the opening 60
From 04, the crystalline silicon film 6002 is doped with phosphorus to form a gettering region 6007. At this time, the acceleration voltage for doping and the thickness of the protective oxide film 6007 made of an oxide film are optimized, and phosphorus is converted to the protective oxide film 6007.
Substantially do not penetrate.

In the doping, the concentration of phosphorus (P) is 1 × 10
^It was adjusted to be about ²⁰ to 1 × 10 ²¹ atoms / cm ³ . In this embodiment, the concentration of phosphorus (P) is 5 × 10 ²⁰
The ion doping apparatus was used to adjust the concentration to atoms / cm ³ .

The acceleration voltage during ion doping is 10
kev. At an acceleration voltage of 10 keV, phosphorus can hardly pass through when the thickness of the protective oxide film 6007 is 100 nm or more.

After that, at a temperature of 600 ° C. in a nitrogen atmosphere,
Thermal annealing was performed for 2 hours (12 hours in this embodiment) to perform gettering of the nickel element. The heating causes nickel to be attracted to the phosphorus. At a temperature of 600 ° C., phosphorus atoms hardly move in the film, while nickel atoms can move a distance of several hundred μm or more. From this, it can be understood that phosphorus is one of the most suitable elements for gettering nickel. (FIG. 5 (C))

Next, the gettering region 6007 is removed by etching using the protective oxide film 6003 as a mask.
(FIG. 5 (D))

After removing the protective oxide film 6003 (FIG. 6A), an oxide film 6008 made of a silicon oxide film is formed on the substrate 6001 so as to cover the amorphous silicon film 6002.
a was formed. In this embodiment, it is formed with a thickness of 20 nm. (FIG. 6 (B))

Next, the crystalline silicon film 6003 was ashed in an oxidizing gas atmosphere to increase the density of silicon of the crystalline silicon film 6003 and to make the film dense. In this embodiment, thermal oxidation was performed at 950 ° C. in an oxygen atmosphere to reduce the thickness of the crystalline silicon film 6003 by about 15 nm. (FIG. 6 (C))

After the heat treatment, the oxide film 6008b whose thickness has been increased by thermal oxidation is removed (FIG. 6D), and the semiconductor films 6010 and 601 are patterned by patterning.
1, 6012 were formed. (FIG. 7 (A))

Then, the semiconductor films 6010, 6011, 6
A first gate insulating film 6013 is formed to cover 012. Typically, a first gate insulating film 6013 made of a silicon oxide film or a silicon nitride film is formed to a thickness of 5 to 200 nm.
(Preferably 100 to 150 nm). In this embodiment, the first gate insulating film 6013 made of a silicon oxide film or a film containing silicon oxide as a main component has a thickness of 40 nm. (FIG. 7 (B))

Next, a part of the first gate insulating film 6013 was etched using the resist mask 6014 to expose a part of the semiconductor film 6012. Then, an impurity region (Cs region) 6015 to be a part of Cs was formed by doping with phosphorus. The doping was performed at an acceleration voltage of about 10 keV, and the concentration of phosphorus (P) was adjusted to be about 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ . In this embodiment, the concentration of phosphorus (P) is 5
As a × 10 ¹⁹ atoms / cm ^3, it was performed using an ion doping apparatus. (FIG. 7 (C))

After removing the resist mask 6014, a second gate insulating film 6016 was formed. Typically, the second
The thickness of the gate insulating film 6016 may be 5 to 200 nm (preferably 100 to 150 nm). In this embodiment, the second gate insulating film 6016 made of a silicon nitride film is formed so as to have a thickness of 20 nm. (FIG. 7 (D))

Then, a first conductive film 6017 and a second conductive film 6018 were sequentially formed. Although the gate electrode has a multilayer structure in this embodiment, the gate electrode may be formed as a single layer.

Then, a resist mask 6005 was formed to cover the opening 6004 and the portion of the crystalline silicon film 6002 where the p-channel TFT was to be formed. Then, in order to control the threshold voltage, a portion of the crystalline silicon film 6002 where the n-channel TFT is formed is doped with boron (B) as an impurity imparting p-type. The doping was performed at an acceleration voltage of about 30 keV, and the concentration of boron (B) was adjusted to be about 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ . In this embodiment, the concentration of boron (B) is set to 1 × 10 ¹⁸ atoms / cm ³ .
Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Then, depending on the characteristics of the crystalline silicon film 6002, phosphorus (P) may be added instead of boron (B) in order to control the threshold voltage. Although the addition of boron (B) here is not necessarily required, a portion (channel doping portion) 6006 of the crystalline silicon film 6002 to which boron (B) is added can set the threshold voltage of the n-channel TFT within a predetermined range. It was preferable to form to fit. (FIG. 8A)

The first conductive film 6017 is a crystalline silicon film having an n-type impurity, and is 150 nm thick by using the CVD method.
m. The second conductive film 6018 is tungsten silicide and is formed with a thickness of 150 nm by sputtering. (FIG. 8B) In this case, although the resistance is slightly increased as compared with the case of using the metal film, the laminated structure of the metal silicide film and the silicon film has high heat resistance.
This is an effective structure because it is resistant to oxidation. The first conductive film 6
021 may be formed of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, molybdenum nitride (MoN), tungsten silicide, titanium silicide, or molybdenum silicide;
The conductive film 6022 is formed using tantalum (Ta), titanium (Ti),
An element selected from molybdenum (Mo) and tungsten (W), an alloy containing the above element as a main component, or an alloy film combining the above elements (typically, a Mo—W alloy film, M
(o-Ta alloy film).

Next, the first conductive film 6017 and the second conductive film 6
018 is patterned to form a p-channel TFT gate electrode 6020 and n-channel TFTs 6021 and 602.
2. A Cs electrode 6023 was formed. (FIG. 8 (C))

The gate electrodes 6020, 6021, 6
022, a part of the semiconductor films 6010, 6011 and the semiconductor film 6012 is doped with an impurity imparting n-type by using the Cs electrode
24 to 6029 were formed. Phosphorus (P) or arsenic (As) may be used as the impurity for imparting n-type. In this case, phosphine (PH ₃ ) is added to add phosphorus (P).
The ion doping method using is applied. The doping is performed at an acceleration voltage of about 40 keV and the concentration of phosphorus (P) is 5 × 1.
It was adjusted to be about 0 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ . In this embodiment, the impurity regions 6024 to 602
The phosphorus (P) concentration of 9 is 1 × 10 ¹⁸ atoms / cm ³
Was performed using an ion doping apparatus.
In this specification, the impurity region 6024 formed here is used.
The concentration of the impurity imparting n-type contained in 6029 is represented by (n−). (FIG. 8 (D))

Next, a semiconductor film 6 to be a p-channel type TFT
010 and a semiconductor film 601 to be an n-channel TFT
1, 6012 so as to cover a part of the resist mask 603.
0, 6031 and 6032 were formed. Then, a part of the semiconductor films 6011 and 6012 was doped with an impurity imparting n-type using the resist masks 6030, 6031 and 6032 to form impurity regions 6033 to 6036.

The formation of the impurity regions 6033 to 6036
Phosphine (PH_Three) Using ion doping method
Doping is performed at an acceleration voltage of about 40 keV,
The concentration of (P) is 5 × 10¹⁹~ 5 × 10²⁰atoms / c
m^ThreeIt was adjusted to the extent. In this embodiment, the impurities
The concentration of phosphorus (P) in the regions 6033 to 6036 is 1 × 10
²⁰atoms / cm^ThreeIt was made to become. In this specification
Are formed in the impurity regions 6033 to 6036 formed here.
The concentration of the impurity that imparts n-type contained is expressed as (n +).
You. (FIG. 9 (A))

The resist masks 6030 to 6032 were removed, and the portion to be an n-channel TFT and the portion to be Cs were covered with a resist mask 6039. And the semiconductor film 6
010 was doped with an impurity imparting p-type. In this embodiment, the impurity regions 6037 and 6038 are formed by an ion doping method using diborane (B ₂ H ₆ ). The doping was performed at an acceleration voltage of about 40 keV, and the concentration of boron (B) was adjusted so as to be about 5 × 10 ^{19 to} 5 × 10 ²⁰ atoms / cm ³ . In this embodiment, the impurity region 603 is used.
The concentration of boron (B) of 7,6038 is 1 × 10 ²⁰ atom
ms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity regions 6037 and 6038 formed here is expressed as (p +).
Although the impurity regions 6037 and 6038 contain phosphorus (P) or boron (B) already added in the previous step, boron (B) is added at a sufficiently high concentration as compared with phosphorus (P) or boron (B). The p-type conductivity is ensured, and does not affect the characteristics of the TFT at all. (FIG. 9 (B))

After removing the resist mask 6039, an insulating film 6040 was formed. The insulating film 6040 is made of a silicon nitride film and has a thickness of 70 nm by a CVD method. (FIG. 9 (C))

Next, by heating in a nitrogen atmosphere at 850 ° C. for 30 minutes, the impurities contained in the impurity regions diffuse in the semiconductor films 6010 to 6012 and spread to below the gate electrodes 6020 to 6022. Gate electrode 6
Impurity region 6041 located below 0200 to 6022
６０6046 is referred to as a Lov region. Also, the gate electrode 60
Impurity regions (source regions or drain regions) 6033 to 6036
The impurity regions 6047 to 6050 in contact with are referred to as Lof regions. Impurity regions 6033 to 6038, 6041
~ 6050 are activated by the heat treatment. (Figure 1
0 (A))

Next, a first interlayer insulating film 6052 made of silicon oxide or silicon oxynitride is
It is formed with a thickness of nm. In this embodiment, silicon nitride is formed with a thickness of 1000 nm. After that, contact holes reaching the source or drain regions 6033 to 6038 are formed, and the source wirings 6053, 6055,
057 and drain wirings 6054, 6056, 6058
To form Although not shown, in this embodiment, the source wiring and the drain wiring are formed of a Ti film 60 nm, a nitrogen-containing Ti film 40 nm, and an Si-containing aluminum film 30.
This was a four-layer laminated film in which 0 nm and a 100 nm Ti film were continuously formed by a sputtering method. (FIG. 10B)

Next, source wirings 6053, 6055, and 60
A passivation film 6060 made of a silicon nitride film is formed with a thickness of 220 nm on the first interlayer insulating film 6052 so as to cover the drain wirings 6054, 6056, and 6058. (FIG. 10C) Then, a second interlayer insulating film 6061 is formed so as to cover the passivation film 6060. This second interlayer insulating film 6061 is made of an acrylic film and has a thickness of 800 nm.

A second interlayer insulating film 606 made of an acrylic film
After the substrate 1 is heated at 150 ° C. for 0.3 hours, a Ti film or a light-shielding film 6062 mainly composed of Ti and having a thickness of 100 nm is formed on the second interlayer insulating film 6061. (FIG. 10A)

Then, the second light-shielding film 6062 is
A third interlayer insulating film 6063 was formed over the interlayer insulating film 6061. The third interlayer insulating film 6063 is made of an acrylic film,
Its thickness is formed between 500 nm and 1000 nm. In this embodiment, the thickness of the third interlayer insulating film 6063 is set to 800 nm.
And (FIG. 10B)

A contact hole is formed in the third interlayer insulating film 6063, and then a pixel electrode 6064 is formed. In this embodiment, the thickness of the pixel electrode 6064 is 2.8 μm
And The pixel electrode 6064 is electrically connected to a drain wiring 6058 through a contact hole. The pixel electrode 6064 may be formed using a transparent conductive film. (FIG. 10
(C))

As described above, the semiconductor device of the present invention has various features in the driver circuit and the pixel matrix circuit. A bright and high-definition image can be obtained by a synergistic effect of these, and the operation performance and the reliability are improved. Obtain a high electro-optical device. Then, a high-performance electronic device in which such an electro-optical device is mounted as a component is obtained.

[Embodiment 3] A CMOS circuit and a pixel portion formed by implementing the present invention are used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). Can be. That is, the invention of the present application can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.

Such electronic devices include a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), car navigation, car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 14, 15 and 16.

FIG. 14A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.

FIG. 14B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102 and other signal control circuits.

FIG. 14C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.

FIG. 14D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302 and other signal control circuits.

FIG. 14E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 14F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.

FIG. 15A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 15B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 15C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 15A and 15B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 15D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 15D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 15, a case in which a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

FIG. 16A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal control circuits.

FIG. 16B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 16C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the first and second embodiments.

[Embodiment 4] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 17A is a top view of an EL display device using the present invention. In FIG. 117A, 401
0 denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, 4013 denotes a gate side driver circuit, and the respective driver circuits are connected to the FPC 401 via wirings 4014 to 4016.
7, and connected to an external device.

At this time, the cover member 600 is formed so as to surround at least the pixel portion, preferably, the driving circuit and the pixel portion.
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 17B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
The FT may use a known structure (top gate structure or bottom gate structure).

The present invention relates to a TFT 4022 for a driving circuit,
It can be used for the TFT 4023 for the pixel portion.

The TFT 402 for a driving circuit is manufactured by using the present invention.
2. When the pixel portion TFT 4023 is completed, the pixel portion TFT is formed on an interlayer insulating film (flattening film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the FT 4023 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

[0176] In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After the EL layer 4029 is formed, a cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, as the cathode 4030,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region shown at 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Further, a sealing material is provided inside the cover material 6000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

Further, a spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have a light transmitting property.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

[Embodiment 5] In this embodiment, an example in which an EL display device having a mode different from that of Embodiment 4 is manufactured by using the present invention will be described with reference to FIGS. 17A and 17B denote the same parts, and a description thereof will not be repeated.

FIG. 18A is a top view of the EL display device of this embodiment, and FIG. 18B is a cross-sectional view taken along line AA ′ of FIG.

In accordance with Embodiment 4, a passivation film 6003 is formed to cover the surface of the EL element.

Further, the filler 6
004 is provided. This filler 6004 is used for the cover material 60.
It also functions as an adhesive for bonding 00. As the filler 6004, PVC (polyvinyl chloride),
Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0192] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the light emitting direction (light emitting direction) from the EL element, the cover material 6000 needs to have a light transmitting property.

Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of a sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

[Embodiment 6] Here, a more detailed sectional structure of a pixel portion in an EL display panel is shown in FIG. 19, an upper surface structure is shown in FIG. 20A, and a circuit diagram is shown in FIG. FIG.
9, and in FIGS. 20A and 20B, common reference numerals are used, so that they may be referred to each other.

In FIG. 19, the switching TFT 3502 provided on the substrate 3501 is the NTF of the present invention.
It is formed using T (see Examples 1 and 2). In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. In addition, the PT of the present invention
It may be formed using FT.

The current controlling TFT 3503 is formed using the NTFT of the present invention. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. The wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.

At this time, it is very important that the current control TFT 3503 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current controlling TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

In this embodiment, the current control TFT 35
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 20A, the wiring to be the gate electrode 37 of the current controlling TFT 3503 is 35
In a region indicated by 04, the region overlaps with the drain wiring 40 of the current control TFT 3503 via an insulating film. At this time, 3
In the region indicated by 504, a capacitor is formed. This capacitor 3504 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is constantly applied.

The first passivation film 4 is formed on the switching TFT 3502 and the current control TFT 3503.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a highly reflective conductive film.
503 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As specific light emitting layers, cyanopolyphenylene vinylene is used for a light emitting layer emitting red light, polyphenylene vinylene is used for a light emitting layer emitting green light, and polyphenylene vinylene or polyalkylphenylene is used for a light emitting layer emitting blue light. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example in which a polymer material is used for the light emitting layer has been described, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
The EL layer has a laminated structure in which a hole injection layer 46 made of (polythiophene) or PAni (polyaniline) is provided. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 3
505 is completed. Note that the EL element 3505 mentioned here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore,
The utilization efficiency of light emission is very high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 19, and a switching TFT having a sufficiently low off-state current value and a current controlling portion having a strong resistance to hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

The structure of the present embodiment can be implemented by freely combining with the structures of the first and second embodiments.
In addition, as a display unit of the electronic device of the third embodiment, E
It is effective to use the L display panel.

[Embodiment 7] In this embodiment, a structure in which the EL element 3505 is inverted in the pixel portion shown in Embodiment 6 will be described. FIG. 21 is used for the description. The structure of FIG. 19 differs from that of FIG. 19 only in the EL element and the current controlling TFT.

In FIG. 21, a current controlling TFT 350
3 is formed using the PTFT of the present invention. Refer to Embodiments 1 and 2 for the manufacturing process.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of an insulating film
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed as shown by the arrow.

The structure of the present embodiment can be implemented by freely combining with the structures of the first and second embodiments.
In addition, as a display unit of the electronic device of the third embodiment, E
It is effective to use the L display panel.

[Embodiment 8] In this embodiment, FIGS. 22A to 22C show examples in which a pixel having a structure different from that of the circuit diagram shown in FIG. 20B is used. In this embodiment, reference numeral 3801 denotes a source wiring of the switching TFT 3802, 3803 denotes a gate wiring of the switching TFT 3802, 3804 denotes a current control TFT, 3805 denotes a capacitor, 3806 and 3808 denote a current supply line, and 3807.
Is an EL element.

FIG. 22A shows an example in which a current supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 22B shows a current supply line 380.
8 is provided in parallel with the gate wiring 3803. Note that FIG. 22B illustrates a structure in which the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

In FIG. 22C, a current supply line 3808 is provided in parallel with the gate wiring 3803 in the same manner as in the structure of FIG. 22B, and two pixels are connected to the current supply line 3808.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of the present embodiment is similar to that of Embodiments 1, 2,
It can be implemented in any combination with the configuration of 4 or 5. In addition, it is effective to use an EL display panel having the pixel structure of the present embodiment as a display unit of the electronic device of the third embodiment.

[Embodiment 9] FIG. 20 shown in Embodiment 6
In FIGS. 7A and 7B, the capacitor 3504 is provided to hold the voltage applied to the gate of the current control TFT 3503; however, the capacitor 3504 can be omitted. In the case of Embodiment 17, the current control TF
Since the NTFT of the present invention as shown in Embodiments 1 and 2 is used as T3503, it has an LDD region provided so as to overlap the gate electrode via the gate insulating film. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

In addition, FIG.
Similarly, in the structures (B) and (C), the capacitor 3
It is possible to omit 805.

The structure of this embodiment is similar to that of Embodiments 1, 2,
The present invention can be implemented by freely combining with the configurations 4 to 8. In addition, it is effective to use an EL display panel having the pixel structure of the present embodiment as a display unit of the electronic device of the third embodiment.

[0231]

According to the present invention, by terminating an amorphous semiconductor film with a halogen element, the orientation of a crystalline semiconductor film formed by a thermal crystallization method or a laser crystallization method can be obtained. Can be enhanced.

Further, by using such a crystalline semiconductor film, the characteristics of the TFT can be improved and the variation in the characteristics can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a pixel circuit and a control circuit.

FIG. 2 illustrates a manufacturing process of a pixel circuit and a control circuit.

FIG. 3 illustrates a manufacturing process of a pixel circuit and a control circuit.

FIG. 4 is a diagram illustrating a manufacturing process of a pixel circuit and a control circuit.

FIG. 5 is a diagram showing a manufacturing process of a TFT.

FIG. 6 illustrates a manufacturing process of a TFT.

FIG. 7 illustrates a manufacturing process of a TFT.

FIG. 8 illustrates a manufacturing process of a TFT.

FIG. 9 illustrates a manufacturing process of a TFT.

FIG. 10 illustrates a manufacturing process of a TFT.

FIG. 11 is a diagram illustrating a crystallization step of a semiconductor film.

FIG. 12 is a diagram showing a cross section of a TFT according to the embodiment.

FIG. 13 is a diagram showing a crystallization step of a semiconductor film.

FIG. 14 illustrates an example of an electronic device.

FIG. 15 illustrates an example of an electronic device.

FIG. 16 illustrates an example of an electronic device.

FIG. 17 illustrates a structure of an EL display device.

FIG. 18 illustrates a structure of an EL display device.

FIG. 19 illustrates a structure of an EL display device.

FIG. 20 illustrates a structure of an EL display device.

FIG. 21 illustrates a structure of an EL display device.

FIG. 22 illustrates a structure of an EL display device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/20 H01L 21/316 M 5F110 21/205 21/318 C 5G435 21/316 21/322 R 29 / 78 627G 21/318 G02F 1/136 500 21/322 H01L 29/78 617V F term (reference) 2H092 JA34 KA05 MA08 MA26 NA24 5C094 AA13 AA21 AA25 AA43 AA56 BA03 BA27 BA43 CA19 DA13 DB01 DB04 EA04 EA02 EB02 FA01 EB02 FA FB05 FB12 FB14 FB15 GB10 5F045 AA03 AA06 AA08 AB01 AB04 AB06 AC01 AC02 AC17 AF07 AF16 BB12 BB16 CA15 DA61 HA15 HA16 5F052 AA15 CA00 DA02 DB02 DB03 DB07 EA15 FA06 GB05 GB09 JA04 JA10 5F058 BA20 BC10 BF04 BC20 BC04 BF04 BF29 BF34 BF62 BF63 BF68 BH01 BJ01 BJ10 5F110 AA12 AA30 BB02 BB04 DD01 DD03 DD05 DD06 DD11 DD13 DD14 DD15 DD25 EE01 EE02 EE04 EE05 EE06 EE08 EE14 EE15 EE27 EE44 FF02 FF03 FF04 FF06 FF09 FF23 FF28 FF30 FF36 GG01 GG02 GG25 GG32 GG33 GG34 GG35 GG36 GG43 GG45 GG47 GG52 GG55 HJ01 HJ04 HJ13 HJ18 HJ23 HL03 HL04 HL06 HL12 HM13 HM14 HM15 NN03 NN04 NN22 NN23 NN24 NN27 NN35 NN40 NN44 NN45 NN46 NN47 NN52 NN54 NN55 NN58 NN72 PP01 PP03 PP10 PP13 PP23 PP34 PP35 QQ01 QQ11 QQ19 QQ24 QQ25 QQ28 5G435 AA16 AA17 BB05 BB12 CC09 EE31 HH12 HH13 HH14 KK05

Claims (9)

[Claims] A first step of exposing the surface of the substrate to a plasma atmosphere containing a halogen element; a second step of forming an amorphous semiconductor film on the substrate; A third step of forming a layer containing a catalytic element that promotes crystallization of the crystalline semiconductor film, a fourth step of forming the crystalline semiconductor film by performing a first heat treatment on the amorphous semiconductor film, A fifth step of selectively removing the crystalline semiconductor film to form an island-shaped crystalline semiconductor film, and a sixth step of forming a gate insulating film on the island-shaped crystalline semiconductor film. And a seventh step of performing a second heat treatment in an oxidizing atmosphere containing halogen after the sixth step. A first step of exposing a surface of the substrate to a plasma atmosphere containing a halogen element; a second step of forming an amorphous semiconductor film on the substrate; A third step of forming a layer containing a catalytic element that promotes crystallization of the crystalline semiconductor film, a fourth step of forming the crystalline semiconductor film by performing a first heat treatment on the amorphous semiconductor film, A fifth step of adding phosphorus to a selected region of the crystalline semiconductor film, and a sixth step of removing the catalytic element promoting crystallization from the crystalline semiconductor film by a second heat treatment. A seventh step of selectively removing the crystalline semiconductor film to form an island-shaped crystalline semiconductor film, and an eighth step of forming a gate insulating film on the island-shaped crystalline semiconductor film. After the seventh step, the second step is performed in an oxidizing atmosphere containing halogen. The method for manufacturing a semiconductor device, characterized in that it comprises a ninth step of performing heat treatment. 3. A first step of exposing a surface of the substrate to a plasma atmosphere containing a halogen element, a second step of forming an amorphous semiconductor film on the substrate, and selecting a step on the amorphous semiconductor film. A third step of forming a first insulating film, a fourth step of forming a layer containing a catalytic element that promotes crystallization of the amorphous semiconductor film on the amorphous semiconductor film, A fifth step of forming a crystalline semiconductor film by performing a first heat treatment on the amorphous semiconductor film, a sixth step of removing the first insulating film, and selectively removing the crystalline semiconductor film. A seventh step of removing and forming an island-shaped crystalline semiconductor film, an eighth step of forming a gate insulating film on the island-shaped crystalline semiconductor film, and halogen after the eighth step. A ninth step of performing a second heat treatment in an oxidizing atmosphere containing A method for manufacturing the body of the device. 4. A first step of exposing a surface of the substrate to a plasma atmosphere containing a halogen element, a second step of forming an amorphous semiconductor film on the substrate, and selecting a step on the amorphous semiconductor film. A third step of forming a first insulating film, a fourth step of forming a layer containing a catalytic element that promotes crystallization of the amorphous semiconductor film on the amorphous semiconductor film, A fifth step of forming a crystalline semiconductor film by performing a first heat treatment on the amorphous semiconductor film, a sixth step of adding phosphorus to a selected region of the crystalline semiconductor film, A seventh step of removing a catalytic element that promotes the above from the crystalline semiconductor film by a second heat treatment, an eighth step of removing the first insulating film, and selectively removing the crystalline semiconductor film. A ninth step of forming an island-shaped crystalline semiconductor film by removing the island-shaped crystalline semiconductor film; A tenth step of forming a gate insulating film on the quality semiconductor film; and an eleventh step of performing a second heat treatment in an oxidizing atmosphere containing halogen after the ninth step. A method for manufacturing a semiconductor device. 5. The method according to claim 1, wherein the step of exposing the surface of the quartz substrate to a plasma containing a halogen element terminates the surface of the quartz substrate with the halogen element. A method for manufacturing a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the plasma containing a halogen element is a plasma containing a fluorine atom or a fluorine radical. 7. The semiconductor according to claim 1, wherein the plasma containing a halogen element exposed to the surface of the quartz substrate is a plasma of silicon tetrafluoride. Method for manufacturing the device. 8. The plasma according to claim 1, wherein the plasma containing a halogen element exposed to the surface of the quartz substrate is a plasma of nitrogen trifluoride. A method for manufacturing a semiconductor device. 9. The method according to claim 1, wherein the catalyst element is nickel (Ni), germanium (G
e), iron (Fe), palladium (Pd), tin (S
n), lead (Pb), cobalt (Co), platinum (Pt),
A method for manufacturing a semiconductor device, comprising copper (Cu) or gold (Au).