JP2000299469A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the opening ratio of the pixel section of an active-matrix liquid crystal display device in which drive circuits such as a shift register, a buffer circuit, etc., are mounted on the same substrate, and at the same time, to provide an optimum TFT constitution. SOLUTION: In a buffer circuit, an n-channel TFT provided with an LDD overlapping a gate electrode is formed, and in the n-channel TFT of a pixel section, an LDD which does not overlap the gate electrode is provided. The retention volume provided in the pixel section is formed of a light shielding film 156, a dielectric film 157 formed on the film 156, and pixel electrodes 160. In particular, the light shielding film 156 is constituted of an aluminum film, and the dielectric film 157 is constituted of an aluminum oxide film formed by anodic oxidation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of thin film transistors on a substrate having an insulating surface, and a method for manufacturing the same. In particular, the present invention can be suitably used for an electro-optical device typified by a liquid crystal display device in which a pixel portion and a driver circuit provided therearound are provided on the same substrate, and an electronic device equipped with the electro-optical device.
Note that in this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic apparatus equipped with the electro-optical device in its category.

[0002]

2. Description of the Related Art A semiconductor device having a large-area integrated circuit formed by a thin film transistor (hereinafter, referred to as a TFT) on a substrate having an insulating surface is being developed. Active matrix liquid crystal display devices, EL display devices, and contact image sensors are known as typical examples. T
FTs are classified according to their structure and manufacturing method. In particular, a TFT in which a semiconductor film having a crystalline structure is used as an active layer
Since the crystalline TFT (described as a crystalline TFT) has high field-effect mobility, various functional circuits could be formed.

For example, an active matrix type liquid crystal display device includes a pixel portion or a pixel matrix circuit composed of n-channel TFTs for each functional block, a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, And a driver circuit such as a sampling circuit was formed on one substrate. In the contact type image sensor, integrated circuits such as a sample hold circuit, a shift register circuit, and a multiplexer circuit are formed using TFTs.

The characteristics of a field effect transistor such as a TFT include a linear region in which the drain current and the drain voltage increase in proportion, a saturation region in which the drain current is saturated even if the drain voltage increases, and a characteristic in which the drain voltage is applied. Ideally, it can be divided into a cut-off region where no current flows. In this specification, the linear region and the saturation region are called an on region of the TFT, and the cutoff region is called an off region. For convenience, the drain current in the ON region is called an ON current, and the current in the OFF region is called an OFF current.

Since the operating conditions of these circuits are not always the same, the characteristics required for the TFT naturally differed to some extent. The pixel portion has a configuration in which a switch element composed of an n-channel TFT and an auxiliary storage capacitor are provided, and a liquid crystal is driven by applying a voltage. Here, the liquid crystal needs to be driven by an alternating current, and a method called frame inversion driving has been adopted. Therefore, the required TFT characteristics required that the leakage current be sufficiently reduced. Further, since a high driving voltage is applied to the buffer circuit, it is necessary to increase the breakdown voltage. Further, in order to enhance the current driving capability, it is necessary to secure a sufficient ON current.

However, there is a problem that the off-current of the crystalline TFT tends to be high. And crystalline TF
It is said that T still falls short of MOS transistors (transistors manufactured on a single crystal semiconductor substrate) used for LSIs and the like in terms of reliability. For example, crystalline TFT
In some cases, a deterioration phenomenon such as a decrease in on-current was observed. The cause is the hot carrier effect, and it has been considered that hot carriers generated by a high electric field near the drain cause a deterioration phenomenon.

The structure of the TFT includes a low concentration drain (LD)
D: Lightly Doped Drain) structure is known. In this structure, a low-concentration impurity region is provided between a channel region and a source or drain region to which an impurity is added at a high concentration.
It is called an area. The LDD structure further has an L overlap with the gate electrode depending on the positional relationship with the gate electrode.
DD structure (hereinafter referred to as GOLD (Gate-drain
Overlapped LDD) and an LDD structure that does not overlap with the gate electrode. GOLD structure is
The high electric field near the drain was relaxed to prevent the hot carrier effect, and the reliability was improved. For example, "Mu
tsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM
97 Technical DIGEST, pp. 523-526, 1997], it is confirmed that a GOLD structure with sidewalls formed of silicon can achieve extremely superior reliability compared to TFTs of other structures.

In the pixel portion of the active matrix type liquid crystal display device, TFTs are arranged in tens to millions of pixels, and each of the TFTs is provided with a pixel electrode. A counter electrode is provided on the counter substrate side sandwiching the liquid crystal, and a kind of capacitor using the liquid crystal as a dielectric has been formed. Then, the potential applied to each pixel is controlled by the switching function of the TFT, and by controlling the charge on the capacitor, the liquid crystal is driven to control the amount of transmitted light to display an image.

Since the capacitance of this capacitor gradually decreases due to the leak current, the amount of transmitted light changes, causing a reduction in the contrast of image display. Therefore, conventionally, a capacitor wiring is provided, and a capacitor (holding capacitor) different from a capacitor using liquid crystal as a dielectric is provided in parallel. This storage capacity compensated for the capacity lost by the capacitor using liquid crystal as a dielectric.

[0010]

However, the required characteristics of a TFT as a switching element in a pixel portion and a TFT of a drive circuit such as a shift register or a buffer circuit are not always the same. For example, a large reverse bias (negative in the case of an n-channel TFT) voltage is applied to the gate electrode of a TFT in a pixel portion, but a reverse bias voltage is basically applied to a TFT constituting a logic circuit of a driving circuit. Never been working. The former operation speed was good at 1/100 or less of the latter. As described above, it is not preferable to use TFTs having greatly different operating conditions and required characteristics with the same structure.

Further, the GOLD structure has a problem that the off-state current becomes larger than that of the normal LDD structure.
In order to prevent an increase in off-state current, a multi-gate structure in which a plurality of gates are provided between a pair of sources and drains is possible, but a GOLD structure TFT alone was insufficient. Therefore, TFTs for large area integrated circuits
Is not necessarily preferred to be formed with the same structure. For example, in the case of an n-channel TFT in a pixel portion, when the off-state current is increased, power consumption is increased or an abnormality is displayed in image display. Therefore, it is not preferable to use a crystalline TFT having a GOLD structure as it is. Further, the LDD structure that does not overlap with the gate electrode has a problem that the on-current is reduced due to an increase in series resistance. The on-current can be freely designed depending on the channel width of the TFT.
It was not necessary to provide a structure.

Further, in order to secure a sufficient capacitance by forming a storage capacitor using a capacitance line in the pixel portion, the aperture ratio has to be sacrificed. In particular, in a small high-definition panel used for a projector-type display device, the pixel area per pixel is small, and therefore, a decrease in the aperture ratio due to the capacitance wiring has been a problem.

The present invention is a technique for solving such a problem, and an object of the present invention is to realize a crystalline TFT having a reliability equal to or higher than that of a MOS transistor. It is another object of the present invention to improve the reliability of a semiconductor device having a large-area integrated circuit in which various functional circuits are formed using such a crystalline TFT. Another object of the present invention relates to a configuration of a TFT and a storage capacitor in a pixel portion, and aims to improve an aperture ratio of an active matrix liquid crystal display device.

[0014]

According to an aspect of the present invention, there is provided a semiconductor device in which a driving circuit and a pixel portion are formed of thin film transistors on the same substrate. Channel formation region and GOLD
A first impurity region having a third impurity region of one conductivity type forming a structure and a first impurity region of one conductivity type forming a source region or a drain region provided outside the gate electrode;
Thin film transistor, channel forming region, and GOLD
A third impurity region of one conductivity type forming a structure, a second impurity region of one conductivity type forming an LDD structure provided outside the gate electrode, and one conductivity type forming a source region or a drain region Having the first impurity region of
A channel formation region, a second impurity region of one conductivity type forming an LDD structure provided outside the gate electrode, and a first impurity region of one conductivity type forming a source region or a drain region. A third thin film transistor having a channel formation region and a fifth impurity region having a conductivity type opposite to the one conductivity type forming a source region or a drain region, for each functional circuit. The pixel portion is provided in consideration of an operation characteristic required for the thin film transistor, and the pixel portion includes a channel formation region, a fourth impurity region of one conductivity type forming an LDD structure provided outside the gate electrode, and a source region. Alternatively, a fourth thin film transistor including a first impurity region of one conductivity type which forms a drain region is provided. It has.

In another aspect of the invention, a storage capacitor provided in the pixel portion is connected to a light-shielding film formed on the fourth thin film transistor via an insulating layer, and the fourth thin film transistor. A pixel electrode, the light-shielding film, a dielectric film in contact with the light-shielding film, and a pixel electrode in contact with the dielectric film, wherein the storage capacitor is connected to the fourth thin film transistor. Have. Preferably, the light-shielding film is made of a material mainly containing one or more elements selected from aluminum, tantalum, and titanium, and the dielectric film is preferably an oxide of the light-shielding film material. Alternatively, the dielectric film may be formed of a material selected from silicon nitride, silicon oxide, silicon oxynitride, DLC, and polyimide.

In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of island-shaped semiconductor layers on a substrate having an insulating surface; Forming a gate insulating film, forming a gate electrode in contact with the gate insulating film, adding one conductivity type impurity element to a selected region of the island-shaped semiconductor layer, Forming a first thin film transistor having a region and a third impurity region overlapping with the gate electrode; adding one conductivity type impurity element to a selected region of the island-shaped semiconductor layer; A first impurity region and a third impurity region overlapping the gate electrode;
Forming a second thin film transistor having an impurity region of (a) and a second impurity region that does not overlap with the gate electrode; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer. Forming a third thin film transistor having a first impurity region and a second impurity region which does not overlap with the gate electrode; and forming an impurity element having a conductivity type opposite to one conductivity type into the island shape. Adding a selected region of the semiconductor layer to form a fifth thin film transistor having a fifth impurity region; and adding an impurity element of one conductivity type to the selected region of the island-shaped semiconductor layer. Forming a fourth thin film transistor having a first impurity region and a fourth impurity region that does not overlap with the gate electrode. The first thin film transistor to the fifth thin film transistor are formed on the same substrate in the same process in consideration of the operation characteristics required for the thin film transistor for each functional circuit.

According to another aspect of the present invention, a storage capacitor provided in the pixel portion includes a step of forming an insulating layer on the fourth thin film transistor, and a step of forming a light shielding film on the insulating film. The step of forming a dielectric film in contact with the light-shielding film and the step of forming a conductive film in contact with the dielectric film, and the step of forming the dielectric film in contact with the light-shielding film is an anodic oxidation method. Is a desirable embodiment. Therefore, the material of the light shielding film is aluminum, tantalum,
It is desirable to form with a material containing one or more elements selected from titanium as a main component.

[0018]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing TFTs of a pixel portion and a driving circuit provided around the pixel portion will be described.

(Step of Forming Island-Shaped Semiconductor Layer and Gate Insulating Film) In FIG. 1, it is desirable to use an alkali-free glass substrate or a quartz substrate as the substrate 101. Alternatively, a substrate obtained by forming an insulating film on the surface of a silicon substrate or a metal substrate may be used as the substrate. Then, a silicon oxide film, a silicon nitride film,
Alternatively, the base film 102 made of a silicon oxynitride film was formed to a thickness of 100 to 400 nm by a plasma CVD method or a sputtering method. For example, as the base film 102, a two-layer structure in which the silicon nitride film 102 has a thickness of 25 to 100 nm, here 50 nm, and the silicon oxide film 103 has a thickness of 50 to 300 nm, here 150 nm, may be used.
The base film 102 is provided to prevent impurity contamination from the substrate, and is not necessarily provided when a quartz substrate is used. Next, 20 to 10 on the base film 102.
An amorphous silicon film having a thickness of 0 nm was formed by a known film forming method. Although it depends on the content of hydrogen, the amorphous silicon film is preferably subjected to a dehydrogenation treatment by heating at 400 to 550 ° C. for several hours to perform the crystallization step with the content of hydrogen being 5 atomic% or less. Although an amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, it is preferable that impurity elements such as oxygen and nitrogen contained in the film be sufficiently reduced. Here, since the base film and the amorphous silicon film can be formed by the same film formation method, both may be formed continuously. Once the base film is formed, it is possible to prevent the surface from being contaminated by not being exposed to the air atmosphere once, and it is possible to reduce the characteristic variation of the TFT to be manufactured. In the step of forming a crystalline silicon film from an amorphous silicon film, a known laser crystallization technique or thermal crystallization technique may be used. Alternatively, a crystalline silicon film may be formed by a thermal crystallization method using a catalyst element that promotes crystallization of silicon. Alternatively, a microcrystalline silicon film may be used, or a crystalline silicon film may be directly deposited. In addition, SOI (Silicon
The crystalline silicon film may be formed using a known technique of On Insulators. Unnecessary portions of the crystalline silicon film thus formed were removed by etching to form island-shaped semiconductor layers 104 to 106. In order to control the threshold voltage, a region of the crystalline silicon film where the n-channel TFT is to be manufactured is previously set to 1 × 10 ^{15 to} 5 × 10 ¹⁷ cm ^−3.
Boron (B) may be added at about the concentration. Next, a gate insulating film 107 containing silicon oxide, silicon nitride oxide, or silicon nitride as a main component was formed to cover the island-shaped semiconductor layers 104 to 106. Gate insulating film 107
May be formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm. For example, N by plasma CVD
75n of silicon oxynitride film made of ₂ O and SiH ₄
m and then thermally oxidized at 800 to 1000 ° C. in an oxygen atmosphere or a mixed atmosphere of oxygen and hydrochloric acid to 115 n
m (FIG. 1A).

(Formation of First Low-Concentration Impurity Region) In order to form a low-concentration impurity region serving as an LDD region in an n-channel TFT of a driving circuit, island-like semiconductor layers 104 and 10 are formed.
6, masks 108 to 111 were formed on the entire surface and the channel formation region of the island-shaped semiconductor layer 105 using a resist film. At this time, a resist mask may be formed in a region around the island-shaped semiconductor layer where a wiring is to be formed. Then, an impurity element imparting n-type was added to form a low concentration impurity region. Here, phosphorus (P) was added by an ion doping method using phosphine (PH ₃ ). In this step, phosphorus was added to the underlying semiconductor layer through the gate insulating film 107. The concentration of phosphorus to be added is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atom
s / cm ³ , preferably 1 × 10 ¹⁸ a
toms / cm ³ . Then, first low-concentration impurity regions 112 and 113 in which phosphorus was added to the island-shaped semiconductor layer 105 were formed. The first low-concentration impurity region is for forming an LDD region in the n-channel TFT, and later overlaps with the second impurity region which does not overlap with the gate electrode due to the positional relationship with the gate electrode. It is distinguished from the third impurity region.

After that, 400 to 900 in a nitrogen atmosphere.
C., preferably 550 to 800.degree. C., for 1 to 12 hours, and a step of activating the impurity element imparting n-type added in this step was performed (FIG. 1B).

(Formation of Gate Electrode and Wiring Conductive Film) The first conductive film 114 is composed mainly of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W). 10 to 10
It was formed to a thickness of 0 nm. It is desirable to use tantalum nitride (TaN) or tungsten nitride (WN) for the first conductive layer. Although not shown, a silicon film may be formed under the first conductive film to a thickness of about 2 to 20 nm. Further, a second conductive film 115 was formed over the first conductive film 114 with a thickness of 100 to 400 nm using a conductive material mainly containing an element selected from Ta, Ti, Mo, and W. For example, Ta may be formed to a thickness of 200 nm (FIG. 1C).

When a Ta film is used for the second conductive film 115, it can be formed by a sputtering method. The Ta film uses Ar as a sputtering gas. When an appropriate amount of Xe or Kr is added to these sputter gases, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The α-phase Ta film has a resistivity of about 20 μΩcm and can be used as a gate electrode, but the β-phase Ta film has a resistivity of about 180 μΩcm and is not suitable for a gate electrode. However, since the TaN film has a crystal structure close to the α phase, if a Ta film is formed thereon, an α phase Ta film can be easily obtained. Accordingly, the first conductive film 114 is
It may be formed of a TaN film with a thickness of 0 nm. Ta
The film preferably has a resistivity in the range of 10 to 50 μΩcm.

In addition, when the second conductive film is formed of a W film, an argon (Ar) gas and a nitrogen (N ₂ ) gas are introduced by a sputtering method using W as a target to form the first conductive film. 114 is formed of a tungsten nitride (WN) film, and a second
Is formed of a W film by Ar gas sputtering. Further, the W film can be formed by thermal CVD using tungsten hexafluoride (WF ₆ ). In any case, in order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains a large amount of impurity elements such as oxygen, crystallization is inhibited and the resistance is increased.
From this, when the sputtering method is used, the purity is 99.99.
By using a 99% W target and forming a W film with sufficient care so as not to mix impurities from the gas phase during film formation, a resistivity of 9 to 20 μΩcm can be realized.

(Formation of Gate Electrode (p-ch), Wiring Electrode, and Formation of Fifth Impurity Region)
119 was formed, and a part of the first conductive film and part of the second conductive film were removed by etching to form a gate electrode 120 and gate wirings 122 and 123 of a p-channel TFT. Since the gate electrode of the n-channel TFT is formed in a later step,
The first conductive film and the second conductive film are formed of the semiconductor layers 105 and 106.
It was made to remain on the whole upper surface. And the resist mask 1
A step of adding an impurity element imparting p-type to a part of the semiconductor layer 104 where the p-channel TFT is formed was performed while leaving 16 to 119 as a mask. Here, boron is used as an impurity element and diborane (B ₂ H ₆ )
And added by an ion doping method. Here 2 × 10
Boron was added to a concentration of ²⁰ atoms / cm ³ . And FIG.
As shown in (A), fifth impurity regions 125 and 126 to which boron was added at a high concentration were formed. In this step, a part of the gate insulating film 107 is removed by etching using the resist masks 116 to 119 to expose a part of the island-shaped semiconductor layer 104, and then an impurity element imparting p-type conductivity is removed. The step of adding may be performed.

(Formation of Gate Electrode (n-ch)) After forming resist masks 127 to 130, an n-channel type TFT is formed.
The gate electrodes 131 and 132 were formed. At this time, the gate electrode 131 was formed so as to partially overlap with the low-concentration impurity regions 112 and 113 (FIG. 2B).

(Formation of First Impurity Region) Resist masks 134 to 136 are formed, and a first functioning as a source region or a drain region in an n-channel TFT is formed.
The step of forming the impurity region was performed. The resist mask 136 was formed so as to cover the gate electrode 132 of the n-channel TFT. This is the n-channel type TF of the pixel section.
At T, it was provided to form a fourth impurity region to be an offset LDD region. Then, the first impurity regions 139 to 143 are added by adding an impurity element imparting n-type.
Was formed. Also in this case, ion doping using phosphine (PH ₃ ) is performed, and the phosphorus concentration in this region is 1 ×.
It is preferably 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ^3, and in this case, 1 × 10 ²⁰ atoms / cm ³ . At the same time, a region 125 of the island-shaped semiconductor layer 104 to which boron is added,
Regions 137 and 138 in which phosphorus is also added to part of 126
Was formed (FIG. 2C).

(Formation of Second Low-Concentration Impurity Region) A low-concentration impurity region (hereinafter, referred to as a fourth impurity region in the present invention) serving as an LDD region of the n-channel TFT in the pixel portion is formed in the island-like semiconductor layer 106. A step of adding an impurity element imparting n-type was performed for formation. The concentration of phosphorus to be added is
It is preferable to make the same as or less than the low-concentration impurity region of 2 × 10 ¹⁷ atoms / cm ³ . Then, second low-concentration impurity regions 144 to 147 in which phosphorus was added to the island-shaped semiconductor layer were formed (FIG. 3A).

(Thermal Activation Step) First interlayer insulating film on the entire surface of the gate insulating film and the gate electrode (and also on the upper surface if a part of the island-shaped semiconductor layers 104 to 106 is exposed) 148 were formed. The first interlayer insulating film may be formed using a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. Further, it may have a two-layer structure of a silicon nitride film and a silicon oxide film or a silicon oxynitride film (not shown). In any case, the first interlayer insulating film is 500 to 1
It may be formed so as to have a thickness of 000 nm. Thereafter, a heat treatment step for activating the n-type or p-type impurity element added at each concentration was performed. This step includes a thermal annealing method using an electric heating furnace,
It can be performed by a rapid thermal annealing method (RTA method) using a halogen lamp. Here, the activation step was performed by a thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550.
C., for example, 525 ° C., and heat treatment was performed for 2 hours. In this process, when a crystalline silicon film is formed by a thermal crystallization method using a catalytic element that promotes crystallization of silicon in the step of crystallizing the semiconductor layer, the catalytic element is doped with phosphorus. Gettering effect to segregate to
The catalyst element could be removed from the channel formation region. Further, in an atmosphere containing 3 to 100% hydrogen,
Heat treatment was performed at 00 to 450 ° C. for 1 to 12 hours to hydrogenate the island-shaped semiconductor layer. In this step, heat treatment at 200 to 450 ° C. may be performed in a hydrogen atmosphere generated by plasma conversion using a plasma hydrogenation method (FIG. 3B).

(Formation of Source / Drain Wiring and Interlayer Insulating Film) The first interlayer insulating film 148
A contact hole reaching the source region and the drain region of the FT was formed. Then, the source wirings 149 and 15
0, 151 and drain wirings 152, 153 were formed. Although not shown, in this embodiment, this electrode is
A film having a thickness of 100 nm, an Al film containing Ti of 300 nm, and a Ti film of 150 nm were successively formed by a sputtering method and used as an electrode having a three-layer structure. Then, a passivation film 154 was formed on the first interlayer insulating film, the source wiring, the drain wiring, and the respective wiring electrodes. The passivation film 154 was formed using a silicon nitride film, a silicon oxide film, or a silicon oxynitride film with a thickness of 50 to 500 nm. Thereafter, when hydrogenation treatment was performed in this state, favorable results were obtained for improving the characteristics of the TFT. For example, 3 ~
It is preferable to perform heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 100% hydrogen, or 200 to 450 in a hydrogen atmosphere generated by being plasmatized using a plasma hydrogenation method. The same effect was obtained by performing a heat treatment at a temperature of ℃. Then, a second organic resin
Was formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used.

(Formation of Storage Capacitor and Pixel Electrode) A light-shielding film 156 was formed on the second interlayer insulating film in the pixel portion. Light shielding film 1
Reference numeral 56 denotes a film mainly containing an element selected from aluminum (Al), titanium (Ti), and tantalum (Ta).
It was formed to a thickness of ~ 300 nm. In order to form a storage capacitor in this portion, the dielectric film 15
7 was formed with a thickness of 50 to 200 nm. As the dielectric film 157, an oxide film formed on the surface of the light shielding film 156 by using an anodic oxidation method may be used. In addition, silicon oxide film, silicon nitride film, silicon oxynitride film, DLC (Di
amond like carbon) film or a polyimide film may be used. However, for example, the relative dielectric constant of polyimide is 3-4.
On the other hand, since the relative dielectric constant of Al oxide produced by the anodic oxidation method is 7 to 9, the latter is much more suitable for forming a large capacity in a small area.

More specifically, an Al oxide film was formed on the Al film by anodic oxidation, an electrode of 0.785 mm 2 was formed thereon, and the capacitance was measured. As a result, the thickness of the Al oxide film was 50 nm. At this time, 1100 pF was obtained, and at 100 nm, 630 pF was obtained.
The value of this capacitance was two to three times the value when the polyimide was formed with the same thickness. The storage capacitance provided in the pixel portion of the liquid crystal display device depends on the size of the pixel.
A capacity of fF was required, and when a storage capacity was formed using an Al oxide film, the area required for obtaining this capacity could be reduced to about 1/3 of that when polyimide was used.

Then, a contact hole reaching the drain wiring 153 is formed by the opening 159 provided in the second interlayer insulating film 155 and the opening 158 provided in the passivation film 154, and the pixel electrode 160 is formed. Formed.
The pixel electrode 160 may use a transparent conductive film in the case of a transmissive liquid crystal display device, and may use a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method. Pixel electrode 1
Numeral 60 is formed to extend over the light shielding film 156 via the dielectric film 157, and the storage capacitor 184 is formed in a region where the pixel electrode 160 overlaps the light shielding film 156 (FIG. 3C).

In the above steps, the n-channel type T
An FT 183 is formed, and driving circuits provided in the periphery include a p-channel TFT 181 and an n-channel TFT 182.
Was formed on the same substrate to produce an active matrix substrate.

In the p-channel TFT 181 of the driving circuit, a channel forming region 161 and fifth impurity regions 162 and 163 functioning as source or drain regions were formed. Then, the fifth impurity region 162 became a source region, and the fifth impurity region 163 became a drain region. The n-channel TFT 182 overlaps the gate electrode from the channel formation region 164, the first impurity regions 165 and 166, and the first low-concentration impurity region, and
Third impurity regions 167 and 168 functioning as regions were formed. The first impurity region 165 functioned as a source region, and the first impurity region 166 functioned as a drain region.

The n-channel TFT 183 in the pixel portion
Include first channel regions 169 and 170, a first impurity region 171 functioning as a source or drain region,
172, 173, and fourth impurity regions 174 to 177 functioning as LDD regions which do not overlap with the gate electrode were formed from the second low-concentration impurity regions.

The present invention considers the operating environment of each of the n-channel TFTs of the pixel portion and the driving circuit, and
The second impurity region, the third impurity region, and the fourth
By making the lengths of the impurity regions in the channel length direction different on the same substrate, an optimum shape could be formed for the TFTs constituting each circuit. n-channel type TFT
182 is suitable for a logic circuit having a driving voltage of about 10 V or the like. The length (Lov) of the LDD region (third impurity region) overlapping the gate electrode with respect to the channel length of 3 to 7 μm is 0.5 to 3.0 μm, typically 1.5.
μm may be used. Also, an n-channel TFT in the pixel portion
Although 183 has a multi-gate structure, fourth impurity regions 174 to 177 which are LDD regions which do not overlap with the gate electrode are provided on both the source side and the drain side in order to be driven with the polarity inverted. The length of this area (Lo
ff) may be set to 0.5 to 3.5 μm, typically 2.0 μm.

As described above, according to the present invention, the T and T constituting each circuit in accordance with the specifications required by the pixel portion and the driving circuit, respectively.
By optimizing the structure of the FT, the operation performance and reliability of the semiconductor device can be improved.
Specifically, the design of the LDD regions of the n-channel TFT is made different according to each circuit specification, and an LDD region that overlaps with the gate electrode or an LDD region that does not overlap is appropriately provided, so that the same substrate can be used. TFT structure that emphasizes measures against hot carrier deterioration,
A TFT structure emphasizing a low off-state current value can be realized.

[Embodiment 2] Another configuration of the storage capacitor connected to the n-channel TFT in the pixel portion of the active matrix substrate will be described. FIG. 4 is a sectional structural view of a pixel portion of an active matrix substrate manufactured in the same manner as in the first embodiment.

Base films 402 and 403 are formed on a substrate 401, and a first impurity region and a fourth impurity region are formed in the island-shaped semiconductor layer 404. Gate insulating film 405
A gate electrode 406 is formed thereon, and a source wiring 408 and a drain wiring 409 are formed over the first interlayer insulating film 407. Then, the passivation film 410,
The light shielding film 412 and the pixel electrode 4 are formed on the second interlayer insulating film 411.
18 are formed.

The storage capacitor 421 connected to the n-channel TFT 420 includes a light-shielding film 412 formed on the second interlayer insulating film 411 and a dielectric film 413 formed thereon.
And the pixel electrode 418. Also, the second
In the region where the opening of the interlayer insulating film is formed, an insulating spacer 414 is provided. An opening 415 provided in the passivation film 410, an opening 416 provided in the second interlayer insulating film 411, and a spacer 414. The pixel electrode 418 is connected to the drain wiring 409 through the opening 417 provided in the pixel electrode 418. By providing the spacer 414 in this manner, a short circuit between the light-shielding film and the pixel electrode can be prevented. The storage capacitor 421 is the light shielding film 41
2, formed at a portion where the dielectric film 413 and the pixel electrode 418 overlap.

[Embodiment 3] FIG. 5 shows another configuration of a storage capacitor connected to an n-channel TFT in a pixel portion. FIG. 5A illustrates an n-channel TFT in a pixel portion manufactured in the same manner as in Embodiment 1. Base films 502 and 503 are formed over a substrate 501, and a first impurity region and a fourth impurity region are formed in the island-shaped semiconductor layer 504. A gate electrode 506 is formed on the gate insulating film 505, and a source line 50 is formed on the first interlayer insulating film 507.
8, a drain wiring 509 is formed. Further, a light-shielding film 512 and a spacer 513 formed of an organic resin were formed over the passivation film 510 and the second interlayer insulating film. Thereafter, as shown in FIG. 5B, a dielectric film 514 was formed on the surface of the light shielding film by an anodic oxidation method. And FIG. 5 (C)
Hole 5 provided in passivation film 510 as shown in FIG.
15. Opening 51 provided in second interlayer insulating film 511
6. The pixel electrode 518 is connected to the drain wiring 509 through an opening 517 provided in the spacer 513. The storage capacitor 521 is formed at a portion where the light shielding film 512, the dielectric film 514, and the pixel electrode 518 overlap. By providing the spacer 513 in this manner, short-circuiting between the light-shielding film and the pixel electrode can be prevented. Wraparound can be prevented.

[0043]

[Embodiment 1] In this embodiment, an example of manufacturing a pixel portion and a driving circuit thereof on the same substrate by using the present invention is shown in FIG.
This will be described with reference to FIGS. In this specification, such a substrate is referred to as an active matrix substrate for convenience. First, a silicon oxynitride film 602a having a thickness of 50 to 500 nm, typically 100 nm, was formed as a base film on a substrate 601. The silicon oxynitride film 602a is made of SiH ₄ , N ₂ O, and NH ₃ , and has a nitrogen concentration of 25 atomic% or more and less than 50 atomic%.
After that, heat treatment at 450 to 650 ° C. was performed in a nitrogen atmosphere to densify the silicon nitride oxide film 602a. Further, a silicon oxynitride film 602b was formed to a thickness of 100 to 500 nm, typically 200 nm, and an amorphous semiconductor film (not shown) was formed continuously to a thickness of 20 to 80 nm. Then, a crystalline silicon film was formed by a known crystallization method (not shown). Unnecessary portions of the crystalline silicon film are removed by etching, and island-like crystalline semiconductor films 603 to 60 are formed.
6 was formed, and further a gate insulating film 607 was formed. The gate insulating film 607 is a silicon oxynitride film made of SiH ₄ and N ₂ O, and here is 10 to 200
nm, preferably a thickness of 50 to 150 nm (FIG. 6A).

Next, resist masks 608 to 611 covering the entire surface of the island-shaped semiconductor layers 603 and 606 and the channel formation regions of the island-shaped semiconductor layers 604 and 605 were formed. Then, an n-type impurity element was added by an ion doping method using phosphine (PH ₃ ) to form a first low-concentration impurity region. In this step, the gate insulating film 607 is
The acceleration voltage was set to 65 keV in order to add phosphorus to the island-like semiconductor layer thereunder through. The concentration of phosphorus added to the island-shaped semiconductor is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms /
cm ³ , preferably 1 × 10 ¹⁸ ato
ms / cm ³ . Then, first low-concentration impurity regions 612 to 615 to which phosphorus was added were formed (FIG. 6B).

The first conductive film 616 is formed by sputtering tantalum nitride (TaN) or tungsten nitride (W).
N). Although not shown, a silicon film may be formed under the first conductive film to a thickness of about 2 to 20 nm. Subsequently, aluminum (Al) or copper (C
u) as the main component, a third conductive film 617 of 100 to 3
It was formed to a thickness of 00 nm (FIG. 6C). Then, the wiring 618 was formed by etching the third conductive film so as to be part of the wiring from the input / output terminal to the input / output of the driver circuit. For example, when Al was used for the third conductive film, etching was performed with phosphoric acid solution with good selectivity to the base TaN. Further, the first conductive layer 616 and the wiring 618
The second conductive film 619 is made of a conductive material mainly containing an element selected from Ta, Ti, Mo, and W, and
It was formed to a thickness of 0 nm. For example, Ta may be formed to a thickness of 200 nm (FIG. 6D).

Next, resist masks 620 to 625 are formed, a part of the first conductive film and a part of the second conductive film are removed by etching, and wirings 626, p from the input / output terminal to the input / output of the drive circuit are removed. A gate electrode 627 of a channel type TFT and a gate wiring 630 were formed. The etching of the TaN film and the Ta film could be performed with a mixed gas of CF ₄ and O ₂ .
Then, while leaving the resist masks 620 to 625 as they are, the island-shaped semiconductor layer 60 where the p-channel TFT is formed is formed.
Step of adding an impurity element imparting p-type to a part of Sample No. 3 was performed. Here, boron was added as an impurity element by ion doping using diborane (B ₂ H ₆ ).
The boron concentration in this region was 2 × 10 ²⁰ atoms / cm ³ .
Then, as shown in FIG. 7A, fifth impurity regions 633 and 634 to which boron was added at a high concentration were formed.

The wiring 626 from the input / output terminal to the input / output of the drive circuit is formed so as to cover around the third conductive layer with the first conductive layer and the second conductive layer.

After removing the resist mask provided in FIG. 7A, new resist masks 635 to 640 were formed. This is for forming the gate electrode of the n-channel TFT, and the gate electrodes 641 to 643 of the n-channel TFT are formed by the dry etching method. At this time, the gate electrodes 641 and 642 were formed so as to overlap with a part of the first low-concentration impurity regions 612 to 615 (FIG. 7B).

As described above, the gate electrodes 627, 641-6
43 is formed from a first conductive film and a second conductive film.

Then, new resist masks 645 to 6
49 were formed. The resist masks 647 and 649 are formed so as to cover the gate electrodes 642 and 643 of the n-channel TFT and part of the second impurity region. Then, a step of forming a first impurity region by adding an impurity element imparting n-type was performed, and the first impurity regions 650 to 655 were formed in the island-shaped semiconductor layer in which the n-channel TFT was formed. (FIG. 7C).

In order to form a second low-concentration impurity region serving as an LDD region of the n-channel TFT in the pixel portion in the island-shaped semiconductor layer 606, a step of adding an impurity element imparting n-type was performed. The concentration of phosphorus to be added is preferably equal to or less than that of the second and third impurity regions.
Here, the concentration is set to 2 × 10 ¹⁷ atoms / cm ^3, and the second low concentration impurity regions 656 to
658 was formed (FIG. 8A).

Then, the first interlayer insulating film 659 is
SiH by CVD method_Four, N_TwoO, NH _ThreeAcid as raw material
Formed of a silicon nitride film. The silicon nitride oxide film contains
Hydrogen concentration should be formed to be 1 to 30 atomic%.
I wanted it. Then, in this state in a nitrogen atmosphere
400 to 800 ° C., 1 to 12 hours, for example 8 at 525 ° C.
Heat treatment was performed for a time. N added by this step
Activates impurity elements that impart type and p-type
did it. After this heat treatment, a hydrogenation step was performed. This
In a 3 to 100% hydrogen atmosphere,
Hydrogenation treatment preferably at 350-450 ° C for 2-12 hours
It is good to carry out the process of processing. Or, 200-500 ° C, good
Preferably, plasma is formed at a substrate temperature of 300 to 450 ° C.
May be hydrotreated with hydrogen produced by
(FIG. 8 (B)).

Thereafter, a predetermined resist mask was formed on the first insulating film 659, and contact holes reaching the source region and the drain region of each TFT were formed by etching. Then, the source wirings 660 and 6
63, 664, 666 and drain wirings 661, 662,
665 and 657 were formed. Although not shown, in this embodiment, this electrode is formed of a Ti film having a thickness of 100 nm and an A film containing Ti.
An l film having a thickness of 300 nm and a Ti film having a thickness of 150 nm were successively formed by a sputtering method and used as an electrode having a three-layer structure.

Then, a passivation film 67 is formed thereon.
0 was formed. The passivation film 670 is made of plasma C
The silicon nitride oxide film formed from SiH ₄ , N ₂ O, and NH ₃ by a VD method or a silicon nitride film formed from SiH ₄ , N ₂ , and NH ₃ may be used. First, prior to the formation of the film, a hydrogenation step was performed by introducing plasma such as N ₂ O, N ₂ , and NH ₃ . Hydrogen generated in the gas phase by being turned into plasma is supplied into the first interlayer insulating film, and if the substrate is heated to 200 to 400 ° C., the hydrogen is diffused to the lower layer side and the semiconductor is diffused. The layer could be hydrogenated. The conditions for forming the passivation film are not particularly limited, but a dense film is desirable. After the passivation film is formed, the hydrogenation step is performed in an atmosphere containing hydrogen or nitrogen.
The heat treatment at 00 to 550 ° C. may be performed by a heat treatment for 1 to 12 hours.

Thereafter, a second interlayer insulating film 671 made of an organic resin was formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used.

If the insulating film 644 is formed on the second interlayer insulating film with a silicon nitride oxide film, a silicon oxide film or the like in a thickness of 5 to 50 nm, the adhesion of the light-shielding film formed thereon can be improved. . Further, when the surface of the second interlayer insulating film formed of an organic resin is treated with CF ₄ plasma to modify the surface,
The adhesion of the film formed thereon could be improved. Then, an Al film was formed by a sputtering method or a vacuum evaporation method, and was subjected to an etching treatment to form a light-shielding film 672. This light shielding film 67
In No. 2, an oxide film having a thickness of 50 to 200 nm was formed on the surface by anodic oxidation. In the anodization, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration was first prepared. The concentration of tartaric acid was adjusted to 0.1 to 10%, preferably 3%, and 1-20% aqueous ammonia was added thereto to adjust the pH to 7 ± 0.5. A platinum electrode serving as a cathode was provided in the solution, and the substrate on which the light-shielding film 672 was formed was immersed in the solution. Then, the DC current was kept constant at 2 mA using the light-shielding film 672 as an anode.
The voltage between the cathode and the anode in the solution changes with time as the oxide film grows, but the voltage is adjusted so that the current is constant, and when the voltage reaches 150 V, the voltage is fixed.
Thereafter, the current was maintained until the current reached 0.1 mA. Thus, an Al oxide film 673 having a thickness of 50 to 200 nm was formed on the surface of the light shielding film 672. It should be noted that the numerical values relating to the anodic oxidation method shown here are merely examples, and the optimum values can naturally vary depending on the size of the element to be manufactured and the like. Then, the insulating film 644 and the second interlayer insulating film 67
1. forming a contact hole reaching the drain wiring 667 at an opening provided in the passivation film 670;
A pixel electrode 676 was formed. For the pixel electrode 676, a transparent conductive film was used for a transmissive liquid crystal display device, and a metal film was used for a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method. The pixel electrode 676 is formed of the Al oxide film 6
The pixel electrode 676 extends over the light-shielding film 672 through the light-shielding film 732.
00 was formed. Through the above steps, an active matrix substrate in which a pixel portion and a TFT of a driving circuit provided around the pixel portion are formed on the same substrate is manufactured (FIG. 8).
(C)).

The p-channel TFT 701 is formed in a self-aligned manner (self-aligned),
Nos. 02 to 704 were formed non-self-aligned (non-self-aligned). A channel formation region 677 and a fifth impurity region 67 are provided in the p-channel TFT 701 of the driver circuit.
8,679 were formed. The fifth impurity region 678 served as a source region, and the fifth impurity region 679 served as a drain region. On the other hand, the n-channel TFT 702 includes a channel formation region 680, a first impurity region 681 serving as a source region, and a first impurity region 68 serving as a drain region.
2. From the first low-concentration impurity region, the gate electrode overlaps L
Third impurity regions 683 and 684 to be DD regions were formed. This n-channel TFT is suitable for a shift register circuit and a buffer circuit. Also, n-channel type TF
T703 includes a channel formation region 685, a first impurity region 686 serving as a source region, and a first impurity region 686 serving as a drain region.
Impurity region 687, third impurity region 68 from the first low-concentration impurity region to overlap the gate electrode and become an LDD region
Second impurity regions 688b and 689b serving as LDD regions which do not overlap with the gate electrodes were formed. Such an n-channel TFT is suitable for a sampling circuit in which an analog switch is formed. The n-channel TFT 704 in the pixel portion includes a channel forming region 6
90, 691, the first impurity regions 692, 696, the second
LDD that does not overlap with gate electrode from low concentration impurity region
Fourth impurity regions 693 to 695 serving as regions were formed.

As described above, according to the present invention, the T and T constituting each circuit according to the specifications required by the pixel portion and the driving circuit, respectively.
By optimizing the structure of the FT, the operation performance and reliability of the semiconductor device can be improved.
For example, the n-channel TFT 702 of the driver circuit is provided with an LDD region (GOLD) overlapping the gate electrode. By providing such an LDD, a change in characteristics due to a kink effect, a hot electron effect, or the like can be prevented, which is suitable for a shift register, particularly a buffer circuit, and the like. In the n-channel TFT 703, an LDD region (G
OLD) 688a and 689a and LDD regions 688b and 689b which do not overlap with the gate electrode are formed, which is effective for the purpose of lowering the off-current value and preventing TFT deterioration due to the hot carrier effect. Further, an n-channel TFT provided in the pixel portion has an LDD region 693 which does not overlap with the gate electrode.
This is effective in reducing the off-current value to ensure the switching operation and reducing the power consumption.

[Embodiment 2] In this embodiment, a process for manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. As shown in FIG.
An alignment film 901 is formed on the substrate in the state shown in FIG.
Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. The transparent conductive film 9 is provided on the substrate 902 on the opposite side.
03 and an alignment film 904 were formed. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were parallel-aligned with a certain pretilt angle. Then, the pixel portion, the active matrix substrate on which the drive circuit is formed, and the counter substrate are attached to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. Thereafter, a liquid crystal material 905 was injected between the two substrates, and completely sealed with a sealant (not shown). Liquid crystal materials include TN liquid crystal and antiferroelectric liquid crystal (Antiferroelectric
Liquid Crystal), anti-ferroelectric liquid crystal without threshold, etc. can be applied. Thus, the active matrix type liquid crystal display device shown in FIG. 9 was completed.

Next, the configuration of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 10 and the top view of FIG. FIGS. 10 and 11 correspond to FIGS.
In order to correspond to the cross-sectional structure diagram of FIG. The active matrix substrate includes a pixel portion 1001, a scanning (gate) line driving circuit 1002, and a signal (source) line driving circuit 1003 formed over a glass substrate 601. An n-channel TFT 704 is formed in the pixel portion, and a driving circuit provided in the periphery is configured based on a CMOS circuit. Scanning (gate) line drive circuit 1
002 and the signal (source) line driver circuit 1003 are connected to the pixel portion 100 by a gate wiring 643 and a source wiring 666, respectively.
1 connected. Further, wirings 626 and 668 are provided from the external input / output terminal 1034 to which the FPC 1031 is connected to the input / output terminal of the driving circuit.

FIG. 11 is a top view showing a part of the pixel portion 1001. Here, FIG. 11A is a top view showing the superposition of a semiconductor layer, a gate electrode, and a source wiring, and FIG. 11B is a top view showing the superposition of a light-shielding film and a pixel electrode formed thereon. It is. The gate electrode 643 is connected to the semiconductor layer 60 thereunder via a gate insulating film (not shown).
Crosses 6. Although not shown, the semiconductor layer 60
6, a source region, a drain region, and a fourth impurity region are formed. A light-shielding film 6 is formed on the pixel TFT.
72, a dielectric film (not shown), and a pixel electrode 676 provided for each pixel are formed, and the storage capacitor 7 is formed in a region where the light-shielding film 672 and the pixel electrode 676 overlap with the dielectric film interposed therebetween.
00 is formed. By oxidizing the surface of the Al film that forms the light-shielding film to form a dielectric film for forming the capacitance portion,
It is possible to reduce an area for forming a necessary capacitor, and further, as in this embodiment, a light-shielding film formed on an n-channel TFT in a pixel portion is used as one electrode of a storage capacitor. Thus, the aperture ratio of the image display section of the active matrix type liquid crystal display device could be improved. The cross-sectional structure along AA ′ shown in FIG. 11 corresponds to the AA ′ cross-sectional view of the pixel portion shown in FIG.

[Embodiment 3] FIG. 12 shows another configuration example of a method of connecting a storage capacitor provided in a TFT in a pixel portion. FIG.
2 is a sectional structural view of a pixel portion of an active matrix substrate manufactured in the same manner as in the first embodiment. Substrate 1201
Base films 1202 and 1203 are formed thereon, and a first impurity region and a fourth impurity region are formed in the island-shaped semiconductor layer 1204. A gate electrode 1206 is formed over the gate insulating film 1205, and a source wiring 1208 and a drain wiring 1209 are formed over the first interlayer insulating film 1207. Further, the passivation film 1211 and the second
A light shielding film 1213 is formed on the interlayer insulating film 1212 of FIG.

In FIG. 12A, n-channel type TF
The storage capacitor 1240 connected to T includes a light-shielding film 1213 formed on the second interlayer insulating film 1212, a dielectric film 1214 formed thereon, and a pixel electrode 1215. The pixel electrode 1215 which is one electrode of the storage capacitor 1240 is connected to the passivation film 12.
11 and opening 12 provided in second interlayer insulating film 1212
At 60, it is connected to the drain wiring 1209. Also,
The light-shielding film serving as the other electrode is a passivation film 121.
Opening 126 provided in first and second interlayer insulating films 1212
1 is connected to the wiring electrode 1210 formed on the first interlayer insulating film 1207. In FIG. 12B, a wiring 1216 formed of the same material as the pixel electrode 1215 is used.
And the light shielding film 1213 are electrostatically coupled at the connection portion 1251 via the dielectric film 1214 to form the passivation film 1211.
And opening 1261 provided in second interlayer insulating film 1212
Wiring electrode 1 formed on first interlayer insulating film 1207
It is also possible to connect with 210. FIG.
In (B), the light-shielding film 1213 is composed of the dielectric film 1214, the alignment film 1217, the liquid crystal 1218, and the alignment film 121 on the counter substrate side.
9, it is also possible to electrostatically couple with the common electrode 1220.

Fourth Embodiment FIG. 13 shows an example of a circuit configuration of the active matrix substrate shown in the first embodiment. The active matrix substrate of this embodiment includes a source signal line side drive circuit 1301 and a gate signal line side drive circuit (A) 130.
7, a gate signal line side driving circuit (B) 1311, a precharge circuit 1312, and a pixel portion 1306. The source signal line side driving circuit 1301 is a shift register circuit 1
302, level shifter circuit 1303, buffer circuit 13
04, and a sampling circuit 1305. Also,
The gate signal line side driver circuit (A) 1307 includes a shift register circuit 1308, a level shifter circuit 1309, and a buffer circuit 1310. The gate signal line side driver circuit (B) 1311 has a similar configuration.

Here, an example of the drive voltage of each circuit is shown.
0 to 16 V, and the level shifter circuits 1303, 130
9, the buffer circuits 1304 and 1310, the sampling circuit 1305, and the pixel portion 1306 were 14 to 16V.
The sampling circuit 1305 and the pixel portion 1306 have the amplitude of the applied voltage, and the polarity-reversed voltage is normally applied alternately. According to the present invention, the length of the second impurity region serving as the LDD region can be easily changed on the same substrate in consideration of the driving voltage of the n-channel TFT, and the TFT constituting each circuit can be easily changed. As a result, an optimal shape could be formed in the same process.

FIG. 14A shows the TF of the shift register circuit.
4 shows a configuration example of T. The n-channel TFT of the shift register circuit has a single-gate structure, and includes third impurity regions (LDD regions) 205 and 206 overlapping the channel formation region 204 and the gate electrode 210. Outside these, first impurity regions 207 and 208 serving as source regions or drain regions are formed. The length of this region in the channel length direction may be 0.5 to 3 μm with the channel length being 3 to 7 μm. This LDD configuration is effective for hot carrier deterioration countermeasures, and is suitable for a shift register circuit or the like in which characteristics in the off region are not emphasized. On the other hand, in the p-channel TFT, the fifth impurity region 20 serving as a source region or a drain region outside the channel formation region 201 and the gate electrode 209 is formed.
2, 203 are formed. Then, source wirings 211 and 212 and a drain wiring 213 which form a contact with the source or drain region of each TFT are formed.

FIG. 14B shows a configuration example of the TFTs of the level shifter circuit and the buffer circuit. Although the n-channel TFTs of these circuits have a double gate structure,
Of course, there is no problem with a single gate structure. This n-channel TFT also has channel forming regions 204a, 204b,
Third impurity regions (LDD regions) 205a, 205b, and 2 which overlap gate electrodes 210a and 210b.
06a, 206b. By providing such an LDD, a high electric field region in the vicinity of the drain is relaxed, and a change in characteristics due to a kink effect, a hot electron effect, or the like can be prevented. As a result, the reliability of the buffer circuit can be improved. The p-channel TFT has a structure similar to that of FIG.

FIG. 14C shows a TFT of a sampling circuit.
2 shows a configuration example. N-channel TFT of this circuit
Has a single gate structure, but outside the channel formation region, corresponding to the drive with the polarity reversed, the second impurity region 205c which becomes an LDD region overlapping with the gate electrode on both the source side and the drain side. , 206
c is provided. Second impurity regions 205c and 20
6c are preferably equal in length,
It is good to form in the range of 0.5 to 3.0 μm. These LDD regions can simultaneously achieve the purpose of reducing the off-current value and the purpose of preventing the TFT from deteriorating due to the hot carrier effect. The p-channel TFT has a structure similar to that of FIG.

FIG. 14D shows a structure suitable for a driving circuit which operates at a high speed with a driving voltage of about 1.5 to 5 V.
On the source region 207 side of the n-channel TFT, a second impurity region 2 not overlapping with the gate electrode 210 is formed.
And a third impurity region 206 overlapping the gate electrode 210 on the drain region 208 side.
d is provided. Thus, the configuration is such that the operating frequency is prevented from lowering due to the parasitic capacitance.

[Embodiment 5] In this embodiment, a method for manufacturing a semiconductor layer applicable to the present invention will be described. In FIG. 15, a substrate 1501 can be a glass substrate, a ceramics substrate, a quartz substrate, or the like. Alternatively, a silicon substrate having a surface on which an insulating film such as a silicon oxide film or a silicon nitride film is formed, or a metal substrate represented by stainless steel may be used. In the case of using a glass substrate, it is desirable to perform a heat treatment in advance at a temperature equal to or lower than the strain point. For example, if a Corning # 1737 substrate is used, 500-6
Heat treatment at 50 ° C, preferably 595 to 645 ° C, for 1 to 24 hours may be performed.

Then, a base film was formed on the main surface of the substrate 1501. Although there is no particular limitation on the material of the base film, the base film was formed using a silicon oxynitride film 1502. In addition, a single layer or a plurality of layers selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a tantalum oxide film can be used. When using a silicon oxynitride film,
The thickness may be 20 to 100 nm, typically 50 nm. A silicon oxynitride film is formed on a silicon nitride film having a thickness of 10 to 100 nm by 50 to 500 nm, typically 50 to 500 nm.
It may be formed to a thickness of 200 nm. Then, an amorphous semiconductor layer 1503 was formed thereon. This is plasma C
Any amorphous semiconductor formed by a film forming method such as a VD method, a low-pressure CVD method, or a sputtering method may be used.
There are germanium (Ge), a silicon germanium alloy, and silicon carbide. In addition, a compound semiconductor material such as gallium arsenide can be used. The semiconductor layer is 1
It was formed to have a thickness of 0 to 100 nm, typically 50 nm. Further, the base film 1501 and the amorphous semiconductor layer 1503
Can be continuously formed by a plasma CVD method or a sputtering method. After each layer is formed, the surface is prevented from being exposed to the atmosphere, thereby preventing the surface from being contaminated (FIG. 15A).

Next, a crystallization step was performed. For the step of crystallizing the amorphous semiconductor layer, a known laser crystallization technique or thermal crystallization technique may be used. In addition, plasma CV
The amorphous semiconductor layer formed by the method D has a thickness of 10 to 40 atomic.
% Hydrogen is contained in the film, and prior to the crystallization step, a heat treatment process at 400 to 500 ° C. is performed to desorb the hydrogen from the film so that the hydrogen content is 5 atomic% or less. Was desirable (FIG. 15B). Then, the crystalline semiconductor layer 1504 is turned into an island-like crystalline semiconductor layer 150.
5 and a gate insulating film 1505 was further formed.
The gate insulating film 1505 may be formed using a material such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. The thickness of the gate insulating film 1505 is 10 to 1000 n.
m, preferably 50 to 400 nm. In the subsequent steps, the semiconductor device of the present invention can be formed according to the first embodiment (FIG. 15C).

FIG. 16 shows that a base film 1602 made of a silicon oxynitride film is formed on the main surface of
Similarly to the above, an amorphous semiconductor layer 1603 was formed on the surface. The thickness of the amorphous semiconductor layer may be from 10 to 200 nm, preferably from 30 to 100 nm. Further, an aqueous solution containing 10 ppm by weight of a catalytic element was applied by spin coating to form a catalytic element-containing layer 1604 over the entire surface of the amorphous semiconductor layer 1603. The catalyst elements that can be used here are germanium (Ge), iron (Fe), palladium (Pd), tin (S) in addition to nickel (Ni).
n), lead (Pb), cobalt (Co), platinum (Pt),
Elements such as copper (Cu) and gold (Au). The internal stress of the amorphous semiconductor layer was not determined uniformly by the manufacturing conditions. However, prior to the crystallization step, 4
It was necessary to perform a heat treatment process at 00 to 600 ° C. to desorb hydrogen from the film (FIG. 16A). And 50
Heat treatment was performed at 0 to 600 ° C. for 4 to 12 hours, for example, at 550 ° C. for 8 hours, whereby a crystalline semiconductor layer 1605 was formed.
(FIG. 16 (B)).

Next, a gettering step of removing the catalytic element used in the crystallization step from the crystalline semiconductor film was performed. By this gettering step, the concentration of the catalytic element in the crystalline semiconductor film could be reduced to 1 × 10 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ . First, the mask insulating film 1 is formed on the surface of the crystalline semiconductor layer 1605.
606 was formed to a thickness of 150 nm, an opening 1607 was provided by patterning, and a region exposing the crystalline semiconductor layer was provided. Then, a step of adding phosphorus was performed to provide a phosphorus-containing region 1608 in the crystalline semiconductor layer (FIG. 16C). In this state, 550 in a nitrogen atmosphere
When heat treatment is performed at 800 ° C. for 5 to 24 hours, for example, at 600 ° C. for 12 hours, the phosphorus-containing region 1608 functions as a gettering site, and the catalytic element remaining in the crystalline semiconductor layer 1605 is transferred to the phosphorus-containing region 1608. Segregation was possible (FIG. 16 (D)). Then, by removing the mask insulating film 1606 and the phosphorus-containing region 1608 by etching, the concentration of the catalytic element used in the crystallization step is reduced to 1 × 10 ¹⁷ atms / cm ³ or less. A high quality semiconductor layer was obtained. Then, a gate insulating film 1610 was formed in close contact with the island-shaped semiconductor layer 1609 (FIG. 16E).

FIG. 17 shows that a base film 1702 and an amorphous semiconductor layer 1703 are formed on a substrate 1701 in this order, and a mask insulating film 1 is formed on the surface of the amorphous semiconductor layer 1703.
704 was formed. At this time, the thickness of the mask insulating film 1704 was set to 150 nm. Further, the mask insulating film 1704
Was selectively formed to form openings 1705, and then an aqueous solution containing 10 ppm by weight of a catalytic element was applied. Thereby, the catalyst element-containing layer 1706
Was formed. The catalyst element-containing layer 1706 has an opening 170
5 contacted the amorphous semiconductor layer 1703 (FIG. 17).
(A)). Next, heat treatment was performed at 500 to 650 ° C. for 4 to 24 hours, for example, 570 ° C. for 14 hours, so that a crystalline semiconductor layer 1707 was formed. In the course of this crystallization, the region of the amorphous semiconductor layer in contact with the catalytic element crystallized first, and the crystallization proceeded laterally from there. The crystalline semiconductor layer 1707 thus formed is made up of a collection of rod-shaped or needle-shaped crystals, each of which grows in a specific direction when viewed macroscopically, and thus has uniform crystallinity. (FIG. 17B).

Next, as in FIG. 16, a step of removing the catalytic element used in the crystallization step from the crystalline semiconductor film was performed. A step of adding phosphorus is performed on the substrate in the same state as in FIG. 17B, and the phosphorus-containing region 1 is formed in the crystalline semiconductor layer.
709 was provided. The phosphorus content in this region is 1 × 10 ¹⁹
１1 × 10 ²¹ / cm ³ (FIG. 17C). In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, at 600 ° C. for 12 hours, the phosphorus-containing region 1709 functions as a gettering site and remains in the crystalline semiconductor layer 1707. The separated catalyst element was segregated in the phosphorus-containing region 1709 (FIG. 17).
(D)).

Then, the mask insulating film 1704 and the phosphorus-containing region 1709 were removed by etching to form an island-shaped crystalline semiconductor layer 1710. Then, a gate insulating film 1711 was formed in close contact with the crystalline semiconductor layer 1710. The gate insulating film 1711 was formed from one or more layers selected from a silicon oxide film and a silicon oxynitride film. Its thickness is 10-100 nm, preferably 50
What is necessary is just to form it as 80 nm. Then, heat treatment was performed in an atmosphere containing halogen (typically chlorine) and oxygen. For example, the temperature was set to 950 ° C. for 30 minutes. The processing temperature may be selected in the range of 700 to 1100 ° C., and the processing time may be selected from 10 minutes to 8 hours. As a result, a thermal oxide film was formed at the interface between the island-shaped semiconductor layer 1710 and the gate insulating film 1711, and a favorable interface with a low interface state density could be formed (FIG. 17E).

[Embodiment 6] In this embodiment, the TFT of the present invention is used.
A semiconductor device incorporating an active matrix type liquid crystal display device using circuits will be described with reference to FIGS.

Such semiconductor devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, still cameras, personal computers,
TV and the like. One example of them is shown in FIG.

FIG. 18A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention provides an audio output unit 9002,
The present invention can be applied to the voice input portion 9003 and the display device 9004 including the active matrix substrate.

FIG. 18B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention relates to a display device 910 including a voice input unit 9103 and an active matrix substrate.
2. It can be applied to the image receiving unit 9106.

FIG. 18C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display device 9205. The invention can be applied to the display device 9205 including the image receiving portion 9203 and the active matrix substrate.

FIG. 18D shows a head-mounted display, which comprises a main body 9301, a display device 9302, and an arm portion 9303. The invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 18E shows a rear type projector, which includes a main body 9401, a light source 9402, a display device 9403,
Polarizing beam splitter 9404, reflector 940
5, 9406 and a screen 9407. The invention can be applied to the display device 9403.

FIG. 18F shows a portable book, and a main body 95.
01, display devices 9502 and 9503, storage medium 950
4, comprising an operation switch 9505 and an antenna 9506 for displaying data stored on a mini disk (MD) or a DVD or data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 19A shows a personal computer, which includes a main body 2401, an image input section 2402, and a display device 2.
403 and a keyboard 2404.

FIG. 19B shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium).
15, a recording medium 2416, and operation switches 2417. This device uses a DVD (Di) as a recording medium.
A digital versatile disc), a CD, and the like can be used for music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 2414 and other signal control circuits.

FIG. 19C shows a digital camera, which comprises a main body 2418, a projection device 2419, an eyepiece 2420, an operation switch 2421, and an image receiving unit (not shown). The present invention can be applied to the display device 2419 and other signal control circuits.

FIG. 20A shows a front type projector, which comprises a projection device 2601 and a screen 2602. The present invention can be applied to a display device and other signal control circuits.

FIG. 20B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3. It is composed of a screen 2704. The present invention can be applied to the display device 2702 (particularly effective in the case of 50 to 100 inches) and other signal control circuits.

FIG. 20C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 20A and 20B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
5 to 2807, dichroic mirror 2803, 280
4. Optical lens 2808, 2809, prism 281
1, a liquid crystal display device 2810 and a projection optical system 2812. The projection optical system 2812 is configured by an optical system having a projection lens. Although this embodiment shows an example of a three-panel type using three liquid crystal display devices 2810, the present invention is not particularly limited.
For example, it may be a single plate type. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 20D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 20C. In this embodiment, the light source optical system 2801 includes the light source 281.
3, 2814, combining prism 2815, collimator lenses 2816, 2820, lens arrays 2817, 281
8. It is composed of a polarization conversion element 2819. Note that FIG.
Although the light source optical system shown in (D) uses two light sources, three to four or more light sources may be used, and of course, one light source may be used. The practitioner may appropriately provide an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like to the light source optical system.

Although not shown here, the present invention can also be applied to an image sensor or an EL display device. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

Although not shown here, the present invention can also be applied to a car navigation system or a display unit of an image sensor personal computer. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

[Embodiment 7] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 21A is a top view of an EL display device using the present invention. In FIG. 21A, reference numeral 4010 denotes a substrate; 4011, a pixel portion; 4012, a source driver circuit; 4013, a gate driver circuit;
And connected to the external device.

At this time, the cover member 600 is formed so as to surround at least the pixel portion, preferably the driving circuit and the pixel portion.
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 21B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed.

The present invention can be used for a TFT 4022 for a driving circuit and a TF 4023 for a pixel portion.

A TFT 402 for a driving circuit according to the present invention
2. When the pixel portion TFT 4023 is completed, the pixel portion TFT is formed on an interlayer insulating film (flattening film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film electrically connected to the drain of the FT 4023 is formed. Pixel electrode 4027
Is a transparent conductive film, the TFT for the pixel portion has p
It is preferable to use a channel type TFT. As the transparent conductive film, a compound of indium oxide and tin oxide (IT
O) or a compound of indium oxide and zinc oxide. Then, the pixel electrode 4027
Is formed, an insulating film 4028 is formed, and the pixel electrode 40 is formed.
An opening is formed on 27.

Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, the cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, as the cathode 4030,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region indicated by 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed.

Further, a sealing material is provided inside the cover material 6000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0109] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001.

An example in which an EL display device having a further different form is manufactured will be described with reference to FIGS. 21A and 21B denote the same parts, and a description thereof will not be repeated.

FIG. 22A is a top view of the EL display device of this embodiment, and FIG. 22B is a cross-sectional view taken along line AA ′ of FIG.

In the same manner as shown in FIG. 21, a passivation film 6003 is formed covering the surface of the EL element.

[0117] Further, the filling material 6 is formed so as to cover the EL element.
004 is provided. This filler 6004 is used for the cover material 60.
It also functions as an adhesive for bonding 00. As the filler 6004, PVC (polyvinyl chloride),
Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

When a spacer is provided, the passivation film 6003 can ease the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

Next, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of the sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.

FIG. 23 shows a detailed sectional structure of the pixel portion of the EL display device, FIG. 24A shows a top view structure thereof, and FIG.
(B) shows. FIGS. 23, 24 (A) and 24 (B)
Then, since a common code is used, they may be referred to each other.

In FIG. 23, a switching TFT 3002 provided on a substrate 3001 is formed by using the n-channel TFT of the present invention (see Examples 1 to 7).
In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted.
However, by using a double gate structure, substantially two T
There is an advantage that the FT has a structure in which the FTs are connected in series, and the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used.

The current controlling TFT 3003 is formed using the n-channel TFT of the present invention. At this time,
Drain wiring 3035 of switching TFT 3002
Is electrically connected to the gate electrode 3037 of the current controlling TFT by a wiring 3036. A wiring denoted by 3038 is a gate wiring for electrically connecting the gate electrodes 3039a and 3039b of the switching TFT 3002.

At this time, it is very important that the current controlling TFT 3003 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which a GOLD region (second impurity region) is provided on the drain side of the current control TFT so as to overlap the gate electrode with the gate insulating film interposed therebetween is extremely effective.

In this embodiment, the current control TFT 30
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 24A, the wiring which becomes the gate electrode 3037 of the current controlling TFT 3003 is a region indicated by reference numeral 3004 in the current controlling TFT 3003.
Overlap with the drain wiring 3040 via the insulating film. At this time, a capacitor is formed in a region indicated by 3004. This capacitor 3004 is used for the current control TFT 30.
It functions as a capacitor for holding the voltage applied to the gate of the gate 03. Note that the drain wiring 3040 is connected to a current supply line (power supply line) 3006, and a constant voltage is constantly applied.

The first passivation film 3 is formed on the switching TFT 3002 and the current control TFT 3003.
041 is provided, and a planarizing film 3042 made of a resin insulating film is formed thereon. TF using the flattening film 3042
It is very important to flatten the step due to T. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, E
It is desirable to planarize the pixel layer before forming the pixel electrode so that the L layer can be formed as flat as possible.

Reference numeral 3043 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
It is electrically connected to the drain of T3003. In this case, an n-channel TF is used as the current control TFT.
It is preferable to use T. As the pixel electrode 3043, a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof is preferably used. Of course, a stacked structure with another conductive film may be employed.

A light emitting layer 3045 is formed in a groove (corresponding to a pixel) formed by banks 3044a and 3044b formed of an insulating film (preferably resin). Although only one pixel is shown here, R
Light emitting layers corresponding to the colors (red), G (green), and B (blue) may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. A typical polymer-based material is polyparaphenylene vinylene (PPV)
System, polyvinyl carbazole (PVK) system, polyfluorene system and the like.

There are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As a specific light emitting layer, cyanopolyphenylene vinylene is used for a light emitting layer emitting red light, polyphenylene vinylene is used for a light emitting layer emitting green light, and polyphenylene vinylene or polyalkylphenylene is used for a light emitting layer emitting blue light. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example in which a polymer material is used as the light emitting layer has been described, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, the PED is formed on the light emitting layer 3045.
EL having a laminated structure provided with a hole injection layer 3046 made of OT (polythiophene) or PAni (polyaniline)
And layers. An anode 3047 made of a transparent conductive film is provided over the hole injection layer 3046. In the case of this embodiment, since the light generated in the light emitting layer 3045 is emitted toward the upper surface (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

At the point when the anode 3047 is formed, the EL element 3005 is completed. The EL element 30 referred to here
05 denotes a pixel electrode (cathode) 3043, a light emitting layer 3045,
It refers to a capacitor formed by the hole injection layer 3046 and the anode 3047. As shown in FIG.
Since 43 substantially corresponds to the area of the pixel, the entire pixel is EL
Functions as an element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

Incidentally, in this embodiment, a second passivation film 3048 is further provided on the anode 3047. As the second passivation film 3048, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. And a TFT. Therefore,
EL with high reliability and good image display
A display panel is obtained.

The configuration shown in FIG. 23 can be implemented by freely combining with the configurations of Embodiment 1 and Examples 1 to 4. In addition, it is effective to use the EL display device of the present embodiment as the display unit of the electronic device of the sixth embodiment.

As another structure of the pixel portion, a structure obtained by inverting the structure of the EL element 3005 will be described. FIG. 25 is used for the description. Note that the difference from the structure of FIG. 23 is only the EL element portion and the current controlling TFT.
Other description is omitted.

In FIG. 25, the current controlling TFT 310
3 is formed using the p-channel TFT of the present invention.
The manufacturing process may refer to Embodiment Mode 1 and Examples 1 to 4.

In FIG. 25, a transparent conductive film is used as the pixel electrode (anode) 3050. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, the bank 3051a made of an insulating film,
After the formation of 3051b, a light emitting layer 3052 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 3053 made of potassium acetylacetonate (denoted as acacK) and a cathode 3054 made of an aluminum alloy are formed thereon. In this case, the cathode 3
054 also functions as a passivation film. Thus, an EL element 3101 is formed.

The light generated in the light emitting layer 3052 is radiated toward the substrate on which the TFT is formed as shown by the arrow.

The configuration shown in FIG. 25 can be implemented by freely combining with the configurations of Embodiment 1 and Examples 1 to 4. In addition, it is effective to use the EL display panel of the present embodiment as the display unit of the electronic device of the sixth embodiment.

FIGS. 26A to 26C show an example in which a pixel having a structure different from that of the circuit diagram shown in FIG.
Shown in In this embodiment, 3201 is a source wiring of the switching TFT 3202, 3203 is a gate wiring of the switching TFT 3202, 3204 is a current control TFT, 3205 is a capacitor, 3206, 32
08 is a current supply line, and 3207 is an EL element.

FIG. 26A shows an example in which a current supply line 3206 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3206. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 26B shows the current supply line 320.
8 is provided in parallel with the gate wiring 3203. Note that in FIG. 26B, the current supply line 3208 and the gate wiring 3203 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3208 and the gate wiring 3203 can share an occupied area, the pixel portion can have higher definition.

FIG. 26C shows that the current supply line 3208 is connected to the gate wiring 3203 similarly to the structure of FIG. 21B.
a and 3203b, and is characterized in that two pixels are formed so as to be symmetric with respect to the current supply line 3208. It is also effective to provide the current supply line 3208 so as to overlap with one of the gate wirings 3203a and 3230b. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The configuration of the circuit shown in FIG. 26 can be implemented by freely combining with the configuration of Embodiment 1 and Examples 1-4. In addition, it is effective to use an EL display device having the pixel structure of this embodiment as a display portion of the electronic device of the sixth embodiment.

In FIGS. 24A and 24B, the current control TF
Although a capacitor 3004 is provided to hold the voltage applied to the gate of T3003, the capacitor 3004 can be omitted. Current control TF
N of the present invention as shown in Examples 1 to 7 as T3003
Since a channel-type TFT is used, a GOLD region (a second impurity region) is provided so as to overlap a gate electrode with a gate insulating film interposed therebetween. In this overlapping region, a parasitic capacitance generally called a gate capacitance is formed. In this embodiment, this parasitic capacitance is
The feature is that it is actively used in place of the 04.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the GOLD region overlap, the GOL included in the overlapping region is included.
It is determined by the length of the D area.

In the structure shown in FIGS. 26A, 26B and 26C, the capacitor 3205 can be omitted in the same manner.

It is to be noted that such a configuration can be implemented by freely combining with the configurations of the first embodiment and the first to fourth embodiments. In addition, it is effective to use an EL display device having the pixel structure of this embodiment as a display portion of the electronic device of the sixth embodiment.

[Eighth Embodiment] FIG. 27 shows an example of the characteristics of an n-channel TFT manufactured based on the description of the first embodiment, and shows the results of a bias temperature (BT) test. FIG.
7 has a channel length of 8 μm, a channel width of 8 μm, Lov = 2.5 μm, and has no Loff. In the BT test, a bias of 20 V was applied to the gate electrode, the temperature was maintained at 150 ° C. for 1 hour, and then the bias was cut off and a heat treatment at 150 ° C. for 1 hour was applied. FIG. 27 shows the results in terms of characteristics of gate voltage (VG) versus drain current (ID) when the drain voltage (Vd) is 1 V and 5 V. With a structure in which an LDD region overlapping with the gate electrode is provided, deterioration due to the hot carrier effect is prevented, and no change in characteristics due to bias stress is observed. Further, the base film is made of SiH ₄ , NH ₃ ,
Silicon oxynitride film made from N ₂ O (100 nm)
Silicon oxynitride film (2) made of SiH ₄ and N ₂ O
00 nm), it is possible to remove the influence of mobile ions contained in the substrate.
No change in threshold voltage due to the -T test was observed.

FIGS. 28A and 28B show such TFTs.
5 shows dynamic characteristics (power supply voltage 10 V) of a ring oscillator manufactured by using FIG. The ring oscillator has 19 stages. FIG. 28A shows a change in the oscillation frequency with respect to the channel length when Lov = 2 μm, using the activation condition of the implanted impurity element as a parameter. The oscillation frequency decreases as the channel length increases, but does not depend much on the activation conditions. When an LDD structure overlapping with the gate electrode is provided, there is a concern that the operating frequency may be reduced due to an increase in parasitic capacitance due to the portion. However, FIG.
As shown in FIG. 8 (B), when the value of Lov is changed from 1 to 3 μm when the channel length is 6 μm, it is possible to oscillate at a frequency of 8 to 12 MHz, although the Lov length dependency is observed. It turned out that there was no problem in practical use.

As described above, a TFT having an LDD structure in which a silicon oxynitride film is provided as a base film and overlaps with a gate electrode has high resistance to stress due to bias and heat, and is free from deterioration due to a hot carrier effect.
And because it is possible to operate at high frequencies,
It is particularly excellent in forming a shift register circuit and a buffer circuit of a driving circuit.

[0160]

According to the present invention, the third impurity region overlapping the gate electrode and the second impurity region not overlapping the gate electrode are formed as an LDD region between the channel forming region and the drain region of the n-channel TFT. , And an n-channel TFT whose structure is optimized according to different operation characteristics can be formed on the same substrate. For example, an n-channel TFT provided with a third impurity region overlapping with a gate electrode is formed in a driver circuit formed based on a CMOS circuit formed on an active matrix substrate.
The n-channel TFT in the pixel portion can have a structure in which a fourth impurity region which does not overlap with the gate electrode is provided.

A storage capacitor provided in the pixel portion is formed by a light-shielding film, a dielectric film formed on the light-shielding film, and a pixel electrode,
In particular, by using Al for the light-shielding film, forming the dielectric film by the anodic oxidation method, and using the Al oxide film, it is possible to reduce an area for forming a capacitor necessary for image display,
Further, by using the light-shielding film formed on the pixel TFT as one electrode of the storage capacitor, the aperture ratio of the image display section of the active matrix liquid crystal display device could be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a peripheral driver circuit.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a peripheral driver circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a peripheral driver circuit.

FIG. 4 is a cross-sectional view illustrating a configuration of a storage capacitor.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a storage capacitor.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a peripheral driver circuit.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a peripheral driver circuit.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a peripheral driver circuit.

FIG. 9 is a cross-sectional structural view of an active matrix liquid crystal display device.

FIG. 10 is a perspective view of an active matrix liquid crystal display device.

FIG. 11 is a top view of a pixel portion.

FIG. 12 is a cross-sectional view illustrating a configuration of a storage capacitor.

FIG. 13 is a circuit block diagram of an active matrix liquid crystal display device.

FIG. 14 is a cross-sectional view illustrating a structure of a TFT of the present invention.

FIG. 15 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 16 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 17 is a cross-sectional view illustrating a manufacturing step of a crystalline semiconductor layer.

FIG. 18 illustrates an example of a semiconductor device.

FIG. 19 illustrates an example of a semiconductor device.

FIG. 20 illustrates an example of a projector.

21A and 21B are a top view and a cross-sectional view of an active matrix EL display device.

FIG. 22 is a top view and a cross-sectional view of an active matrix EL display device.

FIG. 23 is a cross-sectional view of a pixel portion of an active matrix EL display device.

24A and 24B are a top view and a circuit diagram of a pixel portion of an active matrix EL display device.

FIG. 25 is a cross-sectional view of a pixel portion of an active matrix EL display device.

FIG. 26 is a circuit diagram of a pixel portion of an active matrix EL display device.

FIG. 27 is a graph showing the results of a bias temperature test of a TFT provided with Lov.

FIG. 28 is a graph showing characteristics of a ring oscillator using a TFT provided with Lov.

[Explanation of symbols]

 101 substrate 102, 103 base film 104-106 semiconductor layer 107 gate insulating film 120, 131, 132 gate electrode 122, 123 wiring electrode 148 first interlayer insulating film 149, 150, 151 source wiring 152, 153 drain wiring 154 passivation film 155 Second interlayer insulating film 156 Light shielding film 157 Dielectric film 160 Pixel electrode 162, 163 Fifth impurity region 166, 165, 171-173 First impurity region 167, 168 Third impurity region 174-177 Fourth Impurity region

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yukio Tanaka 398 Hase, Hase, Atsugi-shi, Kanagawa Prefecture Inside the Semi-Conductor Energy Laboratory Co., Ltd.

Claims (24)

[Claims] In a semiconductor device in which a driving circuit and a pixel portion are formed of a thin film transistor over the same substrate, the driving circuit includes a channel forming region provided inside a gate electrode and a third conductive type. A first thin film transistor having a first impurity region of one conductivity type forming a source region or a drain region provided outside the gate electrode, and a channel formation region and a source region or a drain region formed outside the gate electrode A fifth thin film transistor having a fifth impurity region having a conductivity type opposite to the one conductivity type, wherein the pixel portion includes a channel formation region provided inside a gate electrode, and a gate electrode. Thin film having a fourth impurity region of one conductivity type provided outside the substrate and a first impurity region of one conductivity type forming a source region or a drain region Wherein a has a transistor. 2. A semiconductor device in which a driving circuit and a pixel portion are formed of a thin film transistor on the same substrate, wherein the driving circuit includes a channel forming region provided inside a gate electrode and a third conductive type. Thin film transistor having a first impurity region of one conductivity type forming a source region or a drain region provided outside the gate electrode, and a channel formation region provided inside the gate electrode And a third impurity region of one conductivity type, a second impurity region of one conductivity type provided outside the gate electrode, and a first impurity region of one conductivity type forming a source region or a drain region. A second thin film transistor;
A fifth thin film transistor having a channel formation region and a fifth impurity region having a conductivity type opposite to the one conductivity type forming a source region or a drain region; and the pixel portion is provided inside a gate electrode. A channel forming region provided outside the gate electrode and a fourth region of one conductivity type provided outside the gate electrode.
And a fourth thin film transistor having a first impurity region of one conductivity type forming a source region or a drain region. 3. A semiconductor device in which a driving circuit and a pixel portion are formed of a thin film transistor on the same substrate, wherein the driving circuit includes a channel forming region provided inside a gate electrode and a third conductive type. A first thin film transistor having a first impurity region of one conductivity type forming a source region or a drain region provided outside the gate electrode, and a channel forming region provided inside the gate electrode. A third thin film transistor having a second impurity region of one conductivity type provided outside the gate electrode and a first impurity region of one conductivity type forming a source region or a drain region; a channel formation region and a source; And a fifth thin film transistor having a fifth impurity region of a conductivity type opposite to the one conductivity type forming the region or the drain region, The pixel portion includes a channel formation region provided inside the gate electrode, a first conductivity type fourth impurity region provided outside the gate electrode, and a first conductivity type first impurity region forming a source region or a drain region. And a fourth thin film transistor having the impurity region described above. 4. A semiconductor device in which a driving circuit and a pixel portion are formed of a thin film transistor over the same substrate, wherein the driving circuit includes a channel forming region provided inside a gate electrode and a third conductive type. Thin film transistor having a first impurity region of one conductivity type forming a source region or a drain region provided outside the gate electrode, and a channel formation region provided inside the gate electrode And a third impurity region of one conductivity type, a second impurity region of one conductivity type provided outside the gate electrode, and a first impurity region of one conductivity type forming a source region or a drain region. A second thin film transistor;
A channel formation region provided inside the gate electrode, a second conductivity region provided outside the gate electrode, and a first conductivity region formed to form a source region or a drain region; A third thin film transistor having a fifth thin film transistor having a channel formation region and a fifth impurity region having a conductivity type opposite to the one conductivity type forming the source region or the drain region,
The pixel portion includes a channel formation region provided inside a gate electrode, a first conductivity type fourth impurity region provided outside the gate electrode, and a first conductivity type first impurity region forming a source region or a drain region. And a fourth thin film transistor having the impurity region described above. 5. The fourth impurity region according to claim 1, wherein the third impurity region and the fourth impurity region include the same impurity element of one conductivity type. A concentration of the impurity element contained in the third impurity region is lower than a concentration of the impurity element contained in the third impurity region. 6. The second impurity region according to claim 2, wherein the second impurity region and the third impurity region contain the same one conductivity type impurity element. A concentration of the impurity element included in the third impurity region is equal to a concentration of the impurity element included in the third impurity region. 7. The pixel unit according to claim 1, wherein the pixel unit is connected to a light-shielding film formed on the fourth thin film transistor via an insulating layer, and to the fourth thin film transistor. A pixel electrode, a light-shielding film, a dielectric film in contact with the light-shielding film, and a storage capacitor composed of a pixel electrode in contact with the dielectric film, wherein the storage capacitance is the fourth thin-film transistor A semiconductor device, which is connected to a semiconductor device. 8. The light-shielding film according to claim 7, wherein the light-shielding film is made of a material mainly containing one or more kinds selected from aluminum, tantalum, and titanium, and the dielectric film is an oxide of the light-shielding film material. A semiconductor device, comprising: 9. The semiconductor device according to claim 7, wherein said dielectric film is formed of a material selected from silicon nitride, silicon oxide, silicon oxynitride, DLC, and polyimide. 10. The semiconductor device according to claim 7, wherein the insulating layer has an inorganic insulating film and an organic insulating film, and the light-shielding film is formed in contact with the organic insulating film. 11. The semiconductor device according to claim 7, wherein said insulating layer has an inorganic insulating film and an organic insulating film, and said light shielding film is formed in contact with said inorganic insulating film. 12. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a mobile computer, a head-mounted display, a projector, a mobile book, a digital camera, a car navigation, a personal computer. A semiconductor device, which is one selected from the group consisting of: 13. A step of forming a plurality of island-shaped semiconductor layers on a substrate having an insulating surface, a step of forming a gate insulating film in contact with the island-shaped semiconductor layers, and a step of forming a gate in contact with the gate insulating film. Forming an electrode; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer to form a first electrode.
Forming a first thin film transistor having an impurity region and a third impurity region overlapping with the gate electrode; and selecting an impurity element having a conductivity type opposite to one conductivity type in the island-shaped semiconductor layer. Added to the
Forming a fifth thin film transistor having a first impurity region and a first impurity region and a fourth impurity region by adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer Forming a fourth thin film transistor. 14. A step of forming a plurality of island-shaped semiconductor layers on a substrate having an insulating surface, a step of forming a gate insulating film in contact with the island-shaped semiconductor layers, and a step of forming a gate in contact with the gate insulating film. Forming an electrode; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer to form a first electrode.
Forming a first thin film transistor having an impurity region and a third impurity region overlapping with the gate electrode; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer. And a first impurity region;
Forming a second thin film transistor having a third impurity region overlapping the gate electrode and a second impurity region not overlapping the gate electrode; and forming an impurity of a conductivity type opposite to the one conductivity type. Adding an element to a selected region of the island-shaped semiconductor layer to form a fifth thin film transistor having a fifth impurity region;
Forming a fourth thin film transistor having a first impurity region and a fourth impurity region by adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer. Of manufacturing a semiconductor device. 15. A step of forming a plurality of island-shaped semiconductor layers on a substrate having an insulating surface, a step of forming a gate insulating film in contact with the island-shaped semiconductor layers, and a step of forming a gate in contact with the gate insulating film. Forming an electrode; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer to form a first electrode.
Forming a first thin film transistor having an impurity region and a third impurity region overlapping with the gate electrode; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer. And a first impurity region;
Forming a third thin film transistor having a second impurity region that does not overlap with the gate electrode; and adding an impurity element having a conductivity type opposite to one conductivity type to a selected region of the island-shaped semiconductor layer. Forming a fifth thin film transistor having a fifth impurity region, and adding a first conductivity type impurity element to a selected region of the island-shaped semiconductor layer by adding a first conductivity region and a fourth impurity element. Forming a fourth thin film transistor having a region. 16. A step of forming a plurality of island-shaped semiconductor layers on a substrate having an insulating surface, a step of forming a gate insulating film in contact with the island-shaped semiconductor layers, and a step of forming a gate in contact with the gate insulating film. Forming an electrode; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer to form a first electrode.
Forming a first thin film transistor having an impurity region and a third impurity region overlapping with the gate electrode; and adding an impurity element of one conductivity type to a selected region of the island-shaped semiconductor layer. And a first impurity region;
Forming a second thin film transistor having a third impurity region overlapping the gate electrode and a second impurity region not overlapping the gate electrode; Forming a third thin film transistor having a first impurity region added to a selected region of the layer and a second impurity region that does not overlap with the gate electrode; and a conductivity type opposite to the one conductivity type. A fifth impurity region having a fifth impurity region by adding an impurity element of a type to a selected region of the island-shaped semiconductor layer.
Forming a thin film transistor, and adding a first conductivity type impurity element to a selected region of the island-shaped semiconductor layer to form a fourth thin film transistor having a first impurity region and a fourth impurity region. A method of manufacturing a semiconductor device. 17. The semiconductor device according to claim 13, wherein the third impurity region and the fourth impurity region are doped with the same one conductivity type impurity element. A method for manufacturing a semiconductor device, wherein the concentration of the impurity element included in a fourth impurity region is lower than the concentration of the impurity element included in the third impurity region. 18. The semiconductor device according to claim 13, wherein the second impurity region and the third impurity region are doped with the same one conductivity type impurity element. A method for manufacturing a semiconductor device, wherein the concentration of the impurity element included in the second impurity region is added at the same concentration as the concentration of the impurity element included in the third impurity region. 19. The light shielding film according to claim 13, wherein an insulating layer is formed on the fourth thin film transistor, a light shielding film is formed on the insulating film, Forming a storage capacitor from a step of forming a dielectric film in contact with the dielectric film and a step of forming a conductive film in contact with the dielectric film. 20. The method for manufacturing a semiconductor device according to claim 19, wherein the step of forming the dielectric film in contact with the light shielding film is an anodic oxidation method. 21. The method for manufacturing a semiconductor device according to claim 19, wherein the light-shielding film is formed of a material containing one or more of aluminum, tantalum, and titanium as main components. 22. A method for manufacturing a semiconductor device according to claim 19, wherein said insulating layer is formed of an inorganic insulating layer and an organic insulating layer, and said light shielding film is formed in contact with said organic insulating layer. . 23. The method according to claim 19, wherein the insulating layer is formed of an inorganic insulating layer and an organic insulating layer,
A method for manufacturing a semiconductor device, which is formed in contact with an inorganic insulating layer. 24. The semiconductor device according to claim 13, wherein the semiconductor device is a mobile phone, a video camera, a mobile computer, a head mounted display, a projector, a mobile book, a digital camera, a car navigation, a personal computer. A method for manufacturing a semiconductor device, which is one selected from the group consisting of: