JP2000340801A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance an operating characteristic and reliability of a semiconductor device by a method wherein an n type impurity element in a higher concentration than an LDD region of an n channel type TFT of a pixel is contained in the LDD region of the n channel type TFT of a device circuit. SOLUTION: In a bottom gate or an invert staggered TFT provided with an LDD region, the LDD region of an n channel TFT of a pixel is formed in an n-- concentration and only in L off, so that an off current can fairly be reduced and this can contribute to suppressing power in the pixel. Furthermore, the LDD region of the n channel TFT of a drive circuit is formed in an n- concentration and only n L oV, so that current drive capability can be increased, and a deterioration due to hot carriers can be prevented, and deterioration of an on current can be decreased. Furthermore, operating performance and reliability of a semiconductor device having a such electric optical device as a display medium can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit formed of thin film transistors (hereinafter, referred to as TFTs) on a substrate having an insulating surface, and a method for manufacturing the same. In particular, the present invention is suitable for an electro-optical device typified by a liquid crystal display device in which a pixel portion (or a pixel matrix circuit) and a driver circuit provided therearound are provided over the same substrate, and an electronic device equipped with the electro-optical device. Available to
Note that in this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic apparatus equipped with the electro-optical device in its category.

[0002]

2. Description of the Related Art Development of a semiconductor device having a circuit formed by a TFT on a substrate having an insulating surface is in progress. An active matrix liquid crystal display device is well known as a typical example. In particular, a TFT in which an active layer is formed of a crystalline silicon film (hereinafter, referred to as a crystalline silicon TFT) has high field-effect mobility, so that various functional circuits can be formed, and these circuits can be formed on the same substrate. The above-mentioned electro-optical device integrally formed with the device has been developed.

For example, an active matrix type liquid crystal display device includes a pixel portion for displaying an image, a driving circuit for displaying an image, and the like. Drive circuit is CMO
It is composed of a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like, which are formed based on the S circuit, and such circuits are mixedly mounted on the same substrate.

When viewed individually, the operating conditions of these circuits are not always the same, and the characteristics required for the TFTs are not less different. For example, the pixel portion has a configuration in which a pixel TFT composed of an n-channel TFT and a storage capacitor are provided, and the pixel TFT is driven by applying a voltage to a liquid crystal as a switching element. Since the liquid crystal is driven by alternating current, a method called frame inversion drive is often used. In this method, in order to suppress power consumption, a characteristic required for the pixel TFT is to sufficiently reduce an off-current value (a drain current flowing when the TFT is turned off). On the other hand, since a high drive voltage is applied to the buffer circuit of the drive circuit, it is necessary to increase the breakdown voltage so that the buffer circuit is not broken even when the high voltage is applied. Further, in order to increase the current driving capability, it is necessary to sufficiently secure an on-current value (a drain current flowing when the TFT is turned on).

However, there is a problem that the off-current value of the crystalline silicon TFT tends to be high. Also, I
As with the MOS transistor used for C and the like, a deterioration phenomenon such as a decrease in the on-current value is observed in the crystalline silicon TFT. The main cause is hot carrier injection, and it is considered that hot carriers generated by a high electric field near the drain cause a deterioration phenomenon.

As a structure of a TFT for reducing an off-current value, a lightly doped drain (LDD) is used.
ain) The structure is known. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source or drain region formed by adding an impurity element at a high concentration. This region is referred to as an LDD region. Calling.

As means for preventing deterioration due to hot carriers, a so-called GOLD in which an LDD region is arranged so as to overlap a gate electrode with a gate insulating film interposed therebetween.
(Gate-drain Overlapped LDD) structure is known. With such a structure, a high electric field in the vicinity of the drain is relaxed to prevent hot carrier injection, which is effective in preventing a deterioration phenomenon. For example, "Mutuko Hatano, Hajime
Akimoto and TakeshiSakai, IEDM97 TECHNICAL DIG
EST, p523-526, 1997 "discloses a GOLD structure formed by sidewalls formed of silicon, but it has been confirmed that extremely superior reliability can be obtained as compared with TFTs of other structures. .

[0008]

However, the required characteristics of the pixel TFT in the pixel portion and the TFT of a driving circuit such as a shift register circuit and a buffer circuit are not necessarily the same. For example, a large reverse bias (negative voltage for an n-channel TFT) is applied to the gate of the pixel TFT, but the TFT of the driving circuit does not basically operate in the reverse bias state. Regarding the operation speed, the pixel TFT is 1/100 of the TFT of the driving circuit.
The following is good.

Although the GOLD structure has a high effect of preventing the deterioration of the ON current value, it has a problem that the OFF current value becomes larger than that of the normal LDD structure. Therefore, it was not a preferable structure to be applied to the pixel TFT. Conversely, the ordinary LDD structure has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain to prevent deterioration due to hot carrier injection. As described above, in a semiconductor device having a plurality of integrated circuits having different operating conditions, such as an active matrix liquid crystal display device, it is not always preferable to form all the TFTs with the same structure. Such problems have become more apparent as the characteristics of crystalline silicon TFTs have increased, and the performance required for active matrix type liquid crystal display devices has increased.

The present invention is a technique for solving such a problem, and includes a TFT arranged in each circuit of a semiconductor device.
The object of the present invention is to improve the operating characteristics and reliability of the semiconductor device by making the structure of the semiconductor device appropriate according to the function of the circuit.

[0011]

According to the present invention, there is provided a semiconductor device having a pixel portion and a driving circuit for the pixel portion on the same substrate, wherein the pixel portion and the driving circuit are provided. An active layer, an LDD region provided in the active layer, a gate insulating film provided between the active layer and the substrate, and a gate insulating film provided between the gate insulating film and the substrate. At least an n-channel TFT having a gate electrode, and an LD of the n-channel TFT in the pixel portion.
The D region is disposed so as not to overlap with the gate electrode of the n-channel TFT of the pixel portion, and the LDD region of the n-channel TFT of the driving circuit overlaps with the gate electrode of the n-channel TFT of the driving circuit. Wherein the LDD region of the n-channel TFT of the driving circuit contains an impurity element imparting n-type at a higher concentration than the LDD region of the n-channel TFT of the pixel portion.

Further, an n-channel type TFT of the driving circuit
Is characterized in that the LDD region contains an impurity element that imparts n-type at a concentration of 2 to 10 times the LDD region of the n-channel TFT in the pixel portion.

At least the n-channel type T of the pixel section
An organic resin film is formed on the FT, and a light-shielding film formed on the organic resin film, a dielectric film formed in close contact with the light-shielding film, and a part thereof are provided so as to overlap the light-shielding film. A pixel electrode connected to the n-channel TFT of the pixel portion;
It is characterized by providing a capacity.

[0014] Further, with regard to a method for manufacturing a semiconductor device, the structure of the present invention relates to a method for manufacturing a semiconductor device having a pixel portion and a driver circuit for the pixel portion over the same substrate. An active layer, an LDD region of the active layer, a gate insulating film provided between the active layer and the substrate, and a gate electrode provided between the gate insulating film and the substrate. forming an n-channel TFT, wherein the LDD region of the n-channel TFT in the pixel portion is
The n-channel TFT of the driving circuit is disposed so as not to overlap with a gate electrode of the n-channel TFT of the pixel portion.
Are arranged so as to overlap the gate electrode of the n-channel TFT of the driving circuit, and the LDD region of the n-channel TFT of the driving circuit is larger than the LDD region of the n-channel TFT of the pixel portion. It is characterized by adding an impurity element imparting n-type at a high concentration.

The LD of the n-channel TFT of the driving circuit
It is characterized in that an impurity element imparting n-type is added to the D region at a concentration of 2 times or more and 10 times or less as compared with the LDD region of the n-channel TFT of the pixel portion.

At least the n-channel type T of the pixel section
Forming an organic resin film on the FT, forming a light-shielding film on the organic resin film, forming a dielectric film in close contact with the light-shielding film, and partially overlapping the light-shielding film And forming a pixel electrode connected to the n-channel TFT of the pixel portion provided as described above.

FIG. 5 is a view for explaining the structure of the present invention, in which an active layer, an LDD region provided in the active layer, a gate insulating film provided on the substrate side of the active layer,
The positional relationship between a gate electrode and an LDD region in a bottom-gate or inverted staggered TFT having a gate electrode provided between a gate insulating film and a substrate is described.

In FIG. 5A, a channel forming region 5 is formed.
03, an active layer having an LDD region 504 and a drain region 505, and a configuration in which a gate insulating film 502 and a gate electrode 501 are provided under the active layer. LDD region 5
04 is provided so as to overlap with the gate electrode 501 with the gate insulating film 502 interposed therebetween. Such an LDD region is referred to herein as Lov. Lov has an action of relaxing a high electric field generated near the drain, and can prevent deterioration due to hot carriers.
Suitable for use in T.

FIG. 5B shows that an active layer on a gate insulating film 507 includes a channel forming region 508, an LDD region 509,
A drain region 510 is provided. LDD region 50
9 is provided so as not to overlap with the gate electrode 506. Such an LDD region is referred to as Loff in this specification. Loff is effective in reducing the off-current value and is suitable for use in an n-channel TFT in a pixel portion.

As described above, according to the present invention, in a semiconductor device having a pixel portion and its driving circuit, an n-channel TFT having Loff is provided in the pixel portion, and an n-channel TFT having Lov is provided in the driving circuit. It is characterized in that the TFT is formed in a bottom gate type or an inverted stagger type.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the following examples.

Embodiment 1 FIGS. 1 and 2 show an embodiment of the present invention.
This will be described with reference to FIG. Here, a method for simultaneously manufacturing TFTs of a pixel portion and a driver circuit provided around the pixel portion will be described in detail according to steps.

(Formation of Gate Electrode, Gate Insulating Film, and Semiconductor Layer: FIG. 1A) In FIG. 1A, a low alkali glass substrate or a quartz substrate is used as a substrate 101. A base film such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film may be formed on the surface of the substrate 101 where the TFT is formed (not shown). The gate electrodes 102 to 104 are made of tantalum (Ta), titanium (T
i) using an element selected from elements selected from tungsten (W), molybdenum (Mo), and aluminum (Al) or a material containing any one of the elements as a main component, using a known film forming method such as a sputtering method or a vacuum evaporation method. After the formation of the coating, an etching process was performed so that the end face became tapered, and a pattern was formed. For example, a Ta film is formed to a thickness of 200 nm by a sputtering method, and a resist mask is formed in a predetermined shape.
If a plasma etching treatment was performed with a mixed gas of F ₄ and O _2, a desired shape could be processed. The gate electrode may have a two-layer structure of tantalum nitride (TaN) and Ta or tungsten nitride (WN) and W (not shown).
Although not shown, a gate wiring connected to the gate electrode is also formed at the same time.

The gate insulating film 105 is made of a material containing silicon oxide and silicon nitride and has a thickness of 10 to 200 nm, preferably 50 to 150 nm. For example, a silicon nitride film 105a made of SiH ₄ , NH ₃ , and N ₂ is formed to a thickness of 50 nm, and a silicon nitride oxide film 105b made of SiH ₄ and N ₂ O is formed to a thickness of 75 nm by a plasma CVD method. It may be used as a gate insulating film. Of course, a single layer made of a silicon nitride film or a silicon oxide film may be used. In addition, in order to obtain a clean surface, it is preferable to perform plasma hydrogen treatment before forming the gate insulating film.

Next, close contact with the gate insulating film 105, 2
An amorphous silicon film having a thickness of 0 to 150 nm is plasma C
It was formed by a known film forming method such as a VD method or a sputtering method. Although there are no limitations on the conditions for forming the amorphous silicon film,
5 × 10 ¹⁸ c of oxygen and nitrogen impurity elements contained in the film
It is desirable to reduce it to m ⁻³ or less. Further, since the gate insulating film and the amorphous silicon film can be formed by the same film formation method, both may be formed continuously. After the gate insulating film is formed, it is possible to prevent the surface from being contaminated by not once exposing it to the air atmosphere.
Variations in the characteristics of T and fluctuations in the threshold voltage can be reduced. Then, the crystalline silicon film 106 is formed by using a known crystallization technique. For example, a laser crystallization method, a thermal crystallization method (solid phase growth method), or a crystallization method using a catalytic element can be used.

In the crystalline silicon film 106, boron (B) of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ is formed in a region where an n-channel TFT is formed, for the purpose of controlling a threshold voltage. It may be added. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film.

(Formation of spacer film, formation of n ⁻ region: FIG. 1)
(B) Next, in order to form an LDD region of an n-channel TFT in the pixel portion, an impurity element imparting n-type was added. First, a silicon oxide film or a silicon nitride film was formed over the entire surface of the crystalline silicon film 106 to a thickness of 100 to 200 nm, for example, 120 nm. After a photoresist film was formed on the entire surface, the photoresist film was exposed to light using the gate electrodes 102 to 104 as a mask by an exposure method from the back surface to form a resist mask on the gate electrode (not shown). At this time, by optimizing the exposure time and the irradiation light intensity, the resist mask could be formed with substantially the same width as the gate electrode. Then, unnecessary portions are etched away using this resist mask,
First spacer films 107 to 109 made of a silicon oxide film or a silicon nitride film were formed. In addition, 50
The second spacer film 110 was formed with a thickness of nm.

Then, an impurity element imparting n-type is added to the crystalline silicon film below the second spacer film 110 through the second spacer film 110 by an ion doping method. The phosphorus (P) concentration of the impurity regions 111 to 115 thus formed is 1 × 1.
Desirably, the range is 0 ^{17 to} 2.5 × 10 ¹⁸ cm ⁻³ , and in this case, the range is 2 × 10 ¹⁷ cm ⁻³ . In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 111 to 115 is expressed as (n ⁻ ).

(Formation of n ⁻ region and n ⁺ region: FIG. 1 (C))
Next, in an n-channel TFT, a step of forming an impurity region functioning as a source region or a drain region and a step of forming an LDD region of the n-channel TFT of the driver circuit were performed. Here, resist masks 116 to 118 were formed by a normal exposure method. The mask 116 was formed so as to cover at least a portion to be a channel formation region of the p-channel TFT. A mask 118 provided for the n-channel TFT in the pixel portion was formed so as to cover a portion to be a channel formation region and an LDD region. Also, the mask 117
Was formed so as to cover a portion to be a channel formation region of an n-channel TFT of a driver circuit. Then, the n-type is provided through the second spacer film 110 and the first spacer film 108, and the impurity regions 119 to 123 to which the impurity element imparting the n-type is added via the second spacer film 110. Regions 124 and 125 to which an impurity element to be added is added
Were formed by ion doping (or ion implantation). The impurity regions 119 to 123 have 1 × 10 ²⁰ to 1 × 1
May if 0 ²¹ cm ^-3, and where to include an impurity element at a concentration of 5 × 10 ²⁰ cm ^-3. This concentration is referred to herein as (n ⁺ ). The impurity regions 124 and 125 have 2 ×
The impurity element may be contained at a concentration of 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , and in this embodiment, the concentration is set to 6 × 10 ¹⁷ cm ⁻³ . This concentration is represented herein as (n ⁻ ).

(Formation of p ⁺ region: FIG. 2A) Next, a step of adding an impurity element imparting p-type to form a source region and a drain region of a p-channel TFT of a driving circuit is described. went. Here, a p-channel TFT
In order to determine the channel formation region, a new resist mask 126 is formed on the second spacer film 110, and the first spacer film and the second spacer film are subjected to an etching process to form a new spacer film. 129 and 130 were formed and the surface of the crystalline silicon film was exposed. At this time, the regions where the n-channel TFT was to be formed were covered with resist masks 127 and 128. And diborane (B
_The impurity regions 131 and 132 were formed by an ion doping method using ₂ H ₆ ) (an ion implantation method may be used). The boron (B) concentration in this region is 1.5 × 10 ^{20 to} 3 × 10 ^21.
cm ^−3, and in this case, 1 × 10 ²¹ cm ⁻³ . In this specification, the impurity region 13 formed here is used.
The concentration of the impurity element imparting p-type contained in the elements ¹ and 132 is represented by (p ⁺ ). Note that, as shown in FIGS. 1B to 1C, a region where phosphorus (P) is mixed is formed in a part of the impurity regions 131 and 132, but is added in this step. By setting the boron (B) concentration to 1.5 to 3 times the p-type conductivity, the characteristics of the TFT were not affected at all.

(Formation of First Interlayer Insulating Film, Step of Thermal Activation, Step of Hydrogenation: FIG. 2B) After the respective impurity elements are selectively added to the crystalline silicon film, the first and second steps are performed. After removing the spacer film of No. 2, the crystalline silicon film was divided into islands by etching, and a protective insulating film 150 which later became a part of the first interlayer insulating film was formed. The protective insulating film 150 may be formed using a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. Further, the film thickness may be 100 to 400 nm.

Thereafter, a heat treatment step was performed to activate the n-type or p-type imparting impurity elements added at the respective concentrations. This process is furnace annealing,
It can be performed by a laser annealing method, a rapid thermal annealing method (RTA method), or the like. Here, the activation step was performed by furnace annealing. The heat treatment is
300-650 ° C., preferably 5 in a nitrogen atmosphere
The heat treatment was performed at 00 to 550 ° C, here 525 ° C, for 4 hours. Further, heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen,
A step of hydrogenating the active layer was performed. In this step, dangling bonds in the active layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

The crystalline silicon film 106 serving as an active layer is
When the amorphous silicon film was formed by a crystallization method using a catalyst element, a small amount of the catalyst element remained in the crystalline silicon film 106. Of course, there is no problem in completing and operating the TFT even in such a state, but it was more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing the gettering action of phosphorus (P). Figure 1 shows the concentration of phosphorus (P) required for gettering.
The same as the impurity region (n ⁺ ) formed in (C),
By the heat treatment in the activation step performed here, the catalyst element can be gettered from the channel formation regions of the n-channel TFT and the p-channel TFT to the peripheral impurity region to which phosphorus (P) is added. did it.

(Formation of interlayer insulating film, formation of source / drain wiring, formation of passivation film, formation of pixel electrode: FIG. 2 (C))
An interlayer insulating film 1 having a thickness of 500 to 1500 nm on 50
51 were formed. The protective insulating film 150 and the interlayer insulating film 1
The laminated film 51 was used as a first interlayer insulating film. Thereafter, a contact hole reaching the source region or the drain region of each TFT is formed, and the source wiring 15 is formed.
2, 153 and 154 and drain wirings 155 and 156 were formed. Although not shown, in this embodiment, this electrode is formed of a Ti film having a thickness of 100 nm and a Ti-containing aluminum film 3.
A three-layer laminated film was formed by continuously forming a Ti film of 00 nm and a Ti film of 150 nm by a sputtering method.

The protective insulating film 150 and the interlayer insulating film 151 may be formed of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like. In any case, it is preferable that the internal stress of the film is set as a compressive stress. Was.

Next, a silicon nitride film, a silicon oxide film,
Alternatively, using a silicon nitride oxide film, the passivation film 157 is formed to have a thickness of 50 to 500 nm (typically, 100 to 300 nm).
nm). Thereafter, when hydrogenation treatment was performed in this state, favorable results were obtained for improving the characteristics of the TFT. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect is obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 157 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later.

Thereafter, a second interlayer insulating film 158 made of an organic resin film was formed to a thickness of about 1 μm. Applicable organic resin materials include polyimide, acrylic, polyamide, polyimide amide, and BCB (benzocyclobutene)
Etc. can be used. Here, after coating on the substrate,
It was formed by sintering at 300 ° C. using a polyimide of a type that undergoes thermal polymerization. Next, in a region to be a pixel portion, the second
A light shielding film 159 was formed on the interlayer insulating film 158 of FIG. The light-shielding film 159 is a film mainly composed of one or more elements selected from Al, Ti, and Ta, and is formed to a thickness of 100 to 300 nm and is patterned into a predetermined shape. Further, a third interlayer insulating film 160 was formed thereon using an organic resin film in the same manner as the second interlayer insulating film. The thickness of the third interlayer insulating film 160 was 0.5 to 1 μm. Then, a contact hole reaching the source wiring 168 was formed in the third interlayer insulating film 160, the second interlayer insulating film 158, and the passivation film 157, and the pixel electrode 161 was provided. The pixel electrode 161 may be formed using a transparent conductive film when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is formed. Here, in order to form a transmissive liquid crystal display device, indium tin oxide (ITO) film is
It was formed to a thickness of 0 nm by a sputtering method.

Through the above steps, an active matrix substrate having a pixel portion and its driving circuit is formed on the same substrate. The driving circuit includes an n-channel TFT 163 and a p-type TFT 163.
The channel type TFT 162 is formed, and a logic circuit based on a CMOS circuit can be formed. An n-channel TFT 164 is formed in the pixel portion, and a light-shielding film 159, a third interlayer insulating film 160, and a pixel electrode 16 are formed.
1 form a storage capacitor 165.

The p-channel type TFT 162 of the driving circuit is
It has a channel formation region 133, a source region 134, and a drain region 135. n-channel TFT 163
Has a channel formation region 136, a source region 139 and a drain region 140, and LDD regions (Lov regions) 137 and 138 overlapping with the gate electrode. The n-channel TFT 164 in the pixel portion includes a channel forming region 1
41, 142, a source region 147 and a drain region 148, 149, and LDD regions (Loff) 143 to 146 which do not overlap with the gate electrode. The LDD region of the n-channel TFT of the drive circuit is provided mainly for the purpose of relaxing the high electric field near the drain to prevent the deterioration of the on-current value due to hot carrier injection. The concentration of the impurity element to be applied is 5 ×
It should have been 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . On the other hand, the LDD region of the n-channel TFT in the pixel portion is provided for the main purpose of reducing the off-current value.

The length in the channel length direction of the Lov region of the n-channel TFT of the drive circuit is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm, for a channel length of 3 to 8 μm.
m. The length in the channel length direction of the Loff region of the pixel portion is 0.5 to 3.5 μm, typically 1.50 μm.
The thickness may be 5 to 2.5 μm. In FIG. 2C, the n-channel TFT 164 in the pixel portion is completed with a double gate structure; however, a single gate structure may be used, or a multi-gate structure provided with a plurality of gate electrodes may be used.

As described above, the present invention makes it possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel portion and the driving circuit, and to improve the operation performance and reliability of the semiconductor device. We were able to. More specifically, the design of the LDD region of the n-channel TFT is made different according to each circuit specification, and the Lov region or the Loff region is appropriately provided, so that the TFT structure emphasizing measures against hot carriers on the same substrate. And T that emphasizes low off-current value
FT structure was realized.

[Embodiment 2] This embodiment will be described with reference to FIGS. 3 and 4 in which a pixel portion and a TFT of a driving circuit provided around the pixel portion are simultaneously manufactured by a method different from that in Embodiment 1.

First, the steps up to the step shown in FIG. 1B are performed in the same manner as in the first embodiment, and the gate electrodes 102 to 1 are formed on the substrate 101.
04, a gate wiring (not shown), a gate insulating film 105,
A crystalline silicon film 106 is formed, first spacer films 107 to 109 and a second spacer film 110 are provided, and impurity regions 111 to 115 to which an n-type element is added at an n ⁻ concentration. Was formed.

Then, as shown in FIG. 3A, a step of adding an impurity element imparting p-type to a region of the crystalline silicon film which becomes a source region and a drain region of the p-channel type TFT of the driving circuit. went. First, a region where an n-channel TFT is formed is formed by resist masks 301 and 30.
2 coated. Then, using the first spacer film 107 as a mask, impurity regions (p ⁺ ) 303 and 304 were formed by ion doping using diborane (B ₂ H ₆ ). The boron (B) concentration in this region was set to 1 × 10 ²¹ cm ⁻³ .

Next, as in the first embodiment, the n-channel type T
In the FT, an impurity region functioning as a source region or a drain region is formed, and an n-channel T
The step of forming the LDD region of the FT was performed. Resist masks 305 to 307 are formed, and impurity regions 308 to 311 to which an impurity element imparting n-type is added through the second spacer film 110 by ion doping.
And the second spacer film 110 and the first spacer film 108
Thus, impurity regions 312 and 313 to which an impurity element imparting n-type is added are formed. Impurity region 308-
Here, 311 is 5 × 10 ²⁰ cm in order to obtain an n ⁺ concentration.
^The impurity element was included at a concentration of ^-3 . Impurity region 312,
Here, 313 is 6 × 10 ¹⁷ cm ^{−3 in} order to obtain a concentration of n ^−.
The concentration was adjusted to

The subsequent steps were performed in the same manner as in Example 1. A protective insulating film 332 was formed as shown in FIG. 4A, and an activation step was performed by furnace annealing. After hydrogenation treatment, an interlayer insulating film 333 was formed as shown in FIG. 4B, and a first interlayer insulating film having a two-layer structure with the protective insulating film 332 was formed. Then, source wirings 334 to 336 and drain wirings 337 and 338 are formed, and the passivation film 339 and the second interlayer insulating film 3 are formed.
40 were laminated. Then, the second interlayer insulating film 340
A light-shielding film 341 is formed thereon, and a third interlayer insulating film 342,
A pixel electrode 343 connected to the drain electrode 338 was provided.

Through the above steps, the p-channel TFT 344 of the driver circuit has the channel formation region 312, the source region 313, and the drain region 314. The n-channel type TFT 345 includes a channel forming region 315, L
ov regions 316 and 317, a source region 318, and a drain region 319. N-channel TFT3 in the pixel section
46, channel forming regions 320 and 321 and Loff
Regions 322 to 325. Further, the light shielding film 34
From the first and third interlayer insulating films 342 and the pixel electrodes 343,
A storage capacitor 347 connected to the n-channel TFT 346 is formed.

[Embodiment 3] In this embodiment, a process of forming a crystalline semiconductor film to be an active layer of the TFT shown in Embodiments 1 and 2 will be described with reference to FIGS. First, 100 to 4 on a substrate (a glass substrate in this embodiment) 1101.
The gate electrodes 1102 and 1103 having a thickness of 00 nm are formed. The gate electrode is formed from a material containing one or more elements selected from Al, Ti, Ta, Mo, and W,
The pattern is formed so that the end face has a tapered shape. Although not shown, a laminated structure of the above materials may be used. For example, tantalum nitride (TaN) and Ta
It may be a two-layer structure. Further, the surface of the gate electrode may be coated with an oxide by an anodic oxidation method or the like.
The gate insulating film 1104 is formed using a silicon nitride film, a silicon oxide film, or a silicon oxynitride film, and has a thickness of 20
To 200 nm, preferably 75 to 125 nm. Then, an amorphous semiconductor film (amorphous silicon film in this embodiment) 110 having a thickness of 50 nm is formed on the gate insulating film 1104.
5 is continuously formed without opening to the atmosphere.

Next, an aqueous solution (aqueous nickel acetate solution) containing 10 ppm by weight of a catalytic element (nickel in this embodiment) is applied by spin coating to form a catalytic element-containing layer 1106 on the amorphous semiconductor film 1105. Formed over the entire surface.
The catalyst elements usable here are germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), and cobalt (C) in addition to nickel (Ni).
o), platinum (Pt), copper (Cu), and gold (Au). In this embodiment, a method of adding nickel by a spin coating method is used. However, a thin film made of a catalytic element (a nickel film in this embodiment) is formed on an amorphous semiconductor film by a vapor deposition method, a sputtering method, or the like. Means for forming may be taken. (FIG. 11A)

Next, before crystallization, at 400 to 500 ° C., 1
After performing a heat treatment process for about an hour to desorb hydrogen from the film, the temperature is 500 to 650 ° C. (preferably 550 to 570 ° C.).
C.) for 4 to 12 hours (preferably 4 to 6 hours). In this embodiment, a heat treatment is performed at 550 ° C. for 4 hours to form a crystalline semiconductor film (a crystalline silicon film in this embodiment).
1107 is formed. (FIG. 11 (B))

The active layer 110 formed as described above
7 is a catalytic element that promotes crystallization (here, nickel)
By using, a crystalline semiconductor film having excellent crystallinity can be formed. Further, in order to further enhance the crystallinity, a laser crystallization method may be used in combination. For example, a linear beam is formed using XeF excimer laser light (wavelength 308 nm), and the oscillation frequency is 5 to 50 Hz.
The crystalline semiconductor film 1107 manufactured in FIG. 11B was irradiated with an energy density of 100 to 500 mJ / cm ^{2 and an} overlap ratio of the linear beam of 80 to 98%. As a result, a crystalline semiconductor film 1108 having more excellent crystallinity could be formed.

By using the crystalline semiconductor film formed on the substrate 1101 as described above, TFTs are manufactured according to the procedure shown in Embodiments 1 and 2, and good characteristics can be obtained. The characteristics of a TFT can be typically represented by a field-effect mobility, and the characteristics of a TFT formed from a crystalline semiconductor film manufactured as in this embodiment are n-channel TFTs.
150~220cm ² / V · sec in FT, a p-channel type TFT 90~120cm ² / V · sec can be obtained,
Moreover, even when the device was continuously operated, almost no deterioration in characteristics from the initial value was observed, and excellent characteristics were obtained from the viewpoint of reliability.

[Embodiment 4] In this embodiment, another configuration of the storage capacitor connected to the n-channel TFT in the pixel portion of the active matrix substrate will be described with reference to FIGS. Here, the cross-sectional structures of FIGS. 9 and 10 are the same up to the point where the second interlayer insulating film 158 made of an organic resin film is formed in accordance with the manufacturing process described in the first embodiment. This has already been described in FIG. 1 and FIG. Therefore, in the present embodiment, description will be made focusing on only the differences from the first embodiment.

In FIG. 9A, first, after the second interlayer insulating film 158 is formed according to the steps of the first embodiment, Al,
Light shielding film 201 made of a material containing an element selected from Ta and Ti
To form Then, 30 to 150 nm (preferably 50 to 75 nm) is formed on the surface of the light shielding film 201 by anodic oxidation.
The dielectric film 202 (oxide film) having a thickness of is formed.

When forming the dielectric film 202 by the anodic oxidation method, first, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration was prepared. It consists of a 15% aqueous solution of ammonium tartrate and ethylene glycol:
It is a solution mixed in 8, ammonia water is added to this,
The pH was adjusted to be 7 ± 0.5. Then, a platinum electrode serving as a cathode was provided in the solution, the substrate on which the light-shielding film 201 was formed was immersed in the solution, and a constant (several mA to several tens mA) DC current was passed using the light-shielding film 201 as an anode. .
The voltage between the cathode and the anode in the solution changes with time as the oxide grows.However, the voltage is adjusted so that the current becomes constant, and the voltage is not maintained when the voltage reaches 150 V, or the voltage is maintained. The holding time was set to several seconds to several tens of seconds to terminate the anodizing treatment. By doing so, it is possible to form the light-shielding film 201 without going around the dielectric film to the surface in contact with the second interlayer insulating film.

In this embodiment, the dielectric film is provided only on the surface of the light-shielding film.
It may be formed by a gas phase method such as a D method or a sputtering method. Also in that case, the film thickness is preferably 30 to 150 nm (preferably 50 to 75 nm). Also, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, DL
A C (Diamond like carbon) film or an organic resin film may be used. Further, a stacked film combining these may be used.

Thereafter, the pixel electrode 203 is formed in the same manner as in the first embodiment.
To form Thus, the light shielding film 201 and the pixel electrode 203
In the region where the storage capacitor 20 overlaps with the dielectric film 202 interposed therebetween.
4 are formed.

In the structure shown in FIG. 9B, a light-shielding film 201 and a dielectric film 202 are formed in the same manner as in FIG. 9A, and then a spacer 205 made of an organic resin is formed. As the organic resin film, a film selected from polyimide, polyamide, polyimide amide, acrylic, and BCB (benzocyclobutene) can be used. Then, the spacer 205, the second
Then, the interlayer insulating film 158 and the passivation film 157 are etched to form contact holes, and the pixel electrode 206 is formed using the same material as in the first embodiment. Thus, a storage capacitor 207 is formed in a region where the light shielding film 201 and the pixel electrode 206 overlap with the oxide 202 interposed therebetween. By providing the spacer 205 in this manner, the light shielding film 201 is provided.
Short-circuit (short-circuit) generated between the pixel electrode 206 and the pixel electrode 206 can be prevented.

In the structure of FIG. 9C, a light-shielding film 201 is formed as in FIG. 9A, and a spacer 208 made of an organic resin is formed so as to cover an end of the light-shielding film 201. As the organic resin, a film selected from polyimide, polyamide, polyimide amide, acrylic, and BCB (benzocyclobutene) can be used. Next, a dielectric film 209 is formed on the exposed surface of the light shielding film 201 by an anodizing method. Note that a dielectric film is not formed in a portion in contact with the spacer 208. Then, the spacer 208 and the second
Then, the interlayer insulating film 158 and the passivation film 157 are etched to form contact holes, and the pixel electrode 210 is formed using the same material as in the first embodiment. Thus, a storage capacitor 211 is formed in a region where the light-shielding film 201 and the pixel electrode 210 overlap with each other via the oxide 209. By providing the spacer 208 in this manner, the light shielding film 201 is provided.
Short-circuit (short-circuit) generated between the pixel electrode 210 and the pixel electrode 210 can be prevented.

In FIG. 10A, first, after a second interlayer insulating film 158 is formed according to the steps of Embodiment 1, an insulating film 212 made of a material such as a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed thereon. To form Insulating film 21
2 was formed by a known film forming method, and among them, the sputtering method was preferably used. Thereafter, a light-shielding film, a dielectric film, and a pixel electrode are formed in the same manner as in FIG.
Is provided. The provision of the insulating film 212 improves the adhesion between the light-shielding film and the base, and prevents the dielectric film from forming around the interface with the light-shielding film when forming the dielectric film by anodization. it can.

In FIG. 10B, after an insulating film and a light-shielding film are similarly formed, a region of the insulating film which is not in close contact with the light-shielding film is removed by etching, and the insulating film 21 is formed so as to overlap under the light-shielding film.
4 was formed. Then, a pixel electrode 215 was provided. With such a configuration, the adhesion of the light-shielding film to the base is improved, and when the dielectric film is formed by the anodic oxidation method, the wraparound of the dielectric film at the interface with the base of the light-shielding film is prevented. In addition, the light transmittance of the pixel region where the light shielding film is formed can be improved.

The structure shown in FIG. 10 can be combined with the structure provided with the spacers shown in FIGS. 9B and 9C. Further, the configuration of this embodiment shown in FIGS. 9 and 10 can be combined with the configuration of the first embodiment or the second embodiment.

[Embodiment 5] TFTs of driving circuits provided in the pixel section and the periphery thereof described in Embodiment 1 and Embodiment 2
In a method for manufacturing an active matrix substrate including a semiconductor film serving as an active layer, an insulating film such as a gate insulating film or an interlayer insulating film and a base film, a gate electrode, a source wiring,
All of the conductive films such as the drain wiring and the pixel electrode can be formed by a sputtering method. The advantage of using the sputtering method is that DC is used for forming a conductive film or the like.
Since a (direct current) discharge method can be adopted, it is suitable for forming a uniform film on a large-area substrate. In addition, silane (SiH4), which requires great care in handling for forming a silicon-based material such as an amorphous silicon film and a silicon nitride film, is not required, and the safety of operation is ensured. Such a point can be utilized as a very merit particularly in a production site. Hereinafter, a manufacturing process using a sputtering method will be described according to the first embodiment.

The gate electrodes 102 to 104 in FIG. 1A can be easily formed by a known sputtering method using a target material such as Ta, Ti, W, and Mo. W-Mo and Ta-M
In the case of using a compound material such as o, a compound target may be similarly used. When TaN or WN is formed, it can be manufactured by appropriately adding nitrogen (N ₂ ) or ammonia (NH ₃ ) in addition to argon (Ar) in a sputtering atmosphere. In addition, Ar gas is used as a sputtering gas.
There is also a method of adding helium (He), krypton (Kr), and xenon (Xe) to control the internal stress of a film to be formed.

Silicon nitride used for gate insulating film 105
The film 105a is formed by using a silicon (Si) target.
r, N_Two, Hydrogen (H_Two), NH_ThreeIf properly mixed with the formation
Wear. Alternatively, using a silicon nitride target material
It can be formed similarly. Silicon nitride oxide film 10
5b, using a Si target, Ar, N_Two, H_Two, N _Two
It is prepared by appropriately mixing O and sputtering.

Similarly, an amorphous silicon film is produced by using a Si target and using Ar and H ₂ as a sputtering gas.
If a small amount of boron (B) is to be added to the amorphous silicon film, several tens ppm
Boron (B) of up to several thousand ppm may be added, or diborane (B ₂ H ₆ ) may be added to the sputtering gas.

A silicon oxide film used for the first spacer films 107 to 109 and the second spacer film 110 is formed by sputtering with Ar or a mixed gas of Ar and oxygen (O 2) using silicon oxide (or quartz) as a target material. Can be produced. Protective insulating film 150, interlayer insulating film 151,
The silicon nitride film, the silicon oxide film, and the silicon nitride oxide film used for the passivation film 157 may be formed as described above.

In the case of using Al for the source wirings 152 to 154 and the drain wirings 155 and 156, T
i, Si, scandium (Sc), vanadium (V),
When Cu or the like is contained in an amount of about 0.01 to 5% by weight, hillocks are effectively prevented. Al used for the light shielding film 159,
A material containing an element selected from Ta and Ti, and a pixel electrode 1
Any of ITO, ZnO, SnO _{2 and the} like used for 61 may be formed by a known sputtering method.

As described above, all of the layers other than the second interlayer insulating film 158 and the third interlayer insulating film 160 made of an organic resin can be formed by the sputtering method. The detailed experimental conditions may be appropriately determined by the practitioner.

[Embodiment 6] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 6, an orientation film 601 is formed on the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element.
A transparent conductive film 603 and an alignment film 604 were formed on the substrate 602 on the opposite side. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the pixel portion, the active matrix substrate on which the CMOS circuit is formed, and the opposing substrate are bonded to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. afterwards,
A liquid crystal material 605 was injected between both substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 6 was completed.

Next, the structure of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 7 and the top view of FIG. 7 and 8 use the same reference numerals in order to correspond to the sectional structural views of FIGS. 1 to 2 and 6.
The cross-sectional structure along the line AA ′ shown in FIG.
This corresponds to the cross-sectional view of the pixel portion shown in FIG.

The active matrix substrate includes a pixel portion 701, a scanning (gate) line driving circuit 702, and a signal (source) line driving circuit 70 formed on the glass substrate 101.
3 The pixel portion has an n-channel TFT 164
Is provided, and the driver circuit provided in the periphery is CMO
It is configured based on an S circuit. The scan (gate) line driver circuit 702 and the signal (source) line driver circuit 703 are each connected to the gate electrode 104 (connected to the gate electrode and represented by the same reference numerals in the sense that they extend and are formed) and the source line 156. Are connected to the pixel portion 701. Also, F
The PC 731 is connected to the external input / output terminal 734.

FIG. 8 is a top view showing a part (one pixel) of the pixel portion 701. The gate wiring 104 intersects an active layer therebelow via a gate insulating film (not shown). Although not shown, a source region, a drain region, an Lov region and an Loff region composed of an n ⁻ region are formed in the active layer. Reference numeral 166 denotes a contact portion between the source wiring 154 and the source region 147, and 167 denotes a contact portion between the drain wiring 156 and the drain region 149.
Denotes a contact portion between the drain wiring 156 and the pixel electrode 161. The storage capacitor 165 is an n-channel TFT 164
The light shielding film 159 and the pixel electrode 161 are formed in a region where the light shielding film 159 and the pixel electrode 161 overlap each other.

Although the active matrix type liquid crystal display device of the present embodiment has been described with reference to the structure described in the first embodiment, the active matrix type liquid crystal display device can be freely combined with any of the structures of the first to fifth embodiments. A display device can be manufactured.

[Embodiment 7] An active matrix substrate in which a pixel portion and a driving circuit manufactured by carrying out the present invention are integrally formed on the same substrate can be used for various electro-optical devices (active matrix liquid crystal display devices, active matrix (A matrix type EL display device, an active matrix type EC display device). That is, the present invention can be applied to all electronic devices incorporating these electro-optical devices as display media.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation system, a personal computer, a mobile phone, and an electronic book. Can be One example of them is shown in FIG.

FIG. 12A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention is an audio output unit 900
2. The present invention can be applied to a display device 9004 including an audio input unit 9003 and an active matrix substrate.

FIG. 12B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention provides a voice input unit 9103,
910 provided with active matrix substrate
2. It can be applied to the image receiving unit 9106.

FIG. 12C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display device 9205. The present invention can be applied to the display device 9205 including the image receiving portion 9203 and the active matrix substrate.

FIG. 12D shows a goggle type display, which includes a main body 9301, a display device 9302, and an arm 93.
03. The present invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 12E shows a rear type projector, which includes a main body 9401, a light source 9402, a display device 9403,
Polarizing beam splitter 9404, reflector 940
5, 9406 and a screen 9407. The invention can be applied to the display device 9403.

FIG. 12F shows a portable book, and the main body 95.
01, display devices 9502 and 9503, storage medium 950
4, comprising an operation switch 9505 and an antenna 9506 for displaying data stored on a mini disk (MD) or a DVD or data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 13A shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display 2402, and a speaker 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 13B shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

FIG. 14A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 14B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 14C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 14A and 14B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 14D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 14C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 14D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 14, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

Although not shown here, the present invention is also applicable to a car navigation system and a display unit of an image sensor personal computer. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using a configuration including any combination of the first to sixth embodiments.

[Embodiment 8] In this embodiment, a self-luminous display panel (hereinafter, referred to as EL display) using an electroluminescent (EL) material by applying the active matrix substrate shown in FIG. Described as device)
An example of manufacturing will be described. FIG. 15A is a top view of an EL display panel using the present invention. FIG. 15 (A)
, 2010 is a substrate, 2011 is a pixel portion, 201
Reference numeral 2 denotes a source-side drive circuit, and 2013, a gate-side drive circuit. Each drive circuit is connected to an external device via wirings 2014 and 2016 to an FPC 2017.

FIG. 15B is a cross-sectional view taken along the line AA ′ of FIG. 20A. At this time, the opposing plate 2080 is provided at least over the pixel portion, preferably over the driving circuit and the pixel portion. The opposite plate 2080 is made of a TFT and an EL with a sealing material 2019.
It is attached to an active matrix substrate on which a layer is formed. A filler (not shown) is mixed in the sealant 2019, and the two substrates are bonded to each other with substantially uniform intervals by the filler. Further, the outside of the sealant 2019 and the top and periphery of the FPC 2017 are sealed with a sealant 2081. As the sealant 2081, a material such as a silicone resin, an epoxy resin, a phenol resin, or butyl rubber is used.

As described above, when the active matrix substrate 2010 and the opposing substrate 2080 are bonded to each other with the sealant 2019, a space is formed therebetween. The space is filled with a filler 2083. This filler 20
83 also has the effect of bonding the opposing plate 2080. As the filler 2083, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), EVA (ethylene vinyl acetate), or the like can be used. Further, since the EL layer is weak to water and moisture and easily deteriorated, it is desirable to mix a desiccant such as barium oxide in the filler 2083 since the moisture absorbing effect can be maintained. Further, a passivation film 2082 formed using a silicon nitride film, a silicon oxynitride film, or the like is formed over the EL layer to prevent corrosion due to an alkali element or the like contained in the filler 2083.

A glass plate, an aluminum plate, a stainless steel plate, FRP (Fiberglass-Reinforced)
Plastics) plate, PVF (polyvinyl fluoride) film, Mylar film (trade name of DuPont), polyester film, acrylic film or acrylic plate can be used. Further, moisture resistance can be enhanced by using a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or mylar films. In this way, the EL element is in a sealed state and is isolated from the outside air.

Further, in FIG.
0, a TFT for a driving circuit (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT) 2022 and a TFT 2023 for a pixel portion are provided on a base film 2021 (here, EL Only the TFT for controlling the current to the element is shown). Of these TFTs, particularly, for an n-channel TFT, a decrease in on-current due to a hot carrier effect and an increase in Vth
In order to prevent characteristic deterioration due to shift and bias stress,
An LDD region having the configuration described in this embodiment is provided.

For example, the driving circuit TFT 2022 is
The p-channel TFT 1 of the CMOS circuit shown in FIG.
62 and an n-channel TFT 163 may be used. Further, an n-channel TFT 164 illustrated in FIG. 2C or a p-channel TFT having a structure similar to that described above may be used as the pixel portion TFT 2023.

However, in order to manufacture an active matrix substrate for manufacturing an EL display device, the pixel electrode 20 is required.
A self-light-emitting layer 2029 is formed on 27 using an EL material. The self-luminous layer 2029 is made of a known EL material (a hole injection layer,
A layered structure or a single-layered structure may be obtained by freely combining a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials. When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

The self-luminous layer 2029 is formed by a vapor deposition method using a shadow mask, an ink jet method, a dispenser method, or the like. In any case, a color display is possible by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, and any method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the self-luminous layer 2029, the cathode 2030 is formed thereon. Cathode 2030 and self-luminous layer 20
It is desirable to remove moisture and oxygen existing at the interface of No. 29 as much as possible. Therefore, it is necessary to devise a method of continuously forming the self-luminous layer 2029 and the cathode 2030 in a vacuum or forming the self-luminous layer 2029 in an inert atmosphere and forming the cathode 2030 in a vacuum without opening to the atmosphere. . In this embodiment, a multi-chamber method (cluster tool method)
By using the film forming apparatus described above, the film forming as described above can be performed.

In this embodiment, the cathode 2030 is
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1 nm-thick LiF (lithium fluoride) film is formed on the self-luminous layer 2029 by a vapor deposition method, and a 300 nm-thick aluminum film is formed thereon.
Of course, a MgAg electrode which is a known cathode material may be used. Then, the cathode 2030 is connected to the wiring 2016 in a region indicated by 2031. The wiring 2016 is the cathode 2
030 is a power supply line for applying a predetermined voltage to
FPC 20 through anisotropic conductive paste material 2032
17 is connected. A resin layer 2080 is further formed on FPC 2017 to increase the adhesive strength at this portion.

In the region shown at 2031, the cathode 20
In order to electrically connect the wiring 30 and the wiring 2016, it is necessary to form a contact hole in the interlayer insulating film 2026 and the insulating film 2028. These are at the time of etching the interlayer insulating film 2026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 2028 is etched (when an opening is formed before the EL layer is formed). The insulating film 20
When etching 28, etching may be performed all at once up to the interlayer insulating film 2026. In this case, the interlayer insulating film 20
If the same resin material is used for the insulating film 26 and the insulating film 2028, the shape of the contact hole can be improved.

The wiring 2016 is electrically connected to the FPC 2017 through a gap (but closed with a sealant 2081) between the seal 2019 and the substrate 2010. Note that although the wiring 2016 has been described here,
Other wirings 2014 and 2015 are similarly connected to the FPC 2017 under the sealing material 2018.

FIG. 21 shows a more detailed sectional structure of the pixel portion, FIG. 17A shows a top view structure, and FIG.
(B) shows. In FIG. 16A, a switching TFT 2102 provided over a substrate 2101 corresponds to FIG.
It is formed with the same structure as the n-channel TFT 164 in the pixel portion of FIG. The double gate structure has a structure in which substantially two TFTs are connected in series, and has an advantage that an off current value can be reduced. Although the double gate structure is used in this embodiment, a triple gate structure or a multi-gate structure having more gates may be used.

The current controlling TFT 2103 is the same as that shown in FIG.
The n-channel TFT 163 of the CMOS circuit shown in FIG.
It is formed using. At this time, the switching TFT 2
A drain line 2135 of 102 is electrically connected to a gate electrode 2137 of the current controlling TFT by a wiring 2136. Further, a wiring indicated by 2138 is a gate electrode 2139a, 213 of the switching TFT 2102.
9b is a gate line for electrically connecting 9b.

When the current controlling TFT 2103 and the switching TFT 2102 are hydrogenated using the method of the present invention, the field-effect mobility and the sub-threshold constant (S
Value), ON current, and other main characteristics of the TFT, and variations in characteristics of individual TFTs can be reduced, which is very effective in manufacturing an EL display element. By improving the various characteristics as described above, gradation display is facilitated, and unevenness in image display can be eliminated by reducing variation in TFT characteristics, thereby improving display quality.

In this embodiment, the current controlling TFT 21
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

As shown in FIG. 17A, the wiring which becomes the gate electrode 2137 of the current controlling TFT 2103 is in a region indicated by reference numeral 2104 in the current controlling TFT 2103.
Overlap with the drain line 2140 via an insulating film. At this time, a capacitor is formed in a region indicated by reference numeral 2104. This capacitor 2104 is a current control TFT 210
3 functions as a capacitor for holding a voltage applied to the gate. Note that the drain line 2140 is connected to a current supply line (power supply line) 2201 and a constant voltage is constantly applied.

The first passivation film 2 is formed on the switching TFT 2102 and the current control TFT 2103.
141 is provided thereon, and a planarizing film 2142 made of a resin insulating film is formed thereon. TF using the flattening film 2142
It is very important to flatten the step due to T. Since a self-light-emitting layer formed later is very thin, light emission failure may occur due to the presence of a step. Therefore,
It is preferable to planarize the pixel electrode before forming it so that the EL layer can be formed on a flat surface as much as possible.

Reference numeral 2143 denotes a pixel electrode (cathode of an EL element) made of a highly reflective conductive film, and a current control TF
It is electrically connected to the drain of T2103. As the pixel electrode 2143, a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof is preferably used. Of course, a stacked structure with another conductive film may be employed. Further, the light emitting layer 2144 is formed in a groove (corresponding to a pixel) formed by the banks 2144a and 2144b formed of an insulating film (preferably resin). Although only one pixel is shown here, R
Light emitting layers corresponding to the colors (red), G (green), and B (blue) may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. A typical polymer-based material is polyparaphenylene vinylene (PPV)
System, polyvinyl carbazole (PVK) system, polyfluorene system and the like. There are various types of PPV-based organic EL materials, for example, “H. Shenk, HB
ecker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,
“Polymers for Light Emitting Diodes”, Euro Displa
y, Proceedings, 1999, p. 33-37 "and JP-A-10-9257.
A material such as that described in Japanese Patent Publication No. 6 may be used.

As a specific light emitting layer, cyanopolyphenylene vinylene is used for a light emitting layer emitting red light, polyphenylene vinylene is used for a light emitting layer emitting green light, and polyphenylene vinylene or polyalkylphenylene is used for a light emitting layer emitting blue light. Good. Thickness is 30-150nm
(Preferably 40 to 100 nm). However, the above example is an example of an organic EL material that can be used as a light emitting layer, and there is no need to limit the invention to this.
An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a polymer material is used as the light emitting layer has been described.
A low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, the PED is formed on the light emitting layer 2145.
EL having a laminated structure provided with a hole injection layer 2146 made of OT (polythiophene) or PAni (polyaniline)
And layers. An anode 2147 made of a transparent conductive film is provided over the hole injection layer 2146. In the case of this embodiment, since the light generated in the light emitting layer 2145 is emitted toward the upper surface (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 2147 is formed, the EL element 2105 is completed. The EL element 21 referred to here
05 denotes a pixel electrode (cathode) 2143, a light emitting layer 2145,
Refers to a capacitor formed by the hole injection layer 2146 and the anode 2147. As shown in FIG.
Since 43 substantially corresponds to the area of the pixel, the entire pixel is EL
Functions as an element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 2148 is further provided on the anode 2147. As the second passivation film 2148, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 22, and has a switching TFT and a current control TFT. Then, these Ts produced using the hydrogenation method of the present invention are used.
FT exhibits extremely stable characteristics, and enables good image display in an EL display device.

FIG. 16B shows an example in which the direction of light emission from the self-luminous layer is opposite to that in FIG. 16A. Current control TFT2
601 is a p-channel type TF of the CMOS circuit of FIG.
It is formed using T162. Embodiment 1 can be referred to for the manufacturing process. In this embodiment, the pixel electrode (anode) 21
As 50, a transparent conductive film is used. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

A bank 2151a made of an insulating film is provided.
After the formation of 2151b, a light emitting layer 2152 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 2153 made of potassium acetylacetonate (denoted as acacK) and a cathode 2154 made of an aluminum alloy are formed thereon. In this case, the cathode 2
154 also functions as a passivation film. Thus, an EL element 2602 is formed. In the case of the present embodiment, the light generated in the light emitting layer 2153 is T light as indicated by the arrow.
The light is emitted toward the substrate on which the FT is formed. In the case of the structure as in this embodiment, the current controlling TFT 260
1 is preferably formed of a p-channel TFT. Such an EL display element can be applied to the semiconductor device described in Embodiment 7.

[Embodiment 9] In this embodiment, FIG.
FIG. 18 shows an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, 270
1 is a source wiring of the switching TFT 2702, 27
03 is the gate wiring of the switching TFT 2702, 2
704 is a current control TFT, 2705 is a capacitor, 2
Reference numerals 706 and 2708 denote current supply lines, and 2707 denotes an EL element.

FIG. 18A shows an example in which the current supply line 2706 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 2706. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 18B shows a current supply line 270.
8 is provided in parallel with the gate wiring 2703. Note that FIG. 18B illustrates a structure in which the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 2708 and the gate wiring 2703 can share an occupied area, the pixel portion can have higher definition.

FIG. 18C shows that a current supply line 2708 is provided in parallel with the gate wiring 2703 and two pixels are connected to the current supply line 2708 similarly to the structure of FIG.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 2708 so as to overlap with one of the gate wirings 2703. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition. FIG. 18 (B)
Although the capacitor 2705 is provided to hold the voltage applied to the gate of the current controlling TFT 2704, the capacitor 2705 can be omitted.

The current control TFT 2704 is shown in FIG.
Since the n-channel TFT of the present invention as shown in FIG. 1A is used, the semiconductor device has an LDD region provided so as to overlap with a gate electrode with a gate insulating film interposed therebetween. A parasitic capacitance generally called a gate capacitance is formed in the overlapping region. The present embodiment is characterized in that this parasitic capacitance is positively used instead of the capacitor 2705. Since the capacitance of the parasitic capacitance changes in the area where the gate electrode and the LDD region overlap, the capacitance is determined by the length of the LDD region included in the overlapping region. 18A, 18B and 18C, the capacitor 2705 can be omitted.

[0122]

According to the present invention, in a semiconductor device in which a plurality of functional circuits are formed on the same substrate (specifically, an electro-optical device in this case) according to specifications required by the functional circuits. It is possible to arrange TFTs having appropriate performance, and the operating characteristics and reliability thereof can be greatly improved.

[0123] Particularly, in the bottom-gate type or an inverted staggered TFT in which LDD regions are provided, the LDD regions of the n-channel type TFT of the pixel portion n ^- and the concentration of the Loff
By forming the pixel only, the off-state current value can be significantly reduced, which can contribute to lower power consumption of the pixel portion. Also, by forming the LDD region of the n-channel TFT of the drive circuit with n ⁻ concentration and only Lov, the current drive capability is increased, deterioration due to hot carriers is prevented, and deterioration of the ON current value is reduced. be able to.

Further, a semiconductor device having such an electro-optical device as a display medium (here, specifically, electronic equipment)
Operating performance and reliability can also be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel portion and a driver circuit.

FIG. 5 illustrates a positional relationship between a gate electrode and an LDD region.

FIG. 6 is a sectional structural view of an active matrix liquid crystal display device.

FIG. 7 is a perspective view of an active matrix liquid crystal display device.

FIG. 8 is a top view of a pixel portion.

FIG. 9 is a cross-sectional view illustrating a configuration of a storage capacitor.

FIG. 10 is a cross-sectional view illustrating a configuration of a storage capacitor.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 12 illustrates an example of a semiconductor device.

FIG. 13 illustrates an example of a semiconductor device.

FIG. 14 illustrates an example of a projector.

15A and 15B are a top view and a cross-sectional view illustrating a structure of an EL display device.

FIG. 16 is a cross-sectional view of a pixel portion of an EL display device.

FIG. 17 is a top view and a circuit diagram of a pixel portion of an EL display device.

FIG. 18 is an example of a circuit diagram of a pixel portion of an EL display device.

[Explanation of symbols]

 Reference Signs List 101 substrate 102 to 104 gate electrode 105 gate insulating film 106 crystalline silicon film 107 to 109 first spacer film 110 second spacer film 150, 332 protective insulating film 151, 333 interlayer insulating film 152 to 154, 334 to 336 source Wirings 155, 156, 337, 338 Drain wirings 157, 339 Passivation films 158, 340 Second interlayer insulating films 159, 341 Light shielding films 160, 342 Third interlayer insulating films 161, 343 Pixel electrodes

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/088 H01L 29/78 612B 27/08 331 619B (72) Inventor Shunpei Yamazaki Hase, Atsugi-shi, Kanagawa 398 Inside Semiconductor Energy Laboratory Co., Ltd.

Claims (11)

[Claims] 1. A semiconductor device having a pixel portion and a driving circuit for the pixel portion over the same substrate, wherein the pixel portion and the driving circuit have an active layer and an LDD region provided on the active layer. At least an n-channel TFT having a gate insulating film provided between the active layer and the substrate, and a gate electrode provided between the gate insulating film and the substrate; The LDD region of the n-channel TFT is disposed so as not to overlap the gate electrode of the n-channel TFT of the pixel portion. The LDD region of the n-channel TFT of the driving circuit is And the LDD region of the n-channel TFT of the driving circuit is
A semiconductor device comprising an impurity element imparting n-type at a higher concentration than an LDD region of an n-channel TFT in the pixel portion. 2. The method according to claim 1, wherein the LDD region of the n-channel TFT of the driving circuit has an n-type concentration of 2 to 10 times the LDD region of the n-channel TFT of the pixel portion. A semiconductor device, comprising an impurity element imparting the following. 3. The pixel according to claim 1, wherein an organic resin film is formed on at least the n-channel TFT in the pixel portion, and a light-shielding film formed on the organic resin film and a light-shielding film formed on the organic resin film. A capacitor is formed by a closely formed dielectric film and a pixel electrode provided so as to partially overlap the light-shielding film and connected to an n-channel TFT of the pixel portion. Semiconductor device. 4. The light-shielding film according to claim 3, wherein the light-shielding film is made of a material containing one or more kinds selected from aluminum, tantalum, and titanium, and the dielectric film is an oxide of a material forming the light-shielding film. A semiconductor device comprising: 5. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a mobile computer, a goggle type display, a projector, a mobile book, a digital camera, a car navigation, a personal computer. A semiconductor device, which is one selected from the group consisting of: 6. A method for manufacturing a semiconductor device having a pixel portion and a driver circuit for the pixel portion over the same substrate, comprising: an active layer; an LDD region of the active layer; Forming an n-channel TFT including a gate insulating film provided between the active layer and the substrate, and a gate electrode provided between the gate insulating film and the substrate. The LDD region of the n-channel TFT of the pixel portion is arranged so as not to overlap with the gate electrode of the n-channel TFT of the pixel portion. The LDD region of the n-channel TFT of the drive circuit is The LDD region of the n-channel TFT of the driving circuit is disposed so as to overlap with the gate electrode of the n-channel TFT.
A method for manufacturing a semiconductor device, comprising adding an impurity element imparting n-type at a higher concentration than an LDD region of an n-channel TFT in the pixel portion. 7. The n-type TFT according to claim 6, wherein the n-type TFT has an n-type concentration in the LDD region of the n-channel type TFT of 2 to 10 times less than that of the n-type TFT in the pixel portion. A method for manufacturing a semiconductor device, comprising adding an impurity element to be provided. 8. The TFT according to claim 6, wherein at least an n-channel TFT of said pixel portion is provided.
Forming an organic resin layer thereon, forming a light-shielding film on the organic resin, forming a dielectric film in close contact with the light-shielding film, and partially overlapping the light-shielding film. Forming a pixel electrode connected to the n-channel TFT of the pixel portion provided in the pixel portion, thereby forming a capacitor. 9. The light-shielding film according to claim 8, wherein the light-shielding film is formed of a material containing one or more of aluminum, tantalum, and titanium, and the dielectric film is formed by oxidizing a material forming the light-shielding film. A method for manufacturing a semiconductor device, comprising forming an object. 10. The method for manufacturing a semiconductor device according to claim 9, wherein said dielectric film is formed by an anodic oxidation method. 11. The semiconductor device according to claim 6, wherein the semiconductor device is a mobile phone, a video camera, a mobile computer, a goggle type display, a projector, a mobile book, a digital camera, a car navigation system,
A method for manufacturing a semiconductor device, which is one selected from a personal computer.