JP2009025453A - Display panel and its manufacture method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display panel capable of achieving excellent display image quality by allowing a light emitting element to perform light emitting operation with appropriate luminance gradation in accordance with display data, and to provide its manufacture method. <P>SOLUTION: An organic EL element OLED (pixel electrode 14 that is an anode electrode), and a capacitor Cs having a conductive layer electrically connected to the gate electrode Tr13g of a transistor Tr13 forming a pixel drive circuit DC as an electrode Eca on one side and the pixel electrode 14 of the organic EL element OLED as an electrode Ecb on the other side are provided in an EL element forming area Fpx on an upper side in a pixel forming area Rpx set on one surface side of a substrate 11, and transistors Tr11 to Tr13 forming the pixel drive circuit DC are provided in a circuit forming area Dpx on a lower side therein. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display panel and a manufacturing method thereof, and more particularly to a display panel having a light emitting element such as an organic electroluminescence element and a manufacturing method of the display panel.

  2. Description of the Related Art In recent years, as a next-generation display device following a liquid crystal display (LCD), self-luminous elements such as organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”) and light-emitting diodes (LEDs) are two-dimensionally arranged. Research and development of light-emitting element type display devices provided with such display panels have been actively conducted.

  In such a light emitting element type display device, the display response speed is faster and the viewing angle dependency is smaller than that of the liquid crystal display device, and no backlight or light guide plate is required unlike the liquid crystal display device. It has characteristics. Therefore, application to various electronic devices is expected in the future.

  In such a display device, a pixel circuit (pixel drive circuit) for causing a light emitting element (organic EL element or the like) to emit light with a desired luminance gradation for each display pixel arranged in the display panel. There is known an active matrix driving system provided with the. As this pixel circuit, one having a switching element such as one or a plurality of thin film transistors and a wiring layer is known.

  For example, Patent Document 1 discloses an active matrix drive type display device (organic EL display device) in which current is controlled by a voltage signal, and a voltage signal corresponding to image data (display data) is applied to a gate to generate an organic EL. A current control thin film transistor that supplies current to the device, a switching thin film transistor that performs switching for supplying a voltage signal corresponding to image data to the gate of the current control thin film transistor, and a voltage component corresponding to the voltage signal are held. A circuit configuration in which a capacitor is provided for each pixel is described.

JP-A-8-330600

  When the pixel circuit as described above is provided for each pixel, for example, if the formation area of each pixel is reduced due to the high definition of the display panel, the formation area of the capacitor is also limited, and the display data depends on the display data. It is impossible to secure a sufficient capacity to hold the voltage component. For this reason, the light emitting element (organic EL element or the like) cannot be operated to emit light at a desired luminance gradation, and there is a problem that display image quality is deteriorated.

  In view of the above-described problems, the present invention provides a display panel capable of realizing a good display image quality by causing a light emitting element to emit light with an appropriate luminance gradation according to display data, and a method for manufacturing the same. For the purpose.

A display panel according to claim 1 is a light emitting element;
A pair of electrodes, wherein at least one of the pair of electrodes has a transmission characteristic for at least a part of a wavelength range of light emitted by the light emitting element, and holds a voltage component according to display data; A voltage holding unit overlapping the light emitting element in a plane;
It is characterized by having.

According to a second aspect of the present invention, in the display panel according to the first aspect, the voltage holding unit is arranged on the radiation side of the light emitted from the light emitting element.
According to a third aspect of the present invention, in the display panel according to the first or second aspect, the voltage holding unit includes a transparent dielectric layer and a pair of transparent electrodes disposed so as to face each other with the dielectric layer interposed therebetween. And a capacitor structure including:
According to a fourth aspect of the present invention, in the display panel according to the first aspect, at least one of the pair of electrodes is formed of a conductive polymer material in the voltage holding portion. To do.
According to a fifth aspect of the present invention, in the display panel according to any one of the first to fourth aspects, the light emitting element includes a light emitting functional layer, a pixel electrode disposed opposite to the light emitting functional layer, and a counter electrode. Of the pair of electrodes of the voltage holding portion, the electrode formed on the light emitting element side is shared with the pixel electrode of the light emitting element.
According to a sixth aspect of the present invention, in the display panel according to the fifth aspect, at least a part of the light emitting functional layer of the light emitting element is formed of a conductive polymer material.
According to a seventh aspect of the present invention, in the display panel according to any one of the first to sixth aspects, a driving current having a predetermined current value is applied to the light emitting element based on a voltage component held in the voltage holding unit. The driving transistor is further provided, and the pair of electrodes of the voltage holding portion are connected to the gate electrode of the driving transistor and the source electrode or the drain electrode of the driving transistor, respectively.
According to an eighth aspect of the present invention, in the display panel according to the seventh aspect, one of the pair of electrodes of the voltage holding unit is formed in the same layer as the source electrode and the drain electrode of the driving transistor. It is connected to the gate electrode of the drive transistor through a layer.
A display panel according to the invention of claim 9 is a light emitting element;
A voltage corresponding to display data for emitting light from the light-emitting element, having a multilayer capacitor comprising a plurality of dielectric layers and a plurality of electrodes arranged opposite to each other with the dielectric layers interposed therebetween A voltage holding unit for holding the component;
It is characterized by having.
According to a tenth aspect of the present invention, in the display panel according to the ninth aspect, the display panel further includes a driving transistor that supplies a driving current having a predetermined current value to the light emitting element based on a voltage component held in the multilayer capacitor. The multilayer capacitor includes at least a first electrode formed in the same layer as the gate electrode of the driving transistor, and a first dielectric formed between the gate electrode of the driving transistor, the source electrode, and the drain electrode. A body layer, a second electrode formed in the same layer as the source electrode and the drain electrode of the driving transistor, a second dielectric layer formed so as to cover the driving transistor, and the second dielectric A third electrode formed on the body layer and electrically connected to the first electrode is sequentially stacked.
According to an eleventh aspect of the present invention, in the display panel according to the tenth aspect, the light emitting element includes a light emitting functional layer, and a pixel electrode and a counter electrode disposed to face each other with the light emitting functional layer interposed therebetween. The second electrode of the voltage holding unit is connected to the pixel electrode of the light emitting element.
According to a twelfth aspect of the present invention, in the display panel according to the tenth aspect, the third electrode of the voltage holding unit is applied with a power supply voltage for allowing the driving current to flow through the source-drain of the driving transistor. It is characterized in that it is formed in the same layer as the power supply wiring.
According to a thirteenth aspect of the present invention, in the display panel according to the twelfth aspect, at least the power supply wiring is formed on the driving transistor via the second dielectric layer. And
According to a fourteenth aspect of the present invention, in the display panel according to any one of the ninth to thirteenth aspects, the light emitting element and the voltage holding portion are arranged on a substrate so as not to overlap in a plane. To do.
According to a fifteenth aspect of the present invention, in the display panel according to any one of the first to fourteenth aspects, in the light emitting element, the pixel electrode is formed of a light transmissive conductive material, and the counter electrode is light reflective. It is characterized by being formed of a conductive material.
According to a sixteenth aspect of the present invention, in the display panel according to any one of the first to fourteenth aspects, in the light emitting element, the pixel electrode is formed of a light reflective conductive material, and the counter electrode is light transmissive. It is characterized by being formed of a conductive material.
According to a seventeenth aspect of the present invention, in the display panel according to any one of the first to sixteenth aspects, the display panel is formed in the same layer as an electrode on one side of the pair of electrodes of the voltage holding portion. With respect to the drive wiring layer in which the applied voltage is switched and set in accordance with the drive control, the other electrode of the pair of electrodes of the voltage holding unit is formed so as to be closer to the one electrode. It is characterized by being.
A method for manufacturing a display panel according to claim 18 includes the step of forming, on a substrate, a first electrode of a voltage holding unit that holds a voltage component corresponding to display data,
Forming a second electrode of the voltage holding unit so as to face the first electrode through a dielectric layer;
Forming a light emitting functional layer on the second electrode;
Forming a counter electrode facing the pixel electrode through the light emitting functional layer;
It is characterized by including.
According to a nineteenth aspect of the present invention, in the display panel manufacturing method according to the eighteenth aspect, the second electrode of the voltage holding portion is formed of a conductive polymer material that forms a part of the light emitting functional layer. It is characterized by.
The invention according to claim 20 is a method for manufacturing a display panel, comprising: a light emitting element; and a pixel driving circuit that supplies a predetermined driving current to the light emitting element.
Based on the first electrode of the voltage holding unit that holds a voltage component corresponding to display data on the substrate and the voltage component held in the voltage holding unit, the driving current having a predetermined current value is Simultaneously forming a gate electrode of a driving transistor to be supplied to the light emitting element;
Forming a first dielectric layer covering the first electrode of the voltage holding unit and the gate electrode of the driving transistor;
Simultaneously forming a second electrode of the voltage holding unit and a source electrode and a drain electrode of the driving transistor on the first dielectric layer;
Forming a second dielectric layer covering the second electrode of the voltage holding unit and the source electrode and the drain electrode of the driving transistor;
Forming a third electrode of the voltage holding unit electrically connected to the first electrode on the second dielectric layer;
It is characterized by including.
According to a twenty-first aspect of the invention, in the display panel according to the twentieth aspect, the step of forming the third electrode of the voltage holding unit is configured to cause the driving current to flow through a source-drain of the driving transistor. A power supply wiring to which a power supply voltage is applied is formed at the same time.

  According to the display panel and the manufacturing method thereof according to the present invention, it is possible to realize a good display image quality by appropriately causing the light emitting element to emit light according to display data.

  Hereinafter, a display panel and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments. Here, in the embodiment described below, a case where an organic EL element is applied as a light emitting element constituting a display pixel will be described.

<First Embodiment>
(Display panel)
First, a display panel (organic EL panel) and display pixels according to the present invention will be described.
FIG. 1 is a schematic plan view showing an example of a pixel arrangement state of a display panel according to the present invention, and FIG. 2 shows each display pixel (light emitting element and pixel driving circuit) two-dimensionally arranged in the display panel according to the present invention. 2 is an equivalent circuit diagram showing a circuit configuration example of FIG. In the plan view shown in FIG. 1, for convenience of explanation, only the relationship between the arrangement of pixel electrodes provided in each display pixel arranged on the display panel (substrate) and the arrangement structure of each wiring layer is shown. In order to drive the organic EL element of each display pixel to emit light, the display of the transistors and the like in the pixel driving circuit shown in FIG. 2 provided in each display pixel is omitted. Further, in FIG. 1, in order to clarify the arrangement of the pixel electrode and each wiring in the pixel formation region, it is shown hatched for convenience.

  As shown in FIG. 1, the display panel 10 according to this embodiment includes a plurality of display pixels PIX arranged in a matrix in a display area on one surface side (front side of the paper) of a transparent substrate 11 such as a glass substrate. Yes. A plurality of data lines Ld are arranged in the vertical direction of the display panel 10 (that is, in the column direction), and a plurality of selection lines Ls are arranged in the horizontal direction of the drawing (that is, in the row direction) orthogonal to the data line Ld. A plurality of power supply voltage lines (for example, anode lines) Lv are provided.

  Here, when the display device including the display panel 10 is compatible with color display, for example, display pixels that are color pixels of three colors of red (R), green (G), and blue (B), for example. PIX is repeatedly arranged in this order in the horizontal direction of the drawing, and a plurality of display pixels PIX of the same color are arranged in the vertical direction of the drawing. In this case, one set of three RGB display pixels PIX adjacent in the left-right direction constitutes one pixel. In the case of a display device including the display panel 10 having only single color light emitting color pixels, one display pixel becomes one pixel.

  In the display panel 10 that supports color display, as shown in a manufacturing method described later, when an organic EL layer is formed by applying a high molecular or low molecular organic material, for example, an insulating property is used. A bank 17 (partition wall; details will be described later) made of a material protrudes from one surface of the substrate 11 and has a planar pattern in a fence shape or a lattice shape so as to surround each formation region for each color pixel (display pixel PIX). Arranged. Thereby, a formation region (EL element formation region Fpx described later) of the organic EL element OLED in the pixel formation region Rpx is defined.

  Specifically, each display pixel PIX (or color pixel) is, for example, as shown in FIG. 2, a pixel driving circuit (corresponding to the above-described pixel circuit) DC including a plurality of transistors (thin film transistors and the like) on the substrate 11. And an organic EL element (light emitting element) OLED that emits light when a light emission driving current (driving current) generated by the pixel driving circuit DC is supplied to the pixel electrode 14 is applied. can do.

  For example, as shown in FIG. 2, the pixel drive circuit DC has a gate terminal on the selection line Ls arranged in the row direction of the display panel 10 (substrate 11), a drain terminal on the power supply voltage line Lv, and a source terminal on Transistor Tr11 connected to contact N11, transistor Tr12 having a gate terminal connected to selection line Ls, a source terminal connected to data line Ld arranged in the column direction of display panel 10, and a drain terminal connected to contact N12 A transistor (drive transistor) Tr13 having a gate terminal connected to the contact N11, a drain terminal connected to the power supply voltage line Lv, and a source terminal connected to the contact N12, and between the contact N11 and the contact N12 (between the gate and source of the transistor Tr13) ) Connected to the capacitor (voltage holding unit) Cs. Here, n-channel thin film transistors are applied to all of the transistors Tr11 to Tr13. The thin film transistor may be an amorphous silicon thin film transistor or a polysilicon thin film transistor.

The organic EL element OLED has an anode electrode (pixel electrode 14) connected to the contact N12 of the pixel drive circuit DC and a cathode electrode provided in common to a plurality of display pixels PIX arranged in a matrix on the display panel 10. A predetermined low voltage (common voltage Vcom; for example, ground potential Vgnd) is applied, for example, directly or indirectly connected to a predetermined low potential power source.
In FIG. 2, a capacitor Cs is a capacitive element additionally formed between the gate and the source in addition to the parasitic capacitance formed between the gate and the source of the transistor Tr13. Details will be described later.

  The selection line Ls connected to the pixel drive circuit DC shown in FIG. 2 is connected to a selection driver (not shown) provided around the display area of the substrate 11, and the display panel 10 has a predetermined timing. A selection signal Ssel for setting a plurality of display pixels PIX arranged in the row direction to a selected state is applied from the selection driver. The power supply voltage line Lv is connected to a power supply driver (not shown), and a predetermined power supply voltage Vsc is applied from the power supply driver to the display pixels PIX arranged in the same row at a timing synchronized with the selection signal Ssel. The data line Ld is connected to a data driver (not shown) provided around the display area of the substrate 11, and a gradation current Idata corresponding to the display data flows at a timing synchronized with the selection state of the display pixel PIX. Alternatively, the gradation voltage Vdata is supplied.

  The drive control in the display pixel PIX (display panel 10) including the pixel drive circuit DC having such a circuit configuration includes current gradation control and voltage gradation control. Here, current gradation control will be described. . First, in the write operation period, a selection signal Ssel of a selection level (on level; for example, high level) is applied from a selection driver (not shown) to the selection line Ls, and is illustrated in synchronization with the selection signal Ssel. A low-level power supply voltage Vsc is applied to a power supply voltage line (anode line) Lv from a power supply driver in which is omitted.

  In synchronization with this timing, the data driver (not shown) controls the gradation current Idata having a current value corresponding to the display data to flow through the data line Ld. That is, the data driver is a driver that controls the current value of the gradation current Idata according to the display data. In the present embodiment, the data driver is set to the power supply voltage Vsc that is a low level voltage fixed during the write operation period. On the other hand, it is assumed that the data driver lowers the potential of the data line Ld and flows the gradation current Idata having a desired current value in the direction of the data line Ld from the display pixel PIX (pixel drive circuit DC) side.

  As a result, the transistors Tr11 and Tr12 of the pixel drive circuit DC are turned on, and the low-level power supply voltage Vsc is applied to the contact N11 (the gate terminal of the transistor Tr13; one end of the capacitor Cs) and the gate of the transistor Tr13 The drain becomes equipotential, and the contact N12 (the source terminal of the transistor Tr13; the other end of the capacitor Cs) is brought to a voltage level lower than the low-level power supply voltage Vsc through the transistor Tr12 by the operation of drawing the gradation current Idata. As a result, the gate-source voltage (= drain-source voltage) of the transistor Tr13 exceeds the threshold voltage of the transistor Tr13, and the gradation current Idata set by the data driver is forcibly supplied to the transistor Tr13. Will be.

  At this time, a charge corresponding to the potential difference generated between the contacts N11 and N12 is accumulated in the capacitor Cs and held (charged) as a voltage component. The amount of accumulated charge is automatically set according to the current value of the gradation current Idata flowing between the drain and source of the transistor Tr13 during the write operation, that is, under the control of the data driver. At this time, since the low-level power supply voltage Vsc is set to be equal to or lower than the common voltage Vcom (ground potential Vgnd) applied to the cathode terminal (counter electrode 16), the organic EL element OLED has a forward bias voltage. Is not applied, the light emission drive current does not flow through the organic EL element OLED during the write operation, and the light emission operation is not performed.

  Next, in the light emission operation period, a selection signal Ssel of a non-selection level (off level; for example, low level) is applied from the selection driver to the selection line Ls, and a voltage applied from the power supply driver to the power supply voltage line Lv. Switches to the high level power supply voltage Vsc. In synchronism with this timing, the operation of extracting the gradation current Idata by the data driver is stopped.

  As a result, the transistors Tr11 and Tr12 are turned off, the application of the power supply voltage Vsc to the contact N11 is interrupted, and the application of the voltage level resulting from the operation of drawing the gradation current Idata to the contact N12 is interrupted. Therefore, the capacitor Cs holds the charge accumulated in the write operation described above.

In this manner, the capacitor Cs holds the charge (charge voltage) accumulated during the write operation, whereby the potential difference between the contacts N11 and N12 (between the gate and the source of the transistor Tr13) is held. A state is maintained in which Tr13 can flow a current having a current value corresponding to the current value of gradation current Idata. In addition, the power source voltage line Lv has a voltage level higher than the common voltage Vcom (ground potential Vgnd), and the drain-source potential difference is sufficiently high so that the current flowing through the transistor Tr13 becomes a saturation current during the light emission operation period. When the power supply voltage Vsc having a predetermined voltage value is applied, the transistor Tr13 has a current value of the gradation current Idata that flows during the writing operation due to the potential difference between the gate and the source due to the charge accumulated during the writing operation. A corresponding light emission driving current is passed through the organic EL element OLED in the forward bias direction, and the organic EL element OLED emits light with a luminance according to the current value of the gradation current Idata and thus the display data.
Then, desired image information can be displayed by repeatedly performing such a series of drive control operations on all the display pixels PIX two-dimensionally arranged on the display panel 10, for example, sequentially for each row.

Next, the device structure of the display panel according to the present embodiment will be described in detail.
FIG. 3 is a plan layout diagram illustrating an example of display pixels applicable to the display panel according to the present embodiment. Here, the layer in which each transistor, wiring, and the like of the pixel driving circuit DC are formed is mainly shown. 4 is an IVA-IVA line in the display pixel PIX having the planar layout shown in FIG. 3 (in this specification, as a symbol corresponding to the Roman numeral “4” shown in FIG. FIG. 5 is a schematic cross-sectional view showing a cross-section along the line IV in FIG. 3, and FIG. 5 is a VB-VB line (shown in FIG. 3 in this specification) in the display pixel PIX having the planar layout shown in FIG. FIG. 5 is a schematic cross-sectional view showing a cross section along “V” as a symbol corresponding to the Roman numeral “5” for convenience. In FIG. 3, hatching is shown for convenience in order to clarify the planar shapes of the electrodes and wiring layers of each circuit element.

  Specifically, the display pixel PIX (color pixel) shown in FIG. 2 extends from the center of the drawing to the upper part in the pixel formation region Rpx set on one surface side of the substrate 11, for example, as shown in FIG. In the region (upper region; EL element formation region Fpx), the organic EL element OLED (only the pixel electrode 14 serving as the anode electrode of the organic EL element OLED is shown) and the gate of the transistor Tr13 that forms the pixel drive circuit DC A capacitor Cs having a conductive layer electrically connected to the electrode Tr13g as one side electrode Eca and the pixel electrode 14 of the organic EL element OLED as the other side electrode Ecb is provided. In the formation region Dpx), transistors Tr11 to Tr13 that form the pixel drive circuit DC are provided.

  In the present embodiment, in the pixel formation region Rpx, the region below the EL element formation region Fpx and the circuit formation region Dpx (the edge region below the planar layout) is arranged in the row direction (the horizontal direction in the drawing). The selection line Ls and the power supply voltage line Lv are arranged in parallel so as to extend to the left edge region of the pixel formation region Rpx in the column direction (up and down in the drawing) so as to be orthogonal to the lines Ls and Lv. The data line Ld is arranged so as to extend in the direction).

  Here, for example, as shown in FIG. 3, the data line Ld is provided below the selection line Ls and the power supply voltage line Lv (on the substrate 11 side), and forms the gate electrodes Tr11g to Tr13g of the transistors Tr11 to Tr13. Contact hole CH11 formed in the gate insulating film 12 (see FIGS. 4 and 5) formed on the gate electrodes Tr11g to Tr13g and formed thereon by patterning the gate metal layer for forming the gate metal layer. Is connected to the source electrode Tr12s of the transistor Tr12. The gate metal layer is made of aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), Zinc (Zn), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), It is an opaque material having a thickness of 10 nm to 5 μm, preferably 20 nm to 50 μm, including platinum (Pt), gold (Au) alone or a compound or alloy containing it.

  Further, as shown in FIGS. 3 to 5, the selection line Ls and the power supply voltage line Lv are provided in the same layer above the data line Ld, and the source electrodes Tr11s to Tr13s and drain electrodes Tr11d to Tr11d of the transistors Tr11 to Tr13. By patterning the source and drain metal layers for forming Tr13d, the source electrodes Tr11s to Tr13s and the drain electrodes Tr11d to Tr13d are formed in the same process. The source and drain metal layers are made of aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu ), Zinc (Zn), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W ), Platinum (Pt), gold (Au) alone or a compound or alloy containing the same, an opaque material having a film thickness of 10 nm to 5 μm, preferably 20 nm to 50 μm.

  Further, as shown in FIG. 5, the selection line Ls is connected to the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12 through a contact hole CH12 provided in the gate insulating film 12, and the power supply voltage line Lv is shown in FIG. As shown, the drain electrodes Tr11d and Tr13d of the transistors Tr11 and Tr13 are integrally formed.

  Each of the transistors Tr11 to Tr13 forming the pixel driving circuit DC has a well-known field effect type thin film transistor structure. For example, as shown in FIGS. 3 to 5, the gate electrodes Tr11g to Tr11g formed on the substrate 11, respectively. Tr13g and the semiconductor layer SMC formed on the gate insulating film 12 covering the gate electrodes Tr11g to Tr13g and corresponding to the gate electrodes Tr11g to Tr13g, and the channel of the semiconductor layer SMC This is an inverted stagger structure having source electrodes Tr11s to Tr13s and drain electrodes Tr11d to Tr13d formed so as to extend on both sides.

  Note that silicon oxide or silicon nitride for preventing etching damage to the semiconductor layer SMC in the manufacturing process is formed on the channel of the semiconductor layer SMC in which the source electrode and the drain electrode of the transistors Tr11 to Tr13 are arranged to face each other. A channel protective layer (block layer) BL is formed, and an ohmic connection between the semiconductor layer SMC and the source and drain electrodes is formed on both sides of the channel of the semiconductor layer SMC where the source electrode and the drain electrode are in contact with each other. An impurity layer OHM for realization is formed. The gate electrodes Tr11g to Tr13g of the transistors Tr11 to Tr13 are all formed by patterning the same gate metal layer, and the source electrodes Tr11s to Tr13s and the drain electrodes Tr11d to Tr13d of the transistors Tr11 to Tr13 are all the same source. The drain metal layer is formed by patterning.

  More specifically, as shown in FIGS. 3 to 5, the transistor Tr11 includes a gate electrode Tr11g provided on the gate insulating film 12 so as to correspond to the circuit configuration of the pixel drive circuit DC shown in FIG. The drain electrode Tr11d is integrally formed with the power supply voltage line Lv together with the drain electrode Tr13d of the transistor Tr13, and the source electrode Tr11s is connected to the selection line Ls arranged in the row direction via the contact hole CH12. It is connected to the gate electrode Tr13g of the transistor Tr13 through a contact hole CH13 provided in the gate insulating film 12.

  The transistor Tr12 has a gate electrode Tr12g connected to the selection line Ls via a contact hole CH12 provided in the gate insulating film 12, and a source electrode Tr12s provided via a contact hole CH11 provided in the gate insulating film 12. The drain electrode Tr12d is connected to the data line Ld, and is formed integrally with the source electrode Tr13s of the transistor Tr13.

  The transistor Tr13 is connected to the source electrode Tr11s of the transistor Tr11 through the contact hole CH13 in which the gate electrode Tr13g is provided in the gate insulating film 12, and to the capacitor Cs through the contact hole CH14 provided in the gate insulating film 12. The source electrode Tr13s is integrally formed with the drain electrode Tr12d of the transistor Tr12, and is the electrode Ecb on the other side (contact N12 side) of the capacitor Cs. The drain electrode Tr13d is connected to the pixel electrode 14 and formed integrally with the power supply voltage line Lv.

  The capacitor Cs has one electrode Eca connected to the gate electrode Tr13g of the transistor Tr13 via a contact hole CH14 provided in the gate insulating film 12, and the other electrode connected to the source electrode Tr13s of the transistor Tr13. An electrode Ecb (pixel electrode 14) and a dielectric layer including an interlayer insulating film 13 located between the electrode Eca and the electrode Ecb are provided.

The organic EL element OLED is provided on the interlayer insulating film 13 and protrudes from the substrate 11 and a pixel electrode (for example, an anode electrode) 14 connected to the drain electrode Tr12d of the transistor Tr12 and the source electrode Tr13s of the transistor Tr13. A hole transport layer (carrier transport layer) 15a formed in the EL element forming region Fpx defined by the bank 17 made of an insulating material (surrounded by the bank 17 and exposing the upper surface of the pixel electrode 14); An organic EL layer (light emitting functional layer) 15 composed of an electron transporting light emitting layer (carrier transport layer) 15b and a counter electrode (for example, a cathode) composed of a single planar electrode (solid electrode) provided in common to each display pixel PIX. Electrode) 16 are sequentially laminated. The organic EL element OLED emits light with luminance according to the current value (or current density) of the current flowing through the organic EL layer 15.
Since the periphery of the EL element formation region Fpx is surrounded by the bank 17 in all directions, the data line Ld, the selection line Ls, the power supply voltage line Lv, and the transistors Tr11 to Tr13 are covered with the bank 17. For this reason, the bank 17 reduces the influence of the parasitic capacitance due to the counter electrode 16.

Here, the display panel 10 according to the present embodiment has a bottom emission type light emitting structure in which light emitted from the organic EL layer 15 is emitted in the direction of the substrate 11 (downward in FIGS. 4 and 5). The pixel electrode 14 (the electrode Ecb on the other side of the capacitor Cs), the interlayer insulating film 13, the electrode Eca on the one side of the capacitor Cs, the gate insulating film 12 and the substrate 11 have a wavelength range of light emitted from the organic EL layer 15. On the other hand, the counter electrode 16 is formed of a film structure or a film quality having a reflection characteristic with respect to at least a part of a wavelength range of light emitted from the organic EL layer 15. For example, the pixel electrode 14 (electrode Ecb) and the electrode Eca are tin-doped indium oxide (ITO) or zinc-doped indium oxide (Indium).
Zinc Oxide (IZO) or other transparent electrode material is used. The gate insulating film 12 and the interlayer insulating film 13 are preferably made of silicon nitride or the like, and the substrate 11 is preferably made of glass.

  In addition, as a transparent electrode material applicable to the pixel electrode 14 (electrode Ecb) and the electrode Eca, a thin film having a transmittance of about 70% or more with respect to the peak wavelength of each organic EL layer 15 can be formed. It is preferable that a sufficient luminance can be obtained. Further, as shown in FIGS. 4 and 5, the counter electrode 16 extends not only on the EL element formation region Fpx of each display pixel PIX but also on the bank 17 that defines the EL element formation region Fpx. Is provided.

  The bank 17 is formed so as to have a planar pattern in a fence shape or a lattice shape at least in a region including a boundary between a plurality of display pixels PIX (color pixels) arranged two-dimensionally on the display panel 10. Here, in the present embodiment, as shown in FIG. 3, in the pixel formation region Rpx of each display pixel PIX, the pixel drive circuit DC is provided in a region below the EL element formation region Fpx (circuit formation region Dpx). Transistors Tr11 to Tr13 to be formed are disposed, and a data line Ld, a selection line Ls, and a power supply voltage line Lv are disposed in a region between the EL element formation regions Fpx of each display pixel PIX. Therefore, as shown in FIGS. 4 and 5, the bank 17 covers the wiring layers such as the transistors Tr11 to Tr13 and the data lines Ld, the selection lines Ls, and the power supply voltage lines Lv in the circuit formation region Dpx. For example, it is formed by laminating a resin layer made of a photosensitive resin material so as to protrude continuously from.

  Thereby, the region surrounded by the bank 17 is a coating region (EL element formation region Fpx) of the organic compound material when forming the organic EL layer 15 (the hole transport layer 15a and the electron transporting light emitting layer 15b) in the manufacturing process. ). Note that a sealing layer 18 is formed on the entire area of the substrate 11 on which the pixel driving circuit DC, the organic EL element OLED, and the bank 17 are formed as shown in FIGS. Furthermore, a sealing substrate made of a glass substrate or the like may be bonded so as to face the substrate 11. When forming the organic EL layer 15, it is preferable that at least the surface of the bank 17 exhibits liquid repellency with respect to a solution or suspension solvent containing an organic compound material that becomes the organic EL layer 15.

  In such a display panel 10, in a pixel driving circuit DC including functional elements such as transistors Tr11 to Tr13 and a capacitor Cs, and wiring layers such as a data line Ld, a selection line Ls, and a power supply voltage line Lv, the data line Ld is interposed. A light emission drive current having a predetermined current value based on the gradation current Idata corresponding to the display data supplied in this way flows between the drain and source of the transistor Tr13, and the transistor Tr13 (source electrode Tr13s) passes through the organic EL element OLED. By being supplied to the pixel electrode 14, the organic EL element OLED of each display pixel PIX emits light with a desired luminance gradation according to the display data.

  At this time, in the display panel 10 shown in the present embodiment, the pixel electrode 14 has light transmission characteristics and the counter electrode 16 has light reflection characteristics (that is, the organic EL element OLED has bottom emission). The light emitted from the organic EL layer 15 of each display pixel PIX is directly transmitted through the pixel electrode 14 (electrode Ecb) and the electrode Eca having light transmission characteristics or opposed to each other having light reflection characteristics. The light is reflected by the electrode 16, passes through the substrate 11, and is emitted to the other surface side of the substrate 11, which is the visual field side (downward in FIGS. 4 and 5).

  In the present embodiment, a display panel (organic EL element) having a bottom emission type light emitting structure has been described. However, the present invention is not limited to this, and the pixel electrode 14 (electrode) having light reflection characteristics is not limited thereto. Ecb), and the counter electrode 16 having light reflection characteristics is applied, and the light emitted from the organic EL layer 15 is directly or directly through the counter electrode 16 having light transmission characteristics, or the pixel electrode having light reflection characteristics. 14 is a top emission type that is emitted to one side of the substrate 11 (display panel 10) (upward in FIGS. 4 and 5) without passing through the substrate 11 on which the organic EL element OLED is formed. A light emitting element having a light emitting structure may be applied.

  Further, in the organic EL element OLED shown in the present embodiment, the case where the organic EL layer 15 includes the hole transport layer 15a and the electron transport light emitting layer 15b has been described, but the present invention is not limited thereto. For example, only the hole transporting / electron transporting light emitting layer may be used, the hole transporting light emitting layer and the electron transporting layer may be used, or a carrier transporting layer may be appropriately interposed between them. It may be a combination.

  Further, in the display panel shown in the present embodiment, the case where the pixel electrode 14 is the anode electrode of the organic EL element OLED has been described. However, the present invention is not limited to this and is a cathode electrode. There may be. In this case, in the organic EL layer 15, the carrier transport layer in contact with the pixel electrode 14 may be an electron transport layer.

(Display panel manufacturing method)
Next, a method for manufacturing a display panel according to this embodiment will be described.
6 to 8 are process cross-sectional views illustrating an example of a display panel manufacturing method according to this embodiment. Here, each part (transistor Tr13, organic EL element OLED, capacitor Cs, power supply voltage line Lv) of the cross section along the IVA-IVA line and the cross section of the display panel along the VB-VB line shown in FIGS. ) Will be described with reference to the plan layout shown in FIG. 3 and the cross-sectional structures shown in FIGS. 4 and 5 as appropriate.

  In the display panel manufacturing method described above, first, as shown in FIGS. 6A to 6C, each display pixel PIX set on one surface side (upper surface side in the drawing) of a transparent substrate 11 such as a glass substrate is used. In the circuit formation region Dpx of the pixel formation region Rpx, the transistors Tr11 to Tr13 and the data line Ld of the above-described pixel drive circuit (see FIGS. 2 and 3) DC are formed.

  Specifically, after forming a gate metal layer on the transparent substrate 11 and patterning the gate metal layer as shown in FIGS. 3 and 6A, the gate electrodes Tr11g to Tr13g and the display are displayed. After the data lines Ld extending in the column direction of the panel 10 (vertical direction in FIG. 3) are formed at the same time, the gate insulating film 12 is formed over the entire area of the substrate 11. Thereafter, the gate insulating film 12 is etched to expose the contact hole CH11 from which the upper surface of the data line Ld is exposed, the contact hole CH12 from which the upper surface of a part of the conductive layer integrally formed with the gate electrodes Tr11g and Tr12g is exposed, the gate Contact holes CH13 and CH14 are formed in which a part of the upper surface of the conductive layer integrally formed with the electrode Tr13 is exposed.

  Next, as shown in FIG. 6B, the gate insulating film 12 is continuously covered with a semiconductor film to be the semiconductor layer SMC made of amorphous silicon or the like and an insulating film such as silicon nitride to be the channel protective layer BL. After the formation, the insulating film and the semiconductor film are appropriately patterned, and an insulating film that becomes a semiconductor layer SMC and an insulating film that becomes a channel protective layer BL is formed on the gate insulating film 12 in a region corresponding to each of the gate electrodes Tr11g to Tr13g. After sequentially forming the films, the upper layer is patterned to form the channel protective layer BL.

Next, after coating an n ⁺ layer serving as the impurity layer OHM for ohmic connection on both ends of the semiconductor layer SMC corresponding to each of the transistors Tr11 to Tr13, patterning is performed together with the film serving as the semiconductor layer SMC to form the impurity layer OHM and the semiconductor layer SMC is formed. Thereafter, the source electrodes Tr11s to Tr13s and the drain electrodes Tr11d to Tr13d are formed via the impurity layers OHM corresponding to the transistors Tr11 to Tr13, and the power supply voltage extends in the row direction (left and right direction in FIG. 3) of the display panel 10. The line Lv and the selection line Ls are formed simultaneously.

  Here, the source electrodes Tr11s to Tr13s, the drain electrodes Tr11d to Tr13d, the selection line Ls, and the power supply voltage line Lv are formed by forming the source and drain metal layers on the substrate 11 and then patterning the source and drain metal layers. Formed simultaneously.

  As a result, as shown in FIGS. 2 and 3, the source electrode Tr11s of the transistor Tr11 is connected to the gate electrode Tr13g of the transistor Tr13 through the contact hole CH13 formed in the gate insulating film 12, and the source electrode Tr12s of the transistor Tr12 is connected. Is connected to the data line Ld through the contact hole CH11 formed in the gate insulating film 12, and the gate electrode Tr11g of each of the transistors Tr11 and Tr12 is connected to the selection line Ls through the contact hole CH12 formed in the gate insulating film 12. Connected to Tr12g.

  Next, as shown in FIG. 3, the EL element formation region Fpx of the pixel formation region Rpx of each display pixel PIX on the gate insulating film 12 has a rectangular planar pattern and is made of ITO, IZO, or the like. An electrode Eca on one side of the capacitor Cs (having light transmission characteristics) made of a transparent electrode material is formed.

As a result, as shown in FIGS. 2 and 3, the electrode Eca on one side of the capacitor Cs is connected to the gate electrode Tr13g of the transistor Tr13 via the contact hole CH14 formed in the gate insulating film 12.
Next, as shown in FIG. 6C, after forming an interlayer insulating film 13 covering the entire region of the substrate 11, a contact hole CH15 is formed in which a part of the upper surface of the source electrode of the transistor Tr13 is exposed.

Next, as shown in FIG. 7A, on the interlayer insulating film 13, the EL element formation region Fpx of each display pixel PIX has a rectangular shape corresponding to the electrode Eca as shown in FIG. A pixel electrode that has a planar pattern and is made of a transparent electrode material such as ITO or IZO (having light transmission characteristics), is an electrode Ecb on the other side of the capacitor Cs, and is also an anode electrode of the organic EL element OLED 14 is formed.
As a result, as shown in FIGS. 2, 3, and 5, the pixel electrode 14 (electrode Ecb) is connected to the drain electrode Tr12d of the transistor Tr12 and the source electrode of the transistor Tr13 through the contact hole CH15 formed in the interlayer insulating film 13. Connected to Tr13s.

  Next, a resin layer film made of, for example, a photosensitive polyimide resin material is formed so as to cover the entire area of the substrate 11, and the resin film is subjected to exposure and development processing. As shown in FIG. 5, a bank 17 for defining an EL element formation region Fpx of each display pixel PIX is formed around each EL element formation region Fpx. As a result, the upper surface of the pixel electrode 14 is exposed in a region (EL element formation region Fpx) surrounded by the bank 17 of each display pixel PIX.

  Next, after cleaning the substrate 11 with pure water, the surface of the pixel electrode 14 exposed to each EL element formation region Fpx defined by the bank 17 by performing, for example, oxygen plasma treatment or UV ozone treatment will be described later. It becomes lyophilic with respect to an organic compound-containing liquid such as a hole transporting material or an electron transporting light emitting material used in the step of forming the organic EL layer 15. Further, as necessary, the surface of the bank 17 is selectively made liquid repellent with respect to the organic compound-containing liquid.

  In this way, the bank 17 defines the organic EL element OLED formation region (EL element formation region Fpx) of each display pixel PIX, and the substrate 11 is subjected to a lyophilic process (and further a liquid repellent process) to be described later. Even in the case of forming a light emitting layer (electron transporting light emitting layer 15b) of the organic EL layer 15 by applying a solution (including a dispersion) of the light emitting material in FIG. 2, between the adjacent display pixels PIX (color pixels). The light emitting material is not mixed, and color mixing between adjacent color pixels can be prevented.

  Note that “liquid repellency” used in the present embodiment refers to an organic compound-containing liquid containing a hole transport material to be a hole transport layer, which will be described later, and an electron transport light-emitting material to be an electron transport light-emitting layer. When the contact angle is measured by dropping an organic compound-containing liquid or an organic solvent used in these solutions onto a substrate or the like, the contact angle is defined as a state where the contact angle is 50 ° or more. In addition, “lyophilic” as opposed to “liquid repellency” is defined as a state in which the contact angle is 40 ° or less in the present embodiment.

  Next, an inkjet method in which the organic compound-containing liquid is discontinuously discharged as a plurality of droplets to a predetermined position on the EL element formation region Fpx of each display pixel PIX, or the organic compound-containing liquid is discharged as a continuous solution Applying the nozzle coating method or the like in the same step while applying or applying the solution or dispersion of the hole transport material, followed by heating and drying to form the hole transport layer 15a. Subsequently, an ink-jet method or a nozzle coating method is applied to the hole-transporting layer 15a while applying or applying a solution or dispersion of the electron-transporting light-emitting material, followed by heating and drying to emit electron-transporting light. Layer 15b is formed. Thereby, as shown in FIG. 8A, the organic EL layer 15 composed of the hole transport layer 15a and the electron transport light emitting layer 15b is laminated on the pixel electrode.

  Specifically, as an organic compound-containing liquid containing an organic polymer-based hole transport material, for example, a polyethylenedioxythiophene / polystyrenesulfonic acid aqueous solution (PEDOT / PSS; polyethylenedioxythiophene PEDOT which is a conductive polymer) and a dopant A dispersion liquid in which polystyrene sulfonic acid PSS is dispersed in an aqueous solvent) is applied onto the pixel electrode 14, and the stage on which the substrate 11 is placed in a nitrogen atmosphere is set to several tens of degrees Celsius or higher and a hole transport material. The organic polymer-based hole transport material is formed on the pixel electrode 14 by heating and drying at a temperature sufficiently lower than the decomposition temperature of the material or a temperature that irreversibly changes to remove the residual solvent. Fixing is performed to form a hole transport layer 15a which is a carrier transport layer.

  Here, since the surface of the pixel electrode 14 is lyophilic with respect to the organic compound-containing liquid (PEDOT / PSS) by the lyophilic process described above, the EL element formation region Fpx defined by the bank 17 is used. The organic compound-containing liquid applied to the layer spreads in a sufficiently familiar manner in the region (on the pixel electrode 14). On the other hand, by setting the bank 17 sufficiently higher than the liquid level of the organic compound-containing liquid (PEDOT / PSS) to be applied, the organic compound is contained in the EL element formation region Fpx of the adjacent display pixel PIX. Liquid leakage and overcoming can be prevented.

  Further, as an organic compound-containing liquid containing an organic polymer-based electron-transporting light-emitting material, for example, a conjugated double bond polymer such as polyparaphenylene vinylene-based or polyfluorene-based or a light-emitting material including a low-molecular material is appropriately used as an aqueous solvent. Alternatively, a solution dissolved or dispersed in an organic solvent such as tetralin, tetramethylbenzene, mesitylene, or xylene is applied onto the hole transport layer 15a, and the stage is heated in a nitrogen atmosphere to perform a drying treatment, and a residual solvent. Is removed to fix the electron transporting light emitting material of an organic polymer type on the hole transporting layer 15a, thereby forming the electron transporting light emitting layer 15b which is a carrier transporting layer and also a light emitting layer.

  Also in this case, the organic compound-containing liquid applied to the EL element formation region Fpx defined by the bank 17 is sufficiently familiar and spreads in the region (on the hole transport layer 15a), while the bank 17 Since it has liquid repellency with respect to the organic compound-containing liquid, it is possible to prevent the organic compound-containing liquid from leaking out and getting over the EL element forming region Fpx of the adjacent display pixel PIX.

  Thereafter, as shown in FIG. 8B, the organic EL layer 15 (the hole transport layer 15a and the electron transport layer) has light reflection characteristics on the substrate 11 including at least the EL element formation region Fpx of each display pixel PIX. A counter electrode (for example, a cathode electrode) 16 is formed so as to face each pixel electrode 14 in common via the luminescent layer 15b). Here, as shown in FIGS. 4, 5, and 8 (b), the counter electrode 16 is not only a region facing the pixel electrode 14 but also a bank 17 that defines an EL element formation region of each display pixel PIX. Formed as a single conductive layer (planar electrode; solid electrode) extending to the top, for example, an electron injection layer having a low work function such as calcium, barium, lithium, and indium, and aluminum (Al) and chromium (Cr) A film structure in which a thin film having a high work function made of an alloy of silver (Ag), palladium silver (AgPd), or the like can be applied.

Next, after the counter electrode 16 is formed, a sealing layer 18 made of a silicon oxide film, a silicon nitride film, an aluminum oxide inorganic film, a polymer film such as polyimide, a composite thereof, or the like is formed on the entire surface of the substrate 11. By using the CVD method or the like, the display panel 10 having a cross-sectional structure (bottom emission type light emitting structure) as shown in FIGS. 4 and 5 is completed. In addition to the sealing layer 18 or in place of the sealing layer 18, a sealing lid or a sealing substrate may be bonded to the substrate 11 using UV curing or thermosetting adhesive. Good.
The manufacturing method described above is merely an example, and it is needless to say that the process order, various conditions, and the like may be changed as necessary.

  As described above, in the display panel according to the present embodiment, the organic EL element OLED (current-controlled light emitting element) provided in the display pixel PIX arranged on the substrate 11 and the organic EL element OLED emit light. A capacitor Cs (voltage holding unit) that defines a current value of a light emission drive current supplied when operating is disposed so as to overlap in a plane (that is, laminated in a cross section), and the organic EL element OLED The pixel electrode 14 and the electrode Ecb on the other side of the capacitor Cs are shared (shared) by a single conductive layer. Further, in the panel structure, the capacitor Cs is disposed on the side from which the light emitted from the organic EL element OLED is emitted (viewing side; in the present embodiment, the substrate 11 side), and a pair of electrodes Eca facing the capacitor Cs, Both Ecb are formed by a conductive layer made of a transparent electrode material (ITO or the like).

  Accordingly, even when the display panel 10 is made high definition and the size (formation area) of the display pixel PIX is reduced, the organic EL element is maintained while maintaining the pixel aperture ratio (area of the EL element formation region Fpx) sufficiently large. Since the capacitance of the capacitor Cs that affects the light emission characteristics of the OLED can be secured sufficiently large, it is possible to realize a good display image quality by causing the light emitting element to perform a light emission operation at an appropriate luminance gradation according to display data. .

  Further, the display panel and the manufacturing method thereof according to the present embodiment have a panel structure in which the electrode Ecb on the other side of the capacitor Cs and the pixel electrode 14 of the organic EL element OLED are shared. A conductive layer (electrode) shared by the film and the patterning step can be formed, and the manufacturing process can be simplified and the number of steps can be reduced.

  That is, as described above, in a display panel applied to an active matrix driving type display device, in order to cause each light-emitting element (organic EL element OLED) to emit light with a desired luminance gradation for each display pixel, 1 to A pixel driving circuit including a plurality of switching elements (transistors Tr11 to Tr13), a voltage holding unit (capacitor Cs), and a wiring layer to which various control signals are applied (data line Ld, selection line Ls, power supply voltage line Lv, etc.) Has a panel structure.

  Since the components (transistors Tr11 to Tr13, capacitors Cs, wiring layers, etc.) in such display pixels are generally formed by using opaque electrode materials or conductive materials, the number of components is large. In such a case, when the size of the display pixel is reduced, the aperture ratio of the display pixel is lowered. Here, even when the pixel aperture ratio is lowered, deterioration in display image quality can be suppressed by increasing the light emission luminance per unit area of the light emitting element. In this case, however, the light emitting element (organic EL element) The current density of the current flowing in the pixel increases, the deterioration of the light emitting material is accelerated (that is, the driving life is shortened), and the voltage efficiency is deteriorated by applying a high voltage to the display pixel (pixel driving circuit). Have a problem.

  Therefore, in the present embodiment, the light emitting element (organic EL element OLED) and the voltage holding unit (capacitor Cs) provided in the display pixel (pixel forming region Rpx) are planarly overlapped on the same region (in cross section). By arranging them in a stacked manner, a sufficiently high pixel aperture ratio can be maintained, so that the current density can be suppressed, the life of the light emitting element can be extended, and the capacity of the voltage holding portion can be secured sufficiently large. Even if a voltage fluctuation of a signal or the like occurs in the pixel drive circuit DC, the displacement of the voltage held by the voltage holding unit can be suppressed, so that more accurate gradation display is possible.

  When the operational effects of this embodiment are specifically verified, in each color pixel which is the display pixel PIX having the planar layout as shown in FIG. 3, for example, the horizontal dimension of the pixel formation region Rpx of each color pixel (left and right in the drawing) (Direction) is 106 μm, the vertical dimension (vertical direction in the drawing) is 318 μm, and red, green, and blue color pixels are arranged in the left-right direction, thereby forming one square pixel of 318 μm × 318 μm in length and width. As transistor sizes, for example, the channel length L11 of the transistor Tr11 is 7 μm, the channel width W11 is 40 μm, the channel length L12 of the transistor Tr12 is 7 μm, the channel width W12 is 40 μm, the channel length L13 of the transistor Tr13 is 7 μm, and the channel width W13 is 350 μm. When arranged in the circuit formation region Dpx, and arranged in the edge region of the pixel formation region Rpx with the wiring width of the selection line Ls being 20 μm and the wiring width of the power supply voltage line Lv being 30 μm, as in this embodiment. By arranging the organic EL element OLED and the capacitor Cs so as to overlap in a plane, each display pixel PIX can secure a light emitting region (opening size) having a horizontal dimension of 90 μm and a vertical dimension of 188 μm, and the pixel forming region Rpx Realizing a high pixel aperture ratio of about 50% of the area (pixel area) It came.

  In the display panel having the bottom emission type light emitting structure, the capacitor Cs is planarly overlapped with the view side (light emission side) of the organic EL element OLED, and the pixel electrode 14 of the organic EL element OLED is connected to the other side of the capacitor Cs. By using a panel structure in which a pair of electrodes Eca and Ecb facing each other of the capacitor Cs are made of a transparent electrode material such as ITO, the electrode Eca and Ecb of the capacitor Cs are used. When a silicon nitride film having a film thickness of 300 nm is used as an interlayer insulating film between them and the dielectric constant is 7, the capacitance of the capacitor Cs is 3.5 pF, and a sufficiently large capacitance is secured while maintaining the above-described high pixel aperture ratio. Thus, the organic EL element OLED was allowed to emit light with an appropriate luminance gradation according to the display data.

  For comparison, when a conventional panel structure in which the capacitor Cs is arranged so as not to overlap with the organic EL element OLED is verified, for example, under the same dimensional condition as the specific example described above, the pixel of each display pixel PIX Of the area (pixel formation region Rpx having a horizontal dimension of 106 μm × vertical dimension of 318 μm), a region excluding the edge region where the circuit formation region Dpx and the wiring layer are disposed (that is, a region approximately 50% of the pixel formation region Rpx) It is necessary to arrange the organic EL element OLED and the capacitor Cs so as not to overlap in a plane (pixel area × 50% = light emitting area area + capacitor area). In this case, even if a capacitor having a capacitance (for example, 2.0 pF) smaller than the capacitance (3.5 pF) of the capacitor Cs shown in the specific example is formed, the capacitor area occupies 30% of the pixel area. In other words, it was found that the light emitting region area is the remaining 20% of the pixel area (pixel aperture ratio 20%), which is much lower than that of the present embodiment (pixel aperture ratio 50% or more).

<Another example of the first embodiment (part 1)>
Next, another configuration example (part 1) of the display panel according to the first embodiment described above will be described. Here, since the pixel arrangement state of the display panel and the circuit configuration of each display pixel are the same as those of the first embodiment described above, specific features of this configuration example will be described with reference to FIGS. 1 and 2 as appropriate. I will explain it.

  FIG. 9A is a plan layout diagram showing a part of a display pixel applicable to a display panel according to another configuration example of the first embodiment. FIG. 9B is a plan layout diagram of FIG. IXC-IXC line (in this specification, “IX” is used for convenience as a symbol corresponding to the Roman numeral “9” shown in FIG. 9A) in the display pixel PIX having the planar layout shown. It is a schematic sectional drawing which shows the cross section along. In FIG. 9A, hatching is shown for convenience in order to clarify the planar shapes of the electrodes and wiring layers of each circuit element. Also, the same or equivalent reference numerals are given to the same components as those in the first embodiment described above, and the description thereof is simplified or omitted.

  In the display panel according to the first embodiment described above, as shown in FIG. 4, the gate electrode Tr13g of the transistor Tr13 provided in the pixel drive circuit DC and the electrode Eca on one side of the capacitor Cs are formed as a gate insulating film. 12 shows a device structure that is directly connected to the contact hole CH14 formed in FIG.

  That is, in the first embodiment described above, the electrode materials for forming the gate electrodes Tr11g to Tr13g and the data line Ld of the transistors Tr11 to Tr13, the source electrodes Tr11s to Tr13s and the drain electrodes Tr11s to Tr13s of the transistors Tr11 to Tr13, Although the electrode material for forming the selection line Ls and the power supply voltage line Lv was not specifically shown, the gate electrodes Tr11g to Tr13g and the data line Ld have at least the upper surface (surface) with low resistance and corrosion resistance such as chromium and titanium. A step of forming contact holes CH11 to CH14 in the gate insulating film 12 by applying an electrode structure formed of a conductive metal material or an alloy containing these as a main component, or patterning the ITO film to form a capacitor Electric power on one side of Cs In the step of forming the pole Eca, it is possible to suppress the phenomenon that the gate electrodes Tr11g to Tr13g are subjected to etching damage or a battery reaction (described later in detail) in which the contact resistance between the electrode gate electrode Tr13g and the electrode Eca increases. Can do.

  On the other hand, when a metal material having low corrosion resistance against the influence of an etchant for patterning the ITO film, such as aluminum or aluminum alloy, is applied to the gate insulating film 12 as the gate electrodes Tr11g to Tr13g and the data line Ld. In the step of forming the contact holes CH11 to CH14 and the step of forming the electrode Eca on one side of the capacitor Cs made of ITO or the like, the gate electrodes Tr11g to Tr13g are subjected to etching damage or a reduction reaction occurs on the ITO surface. There is a problem that an oxidation reaction occurs on the aluminum surface of the gate electrode Tr13g in contact with the ITO to increase the resistance, and a battery reaction that is a phenomenon in which aluminum corrodes and peels off occurs.

  Therefore, in this configuration example, for example, as shown in FIGS. 9A and 9B, the gate electrode Tr13g of the transistor Tr13 and the electrode Eca on one side of the capacitor Cs are formed on the gate insulating film 12. It has a device structure electrically connected via a contact metal (contact layer) CM1 formed so as to fill the hole CH14.

  Here, the contact metal CM1 is formed by patterning the source and drain metal layers for forming the source electrodes Tr11s to Tr13s and the drain electrodes Tr11d to Tr13d of the transistors Tr11 to Tr13, thereby forming the source electrodes Tr11s to Tr13s and the drain electrodes Tr11d. It is formed in the same process as that of Tr13d.

Next, a method for manufacturing the display panel according to this configuration example described above will be described.
FIG. 10 is a process cross-sectional view illustrating an example of a method for manufacturing a display panel according to this configuration example. Here, a part of the cross-sectional structure of the display panel taken along lines IXC-IXC and VB-VB shown in FIGS. 9B and 5 (transistor Tr13, organic EL element OLED, capacitor Cs, power supply voltage line Lv). The manufacturing process will be described with reference to FIG. 9A and will be described with reference to the planar layout shown in FIG. Note that the description of the manufacturing process equivalent to that of the above-described first embodiment is simplified or omitted.

  In the manufacturing method of the display panel according to this configuration example, first, the gate electrodes Tr11g to Tr13g and the data lines Ld are simultaneously formed by patterning a gate metal layer made of aluminum or the like formed on the transparent substrate 11, A gate insulating film 12 is formed over the entire substrate 11. Thereafter, a transparent electrode layer such as an ITO film is formed on the gate insulating film 12, and the transparent electrode layer is wet-patterned with an etchant. As shown in FIG. 3, the pixel formation region Rpx of each display pixel PIX is formed. In the EL element formation region Fpx, an electrode Eca on one side of the capacitor Cs having a rectangular planar pattern and having light transmission characteristics is formed. At this time, since the contact holes CH11 to CH14 are not yet formed, the gate electrode Tr13g and the like are not exposed. Next, in the gate insulating film 12, a resist mask is coated in a region other than the region where the contact holes CH11 to CH14 are formed, and the gate insulating film 12 is etched to form contact holes CH11 to CH14, as shown in FIG. Then, the gate electrode Tr13g and the like are exposed.

  Next, as shown in FIG. 10B, on the gate insulating film 12 in the region corresponding to each of the gate electrodes Tr11g to Tr13g, a semiconductor layer SMC made of amorphous silicon or the like and a channel protective layer BL made of silicon nitride or the like. Are stacked. Thereafter, source electrodes Tr11s to Tr13s and drain electrodes Tr11d to Tr13d are formed on both sides of the channel of the semiconductor layer SMC corresponding to the transistors Tr11 to Tr13 via the impurity layer OHM, and a selection line Ls and a power supply voltage line Lv, In addition, the contact metal CM1 extending from the contact hole CH14 to the above-described electrode Eca is formed at the same time.

Here, the source electrodes Tr11s to Tr13s, the drain electrodes Tr11d to Tr13d, the selection line Ls and the power supply voltage line Lv, and the contact metal CM1 are formed on the substrate 11 after the source and drain metal layers are formed. It is formed simultaneously by patterning the metal layer.
Thus, as shown in FIGS. 9A and 9B, the gate electrode Tr13g of the transistor Tr13 is provided on one side of the capacitor Cs through the contact metal CM1 filled in the contact hole CH14 formed in the gate insulating film 12. The electrode Eca is electrically connected.

  Next, as shown in FIG. 10C, after forming the interlayer insulating film 13 covering the entire area of the substrate 11, a contact hole CH15 in which the upper surface of the source electrode Tr13s of the transistor Tr13 is exposed is formed. Thereafter, as in the manufacturing method shown in the first embodiment (see FIGS. 7 and 8), the capacitor connected to the drain electrode Tr12d of the transistor Tr12 and the source electrode Tr13s of the transistor Tr13 through the contact hole CH15. The pixel electrode 14 which is the electrode Ecb on the other side of Cs and also the anode electrode of the organic EL element OLED is formed.

  Next, a bank 17 made of a resin material is formed to define an EL element formation region Fpx of each display pixel PIX, and then the exposed surface of the pixel electrode 14 is made lyophilic, and the surface of the bank 17 is further formed as necessary. A liquid repellency treatment is selectively performed, and then, an organic EL layer 15 including a hole transport layer 15a and an electron transport light emitting layer 15b is stacked on the pixel electrode 14 exposed in the EL element formation region Fpx.

  Then, a counter electrode (for example, a cathode electrode) 16 having light reflection characteristics is formed on the substrate 11 including the EL element formation region Fpx of each display pixel PIX, and a sealing layer 18 is formed over the entire area of one surface of the substrate 11. Thus, the display panel 10 having the cross-sectional structure (bottom emission type light emitting structure) as shown in FIG. 9B is completed.

  Even when a metal material such as aluminum is used for the gate electrodes Tr11g to Tr13g and the data line Ld by such a display panel and a method for manufacturing the display panel, the display panel and the manufacturing method can be made from ITO or the like that is electrically connected through the contact hole CH14. As a result, it is possible to prevent an increase in resistance due to a battery reaction, peeling of the electrode, or the like between the electrode Eca on one side of the capacitor Cs to be obtained. In addition to realizing display characteristics, it is possible to improve the reliability of the display panel (display device) by extending the lifetime of the components of the pixel drive circuit DC.

  In this configuration example, as shown in FIGS. 9A and 9B, only in the contact hole CH14 that electrically connects the gate electrode Tr13g of the transistor Tr13 and the electrode Eca on one side of the capacitor Cs. The case where the contact metal CM1 is formed has been described. However, the present invention is not limited to this. The source Tr13s of the transistor Tr13 and the electrode on the other side of the capacitor Cs that is also the pixel electrode 14 of the organic EL element OLED shown in FIG. A similar connection structure may also be applied to the contact hole CH15 for electrically connecting Ecb and the connection part between other conductive layers.

<Another example of the first embodiment (part 2)>
Next, still another configuration example (No. 2) of the display panel according to the first embodiment described above will be described. Here, since the pixel arrangement state of the display panel, the circuit configuration of each display pixel, and the planar layout are the same as those of the first embodiment described above, the features of this configuration example are described with reference to FIGS. The part will be specifically described.

  FIG. 11 is a schematic cross-sectional view showing a cross section taken along the line IVA-IVA in the display pixel PIX having the planar layout shown in FIG. 3, and FIG. 12 is a diagram in the display pixel PIX having the planar layout shown in FIG. It is a schematic sectional drawing which shows the cross section along a VB-VB line. In addition, about the structure equivalent to 1st Embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified or abbreviate | omitted.

  In the display panel according to the first embodiment described above, as shown in FIG. 5, it is the electrode Ecb on the other side of the capacitor Cs provided in the pixel drive circuit DC and also the anode electrode of the organic EL element OLED. The device structure in which the pixel electrode 14 made of ITO or the like is connected to the source electrode Tr13s of the transistor Tr13 through the contact hole CH15 formed in the interlayer insulating film 13 is shown. In this configuration example, the other of the capacitor Cs is shown. The side electrode Ecb has a device structure in which a conductive layer made of a conductive polymer material having light transmission characteristics is applied instead of the above-described pixel electrode 14 made of a transparent electrode material such as ITO.

  Specifically, as shown in FIGS. 11 and 12, the first implementation described above is formed on the interlayer insulating film 13 in a region corresponding to the electrode Eca on one side of the capacitor Cs formed on the gate insulating film 12. Organic compound containing PEDOT which is a conductive polymer material for forming the hole transport layer 15a of the organic EL layer 15 without having the pixel electrode 14 made of a transparent electrode material such as ITO as shown in the embodiment A transparent conductive layer, which is formed by directly applying and drying the containing liquid, is formed integrally with the hole transport layer 15a, whereby the function of the pixel electrode 14 which is also the electrode Ecb on the other side of the capacitor Cs described above. It has a device structure that can also be used as a device.

  That is, the hole transport layer 15a and the electron transporting light emitting layer are provided on the interlayer insulating film 13 in the region corresponding to the electrode Eca on one side of the capacitor Cs without having the pixel electrode 14 shown in the first embodiment. The organic EL layer 15 formed by laminating 15b is directly formed, and the source electrode Tr13s of the transistor Tr13 is connected via the contact hole CH15 formed in the interlayer insulating film 13 by extending a part of the hole transport layer 15a. Connected directly to.

Next, a method for manufacturing the display panel according to this configuration example described above will be described.
13 and 14 are process cross-sectional views illustrating an example of a method for manufacturing a display panel according to this configuration example. Here, a part of the cross-sectional structure (transistor Tr13, organic EL element OLED, capacitor Cs, power supply voltage line Lv) of the display panel shown in FIGS. 11 and 12 is extracted to show the manufacturing process, and the plane shown in FIG. This will be described with reference to the layout as appropriate. Note that the description of the manufacturing process equivalent to that of the first embodiment described above (see FIGS. 6 to 8) is simplified or omitted.

  In the display panel manufacturing method according to this configuration example, the gate electrodes Tr11g to Tr13g and the data line Ld are first formed on the transparent substrate 11 at the same time as in the first embodiment, and then the entire region of the substrate 11 is formed. Then, the gate insulating film 12 is formed so as to cover it, and then the gate insulating film 12 is etched to form contact holes CH11 to CH14 in predetermined regions.

  Next, a semiconductor layer SMC and a channel protective layer BL are stacked on the gate insulating film 12 in a region corresponding to each of the gate electrodes Tr11g to Tr13g, and then the impurity layers OHM are provided on both sides of the channel of each semiconductor layer SMC. The source electrodes Tr11s to Tr13s and the drain electrodes Tr11d to Tr13d are formed, and the selection line Ls and the power supply voltage line Lv are simultaneously formed.

  As a result, the source electrode Tr11s of the transistor Tr11 is connected to the gate electrode Tr13g of the transistor Tr13 via the contact hole CH13, the source electrode Tr12s of the transistor Tr12 is connected to the data line Ld via the contact hole CH11, and the selection line Ls is The transistors Tr11 and Tr12 are connected to the gate electrodes Tr11g and Tr12g through the contact holes CH12.

  Next, after coating a transparent electrode material such as ITO on the gate insulating film 12 and in the contact hole CH14, a resist mask is provided and patterned with an etchant to form an electrode Eca on one side of the capacitor Cs, and contact An interlayer insulating film 13 that covers the entire area of the substrate 11 is formed as shown in FIG. 13A after being connected to the gate electrode Tr13g of the transistor Tr13 through the hole CH14.

  Next, as shown in FIG. 13B, a part of the interlayer insulating film 13 in the EL element formation region Fpx is etched to form a contact hole CH15 in which the upper surface of the source electrode Tr13s of the transistor Tr13 is exposed. Next, a bank 17 made of a resin material is formed to define an EL element formation region Fpx of each display pixel PIX.

  Next, the EL element formation region Fpx is subjected to a lyophilic process, and the surface of the bank 17 is subjected to a liquid repellency process as necessary. Then, as shown in FIG. 13C, the EL element formation area defined by the bank 17 A hole transport layer 15a that functions as the pixel electrode (anode electrode) 14 of the organic EL element OLED and also functions as the electrode Ecb on the other side of the capacitor Cs is formed on Fpx. Here, the hole transport layer 15a is connected to the drain electrode Tr12d of the transistor Tr12 and the source electrode Tr13s of the Tr13 through the contact hole CH15.

  Next, as shown in FIG. 14A, an electron transporting light emitting layer 15b is laminated on the hole transporting layer 15a in the EL element formation region Fpx, and the hole transporting layer 15a and the electron transporting light emitting layer 15b are formed. Then, as shown in FIG. 14B, a counter electrode (for example, a cathode electrode) having light reflection characteristics on the substrate 11 including the EL element formation region Fpx of each display pixel PIX is formed. 16 and further, the sealing layer 18 is formed, whereby the display panel 10 having a cross-sectional structure as shown in FIGS. 11 and 12 is completed.

  With such a display panel and a manufacturing method thereof, the interlayer insulating film 13 in the region corresponding to the electrode Eca on one side of the capacitor Cs without forming the pixel electrode 14 made of ITO or the like as the electrode Ecb on the other side of the capacitor Cs. A hole transport layer 15a to be the organic EL layer 15 is directly formed thereon, and functions as the electrode Ecb on the other side of the capacitor Cs (voltage holding unit) and as the pixel electrode 14 of the organic EL element OLED (light emitting element). (That is, having a panel structure in which the hole transport layer 15a of the organic EL element OLED, the pixel electrode 14 and the electrode Ecb on the other side of the capacitor Cs are shared). Simplification can simplify the manufacturing process. Since the organic EL layer 15 has a property of transmitting at least part of the light emission of the organic EL layer 15, the light of the organic EL element OLED can be emitted from the substrate 11 via the electrode Eca, and the pixel electrode 14 The transmission characteristics can be improved as much as possible.

  In this configuration example, as shown in FIGS. 11 and 12, the function of the pixel electrode 14 of the organic EL element OLED which is also the electrode Ecb on the other side of the capacitor Cs is made to be highly conductive having light transmission characteristics. The device structure provided to the hole transport layer 15a, which is a conductive layer made of a molecular material, has been described. However, the present invention is not limited to this, and the electrode Eca on one side of the capacitor Cs is also connected to the hole transport layer 15a. Similarly, a conductive layer made of a conductive polymer material having light transmission characteristics may be applied.

<Second Embodiment>
Next, a second embodiment of the display panel according to the present invention will be described. Here, since the pixel arrangement state of the display panel and the circuit configuration of each display pixel are the same as those of the first embodiment described above, the present embodiment will be described with reference to FIGS. 1 and 2 as appropriate in the following description. The characteristic part of the form will be specifically described.

(Display panel)
FIG. 15 is a plan layout diagram illustrating an example of display pixels applicable to the display panel according to the present embodiment. Here, the layer in which each transistor, wiring, and the like of the pixel driving circuit DC are formed is mainly shown. 16 is an XVID-XVID line in the display pixel PIX having the planar layout shown in FIG. 15 (in this specification, as a symbol corresponding to the Roman numeral “16” shown in FIG. FIG. 6 is a schematic cross-sectional view showing a cross section along “XVI”. In FIG. 15, hatching is shown for convenience in order to clarify the planar shapes of the electrodes and wiring layers of each circuit element.

  In the first embodiment described above, for the display pixel PIX (organic EL element OLED and pixel driving circuit DC) having the circuit configuration shown in FIG. 2, as shown in FIGS. 3 to 5, the organic EL element OLED is used. The capacitor Cs is provided on the lower layer side (substrate 11 side) of the organic EL element OLED (light emission) while maintaining the pixel aperture ratio sufficiently large by arranging both of them in a planar manner (that is, by laminating in a cross section). In the second embodiment, the capacitor structure outside the EL element formation region Fpx is shown. However, in the second embodiment, the capacitor Cs (voltage holding unit) that affects the light emission characteristics of the element is secured. It has a panel structure that can secure a sufficiently large capacity while disposing Cs.

  Specifically, for example, as shown in FIG. 15, in a pixel formation region Rpx set on one surface side of the substrate 11, an organic EL element OLED (an organic EL element in the drawing) is provided in an upper region (EL element formation region Fpx) of the drawing. On the other hand, transistors Tr11 to Tr13 and a capacitor Cs that form a pixel driving circuit DC are provided in a lower region (circuit formation region Dpx) of the OLED. On the circuit formation region Dpx, a selection line Ls and a power supply voltage line Lv are arranged in parallel so as to extend in the row direction (the left-right direction in the drawing), and the edge region on the left side in the drawing has a column direction ( A data line Ld is arranged so as to extend in the vertical direction of the drawing.

  Here, for example, as shown in FIG. 15, the data line Ld is provided below the selection line Ls and the power supply voltage line Lv (on the substrate 11 side), and the source electrodes of the transistors Tr11 to Tr13 are formed on the gate insulating film 12. By patterning the source and drain metal layers for forming Tr11s to Tr13s and drain electrodes Tr11d to Tr13d, the source electrodes Tr11s to Tr13s and the drain electrodes Tr11d to Tr13d are formed in the same process.

  Further, as shown in FIGS. 15 and 16, the selection line Ls and the power supply voltage line Lv are provided on the interlayer insulating film 13 covering the transistors Tr11 to Tr13 forming the data line Ld and the pixel driving circuit DC. By patterning a single wiring metal layer, it is formed in the same layer in the same process. Further, as will be described later, the selection line Ls is connected to the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12 through a contact hole CH22 provided in the gate insulating film 12 and the interlayer insulating film 13, and the power supply voltage line Lv is The transistors Tr11 and Tr13 are connected to the drain electrodes Tr11d and Tr13d via contact holes CH21 provided in the interlayer insulating film 13.

  Each of the transistors Tr11 to Tr13 forming the pixel driving circuit DC has a field effect type thin film transistor structure. As shown in FIGS. 15 and 16, gate electrodes Tr11g to Tr13g formed on the substrate 11, respectively, A semiconductor layer SMC formed in a region corresponding to each of the gate electrodes Tr11g to Tr13g via the gate insulating film 12, and source electrodes Tr11s to Tr13s and drain electrodes formed to extend at both ends of the semiconductor layer SMC Tr11d to Tr13d.

  As in the first embodiment described above, the channel protection layer BL is formed on the semiconductor layer SMC of each of the transistors Tr11 to Tr13, and on the semiconductor layer SMC where the source electrode and the drain electrode are in contact with each other, An impurity layer OHM is formed. The gate electrodes Tr11g to Tr13g of the transistors Tr11 to Tr13 are all formed by patterning the same gate metal layer, and the source electrodes Tr11s to Tr13s and the drain electrodes Tr11d to Tr13d are all made of the same source and drain metal layers. It is formed by patterning.

  In the transistor Tr11, the gate electrode Tr11g is connected to the selection line Ls via a contact hole CH22 provided in the gate insulating film 12 and the interlayer insulating film 13, and the drain electrode Tr11d is formed integrally with the drain electrode Tr13d of the transistor Tr13. The source electrode Tr11s is connected to the power supply voltage line Lv through a contact hole CH21 provided in the interlayer insulating film 13, and the source electrode Tr11s is connected to the gate electrode of the transistor Tr13 through a contact hole CH23 provided in the gate insulating film 12. It is connected to the electrode Eca on one side (contact N11 side) of the Tr 13g and the capacitor Cs.

  In the transistor Tr12, the gate electrode Tr12g is integrally formed with the gate electrode Tr11g of the transistor Tr11, and is connected to the selection line Ls via the contact hole CH22 provided in the gate insulating film 12 and the interlayer insulating film 13. The source electrode Tr12s is formed integrally with the data line Ld, and the drain electrode Tr12d is formed integrally with the source electrode Tr13s of the transistor Tr13 and the electrode Ecb on the other side (contact N12 side) of the capacitor Cs.

  In the transistor Tr13, the gate electrode Tr13g is integrally formed with the electrode Eca on one side of the capacitor Cs, and is connected to the source electrode Tr11s of the transistor Tr11 through a contact hole CH23 provided in the gate insulating film 12. The source electrode Tr13s is formed integrally with the drain electrode Tr12d of the transistor Tr12, and is connected to the electrode Ecb on the other side of the capacitor Cs and the pixel electrode 14 of the organic EL element OLED provided on the gate insulating film 12. The drain electrode Tr13d is connected to the power supply voltage line Lv through a contact hole CH21 provided in the interlayer insulating film 13.

  The capacitor Cs includes one electrode (first electrode) Eca formed integrally with the gate electrode Tr13g of the transistor Tr13 and the other electrode Ecb formed integrally with the source electrode Tr13s of the transistor Tr13. Extending opposite to each other via the gate insulating film (first dielectric layer) 12, and the other electrode (second electrode) Ecb, the gate insulating film 12, and the interlayer insulating film 13. The upper-layer side electrode (third electrode) Ecx connected to the gate electrode Tr13g of the transistor Tr13 through the contact hole CH24 provided in is opposed to the interlayer insulating film (second dielectric layer) 13 The multilayer capacitor structure is formed so as to extend. Here, the electrode Ecx on the upper layer side of the capacitor Cs is formed by patterning a single wiring metal layer for forming the selection line Ls and the power supply voltage line (power supply wiring) Lv, thereby selecting the selection line Ls and the power supply voltage line Lv. Are formed in the same layer in the same process.

  That is, in the display panel according to the present embodiment, as the capacitor Cs provided in the pixel drive circuit DC of each display pixel PIX, a capacitive component having the gate insulating film 12 overlapping between the electrode Eca and the electrode Ecb as a dielectric layer, and A capacitor having a laminated structure composed of an electrode Ecx connected to the electrode Eca and a capacitive component having an interlayer insulating film 13 overlapping between the electrodes Ecb as a dielectric layer, whereby only a pair of electrodes face each other Compared to a capacitor having a structure, a sufficiently large capacitance can be formed in the same region.

  Further, the organic EL element OLED is formed on the gate insulating film 12 and protrudes from the substrate 11 and a pixel electrode (for example, an anode electrode) 14 connected to the drain electrode Tr12d of the transistor Tr12 and the source electrode Tr13s of the transistor Tr13. The organic EL layer 15 including the hole transport layer 15a and the electron transport light emitting layer 15b formed in the EL element formation region Fpx defined by the bank 17 made of the insulating material formed, and provided in common to each display pixel PIX. The counter electrode 16 made of a single flat electrode (solid electrode) is sequentially laminated.

  Here, also in the display panel 10 according to the present embodiment, as in the first embodiment described above, in the case of having a bottom emission type light emitting structure, the pixel electrode 14 and the gate insulating film 12 are made of light. The counter electrode 16 is formed with a film structure or film quality that has transmission characteristics and light reflection characteristics. On the other hand, in the case of having a top emission type light emitting structure, the pixel electrode 14 has a light reflection characteristic and the counter electrode 16 has a film structure or film quality having a light transmission characteristic.

  Similarly to the first embodiment described above, the bank 17 is formed in a region including a boundary between display pixels PIX two-dimensionally arranged on the display panel 10 so as to have a fence-like or grid-like plane pattern, In particular, in the present embodiment, as shown in FIG. 16, transistors Tr11 to Tr13 and capacitors arranged in a region (circuit formation region Dpx) other than the EL element formation region Fpx of each display pixel PIX (pixel formation region Rpx). Cs, the selection line Ls, the power supply voltage line Lv, and the like are covered, and the data line Ld is covered.

  In such a pixel drive circuit DC, a light emission drive current having a predetermined current value corresponding to display data is generated and supplied from the transistor Tr13 (source electrode Tr13s) to the pixel electrode 14 of the organic EL element OLED. Thus, the organic EL element OLED of each display pixel PIX emits light with a desired luminance gradation corresponding to the display data.

(Display panel manufacturing method)
Next, a method for manufacturing a display panel according to this embodiment will be described.
17 to 19 are process cross-sectional views illustrating an example of a display panel manufacturing method according to this embodiment. Here, the manufacturing process of the cross-sectional structure of the display panel taken along the line XVID-XVID shown in FIG. 16 will be described with reference to the plane layout shown in FIG. 15 as appropriate. Note that the description of the manufacturing process equivalent to that of the above-described first embodiment is simplified or omitted.

  In the manufacturing method of the display panel according to the present embodiment, first, as shown in FIG. 17A, the gate metal layer formed on the transparent substrate 11 is patterned to pattern the gate electrodes Tr11g to Tr11g of the transistors Tr11 to Tr13. The Tr 13g and the electrode Eca on one side of the capacitor Cs are formed simultaneously. Here, the electrode Eca on one side of the capacitor Cs is formed integrally with the gate electrode Tr13g of the transistor Tr13.

  Thereafter, as shown in FIG. 17B, after covering and forming the gate insulating film 12 over the entire area of the substrate 11, by patterning the transparent electrode layer made of ITO or the like formed on the gate insulating film 12, As shown in FIG. 15, a pixel electrode 14 having a rectangular planar pattern and light transmission characteristics and serving as an anode electrode of the organic EL element OLED is formed.

  Next, as shown in FIG. 17C, the semiconductor layer SMC and the channel protective layer BL are stacked on the gate insulating film 12 in the region corresponding to each of the gate electrodes Tr11g to Tr13g, and the gate insulating film 12 is formed. Is etched to form a contact hole CH23 in which the upper surface of the gate electrode Tr13g is exposed, and then the source electrodes Tr11s to Tr13s and the both ends of the channel of the semiconductor layer SMC corresponding to the transistors Tr11 to Tr13 through the impurity layer OHM. The drain electrodes Tr11d to Tr13d, the data line Ld, and the electrode Ecb on the other side of the capacitor Cs are formed.

  Here, the source electrodes Tr11s to Tr13s, the drain electrodes Tr11d to Tr13d, the data line Ld, and the electrode Ecb on the other side of the capacitor Cs are formed on the substrate 11 after the source and drain metal layers are formed. Are simultaneously formed by patterning.

  As a result, as shown in FIGS. 15 and 16, the source electrode Tr11s of the transistor Tr11 is connected to the gate electrode Tr13g of the transistor Tr13 through the contact hole CH23, and the drain electrode Tr12d of the transistor Tr12 and the source electrode of the transistor Tr13 are connected. A part of the Tr 13s extends to the pixel electrode 14 and is connected thereto. In addition, the electrode Eca on one side and the electrode Ecb on the other side of the capacitor Cs are formed to extend opposite to each other with the gate insulating film 12 interposed therebetween.

  Next, as shown in FIG. 18A, after forming an interlayer insulating film 13 covering the entire region of the substrate 11, the interlayer insulating film 13 is etched to expose the upper surface of the drain electrode Tr13d of the transistor Tr13. In addition to forming CH21, the interlayer insulating film 13 and the gate insulating film 12 are etched to expose the upper surface of the electrode Eca on one side of the capacitor Cs, and the upper surfaces of the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12 A contact hole CH22 is formed through which is exposed. Here, in the etching process for forming each contact hole, the interlayer insulating film 13 in the EL element formation region Fpx of each display pixel PIX is simultaneously etched to expose the upper surface of the pixel electrode 14.

  Next, as shown in FIG. 18B, by forming a wiring metal layer on the substrate 11 and patterning the wiring metal layer, the upper layer side electrodes of the selection line Ls, the power supply voltage line Lv, and the capacitor Cs are formed. Ecx is formed simultaneously. As a result, the power supply voltage line Lv is connected to the drain electrode Tr13d of the transistor Tr13 through the contact hole CH21, the selection line Ls is connected to the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12 through the contact hole CH22, and The electrode Ecx on the upper layer side of the capacitor Cs is connected to the electrode Eca on one side of the capacitor Cs through the contact hole CH24.

  Here, in the contact holes CH22 and CH24 formed through the interlayer insulating film 13 and the gate insulating film 12, for example, the contact holes CH22 and CH24 are filled and formed as shown in FIG. 18B. An electrical connection between different layers may be performed via the contact metal CM2 (illustration of the contact metal filled and formed in the contact hole CH22), and one of the electrodes Ecx may be used without using the contact metal CM2. The portion may be embedded in the contact hole CH24 and directly connected to the electrode Eca.

  Next, as shown in FIG. 19A, after a bank 17 made of a resin material is formed to define an EL element formation region Fpx of each display pixel PIX, the surface of the pixel electrode 14 is lyophilic, and further necessary. Accordingly, the surface of the bank 17 is subjected to a lyophobic treatment, and then, as shown in FIG. 19B, the hole transport layer 15a and the electron transporting light emitting layer 15b are formed on the pixel electrode 14 exposed in the EL element formation region Fpx. The organic EL layer 15 to be formed is laminated.

  Next, after forming the counter electrode 16 having light reflection characteristics and also serving as a cathode electrode on the substrate 11 including the EL element formation region Fpx of each display pixel PIX, the sealing layer 18 is formed over the entire area of one surface of the substrate 11. Thus, the display panel 10 having a cross-sectional structure as shown in FIG. 16 is completed.

  As described above, in the display panel according to the present embodiment, the transistors Tr11 to Tr13 of the pixel drive circuit DC provided in the display pixel PIX, the selection line Ls, and the power supply voltage power supply voltage line Lv are overlapped in a plane. (Ie, so as to have a laminated structure in cross section), and the capacitor (voltage holding portion) Cs provided in the pixel drive circuit DC is electrically connected as a laminated structure with one electrode Eca and the upper layer side A panel structure in which the other electrode Ecb is interposed between the first electrode Ecx and the other electrode Ecb via the insulating films 12 and 13, respectively.

  As a result, the formation area of the pixel drive circuit and various wiring layers in the display pixel (pixel formation region) can be reduced, which is a case where the display panel is made high definition and the size (formation area) of the display pixel is reduced. However, while maintaining a sufficiently large pixel aperture ratio, the capacitance of the capacitor that affects the light emission characteristics of the light emitting element can be secured sufficiently large, and the light emitting element emits light with an appropriate luminance gradation according to display data. As a result, a good display image quality can be realized.

  Specifically, for example, in a display pixel having a pixel aperture ratio of 40%, the thickness of the dielectric layers (gate insulating film 12 and interlayer insulating film 13) between the layers is set with the capacitor Cs as in the present embodiment. In the case where the specific dielectric constant is 300 nm, the film quality is a silicon nitride film SiNx, the capacitance of the capacitor Cs is estimated to be 1.5 pF. On the other hand, if an equivalent capacitor is formed by a capacitor consisting only of a pair of opposing electrodes Eca and Ecb, it requires approximately twice the area and occupies 10% of the pixel formation region. The aperture ratio is reduced to 30%. In this embodiment, since the capacitor has a multilayer structure, the pixel aperture ratio can be improved from 30% to 40%.

  In the display panel and the manufacturing method thereof according to the present embodiment, the upper layer side electrode Ecx electrically connected to the one side electrode Eca of the capacitor (voltage holding portion) Cs, the selection line Ls, and the power supply voltage line Since Lv can be formed simultaneously by patterning the same wiring metal layer, the manufacturing process can be simplified and the number of steps can be reduced.

  In the present embodiment, the selection line Ls and the power supply voltage line Lv are disposed on the transistors Tr11 to Tr13 provided in the pixel driving circuit DC of each display pixel PIX, and the opaque electrodes Eca, Ecb, and Ecx are provided. Although the panel structure in which the capacitor Cs is arranged in a region that does not overlap with the organic EL element OLED (pixel electrode 14) in the plane has been described, the present invention is not limited to this, and the first embodiment described above is applied. As shown, a capacitor Cs having electrodes Eca, Ecb, Ecx made of a transparent electrode material in the EL element formation region Fpx is disposed so as to overlap the organic EL element OLED in a planar manner (stacked in a cross section), In the formation region Dpx, the selection line Ls and the power supply voltage line Lv are planar with the transistors Tr11 to Tr13 of the pixel drive circuit DC. In this case, the ratio of the EL element formation region Fpx to the pixel formation region Rpx can be further increased. Therefore, the capacitance of the capacitor Cs can be set larger while improving the pixel aperture ratio.

<Third Embodiment>
Next, a third embodiment of the display panel according to the present invention will be described. Here, since the pixel arrangement state of the display panel and the circuit configuration of each display pixel are the same as those of the first embodiment described above, the present embodiment will be described with reference to FIGS. 1 and 2 as appropriate in the following description. The characteristic part of the form will be specifically described.

(Display panel)
FIG. 20A is a plan layout view showing an example of a display pixel applicable to the bottom emission type display panel according to this embodiment, and FIG. 20B is a feature of the display pixel according to this embodiment. It is a plane layout figure which shows an example of the display pixel used as the comparison object for demonstrating. Here, the layer in which each transistor, wiring, and the like of the pixel driving circuit DC are formed is mainly shown. In FIG. 20, hatching is shown for convenience in order to clarify the planar shapes of the electrodes and wiring layers of each circuit element.

  Here, in the first and second embodiments described above, for the display pixel PIX, as shown in FIGS. 3 and 15, the EL for forming the organic EL element OLED in the upper region of the pixel formation region Rpx. The element formation region Fpx is arranged by being surrounded by the bank 17 on all sides, and a circuit formation region Dpx and a wiring layer (selection line Ls, etc.) for forming the pixel drive circuit DC (transistors Tr11 to Tr13, etc.) in the lower region are arranged. In the third embodiment, the EL element formation region Fpx is arranged in the central region of the pixel formation region Rpx, and the pixel formation region surrounding the central region is shown. A configuration example is shown in which circuit elements and wiring layers of the pixel drive circuit DC are arranged in the Rpx edge region.

  Specifically, as shown in FIG. 20A, in the pixel formation region Rpx set on the one surface side of the substrate 11, the capacitor Cs and the organic EL element OLED (which forms the pixel drive circuit DC) are formed in a substantially central region. In the figure, there is provided a pixel electrode 14 which is shared (shared) with the electrode Ecb on the other side of the capacitor Cs and only the pixel electrode 14 serving as an anode electrode is provided. On the other hand, a pixel driving circuit DC is formed in an edge region surrounding the central region. Transistors Tr11 to Tr13, a data line Ld, a selection line Ls, and a power supply voltage line Lv are provided.

FIG. 21 is an equivalent circuit showing capacitance components such as parasitic capacitance existing in the display pixel (pixel drive circuit and organic EL element) applied to this embodiment, and FIG. 22 is for explaining the effect in the display pixel. FIG.
XIIG-XXIIG line of the display pixel shown in FIGS. 20A and 20B (in this specification, “XXII” is used as a symbol corresponding to the Roman numeral “22” shown in FIG. 20 for the sake of convenience). ) And XXIIH-XXIIH lines are verified using a simple cross-sectional model as shown in FIGS. In FIGS. 22A and 22B, electrodes EA and EB correspond to the electrode Eca on one side and the electrode Ecb on the other side of the capacitor Cs shown in FIGS. Lx corresponds to the selection line Ls or the power supply voltage line Lv. The gate insulating film 12 serving as a dielectric of the capacitor Cs is made of silicon nitride, the bank 17 is made of polyimide, the substrate 11 is made of a glass substrate, and the dielectric constant of each member is set to 7, 3, and 4, respectively. The wiring Lx and the electrodes EA and EB are all 0.1 μm thick.

  Here, the transistors Tr11 and Tr12 are arranged to extend in the column direction (vertical direction in the drawing) in the left edge region of the pixel formation region Rpx in the drawing, and the transistor Tr13 is arranged on the right side of the pixel formation region Rpx in the drawing. It arrange | positions so that it may extend in a row direction in an edge area | region. The data line Ld, together with the transistors Tr11 and Tr12, is arranged so as to extend in the column direction in the left edge region of the pixel formation region Rpx, and the selection line Ls is located above the pixel formation region Rpx in the drawing. The power supply voltage line Lv is disposed in the edge region so as to extend in the row direction (left and right direction in the drawing), and the power supply voltage line Lv is disposed in the edge region below the pixel formation region Rpx in the drawing. .

  The selection line Ls and the power supply voltage line Lv are provided below the data line Ld (on the substrate 11 side), and the gate metal layer is patterned together with the gate electrodes Tr11g to Tr13g of the transistors Tr11 to Tr13 formed on the substrate 11. It is formed by. The data line Ld is formed by patterning the source-drain metal layer together with the source electrodes Tr11s to Tr13s and the drain electrodes Tr11d to Tr13d of the transistors Tr11 to Tr13 formed on the gate insulating film 12.

  In the transistor Tr11, the gate electrode Tr11g is formed integrally with the selection line Ls, the drain electrode Tr11d is connected to the power supply voltage line Lv through the contact hole CH31 provided in the gate insulating film 12, and the source electrode Tr11s is The contact hole CH33 provided in the gate insulating film 12 is connected to the gate electrode Tr13g of the transistor Tr13 and the electrode Eca on one side of the capacitor Cs.

  In the transistor Tr12, the gate electrode Tr12g is formed integrally with the gate electrode Tr11g of the transistor Tr11, is formed integrally with the selection line Ls, the source electrode Tr12s is formed integrally with the data line Ld, and the drain The electrode Tr12d is formed integrally with the source electrode Tr13s of the transistor Tr13 and the electrode Ecb on the other side of the capacitor Cs.

  In the transistor Tr13, the gate electrode Tr13g is formed integrally with the electrode Eca on one side of the capacitor Cs, the source electrode Tr13s is formed integrally with the drain electrode Tr12d of the transistor Tr12 and the electrode Ecb on the other side of the capacitor Cs, The drain electrode Tr13d is connected to the power supply voltage line Lv through a contact hole CH32 provided in the gate insulating film 12.

  The capacitor Cs has one electrode Eca in the same layer as the gate electrodes Tr11g to Tr13g of the transistors Tr11 to Tr13, and is formed integrally with the gate electrode Tr13g of the transistor Tr13, and the other electrode Ecb is the transistor Tr11. Are the same layer as the source electrodes Tr11s to Tr13s and the drain electrodes Tr11d to Tr13d of the transistor Tr13, and are formed integrally with the drain electrode Tr12d of the transistor Tr12 and the source electrode Tr13s of the transistor Tr13. That is, the electrode Eca on one side and the electrode Ecb on the other side are formed so as to extend opposite to each other with the gate insulating film 12 interposed therebetween. However, as shown in FIG. 22, in plan view, the electrodes EA and EB are both formed in an annular shape around the EL element formation region Fpx so that the inner peripheral edges coincide with each other in plan view. 17.

  And in this embodiment, as shown to the G section enclosed by the ellipse in Fig.20 (a), the electrode Ecb of the other side used as the upper layer side among the pair of electrodes Eca and Ecb of the capacitor Cs is, for example, It has a panel structure that is formed so as to protrude outward from the electrode Eca on one side that is the lower layer side. That is, in the planar layout shown in FIG. 20A, the other-side electrode Ecb is compared with the one-side electrode Eca, and the selection line Ls and the power supply voltage line Lv disposed in the edge region of the pixel formation region Rpx. Is formed so as to have a planar pattern that is closer to the surface.

  In the first and second embodiments described above, the display capacitor PIX (organic EL element OLED and pixel driving circuit DC) having the circuit configuration shown in FIG. However, the third embodiment has a panel structure that takes into account the influence of parasitic capacitance.

  That is, as described above, in the display panel corresponding to the active matrix driving method, circuit elements such as the plurality of transistors Tr11 to Tr13, the capacitor Cs, and the organic EL element OLED as shown in FIG. Various wiring layers (data line Ld, selection line Ls, power supply voltage line Lv, etc.) are provided, and these circuit elements and wiring layers are arranged in a specific limited region (pixel formation region Rpx). In this case, parasitic capacitance is generated between the circuit elements and the wiring layer.

  In particular, when the formation area of each pixel becomes smaller as the display panel becomes higher in definition (higher resolution), the distance between the circuit elements and the wiring layer becomes closer, so that the capacitor Cs originally used for display driving is reduced. In comparison, the capacitance value of the parasitic capacitance becomes relatively large, and its influence cannot be ignored. In addition, in the active matrix drive system, the display pixel PIX (pixel drive circuit DC) is applied to various wiring layers (data line Ld, selection line Ls, power supply voltage line Lv; drive wiring layer) in accordance with drive control of the display pixel PIX (pixel drive circuit DC). Although the voltage is controlled so as to change with time, as described above, when the parasitic capacitance between these wiring layers and each electrode of the capacitor Cs increases, the voltage change of each wiring layer passes through the parasitic capacitance. The voltage component held in the capacitor Cs is affected. For this reason, the capacitor Cs originally needs to hold a constant voltage component corresponding to the display data, but the voltage component varies due to a change in voltage applied to the parasitic capacitance or the wiring layer, thereby causing light emission. There arises a problem that the current value of the light emission driving current flowing through the organic EL element during operation varies, and light emission at a desired luminance gradation cannot be performed.

  Further, as the display panel becomes higher in definition, as the pixel formation region Rpx of each display pixel PIX becomes narrower, the light emission area (that is, the EL element formation region Fpx) in each display pixel PIX also becomes smaller and the pixel aperture ratio decreases. Therefore, in order to maintain and improve the display image quality, it is necessary to apply a high voltage or a large current to the organic EL element to increase the light emission luminance. In this case, the deterioration of the organic EL element over time becomes significant, and the product life is shortened. The problem of shortening arises.

  In the display pixel PIX applied to the present embodiment, as shown in FIG. 21, it is roughly divided into a parasitic capacitance Cgs between the gate and source of the transistor Tr11 (that is, between the contact N11 and the contact N13), and the gate and source of the transistor Tr13. A parasitic capacitance Cgd between the drains (ie, between the contact N11 and the contact N14), a parasitic capacitance Cgl between the gate of the transistor Tr13 (the electrode Eca on one side of the contact N11 or the capacitor Cs) and the data line Ld, and a gate of the transistor Tr13 The capacitor Cs between the sources (that is, between the contact N11 and the contact N12), the junction capacitance Cel between the anode and the cathode of the organic EL element OLED, the source of the transistor Tr13 (the contact E12 or the electrode Ecb on the other side of the capacitor Cs), and data There is a capacitance component consisting of the parasitic capacitance Csl between the lines Ld. To.

  Among these various capacitance components, the signal level of the selection signal Ssel and the switching control of the power supply voltage Vsc cause the voltage fluctuations to be relatively large between the selection line Ls and the power supply voltage line Lv and the capacitor Cs (electrodes Eca and Ecb). We will examine the influence of the parasitic capacitance component. Here, as shown in FIG. 20B, the outer edge of the electrode Eca on the lower side of the pair of electrodes Eca and Ecb of the capacitor Cs, as shown in the H portion surrounded by an ellipse in the figure. A panel structure formed so that the portion protrudes outward from the outer edge portion of the other-side electrode Ecb whose upper side is the upper layer side is used as a comparison target of the present embodiment.

  As shown in FIGS. 22A and 22B, the wiring Lx and the electrode EA are each formed on the substrate 11 with an interval of 2 μm, the wiring Lx has a wiring width of 5 μm, and the wiring A gate insulating film 12 having a film thickness of 0.3 μm is formed on the substrate 11 so as to cover Lx and the electrode EA, an electrode EB is formed in a region corresponding to the electrode EA on the gate insulating film 12, and It is assumed that an interlayer insulating film 13 having a thickness of 3 μm is formed on the gate insulating film 12 so as to cover the electrode EB.

  Here, in this embodiment, as shown in FIG. 22A, the outer peripheral edge of the electrode EB corresponding to the electrode Ecb on the other side of the capacitor Cs shown in FIG. It is formed so as to protrude 2 μm in the wiring Lx direction (left side of the drawing) from the outer peripheral edge of the electrode EA corresponding to Eca. On the other hand, in the comparison object, as shown in FIG. The outer edge is formed to be 2 μm shorter than the outer edge of the electrode EA (that is, the end of the electrode EB is positioned to the right of the end of the electrode EA).

  Further, in the panel structure having such a cross-sectional model, a capacitance component C23 corresponding to the capacitor Cs is formed between the electrode EA and the electrode EB facing each other via the gate insulating film 12, and between the electrode EA and the wiring Lx. A capacitance component C12 corresponding to the parasitic capacitance Cgl shown in FIG. 21 is formed, and a capacitance component C13 corresponding to the parasitic capacitance Csl shown in FIG. 21 is formed between the electrode EB and the wiring Lx.

  Table 1 shows the results obtained by conducting electromagnetic wave analysis in such a panel structure and deriving the capacitance values of the respective capacitance components.

  Specifically, as shown in FIG. 22A, the capacitive component C12 that is parasitic between the electrode EA and the wiring Lx causes the electrode EB to protrude from the end of the electrode EA and be close to the wiring Lx. Since it is arranged, it acts as a kind of shield, and in the comparative example (see FIGS. 20B and 22B), a parasitic capacitance of 46.8 pF / m is generated, whereas this embodiment (FIG. 20 (a) and FIG. 22 (a)), it was found to be 21.01 pF / m, and the capacitance value was reduced to 1/2 or less.

  On the other hand, the capacitance component C13 parasitic between the electrode EB and the wiring Lx generates a parasitic capacitance of 8.4 pF / m in the comparative example, whereas it is 53.01 pF / m in the present embodiment. The capacitance value of the capacitance component C23 generated between the electrode EA and the electrode EB corresponding to the capacitor Cs has a parasitic capacitance of 1.957 nF / m in the comparative example. On the other hand, in the present embodiment, it is 2.185 nF / m, and it has been found that the capacitance value can be increased.

  As described above, in the display panel according to this embodiment, the pair of electrodes Eca and Ecb of the capacitor Cs provided in the display pixel PIX (pixel drive circuit DC and organic EL element OLED) is on the fixed potential side. The other end of the electrode Ecb (electrode EB shown in FIG. 22A) is connected to the wiring layer (selection line LS, power supply voltage line Lv, etc .; drive wiring layer) based on display driving. The other side electrode Ecb and the wiring layer are projected outward from the end of one side electrode Eca (electrode EA shown in FIG. 22A) whose potential changes in accordance with the change (switching control). Is set to be short, the parasitic capacitance between the electrode Eca on one side and the wiring layer can be reduced, and the fluctuation of the voltage component held in the capacitor Cs can be suppressed.

  Further, since the electrode Eca of the capacitor Cs and the wiring layer can be disposed close to each other, as shown in the first embodiment, the pixel electrode 14 of the organic EL element OLED and the electrode Ecb on the other side of the capacitor Cs. In the display panel that shares (also serves as) the same, the formation area of the capacitor Cs can be enlarged to increase the capacitance, and the EL element formation region Fpx can be similarly enlarged to improve the pixel aperture ratio. it can.

  Therefore, even when the display panel is made high definition and the size (formation area) of the display pixel is reduced, the capacitance of the capacitor can be secured sufficiently large while reducing the parasitic capacitance in the display pixel. Since the aperture ratio can be improved, a good display image quality can be realized by causing the light emitting element to emit light with an appropriate luminance gradation according to display data.

  Further, in the display panel and the manufacturing method thereof according to the present embodiment, it is only necessary to change the plane pattern of the electrode on the other side of the capacitor. Therefore, only the mask pattern is changed in the patterning process of the electrode. ), The panel structure shown in FIG. 22A can be realized, and a change in the manufacturing process and an increase in the number of steps can be suppressed.

  In each of the above embodiments, the pixel driving circuit DC includes the n-channel transistors Tr11 to Tr13. However, the pixel driving circuit DC may be a p-channel, and is a circuit that holds write data or the like as charges in the capacitor Cs in active driving. If there are any, the number of transistors, transistor size, connection structure, operation control and the like are not particularly limited. However, in the case of the bottom emission type, it is preferable that the number and size of the transistors be small in order to achieve a high aperture ratio.

  Further, in each of the above embodiments, each color pixel is partitioned by the bank 17, but the present invention is not limited to this, and a stripe pattern including a plurality of color pixels of the same color along the column direction as its unit May be partitioned by the bank 17. In this case, since it is the same color, it can be formed by continuously applying an organic material so as to straddle the formation region of a plurality of color pixels along the column direction.

It is a schematic plan view which shows an example of the pixel array state of the display panel which concerns on this invention. FIG. 6 is an equivalent circuit diagram showing a circuit configuration example of each display pixel (light emitting element and pixel driving circuit) two-dimensionally arranged on the display panel according to the present invention. FIG. 3 is a plan layout diagram illustrating an example of display pixels applicable to the display panel according to the first embodiment. FIG. 3 is a schematic cross-sectional view (part 1) illustrating a cross-sectional structure of a display pixel PIX having a planar layout according to the first embodiment. FIG. 6 is a schematic cross-sectional view (part 2) illustrating a cross-sectional structure of the display pixel PIX having the planar layout according to the first embodiment. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the display panel which concerns on 1st Embodiment. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the display panel which concerns on 1st Embodiment. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the display panel which concerns on 1st Embodiment. FIG. 6 is a plan layout view showing a part of display pixels applicable to a display panel according to another configuration example of the first embodiment, and a schematic cross-sectional view showing a cross-sectional structure. It is process sectional drawing which shows an example of the manufacturing method of the display panel which concerns on this structural example. FIG. 14 is a schematic cross-sectional view (part 1) illustrating a cross-sectional structure of a display pixel PIX having a planar layout according to still another configuration example of the first embodiment. FIG. 14 is a schematic cross-sectional view (part 2) illustrating a cross-sectional structure of a display pixel PIX having a planar layout according to still another configuration example of the first embodiment. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the display panel which concerns on this structural example. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the display panel which concerns on this structural example. It is a plane layout figure which shows an example of the display pixel applicable to the display panel which concerns on 2nd Embodiment. It is a schematic sectional drawing which shows the cross-sectional structure in the display pixel PIX which has the plane layout which concerns on 2nd Embodiment. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the display panel which concerns on 2nd Embodiment. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the display panel which concerns on 2nd Embodiment. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the display panel which concerns on 2nd Embodiment. The plane layout figure which shows an example of the display pixel applicable to the display panel which concerns on 3rd Embodiment, and the plane which shows an example of the display pixel used as the comparison object for demonstrating the characteristic of the display pixel which concerns on this embodiment FIG. It is an equivalent circuit which shows capacitive components, such as a parasitic capacitance, which exists in the display pixel (a pixel drive circuit and an organic EL element) applied to 3rd Embodiment. It is a schematic sectional drawing for demonstrating the effect in the display pixel which concerns on 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display panel 11 Board | substrate 12 Gate insulating film 13 Interlayer insulating film 14 Pixel electrode 15 Organic EL layer 16 Counter electrode 17 Bank PIX Display pixel Rpx Pixel formation area Fpx EL element formation area DC Pixel drive circuit Tr11-Tr13 Transistor Cs Capacitor Eca, Ecb , Ecx electrode OLED Organic EL element Ls Selection line Lv Power supply voltage line Ld Data line

Claims (21)

A light emitting element;
A pair of electrodes, wherein at least one of the pair of electrodes has a transmission characteristic for at least a part of a wavelength range of light emitted by the light emitting element, and holds a voltage component according to display data; A voltage holding unit overlapping the light emitting element in a plane;
A display panel comprising: The display panel according to claim 1, wherein the voltage holding unit is disposed on a radiation side of light emitted from the light emitting element. The voltage holding unit has a capacitor structure including a transparent dielectric layer and a pair of transparent electrodes arranged to face each other with the dielectric layer interposed therebetween. The display panel according to 1 or 2. The display panel according to claim 1, wherein at least one of the pair of electrodes is formed of a conductive polymer material. The light-emitting element includes a light-emitting functional layer, and a pixel electrode and a counter electrode disposed to face each other with the light-emitting functional layer interposed therebetween,
5. The electrode according to claim 1, wherein, of the pair of electrodes of the voltage holding unit, the electrode formed on the light emitting element side is shared with the pixel electrode of the light emitting element. Display panel. The display panel according to claim 5, wherein at least a part of the light emitting functional layer of the light emitting element is formed of a conductive polymer material. A driving transistor that supplies a driving current having a predetermined current value to the light emitting element based on the voltage component held in the voltage holding unit;
The pair of electrodes of the voltage holding unit are connected to a gate electrode of the driving transistor and a source electrode or a drain electrode of the driving transistor, respectively. Display panel. One electrode of the pair of electrodes of the voltage holding unit is connected to the gate electrode of the driving transistor through a contact layer formed in the same layer as the source electrode and the drain electrode of the driving transistor. The display panel according to claim 7. A light emitting element;
A voltage corresponding to display data for emitting light from the light-emitting element, having a multilayer capacitor comprising a plurality of dielectric layers and a plurality of electrodes arranged opposite to each other with the dielectric layers interposed therebetween A voltage holding unit for holding the component;
A display panel characterized by comprising: A driving transistor that supplies a driving current having a predetermined current value to the light emitting element based on a voltage component held in the multilayer capacitor;
The multilayer capacitor includes at least a first electrode formed in the same layer as the gate electrode of the driving transistor, and a first dielectric layer formed between the gate electrode of the driving transistor, the source electrode, and the drain electrode. A second electrode formed in the same layer as a source electrode and a drain electrode of the drive transistor, a second dielectric layer formed so as to cover the drive transistor, and the second dielectric layer The display panel according to claim 9, wherein the display panel has a structure in which a third electrode formed thereon and electrically connected to the first electrode is sequentially laminated. The light-emitting element includes a light-emitting functional layer, and a pixel electrode and a counter electrode disposed to face each other with the light-emitting functional layer interposed therebetween,
The display panel according to claim 10, wherein the second electrode of the voltage holding unit is connected to the pixel electrode of the light emitting element. The third electrode of the voltage holding unit is formed in the same layer as a power supply wiring to which a power supply voltage for flowing the drive current is applied via the source-drain of the drive transistor. The display panel according to claim 10. 13. The display panel according to claim 12, wherein at least the power supply wiring is formed on the drive transistor via the second dielectric layer. 14. The display panel according to claim 9, wherein the light emitting element and the voltage holding portion are arranged on a substrate so as not to overlap in a plane. 15. The light emitting element according to claim 1, wherein the pixel electrode is formed of a light transmissive conductive material, and the counter electrode is formed of a light reflective conductive material. Display panel as described. 15. The light emitting element according to claim 1, wherein the pixel electrode is made of a light reflective conductive material, and the counter electrode is made of a light transmissive conductive material. Display panel as described. The voltage holding unit is formed on the same layer as the electrode on one side of the pair of electrodes of the voltage holding unit, and the applied wiring is switched according to the drive control of the light emitting element. The display panel according to claim 1, wherein an electrode on the other side of the pair of electrodes is formed so as to be closer to the electrode on the one side. Forming a first electrode of a voltage holding unit that holds a voltage component according to display data on a substrate;
Forming a second electrode of the voltage holding unit so as to face the first electrode through a dielectric layer;
Forming a light emitting functional layer on the second electrode;
Forming a counter electrode facing the pixel electrode through the light emitting functional layer;
A display panel manufacturing method comprising: 19. The method for manufacturing a display panel according to claim 18, wherein the second electrode of the voltage holding unit is formed of a conductive polymer material that forms a part of the light emitting functional layer. In a method for manufacturing a display panel having a light emitting element and a pixel driving circuit for supplying a predetermined driving current to the light emitting element,
Based on the first electrode of the voltage holding unit that holds a voltage component corresponding to display data on the substrate and the voltage component held in the voltage holding unit, the driving current having a predetermined current value is Simultaneously forming a gate electrode of a driving transistor to be supplied to the light emitting element;
Forming a first dielectric layer covering the first electrode of the voltage holding unit and the gate electrode of the driving transistor;
Simultaneously forming a second electrode of the voltage holding unit and a source electrode and a drain electrode of the driving transistor on the first dielectric layer;
Forming a second dielectric layer covering the second electrode of the voltage holding unit and the source electrode and the drain electrode of the driving transistor;
Forming a third electrode of the voltage holding unit electrically connected to the first electrode on the second dielectric layer;
A display panel manufacturing method comprising: The step of forming the third electrode of the voltage holding unit simultaneously forms a power supply wiring to which a power supply voltage for flowing the drive current is applied through the source and drain of the drive transistor. The display panel according to claim 20.

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