JP2010191368A - Display panel and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display panel that has satisfactory display characteristics, by suppressing the contact resistance at a contact portion between a counter electrode and a power feed wire for applying a predetermined voltage to the counter electrode of an organic EL element, and to provide a method for manufacturing the display panel. <P>SOLUTION: In the display panel, source electrodes Tr11s, Tr12S and drain electrodes Tr11d, Tr12d of transistors Tr11 and Tr12 of each pixel formation area Ppx of the display area 20, and a contact electrode Ect that is disposed in a peripheral area 30 and supplies a predetermined voltage to the counter electrode (e.g., cathode electrode) 16 are simultaneously formed by patterning the same source and drain metal layer formed of, e.g., molybdenum-niobium (MoNb), etc. Also, a metal material such as aluminum is used as a counter electrode 16 (the thin film 16b of a high work function) connected to the contact electrode Ect. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display panel and a method for manufacturing the same, and more particularly to a display panel in which a plurality of light-emitting elements having an element structure in which a pair of electrode layers are arranged to face each other via a light-emitting functional layer are arranged on a substrate and the same It relates to a manufacturing method.

  2. Description of the Related Art In recent years, a display panel (organic EL display panel) in which organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”) are two-dimensionally arranged as a display device for electronic devices such as mobile phones and portable music players is provided. It has been known.

  As is well known, an organic EL element has an element structure in which, for example, an anode (anode) electrode, an organic EL layer (light emitting functional layer), and a cathode (cathode) electrode are sequentially laminated on one side of a glass substrate or the like. Have. Based on the energy generated when the holes and electrons injected in the organic EL layer recombine by applying a voltage between the anode electrode and the cathode electrode so as to exceed the emission threshold value in the organic EL layer. Light (excitation light) is emitted.

  For example, in Patent Document 1, a transistor, a wiring layer, and the like for driving the organic EL element to emit light are formed on a transparent substrate, and then a planarizing film that covers the transparent substrate is formed, and the organic EL element is formed on the upper layer. A panel structure in which is formed is disclosed. Here, the organic EL element includes a lower electrode (anode electrode) made of a transparent electrode material film such as ITO (Indium Thin Oxide), a light emitting element layer (organic EL layer), and a lower electrode through the light emitting element layer. And an upper electrode (cathode electrode) made of aluminum (Al) or an aluminum alloy. That is, Patent Document 1 discloses a display panel having a so-called bottom emission type light emitting structure in which light emitted from a light emitting element layer (organic EL layer) is emitted to the outside through a lower electrode (anode electrode) and a transparent substrate. Is disclosed.

JP 2006-228573 A

  As disclosed in Patent Document 1 described above, in a display panel having a bottom emission type light emitting structure, an upper electrode serving as a cathode electrode has light reflection characteristics, and is excellent in conductivity, heat resistance, and the like. Aluminum (Al) or an aluminum alloy (aluminum metal) is generally applied. In general, the cathode electrode is connected to a power supply wiring disposed in a lower layer through a contact hole (cathode contact portion) provided at a predetermined position of an insulating film provided on the substrate, and through these, Cathode voltage is supplied.

  On the other hand, when the lower electrode (anode electrode) made of ITO or the like is formed on the insulating film by patterning, the lower layer electrode and the lower layer wiring (including the power supply wiring) exposed in the contact hole provided in the insulating film are damaged by etching. In order to prevent the contact from being received, a contact structure is known in which each contact hole is filled with and covered with a transparent electrode material such as ITO used for a lower electrode (anode electrode).

  However, when such a contact structure is applied to the cathode contact portion described above, a combination of a transparent electrode material (ITO or the like) filled in the contact hole and a metal material (aluminum metal) used for the cathode electrode is used. Has a problem that the contact resistance between the two becomes high and affects the display performance of the display. The structure of the cathode contact portion will be described in detail in the embodiments described later.

  Therefore, in view of the above-described problems, the present invention suppresses the contact resistance at the contact portion between the counter electrode and the power supply wiring for applying a predetermined voltage to the counter electrode of the organic EL element, and provides a good display. It is an object of the present invention to provide a display panel having characteristics and a manufacturing method thereof.

  In the display panel in which at least a display element and a functional element for driving the display element are formed on a substrate, the functional element includes at least a first electrode, A second electrode provided on the first electrode via a first insulating film, and the display element is electrically connected to at least the second electrode of the functional element. 3 and a fourth electrode provided above the third electrode through a display functional layer, and the fourth electrode of the display element covers at least the functional element And is electrically connected to a fifth electrode provided in the same layer as the second electrode of the functional element through an opening provided in the second insulating film formed on the first insulating film. The second electrode and the fifth electrode are made of molybdenum-niobium. It characterized by having an electrode structure including a conductive layer.

The functional element may be a thin film transistor, and the first electrode may be a gate electrode of the thin film transistor, and the second electrode may be a source electrode and a drain electrode of the thin film transistor.
The display element is a light emitting element, the third electrode is a pixel electrode made of an electrode material having light transmission characteristics, and the fourth electrode is a counter electrode made of an electrode material having light reflection characteristics. It may be.
The fourth electrode may be a conductive layer containing aluminum.
The fifth electrode may be connected to a power supply wiring for applying a predetermined voltage to the fourth electrode.
The fifth electrode may have a laminated structure including a plurality of conductive layers including an electrode layer provided in the same layer as the second electrode.
The fifth electrode has a stacked structure including at least the electrode layer provided in the same layer as the second electrode and a conductive layer provided in the same layer as the semiconductor layer of the thin film transistor. Also good.
The fifth electrode includes at least an electrode layer provided in the same layer as the third electrode, a first wiring layer formed so as to cover the electrode layer of the same layer as the third electrode, May be connected to the fourth electrode.
The first wiring layer may be formed by being stacked on a second wiring layer provided in the same layer as the second electrode.
The first wiring layer may be an aluminum alloy.
The display element may be an organic electroluminescence element.

According to a seventh aspect of the present invention, in the method of manufacturing a display panel in which at least a display element and a functional element for driving the display element are formed on a substrate, the functional element includes at least a first electrode. And a second electrode provided on the first electrode via a first insulating film, and the display element is electrically connected to at least the second electrode of the functional element And the fourth electrode provided on the third electrode via a display functional layer, and the first electrode of the functional element is formed on the substrate. Connecting the third electrode of the display element to the third electrode of the display element via the first insulating film on the first conductive layer. In addition, the fifth electrode is formed simultaneously with the formation of the second electrode of the functional element. A step of forming a second insulating film on the substrate so as to cover the second electrode, the third electrode, and the fifth electrode, and the second insulating film, Forming at least an opening through which the third electrode and the fifth electrode are exposed; forming the display functional layer on the third electrode of the display element; and The fourth electrode of the display element that is opposed to the third electrode of the display element and is electrically connected to the fifth electrode through the opening of the second insulating film. Forming an electrode, wherein at least the second electrode and the fifth electrode have an electrode structure including a conductive layer made of molybdenum-niobium.
The invention according to claim 8 is a method for manufacturing a display panel in which at least a display element and a functional element for driving the display element are formed on a substrate, wherein the functional element includes at least a first electrode. And a second electrode provided on the first electrode via a first insulating film, and the display element is electrically connected to at least the second electrode of the functional element And the fourth electrode provided on the third electrode via a display functional layer, and the first electrode of the functional element is formed on the substrate. Forming the second electrode of the functional element on the first conductive layer via the first insulating film, and simultaneously forming the fifth electrode, Forming a second insulating film on the substrate so as to cover the electrode and the fifth electrode; Forming an opening in the second insulating film through which at least the second electrode and the fifth electrode are exposed, and through the opening of the second insulating film, Forming the third electrode of the display element so as to connect to the second electrode of the functional element; forming the display functional layer on the third electrode of the display element; The display is opposed to the third electrode of the display element through the display functional layer and is electrically connected to the fifth electrode through the opening of the second insulating film. Forming the fourth electrode of the element, wherein at least the second electrode and the fifth electrode have an electrode structure including a conductive layer made of molybdenum-niobium.
The invention according to claim 9 is a method of manufacturing a display panel in which at least a display element and a functional element for driving the display element are formed on a substrate, wherein the functional element includes at least a first electrode. And a second electrode provided on the first electrode via a first insulating film, and the display element is electrically connected to at least the second electrode of the functional element And the fourth electrode provided on the third electrode via a display functional layer, and the first electrode of the functional element is formed on the substrate. Forming the second electrode of the functional element on the first conductive layer via the first insulating film, and simultaneously forming the fifth electrode, Forming a second insulating film on the substrate so as to cover the electrode and the fifth electrode; Forming an opening in the second insulating film through which at least the second electrode and the fifth electrode are exposed, and through the opening of the second insulating film, Simultaneously forming the third electrode of the display element connected to the second electrode of the functional element and the electrode layer connected to the fifth electrode; and at least the connection to the fifth electrode A step of forming a first wiring layer so as to cover the electrode layer; a step of forming the display functional layer on the third electrode of the display element; and the display function layer via the display functional layer. The display element that faces the third electrode of the element and is electrically connected to the fifth electrode through the electrode layer and the first wiring layer connected to the fifth electrode. Forming a fourth electrode, at least comprising: Serial second electrode and the fifth electrode, molybdenum - and having an electrode structure including a conductive layer made of niobium.
The functional element is a thin film transistor, and the step of forming the fifth electrode includes the step of forming the second electrode and the fifth electrode and at least a layer below the second electrode and the fifth electrode. The formed semiconductor layer of the thin film transistor may be patterned using the same mask.
The first wiring layer may be formed by being stacked on a second wiring layer formed simultaneously with the second electrode and the fifth electrode.

  According to the display panel and the manufacturing method thereof according to the present invention, a contact portion (cathode contact portion) between the counter electrode and the power supply wiring for applying a predetermined voltage to the counter electrode (for example, cathode electrode) of the organic EL element. It is possible to achieve good display characteristics by suppressing the contact resistance.

FIG. 1 is a schematic plan view showing an example of a display panel according to the present invention. FIG. 2 is a schematic plan view showing an example of a pixel arrangement state of the display panel according to the present invention. FIG. 3 is an equivalent circuit diagram showing a circuit configuration example of each display pixel two-dimensionally arranged on the display panel according to the first embodiment. FIG. 4 is a plan layout diagram illustrating an example of display pixels applicable to the display panel according to the first embodiment. FIG. 5 is a cross-sectional view (No. 1) of the main part of the display panel according to the first embodiment. FIG. 6 is a sectional view (No. 2) of the principal part of the display panel according to the first embodiment. FIG. 7 is a process cross-sectional view (part 1) illustrating the method for manufacturing the display panel according to the first embodiment. FIG. 8 is a process cross-sectional view (part 2) illustrating the method for manufacturing the display panel according to the first embodiment. FIG. 9 is a process cross-sectional view (part 3) illustrating the method for manufacturing the display panel according to the first example. FIG. 10 is a process cross-sectional view (part 4) illustrating the method for manufacturing the display panel according to the first example. FIG. 11 is a process cross-sectional view (part 5) illustrating the method for manufacturing the display panel according to the first example. FIG. 12 is a cross-sectional view of an essential part showing an example of a display panel to be compared with the first embodiment. FIG. 13 is a cross-sectional view of an essential part showing another configuration example of the display panel according to the first embodiment. FIG. 14 is a cross-sectional view of a principal part showing a second embodiment of the display panel according to the present invention. FIG. 15 is a cross-sectional view of a main part showing another configuration example of the display panel according to the second embodiment. FIG. 16 is a cross-sectional view of an essential part showing still another configuration example of the display panel according to the second embodiment.

  Hereinafter, the display panel and the manufacturing method thereof according to the present invention will be described in detail with reference to examples. Here, in the embodiments described below, a case will be described in which an organic EL element including a light emitting functional layer (organic EL layer) formed by applying an organic material is applied as a light emitting element constituting a display pixel. .

<First embodiment>
(Display panel)
First, a display panel and display pixels according to the present invention will be described.
FIG. 1 is a schematic plan view showing an example of a display panel according to the present invention, and FIG. 2 shows an example of a pixel array state (lower panel structure such as a partition wall layer and an insulating film) of the display panel according to the present invention. It is a schematic plan view shown.

  Here, in the plan view shown in FIG. 1, for the convenience of explanation, each display pixel (sub-pixel of each color; hereinafter referred to as a convenience) viewed from one side of the display panel (insulating substrate) (the side on which the organic EL element is formed). (Referred to as “color pixel”) provided on the side wall of the partition wall layer, the insulating film, etc. that define the arrangement of the pixel electrodes and contact electrodes, external junction terminals, and the formation region of each display pixel (or light emitting element). Only the arrangement relationship with the opening is shown. Further, in the plan view shown in FIG. 2, only the relationship between the arrangement of the pixel electrodes and the arrangement structure of each wiring layer is shown, and each display pixel is used to drive the light emitting element (organic EL element) of each display pixel to emit light. The display of the transistors and the like in the pixel driving circuit (see FIG. 3 described later) provided in FIG. In FIGS. 1 and 2, hatching is shown for convenience in order to clarify the arrangement and covering state of the pixel electrode, each wiring layer, the partition layer, the insulating film, and the like.

  In the display panel 10 according to the first embodiment, as shown in FIGS. 1 and 2, for example, a display region 20 and a peripheral region 30 around the display region 20 are set on one surface side of an insulating substrate 11 such as a glass substrate. Has been. In the display area 20, a plurality of display pixels PIX are arranged. Further, in the peripheral region 30, external junction terminals (connection electrodes) TMi connected to the respective wirings in the display region 20 and the contact electrodes (connection electrodes) Ect via the routing wirings Lh described later are arranged at predetermined positions. ing. The display pixel PIX is formed by a set of each color pixel (sub-pixel of each color) PXr, PXg, and PXb composed of three colors of red (R), green (G), and blue (B) arranged adjacent to each other. Yes. In this embodiment, as shown in FIG. 1, one display pixel PIX is formed by combining a plurality of RGB color pixels PXr, PXg, and PXb, which are repeatedly arranged in the row direction (left and right in the drawing). . A plurality of color pixels PXr, PXg, and PXb of the same color are arranged in the column direction (up and down direction in the drawing).

  In addition, the display region 20 of the display panel 10 is provided so that the insulating film 13 is exposed so as to surround at least the periphery of each color pixel PXr, PXg, or PXb. Further, a region including the boundary region between the color pixels PXr, PXg, or PXb arranged substantially on the insulating film 13 in the column direction (vertical direction in the drawing) protrudes from an EL element formation region Rel described later. A plurality of barrier ribs 17 extending in the column direction (vertical direction in the drawing) are provided. A region surrounded by the insulating film 13 and the partition layer 17 and exposing the pixel electrode (for example, anode electrode) 14 forms a light emitting element (organic EL element; display element) of each color pixel PXr, PXg, or PXb. Therefore, it is defined as an EL element formation region (see FIGS. 4 and 5 to be described later). Then, this EL element formation region and a region including the insulating film 13 and the partition wall layer 17 in the surrounding boundary region are defined as pixel formation regions of the respective color pixels PXr, PXg, or PXb (FIG. 4 described later). FIG. 5).

  Here, around the pixel electrode 14 (EL element formation region) in the pixel formation region of each color pixel PXr, PXg, or PXb, for example, as shown in FIG. A signal line Ld is disposed, and a selection line Ls is disposed in a row direction (left and right direction in the drawing) orthogonal to the data line Ld. A power supply voltage line (for example, an anode line) La is disposed in the row direction parallel to the selection line Ls. As will be described in detail later, the display panel 10 is formed from a single electrode layer (solid electrode) so as to face the plurality of pixel electrodes 14 arranged two-dimensionally on the insulating substrate 11 in common. A counter electrode (for example, a cathode electrode) 16 is formed.

  On the other hand, at the four corners of the peripheral region 30 of the display panel 10, for example, as shown in FIGS. 1 and 2, it will be described later in the vicinity of the display region 20 via routing wiring (feeding wiring) Lh (not shown). Contact electrodes Ect connected to the external junction terminals TMi are respectively arranged. In addition, a specific end region of the insulating substrate 11 (the end region in the lower part of the drawing in FIGS. 1 and 2) is for electrically connecting to a flexible substrate, a driver IC for driving, or the like that is not shown. A plurality of external junction terminals TMi are regularly arranged.

  Here, in the peripheral region 30 of the display panel 10, the insulating film 13 is provided on the insulating substrate 11, and the contact hole CH4 in which the contact electrode Ect is exposed and the external junction terminal TMi are exposed in the insulating film 13. An opening 13t is provided. The counter electrode 16 formed of a single electrode layer (solid electrode) in the display region 20 extends at least partially to the peripheral region 30 and is connected to the contact electrode Ect via the contact hole CH4. Yes. As a result, a predetermined voltage (cathode voltage) is applied to the counter electrode 16 via the contact electrode Ect.

  The various wirings arranged in the display area 20 and the contact electrodes Ect arranged in the peripheral area 30 are connected to the insulating substrate via a part of the wiring lines Lh arranged in the peripheral area 30. 11 are connected to external junction terminals TMi arranged in 11 specific end regions.

(Display pixel)
FIG. 3 is an equivalent circuit diagram illustrating a circuit configuration example of each display pixel (light emitting element and pixel driving circuit) two-dimensionally arranged on the display panel according to the present embodiment.
As shown in FIG. 3, each color pixel PXr, PXg, PXb of the display pixel PIX includes a pixel drive circuit DC and an organic EL element (light emitting element) OEL. The pixel drive circuit DC has a circuit configuration including one or more transistors (for example, amorphous silicon thin film transistors; functional elements). The organic EL element (light emitting element) OEL emits light when a light emission driving current controlled by the pixel driving circuit DC is supplied to the pixel electrode 14.

  Specifically, the pixel drive circuit DC includes a transistor (selection transistor) Tr11, a transistor (light emission drive transistor) Tr12, and a capacitor Cs as shown in FIG. 3, for example. The transistor Tr11 has a gate terminal connected to the selection line Ls, a drain terminal connected to the data line Ld arranged in the column direction of the display panel 10, and a source terminal connected to the contact N11. The transistor Tr12 has a gate terminal connected to the contact N11, a drain terminal connected to the power supply voltage line La, and a source terminal connected to the contact N12. The capacitor Cs is connected between the gate terminal and the source terminal of the transistor Tr12.

  Here, n-channel thin film transistors (field effect transistors) are applied to the transistors Tr11 and Tr12. If the transistors Tr11 and Tr12 are p-channel type, the source terminal and the drain terminal are opposite to each other. The capacitor Cs is a parasitic capacitance formed between the gate and the source of the transistor Tr12, an auxiliary capacitance additionally provided between the gate and the source, or a capacitance component composed of these parasitic capacitance and auxiliary capacitance. It is.

  The organic EL element OEL has an anode terminal (pixel electrode 14 serving as an anode electrode) connected to the contact N12 of the pixel drive circuit DC, and a cathode terminal (cathode electrode) formed by the single electrode layer described above. The counter electrode 16 is integrally formed. The counter electrode 16 is directly or indirectly connected to, for example, a predetermined low potential power source via the contact electrode Ect described above. Thus, a predetermined low voltage (reference voltage Vss; for example, ground potential Vgnd) is commonly applied to all the display pixels PIX (cathode electrodes of the organic EL element OEL) two-dimensionally arranged on the insulating substrate 11. Is done.

  In the display pixel PIX (pixel drive circuit DC and organic EL element OEL) shown in FIG. 3, the selection line Ls is connected to a selection driver (not shown), for example, in the row direction of the display panel 10 at a predetermined timing. A selection voltage Ssel for setting the plurality of arranged display pixels PIX (color pixels PXr, PXg, PXb) to a selected state is applied. The data line Ld is connected to a data driver (not shown), and a gradation signal (data voltage) Vpix corresponding to display data is applied at a timing synchronized with the selection state of the display pixel PIX.

  The power supply voltage line La is connected directly or indirectly to a predetermined high potential power supply, for example, and is a pixel electrode (for example, an anode electrode) of the organic EL element OEL provided in each display pixel PIX (color pixels PXr, PXg, PXb). ) 14 is supplied with a predetermined high voltage (supply voltage Vdd) having a higher potential than the reference voltage Vss applied to the counter electrode 16 of the organic EL element OEL in order to flow a light emission driving current according to display data. .

  That is, in each display pixel PIX, the supply voltage Vdd and the reference voltage Vss are applied to both ends (the drain terminal of the transistor Tr12 and the cathode terminal of the organic EL element OEL) of the pair of the transistor Tr12 and the organic EL element OEL connected in series. Then, a forward bias is applied to the organic EL element OEL so that the organic EL element OEL can emit light, and the current value of the light emission driving current that the transistor Tr12 passes through the organic EL element OEL according to the gradation signal Vpix is controlled. ing.

(Light emission operation of display pixel)
In the drive control operation in the display pixel PIX having such a circuit configuration, first, a selection driver (not shown) selects a selection level (on level; for example, high level) for a selection line Ls during a predetermined selection period. When the selection voltage Ssel is applied, the transistor Tr11 is turned on and set to the selected state. In synchronization with this timing, control is performed so that a gradation signal Vpix having a voltage value corresponding to display data is applied to the data line Ld from a data driver (not shown). Thereby, a potential corresponding to the gradation signal Vpix is applied to the contact N11, that is, the gate terminal of the transistor Tr12 via the transistor Tr11.

  In the pixel drive circuit DC having the circuit configuration shown in FIG. 3, the current value of the drain-source current of the transistor Tr12 (that is, the light emission drive current flowing in the organic EL element OEL) is the potential difference between the drain-source and the gate. -Determined by the potential difference between the sources. Here, since the supply voltage Vdd applied to the drain terminal (drain electrode) of the transistor Tr12 and the reference voltage Vss applied to the cathode terminal (cathode electrode) of the organic EL element OEL are fixed values, the drain of the transistor Tr12 The potential difference between the sources is fixed beforehand by the supply voltage Vdd and the reference voltage Vss. Since the potential difference between the gate and source of the transistor Tr12 is uniquely determined by the potential of the gradation signal Vpix, the current value of the current flowing between the drain and source of the transistor Tr12 is controlled by the gradation signal Vpix. be able to.

  As described above, the transistor Tr12 is turned on in a conductive state corresponding to the potential of the contact N11 (that is, a conductive state corresponding to the gradation signal Vpix), and the transistor Tr12 and the organic EL element OEL are supplied from the supply voltage Vdd on the high potential side. Since the light emission driving current having a predetermined current value flows to the reference voltage Vss (ground potential Vgnd) on the low potential side through the organic EL element OEL, the organic EL element OEL has a luminance gradation corresponding to the gradation signal Vpix (that is, display data). Lights up. At this time, charges are accumulated (charged) in the capacitor Cs between the gate and the source of the transistor Tr12 based on the gradation signal Vpix applied to the contact N11.

  Next, in a non-selection period after the end of the selection period, by applying a selection voltage Ssel of a non-selection level (off level; for example, low level) to the selection line Ls, the transistor Tr11 of the display pixel PIX is turned off and non-selected. The selected state is set, and the data line Ld and the pixel drive circuit DC are electrically disconnected. At this time, the charge accumulated in the capacitor Cs is held, so that the voltage corresponding to the gradation signal Vpix is held at the gate terminal of the transistor Tr12 (that is, the potential difference between the gate and the source is held). It becomes a state.

  Therefore, similarly to the light emission operation in the selected state, a predetermined light emission drive current flows from the supply voltage Vdd to the organic EL element OEL via the transistor Tr12, and the light emission operation state is continued. This light emitting operation state is controlled so as to continue, for example, for one frame period until the next gradation signal Vpix is applied (written). Then, such a drive control operation is sequentially executed for every row, for example, for all the display pixels PIX (each color pixel PXr, PXg, PXb) two-dimensionally arranged on the display panel 10, thereby obtaining desired image information. An image display operation to be displayed can be executed.

  In FIG. 3, the pixel driving circuit DC provided in the display pixel PIX is written in each display pixel PIX (specifically, the gate terminal of the transistor Tr12 of the pixel driving circuit DC; the contact N11) according to display data. By adjusting (specifying) the voltage value of the gradation signal Vpix, the current value of the light emission drive current that flows through the organic EL element OEL is controlled to perform the light emission operation at a desired luminance gradation. The circuit configuration of was shown. The present invention is not limited to this, and by adjusting (specifying) the current value of the current written to each display pixel PIX according to the gradation of the display data, the light emission drive current to be passed through the organic EL element OEL is adjusted. It may have a circuit configuration of a current designation type gradation control system in which a current value is controlled to perform light emission operation at a desired luminance gradation.

(Device structure of display pixel)
Next, a specific device structure (planar layout and cross-sectional structure) of the display pixel (light emission drive circuit and organic EL element) having the circuit configuration as described above will be described. Here, an organic EL display panel having a bottom emission type light emitting structure in which light emitted from the organic EL layer is emitted to the viewing side (the other surface side of the insulating substrate) through the insulating substrate will be described.

  FIG. 4 is a plan layout diagram illustrating an example of display pixels applicable to the display panel according to the present embodiment. Here, the planar layout of one specific color pixel among the red (R), green (G), and blue (B) color pixels PXr, PXg, and PXb of the display pixel PIX shown in FIGS. Indicates. In FIG. 4, the layer in which each transistor, wiring, and the like of the pixel driving circuit DC shown in FIG. 3 are formed is mainly shown, and the exposed areas of the electrodes, wiring layers, and pixel electrodes of each transistor are clarified. Therefore, hatching is shown for convenience.

  5 and 6 are cross-sectional views of the main part of the display panel according to this example. Here, FIG. 5A and FIG. 5B each show a VA-VA line (in this specification, the Roman numerals “A” shown in FIG. 4) in the display pixel having the planar layout shown in FIG. For convenience, “V” is used as a symbol corresponding to “5”. The same applies hereinafter) and a schematic cross-sectional view showing a cross section taken along the line VB-VB. 6A is a VIC-VIC line in the display pixel having the planar layout shown in FIG. 4 (in this specification, as a symbol corresponding to the Roman numeral “6” shown in FIGS. 1 and 4). FIG. 6 is a schematic cross-sectional view showing a cross section along “VI”. FIG. 6B is a schematic cross-sectional view showing a cross section taken along the line VID-VID in the display panel having the planar layout shown in FIG.

  Specifically, each color pixel PXr, PXg, PXb forming the display pixel PIX shown in FIG. 3 is provided for each pixel formation region Rpx set on one surface side of the insulating substrate 11 as shown in FIG. It has been. In this pixel formation region Rpx, at least the formation region (EL element formation region; details will be described later) Rel of the organic EL elements OEL of the color pixels PXr, PXg, and PXb and the boundary regions between the color pixels PXr, PXg, and PXb And are set. A selection line Ls and a power supply voltage line La are arranged in the edge region above and below the pixel formation region Rpx so as to extend in the row direction (left-right direction in FIG. 4), respectively. In the right edge region of the pixel formation region Rpx in the drawing, the data line Ld extends in the column direction (vertical direction in FIG. 4) so as to be orthogonal to the selection line Ls and the power supply voltage line La. Is arranged. In addition, as shown in FIG. 4 and FIG. 5A, the border region set in the left and right edge regions of the pixel formation region Rpx extends across the color pixels arranged adjacent to each other in the left-right direction. The partition wall layer 17 is disposed so as to extend in the column direction. On the other hand, in the boundary region set in the upper and lower edge regions of the pixel formation region Rpx, as shown in FIG. 4 and FIG. The insulating film 13 is exposed. A region surrounded by the side wall 17e of the partition wall layer 17 and the opening 13e of the insulating film 13 and exposing the pixel electrode 14 (shown by hatching for convenience in FIG. 4) is defined as an EL element formation region Rel. Has been.

  Here, the data line Ld is provided on the lower layer side (insulating substrate 11 side) than the selection line Ls and the power supply voltage line La, for example, as shown in FIGS. 4, 5A, and 5B. . The data line Ld is formed in the same process as the gate electrode by patterning the gate metal layer for forming the gate electrodes (first electrodes) Tr11g and Tr12g of the transistors (functional elements) Tr11 and Tr12. As shown in FIG. 4, the data line Ld is connected to the drain electrode Tr11d of the transistor Tr11 through a contact hole CH1 provided in a gate insulating film (first insulating film) 12 formed thereon. Has been.

  The selection line Ls and the power supply voltage line La are source and drain metal layers for forming source electrodes (second electrodes) Tr11s and Tr12s and drain electrodes (second electrodes) Tr11d and Tr12d of the transistors Tr11 and Tr12. Is formed in the same process as the source electrode and the drain electrode. As shown in FIG. 4, the selection line Ls is connected to the gate electrode Tr11g of the transistor Tr11 via a contact hole CH2 provided in the lower gate insulating film 12. The power supply voltage line La is formed integrally with the drain electrode Tr12d of the transistor Tr12.

  Here, although the selection line Ls and the power supply voltage line La are not shown, the selection line Ls and the power supply voltage line La may have a laminated structure of a plurality of wiring layers such as a lower layer wiring and an upper layer wiring provided on the lower layer wiring. The lower layer wiring reduces, for example, a transition metal layer for reducing migration such as chromium (Cr) or titanium (Ti), and wiring resistance of an aluminum simple substance or aluminum alloy provided on the transition metal layer. Therefore, a laminated structure of a low resistance metal layer can be applied. In addition, the upper layer wiring is on a single layer of low resistance metal such as aluminum simple substance or aluminum alloy or a transition metal layer for reducing migration of chromium (Cr) or titanium (Ti). A laminated structure provided with the low-resistance metal layer can be applied.

  Further, the transistors Tr11 and Tr12 of the pixel drive circuit DC shown in FIG. 3 are specifically arranged so as to extend in the column direction along the data line Ld as shown in FIG. That is, the channel width direction of the transistors Tr11 and Tr12 is set in parallel to the data line Ld.

  Here, each of the transistors Tr11 and Tr12 has a field effect thin film transistor structure. That is, the transistors Tr11 and Tr12 are formed in regions corresponding to the gate electrodes Tr11g and Tr12g via the gate electrodes Tr11g and Tr12g and the gate insulating film 12, respectively, as shown in FIGS. A semiconductor layer SMC, and source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d formed to extend to both ends of the semiconductor layer SMC.

  As shown in FIG. 5A, a channel protective layer BL is formed on the semiconductor layer SMC where the source electrodes Tr11s and Tr12s of the transistors Tr11 and Tr12 face each other and the drain electrodes Tr11d and Tr12d face each other. The channel protective layer BL is formed of silicon oxide, silicon nitride, or the like, and has a function of preventing damage such as etching to the semiconductor layer SMC. Further, impurity layers OHM are formed between the source electrodes Tr11s and Tr12s, the drain electrodes Tr11d and Tr12d, and the respective semiconductor layers SMC. The impurity layer OHM is formed of an amorphous silicon layer containing n-type impurities and has a function of realizing ohmic connection between the semiconductor layer SMC and the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d.

  Then, so as to correspond to the circuit configuration of the pixel drive circuit DC shown in FIG. 3, the transistor Tr11 is selected through the contact hole CH2 in which the gate electrode Tr11g is provided in the gate insulating film 12, as shown in FIG. It is connected to the line Ls. The drain electrode Tr11d of the transistor Tr11 is connected to the data line Ld through a contact hole CH1 provided in the gate insulating film 12. Further, the source electrode Tr11s of the transistor Tr11 is connected to the gate electrode Tr12g of the transistor Tr12 through a contact hole CH3 provided in the gate insulating film 12, as shown in FIG.

  As shown in FIGS. 4 and 6A, the transistor Tr12 has a gate electrode Tr12g connected to the source electrode Tr11s of the transistor Tr11 through a contact hole CH3 provided in the gate insulating film 12. Are directly connected to the lower electrode Eca of the capacitor Cs. Further, as shown in FIG. 4, the drain electrode Tr12d of the transistor Tr12 is formed integrally with the power supply voltage line La. Further, as shown in FIGS. 4 and 5A, the source electrode Tr12s of the transistor Tr12 is directly connected to the pixel electrode 14 of the organic EL element OEL that also serves as an upper electrode Ecb of the capacitor Cs described later.

  Here, in the display panel 10 according to the present embodiment, at least the source and drain metal layers to be the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 are, for example, molybdenum-niobium (MoNb) or the like. It is made of an alloy. Thus, the selection line Ls and the power supply voltage line La formed simultaneously with the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 are also formed of an alloy such as molybdenum-niobium (MoNb). As will be described in detail later, the upper electrode portion of the external junction terminal TMi formed simultaneously with the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 and the contact electrode Ect of the cathode contact portion are also molybdenum-niobium. It is made of an alloy such as (MoNb). Similarly, for example, an alloy such as molybdenum-niobium (MoNb) can be applied to the gate metal layers to be the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12. As a result, the lower electrode portion of the data line Ld and the external junction terminal TMi is also formed of the same material.

  The capacitor Cs is interposed between the lower electrode Eca, the upper electrode Ecb facing the lower electrode Eca, and the lower electrode Eca and the upper electrode Ecb, as shown in FIGS. 4, 5A, and 6A. And a gate insulating film 12 to be operated. Here, the gate insulating film 12 is also used as a dielectric layer of the capacitor Cs. The upper electrode Ecb also serves as the pixel electrode 14 of the organic EL element OEL described later. That is, the capacitor Cs is provided on the lower layer side (insulating substrate 11 side) of the organic EL element OEL.

  As shown in FIGS. 4, 5A, and 5B, the organic EL element OEL includes a pixel electrode (for example, an anode electrode; a third electrode) 14 and an organic EL layer (a light emitting functional layer; a display functional layer). 15 and a counter electrode (for example, a cathode electrode; a fourth electrode) 16 are sequentially stacked. The pixel electrode 14 is provided on the gate insulating film 12 of the transistors Tr11 and Tr12, and also serves as the upper electrode Ecb of the capacitor Cs as described above. Further, the pixel electrode 14 is directly connected to the source electrode Tr12s of the transistor Tr12, and a predetermined light emission drive current is supplied from the pixel drive circuit DC. The organic EL layer 15 is formed on the pixel electrode 14 exposed to the EL element formation region Rel defined by the opening 13e of the insulating film 13 formed on the insulating substrate 11 and the side wall 17e of the partition wall layer 17. The organic EL layer 15 includes, for example, a hole transport layer 15a (carrier transport layer) and an electron transport light emitting layer 15b (carrier transport layer).

  The counter electrode 16 is provided so as to face the pixel electrode 14 of each display pixel PIX arranged two-dimensionally on the insulating substrate 11 in common. The counter electrode 16 is formed of a single electrode layer (solid electrode) so as to correspond to, for example, the display region 20 of the insulating substrate 11. Further, the counter electrode 16 is provided so as to extend not only on the EL element formation region Rel of each display pixel PIX but also on the insulating film 13 and the partition wall layer 17 that define the EL element formation region Rel. Further, the counter electrode 16 is provided so as to extend to the peripheral region 30 outside the display region 20, and as shown in FIGS. 1 and 6B, a contact electrode (fifth electrode) disposed in the peripheral region 30 is provided. Electrode) Ect is electrically connected through a contact hole (opening) CH4 provided in the insulating film 13. Thus, a predetermined reference voltage Vss (cathode voltage; for example, ground potential Vgnd) is applied to the counter electrode 16 through the contact electrode Ect.

  Here, the contact electrode Ect is formed by patterning the source and drain metal layers for forming the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 described above. In the same process, it is formed using an alloy such as molybdenum-niobium (MoNb). Further, since the display panel 10 according to the present embodiment has a bottom emission type light emitting structure, the pixel electrode 14 is formed of a transparent electrode material having light transmission characteristics such as ITO. On the other hand, the counter electrode 16 is formed of an electrode material having light reflection characteristics such as aluminum (Al) alone or an aluminum alloy.

  As shown in FIG. 1, the partition wall layer 17 includes at least the display panel 10 (insulating properties) among the boundary regions between the plurality of display pixels PIX (each color pixel PXr, PXg, PXb) two-dimensionally arranged on the display panel 10. A plurality of strips are arranged in stripes so as to extend in the column direction of the substrate 11). On the other hand, as shown in FIGS. 1, 5, and 6, the insulating film (second insulating film) 13 forms a boundary region between the display pixels PIX (the color pixels PXr, PXg, and PXb) in the display region 20. It is provided on the insulating substrate 11 so as to cover it. Thus, the transistors Tr11 and Tr12 are disposed at the end portions of the pixel formation regions Rpx of the display panel 10 so as not to be completely covered with the insulating film 13 and the partition layer 17 and exposed.

  Further, as shown in FIGS. 1, 4 and 5B, the insulating film 13 has two opposite sides in the column direction of the exposed region of each pixel electrode 14 which is the EL element forming region Rel of each color pixel. An opening 13e is provided for demarcating (the two sides on the upper and lower sides in FIGS. 1 and 4 and corresponding to the two sides on the left and right sides in FIG. 5B). Further, as shown in FIGS. 1, 4 and 5A, two opposite sides (in the row direction) of the exposed region of each pixel electrode 14 are formed by the side wall 17e of the partition wall layer 17 arranged adjacent to each other. 1 and 4 (corresponding to the left and right sides in FIG. 5A) are defined. Thereby, a region defined by the insulating film 13 and the partition layer 17 (exposed region of the pixel electrode 14; hatched in FIG. 4 for convenience) is defined as the EL element formation region Rel of the display pixel PIX. . And the area | region containing this EL element formation area Rel is prescribed | regulated as an application | coating area | region of the organic compound material at the time of forming the organic EL layer 15 (The hole transport layer 15a and the electron transport light emitting layer 15b).

  On the other hand, in the peripheral region 30 of the display region 20, at least the insulating film 13 is provided so as to cover the insulating substrate 11. As shown in FIGS. 1 and 6B, the insulating film 13 in the peripheral region is provided with a contact hole CH4 from which the contact electrode Ect is exposed and an opening 13t from which the external junction terminal TMi is exposed. Yes.

  The partition layer 17 is formed by, for example, laminating a photosensitive resin material on the insulating substrate 11. Here, for example, at the time before the organic compound-containing liquid is applied to the EL element forming region Rel, at least the surface (side surface and upper surface) of the partition layer 17 is applied to the organic compound-containing liquid to be applied. And surface treatment is performed so as to have liquid repellency. On the other hand, at this time, the surface of the pixel electrode 14 of the organic EL element OEL is subjected to surface treatment so as to be lyophilic with respect to the organic compound-containing liquid.

  In addition, an insulating substrate 11 on which the pixel driving circuit DC, the organic EL element OEL (the pixel electrode 14, the organic EL layer 15, and the counter electrode 16), the insulating film 13, and the partition wall layer 17 are formed is insulated. The sealing layer 18 is formed except for the external joint terminals TMi exposed at the openings 13t of the film 13, and the display panel 10 is sealed. Here, in addition to or instead of the sealing layer 18, a sealing structure in which a sealing substrate such as a metal cap (sealing lid) or glass (not shown) is bonded is applied. You can also.

  In the above-described device structure, the data line Ld is formed by patterning the gate metal layer, the selection line Ls is formed by patterning the source and drain metal layers, and the data line Ld and the selection line Ls are formed. However, the description has been given of the case of connecting to the drain electrode Tr11d and the gate electrode Tr11g of the transistor Tr11 through the contact holes CH1 and CH2, respectively. The present invention is not limited to this, the data line Ld is formed by patterning the source and drain metal layers instead of the gate metal layer, and the selection line Ls is patterned by replacing the gate metal layer with the gate metal layer. Thus, it may be formed integrally with the drain electrode Tr11d and the gate electrode Tr11g of the transistor Tr11 without passing through the contact holes CH1 and CH2. However, since it is necessary to form the power supply voltage line La by patterning the gate metal layer at this time, it is necessary to form a contact hole between the power supply voltage line La and the drain electrode Tr12d of the transistor Tr12.

  In the display pixel PIX having such a device structure, the light emission driving current having a predetermined current value is supplied to the source of the transistor Tr12 based on the gradation signal Vpix corresponding to the display data supplied via the data line Ld. By flowing between the drains and being supplied to the pixel electrode 14, the organic EL element OEL emits light with a desired luminance gradation according to the display data.

  At this time, since the pixel electrode 14 of the display panel 10 has a light transmission characteristic and the counter electrode 16 has a light reflection characteristic (that is, the organic EL element OEL is a bottom emission type), each display pixel PIX. Light emitted from the organic EL layer 15 of each color pixel PXr, PXg, and PXb is reflected directly through the pixel electrode 14 having light transmission characteristics or reflected by the counter electrode 16 having light reflection characteristics, thereby insulating the light. The light passes through the substrate 11 and is emitted to the other side of the insulating substrate 11 that is the visual field side (downward in FIGS. 5A and 5B).

  In the present embodiment, a panel structure in which the partition wall layers 17 are arranged in a striped manner so as to extend at least in the column direction (vertical direction in FIG. 1) in the display region 20 is shown. It is not limited to this. For example, the display region 20 has a panel structure in which partition walls 17 are formed in a lattice shape in the upper, lower, left, and right boundary regions of each display pixel PIX so that only the pixel electrode 14 of each display pixel PIX is exposed. It may be. Further, the peripheral region 30 may have a panel structure in which the partition layer 17 is formed on the insulating substrate 11 so that only the contact electrode Ect and the external junction terminal TMi are exposed.

(Manufacturing method of display device)
Next, a method for manufacturing the display panel according to this example will be described.
7 to 11 are process cross-sectional views illustrating a display panel manufacturing method according to this embodiment. Here, for convenience of explanation, for the sake of convenience, the cross section of the display pixel along the line VA-VA of FIG. 4 shown in FIG. 5A is arranged on the right side of each of FIGS. 6A is a cross-sectional view of the connection portion of the transistors Tr11 and Tr12 along the VIC-VIC line of FIG. 4 and FIG. 6B is a cross-sectional view of the cathode contact portion along the VID-VID line of FIG. The section VIEI-VIIE in the display panel 10 shown in FIG. 1 (in this specification, “VII” is used as a symbol corresponding to the Roman numeral “7” shown in FIG. 1 for convenience. A cross section of the external connection terminal along the same line is shown on the left side of each of FIGS.

  In the manufacturing method of the display device (display panel) described above, first, as shown in FIGS. 7A to 9A, the pixel drive circuit DC described above is formed on one surface side of the insulating substrate 11 such as a glass substrate. Functional elements such as the transistors Tr11 and Tr12 and the capacitor Cs constituting the circuit (see FIGS. 3 and 4) and wiring layers such as the data line Ld, the selection line Ls, and the power supply voltage line La are formed.

  Specifically, first, as shown in FIG. 7A, pixels of the display pixels PIX (color pixels PXr, PXg, and PXb) set on one surface side (upper surface side of the drawing) of the transparent insulating substrate 11. For each region corresponding to the EL element formation region Rel in the formation region Rpx, the lower electrode Eca of the capacitor Cs is formed. Here, the lower electrode Eca is formed by depositing a transparent electrode material film such as ITO or zinc-doped indium oxide (indium zinc oxide) and then patterning it by photolithography.

  Next, as shown in FIG. 7B, the same gate metal layer formed on one surface side of the insulating substrate 11 is patterned by using a photolithography method, so that the region other than the EL element formation region Rel is formed. The gate electrodes Tr11g and Tr12g and the data line Ld are formed simultaneously. At this time, as shown in FIGS. 4, 6A and 7B, the gate electrode Tr12g and the lower electrode Eca are patterned and formed so that one end of the gate electrode Tr12g extends on the lower electrode Eca. Are electrically connected. At this time, the lower layer electrode portion TMa of the external junction terminal TMi is simultaneously formed in the end region of the insulating substrate 11 outside the display region 20. Here, an alloy such as molybdenum-niobium (MoNb) is preferably used for the gate metal layer for forming the gate electrodes Tr11g, Tr12g, the data line Ld, and the lower electrode portion TMa of the external junction terminal TMi. When MoNb is used as a gate electrode, it is etched with an ITO etchant. Therefore, it is desirable to form MoNb after patterning the lower electrode Eca.

  Note that the lower layer electrode portion TMa constituting the external junction terminal TMi is connected to the data line Ld formed simultaneously in the step of patterning the gate metal layer via a lead wiring (noted in FIG. 2) (not shown). Electrically connected. Here, the lower layer electrode portion TMa and the routing wiring Lh may be formed integrally with the data line Ld by patterning the gate metal layer.

  Next, a gate insulating film 12 made of silicon nitride or the like, a semiconductor film SMCx made of intrinsic amorphous silicon or the like, and an insulating film made of silicon nitride or the like are continuously formed over the entire area of the insulating substrate 11. After that, as shown in FIG. 7C, the insulating film such as silicon nitride is patterned using a photolithography method, so that a channel protective layer is formed in a region corresponding to the gate electrodes Tr11g and Tr12g on the semiconductor film SMCx. BL is formed.

  Next, after an impurity layer made of n-type amorphous silicon or the like is deposited on the entire surface of the insulating substrate 11, the photolithography method is used on both sides of the channel protective layer BL on the semiconductor film SMCx at the position to be the semiconductor layer SMC. The impurity layer OHM is formed by patterning so as to leave the impurity layer, and then the semiconductor film SMCx is patterned so as to leave below the impurity layer OHM and the channel protective layer BL. Thus, as shown in FIG. 8A, the semiconductor layer SMC and the impurity layer OHM for ohmic connection are formed at both ends of the semiconductor layer SMC.

  Next, after depositing a transparent electrode material film such as ITO or zinc-doped indium oxide over the entire area of the insulating substrate 11, the electrode material film is patterned using a photolithography method. As shown in FIG. 8B, a pixel electrode 14 having, for example, a rectangular planar pattern is formed on the gate insulating film 12 for each EL element formation region Rel of each display pixel PIX (pixel electrode formation step). As a result, the capacitor Cs in which the pixel electrode 14 and the lower electrode Eca are arranged to face each other through the gate insulating film 12 is formed (capacitor forming step). That is, the pixel electrode 14 is an anode electrode of the organic EL element OEL, and is also used as the upper electrode Ecb facing the lower electrode Eca, and the gate insulating film 12 is also used as a dielectric layer.

  As described above, since the upper electrode Ecb (pixel electrode 14) and the lower electrode Eca of the capacitor Cs are formed of a transparent electrode material, even a display panel having a bottom emission type light emitting structure has a high aperture ratio. Can be realized. Note that the thickness of the gate insulating film 12 interposed between the upper electrode Ecb (pixel electrode 14) and the lower electrode Eca is as thin as possible in order to flow a large current (light emission drive current) to the transistor Tr12. However, if the gate insulating film 12 is too thin, there is a high possibility of causing a vertical short circuit at the intersection of the data line Ld below the gate insulating film 12 and an upper selection line Ls or power supply voltage line La described later. As a result, the product yield is reduced. In view of such a trade-off with the product yield, the thickness of the gate insulating film 12 is set in a range of approximately 200 nm to 400 nm in terms of silicon nitride film, thereby improving the product yield and reducing the capacitance of the capacitor Cs. It was found that the capacitance could be set sufficiently large and good display characteristics could be realized.

  Next, as shown in FIG. 8C, the contact holes shown in FIG. 4 are formed in the gate insulating film 12 so that the upper surfaces of the data lines Ld and the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12 at predetermined positions are exposed. Each of CH1, CH2, and CH3 is formed, and an opening 12t is formed in the gate insulating film 12 on the lower electrode portion TMa. Thus, since the contact holes CH1 to CH3 are formed after the pixel electrode 14 is formed by patterning an electrode material film such as ITO, the contact holes CH1 to CH3 are not formed when the pixel electrode 14 is patterned. . Therefore, the etchant for patterning the pixel electrode 14 is not etched in the gate metal layer exposed by the contact holes CH1 to CH3.

  Next, as shown in FIG. 9A, the same source and drain metal layers formed on one surface side of the insulating substrate 11 are patterned using a photolithographic method, whereby the semiconductor layers SMC of the transistors Tr11 and Tr12. The source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d are formed at both ends of the contact electrode Ect through the impurity layer OHM, and the contact electrode Ect, the intermediate electrode layer TMb, the selection line Ls, and the power supply voltage line La is formed simultaneously.

  At this time, as shown in FIG. 4, the drain electrode Tr11d of the transistor Tr11 is electrically connected to the lower data line Ld through the contact hole CH1 formed in the gate insulating film 12. Further, the source electrode Tr11s of the transistor Tr11 is electrically connected to the gate electrode Tr12g of the lower transistor Tr12 through a contact hole CH3 formed in the gate insulating film 12. The source electrode Tr12s of the transistor Tr12 is formed so that one end thereof extends on the pixel electrode 14 formed on the gate insulating film 12, and the source electrode Tr12s and the pixel electrode 14 are electrically connected. The selection line Ls is electrically connected to the lower gate electrode Tr11g through the contact hole CH2 formed in the gate insulating film 12. The power supply voltage line La is formed integrally with the source electrode Tr12s.

  In the step of patterning the source and drain metal layers, the contact electrode Ect is simultaneously formed on the gate insulating film 12 at a predetermined position in the peripheral region 30 as shown in FIGS. At the same time, the intermediate electrode layer TMb is simultaneously formed so as to be electrically connected to the lower layer electrode portion TMa through the opening 12t formed in the gate insulating film 12 in the end region of the insulating substrate 11.

Here, the source for forming the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12, the selection line Ls, the power supply voltage line La, the contact electrode Ect, and the intermediate electrode layer TMb of the external junction terminal TMi. The drain metal layer is formed of a material having a low contact resistance with a metal material used for the counter electrode 16 described later, for example, an alloy material such as molybdenum-niobium (MoNb). As described later, aluminum (Al) is usually used for the counter electrode. The contact resistance per 100 μm ² apparent area between Al and MoNb is 10 Ω or less, sufficiently lower than the contact resistance of 20 kΩ or more per 100 μm ² apparent area between Al and ITO, and good display characteristics Is obtained. The reason why the contact resistance between Al and ITO is high is that Al is easily oxidized by being combined with oxygen in the ITO, thereby forming an insulating film.

  Note that the intermediate electrode layer TMb constituting the external junction terminal TMi is a selection line that is simultaneously formed in the step of patterning the source and drain metal layers via routing wiring (noted in FIG. 2). Ls, power supply voltage line La, and contact electrode Ect are electrically connected. Here, the intermediate electrode layer TMb and the routing wiring Lh may be formed integrally with the selection line Ls, the power supply voltage line La, and the contact electrode Ect by patterning the source and drain metal layers. .

  Next, the insulating film 11 is made of an inorganic insulating material such as silicon nitride or silicon oxide so as to cover the entire area of one surface of the insulating substrate 11 including the pixel electrode 14, the transistors Tr11 and Tr12, the selection line Ls, and the power supply voltage line La. Then, an insulating film 13 that functions as an interlayer insulating film or a protective insulating film is formed. Thereafter, the insulating film 13 is patterned, and as shown in FIGS. 1 and 9B, an opening 13e through which the upper surfaces of the pixel electrode 14, the contact electrode Ect, and the intermediate electrode layer TMb of each display pixel PIX are exposed. The contact hole CH4 and the opening 13t are formed. Here, the transistors Tr11 and Tr12, the selection line Ls, the power supply voltage line La, and the routing wiring Lh are completely covered with the insulating film 13.

  Next, after applying a photosensitive organic resin material such as polyimide or acrylic on the insulating substrate 11 on which the insulating film 13 is formed, a resin layer having a film thickness of 1 to 5 μm, for example, is formed. By patterning the resin layer, at least as shown in FIG. 10A, the display region 20 protrudes to one surface side of the insulating substrate 11, and as shown in FIGS. A partition wall layer 17 extending in a striped pattern is formed (up and down direction in FIG. 1) (partition wall layer forming step). Here, the partition wall layer 17 is slightly wider than the width of the insulating film 13 extending in the column direction at a portion in contact with the insulating film 13 extending in the column direction, and is an opening serving as a side wall of the insulating film 13 extending in the column direction. 13e is covered, the insulating film 13 formed in the boundary region between the adjacent display pixels PIX arranged in the row direction (left-right direction in FIG. 1) of the display region 20 is completely covered. Further, the partition wall layer 17 is not formed in a boundary region between the plurality of display pixels PIX adjacent in the column direction of the display region 20, and the insulating film 13 is exposed in the region. The partition wall layer 17 is also formed in a boundary region between a plurality of display pixels PIX adjacent to each other in the column direction of the display region 20, and covers the periphery in the column direction and the row direction for each color pixel PXr, PXg, PXb. It may be formed as follows.

  As a result, in each pixel formation region Rpx, opposite ends in the column direction (vertical direction in FIG. 4) of the openings 13e formed in the insulating film 13 and the row direction of the partition wall layer 17 (horizontal direction in FIG. 4). A region surrounded by the opposite side wall 17e, that is, an exposed region of the pixel electrode 14 is defined as an EL element formation region Rel. Here, as the photosensitive organic resin material for forming the partition wall layer 17, for example, polyimide coating material “Photo Nice PW-1030” or “Photo Nice DL-1000” manufactured by Toray Industries, Inc. can be preferably applied. it can.

  Next, after the insulating substrate 11 is washed with pure water, it is exposed to at least each EL element forming region Rel defined by the insulating film 13 and the partition wall layer 17 by performing, for example, oxygen plasma treatment or UV ozone treatment. The surface of the pixel electrode 14 to be processed is made lyophilic with respect to the organic compound-containing liquid of the hole transport material and the electron transporting light emitting material used in the carrier transport layer forming process described later (lyophilic process).

  As described above, the region where the organic compound-containing liquid is applied is defined by the insulating film 13 and the partition wall layer 17, and in addition, the surface of the pixel electrode 14 of each display pixel PIX (organic EL element OEL) is made lyophilic. In the carrier transport layer forming step, the organic compound-containing liquid is applied by using a nozzle printing method or an ink jet method to form a light emitting layer (electron transporting light emitting layer 15b) of the organic EL layer 15. It is possible to suppress the leakage and overcoming of the organic compound-containing liquid to the EL element formation region Rel of the display pixels PIX of different colors arranged adjacent to each other in the row direction of the panel 10, and prevent color mixing between adjacent pixels. Thus, the red, green, and blue light-emitting materials can be satisfactorily applied separately.

  In this embodiment, only the step of making the surface of the pixel electrode 14 lyophilic has been described. However, the present invention is not limited to this, and at least the partition wall after the lyophilic treatment of the surface of the pixel electrode 14 described above. A treatment for making the surface of the layer 17 lyophobic may be applied. Specifically, the insulating substrate 11 is subjected to plasma treatment (fluorine carbide gas plasma treatment), for example, in a fluorine gas atmosphere, thereby further repelling the surface of the partition wall layer 17 with respect to the organic compound-containing liquid. (Liquid repellency process). According to this, it is possible to realize a substrate surface in which the surface of the partition wall layer 17 has high liquid repellency and the surface of the pixel electrode 14 exposed in each EL element formation region Rel has high lyophilicity. Therefore, it is possible to further suppress the phenomenon that the organic compound-containing liquid applied to the surface of the insulating substrate 11 in the carrier transport layer forming step rushes to the side wall 17e of the partition wall layer 17, and is sufficiently familiar with the surface of the pixel electrode 14. Therefore, the organic EL layer 15 (each layer of the hole transport layer 15a and the electron transport light emitting layer 15b) having a substantially uniform film thickness can be formed over the entire area on the pixel electrode 14.

  In addition, “liquid repellency” used in this example means an organic compound-containing liquid containing a hole transport material to be a hole transport layer, which will be described later, and an electron transport luminescent material to be an electron transport luminescent layer. When the contact angle is measured by dropping the organic compound-containing liquid or the organic solvent used in these solutions onto an insulating substrate and the like, and the contact angle is approximately 50 ° or more, Stipulate. In addition, “lyophilic” as opposed to “liquid repellency” is defined as a state in which the contact angle is approximately 40 ° or less, preferably approximately 10 ° or less in the present embodiment.

  Next, as shown in FIG. 10B, the nozzle printing (or nozzle coating) method in which a continuous solution (liquid flow) is discharged to the EL element forming regions Rel of the respective colors in the display region 20 or separated from each other. After applying a solution or dispersion of a hole transport material using an inkjet method or the like that discharges a plurality of discontinuous droplets to a predetermined position, the hole transport layer (carrier transport layer) 15a is formed by heating and drying. Form.

  Specifically, as an organic compound-containing liquid (organic solution) containing an organic polymer-based hole transport material (carrier transport material), for example, a polyethylenedioxythiophene / polystyrene sulfonic acid aqueous solution (PEDOT / PSS; conductive polymer) A polyethylenedioxythiophene PEDOT and a dispersion of polystyrene sulfonate PSS as a dopant in an aqueous solvent are applied onto the pixel electrode 14. After that, the stage on which the insulating substrate 11 is placed is heated under a temperature condition of 100 ° C. or higher and dried to remove the residual solvent, whereby the pixel electrode 14 exposed to each EL element formation region Rel is removed. The hole transport layer 15a as the carrier transport layer is formed by fixing the organic polymer-based hole transport material only on the substrate.

  Here, the upper surface of the pixel electrode 14 exposed in each EL element formation region Rel is lyophilic with respect to the organic compound-containing liquid containing the hole transport material by the lyophilic treatment, and thus is applied. The organic compound-containing liquid spreads well on the pixel electrode 14. On the other hand, the partition wall layer 17 is formed sufficiently high with respect to the liquid level of the organic compound-containing liquid (PEDOT / PSS) to be applied, and generally has liquid repellency with respect to the organic compound-containing liquid. Therefore, leakage of the organic compound-containing liquid into the EL element formation region Rel of the adjacent display pixel PIX can be prevented.

  Next, as shown in FIG. 10B, for each color EL element formation region Rel, using a nozzle printing method or an ink jet method, a solution of an electron transporting luminescent material on the hole transport layer 15a or After the dispersion is applied, it is heated and dried to form an electron transporting light emitting layer (carrier transporting layer) 15b.

  Specifically, as an organic compound-containing liquid (organic solution) containing an organic polymer-based electron transporting light emitting material (carrier transporting material), for example, a conjugated double bond polymer such as polyparaphenylene vinylene or polyfluorene. 0.1 wt% to 5 wt% of red (R), green (G), and blue (B) luminescent materials containing benzene, dissolved or dispersed in an aqueous solvent or an organic solvent such as tetralin, tetramethylbenzene, mesitylene, and xylene as appropriate. % Solution is applied on the hole transport layer 15a. Thereafter, the stage is heated in a nitrogen atmosphere and dried to remove the residual solvent, thereby fixing the organic polymer-based electron-transporting light-emitting material on the hole-transporting layer 15a, and the carrier-transporting layer. And the electron transporting light emitting layer 15b which is also the light emitting layer.

Here, since the surface of the hole transport layer 15a formed in the EL element formation region Rel is lyophilic with respect to the organic compound-containing liquid containing the electron transporting light emitting material, each EL element The organic compound-containing liquid applied to the formation region Rel spreads well on the hole transport layer 15a. On the other hand, the partition wall layer 17 is set sufficiently high with respect to the height of the organic compound-containing liquid to be applied, and generally has liquid repellency with respect to the organic compound-containing liquid. It is possible to prevent the organic compound-containing liquid from leaking out and over the EL element forming region Rel of the display pixel PIX.
In this manner, the organic EL layer (light emitting functional layer) 15 is formed by sequentially stacking the hole transport layer 15a and the electron transporting light emitting layer 15b on the pixel electrode 14 (carrier transport layer forming step).

  Next, as shown in FIG. 11 (a), light reflection characteristics are provided on the insulating substrate 11 on which the partition wall layer 17 and the organic EL layer 15 (the hole transport layer 15a and the electron transport light emitting layer 15b) are formed. A common counter electrode (for example, cathode electrode) 16 is formed to face each pixel electrode 14 via the organic EL layer 15 in each EL element formation region Rel (counter electrode forming step).

  Here, in this embodiment, the counter electrode 16 is made of, for example, calcium (Ca), barium (Ba), lithium (Li), or indium (In) having a thickness of 1 to 10 nm by using a vacuum deposition method or a sputtering method. One of the electron injection layer (cathode electrode) 16a having a low work function and any one of aluminum (Al), chromium (Cr), silver (Ag), and palladium (Pd) having a thickness of 100 nm or more, or An electrode structure in which a high work function thin film (feeding electrode) 16b made of an alloy containing at least one of these is laminated can be applied. When forming the counter electrode 16 using the vapor deposition method, first, the electron injection layer 16a is vapor-deposited on the display region 20 including each EL element formation region Rel through the vapor deposition mask, and then using another mask, For example, a high work function thin film 16 b such as aluminum is deposited on the display region 20 and the peripheral region 30.

  At this time, as shown in FIG. 11A, in the vapor deposition mask of the electron injection layer 16a, a portion corresponding to the display region 20 is opened, and a portion and an opening corresponding to the contact hole CH4 in the surrounding peripheral region 30 are opened. Since the portion corresponding to 13t is shielded, the electron injection layer 16a is not deposited on the exposed contact electrode Ect and the exposed intermediate electrode layer TMb, but is formed to extend to the peripheral region 30. The high work function thin film 16 b is directly connected to the lower contact electrode Ect through the contact hole CH 4 formed in the insulating film 13. Further, by patterning the high work function thin film 16b, the upper layer electrode portion TMc connected to the intermediate electrode layer TMb through the opening 13t of the insulating film 13 formed in the end region of the insulating substrate 11 is used. Form. As a result, the external joint terminal TMi composed of the three electrode layers of the lower layer, the middle layer, and the upper layer is formed.

  Next, after the counter electrode 16 is formed, as shown in FIG. 11B, a sealing layer 18 made of a silicon oxide film, a silicon nitride film, or the like is formed on the entire surface of the insulating substrate 11 using a CVD method or the like. Form. Thereafter, an opening is formed in the sealing layer 18 so that the upper surface of the external joint terminal TMi formed in the end region of the insulating substrate 11 is exposed. Thereby, the display panel 10 having the cross-sectional structure (bottom emission type light emitting structure) as shown in FIGS. 5 and 6 is completed. In addition to or in place of the sealing layer 18, a sealing substrate such as a metal cap (sealing lid) or glass may be bonded to the insulating substrate 11. At this time, it can be satisfactorily bonded to the insulating substrate 11 by interposing a UV curing or thermosetting adhesive therebetween.

  Thus, in the display panel and the manufacturing method thereof according to the present embodiment, the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 in each pixel formation region Rpx of the display region 20 and the peripheral region 30 are provided. The contact electrode Ect that is disposed and supplies a predetermined voltage to the counter electrode (for example, cathode electrode) 16 is simultaneously formed by patterning the same source and drain metal layers made of, for example, a molybdenum-niobium (MoNb) alloy. Further, by applying a metal material such as aluminum as the counter electrode 16 (specifically, the high work function thin film 16b) connected to the contact electrode Ect, the contact resistance between the contact electrode Ect and the counter electrode 16 It is characterized by lowering.

(Verification of effects)
Next, the display panel having the above-described features and the functions and effects unique to the manufacturing method thereof will be described in detail.
FIG. 12 is a cross-sectional view of an essential part showing an example of a display panel to be compared with this embodiment. Here, components equivalent to those in the above-described embodiment are denoted by the same reference numerals.

  As shown in FIG. 12A, the display panel to be compared with the present embodiment has a protective insulating film 13a and a protective insulating film 13a on the insulating substrate 11 on which the transistor Tr101 and the wiring layer that are to be the pixel driving circuit DC are formed. An insulating layer 13p made of a flattening film 13b for relaxing the undulations on the surface of the insulating substrate 11 was formed, and a pixel electrode 14 made of ITO or the like was formed on the insulating layer 13p (flattening film 13b). It has a panel structure. The partition layer 17, the organic EL layer 15, and the counter electrode 16p are formed on the insulating layer 13p.

  In the display panel having such a panel structure, external junction terminals (corresponding to TMi in FIGS. 1 and 11B) and cathode contact portions arranged in the peripheral region 30 of the display region 20 are as follows. It has a simple electrode structure.

  An external junction terminal for supplying the selection voltage Ssel for setting the display pixel PIX to the selection state to the selection line Ls and an external junction terminal for supplying the predetermined supply voltage Vdd to the power supply voltage line La are shown in FIG. As shown in b), it has an electrode structure in which a first electrode layer TM1, a second electrode layer TM2, and a third electrode layer TM3 are sequentially laminated. The first electrode layer TM1 is integrated with the selection line Ls and the power supply voltage line La in the same process as the gate electrode Tr101g of the transistor Tr101, for example, by patterning a gate metal layer formed on the insulating substrate 11. Formed.

  The second electrode layer TM2 is formed by patterning the source and drain metal layers formed on the gate insulating film 12 that covers the insulating substrate 11, so that the source electrode Tr101s, the drain electrode Tr101d, and the data line Ld of the transistor Tr101 It is formed in the same process. The second electrode layer TM2 is connected to the first electrode layer TM1 through an opening provided in the gate insulating film 12.

  The third electrode layer TM3 is formed by patterning a transparent electrode layer made of ITO or the like formed on the insulating layer 13p (planarization film 13b) covering the gate insulating film 12 to thereby form the pixel electrode 14 of the organic EL element OEL. It is formed in the same process. The third electrode layer TM3 is connected to the second electrode layer TM2 through an opening provided in the insulating layer 13p.

  The external junction terminals for supplying the gradation signal Vpix corresponding to the display data to the data line Ld are, for example, as shown in FIG. 12C, the second electrode layer TM2 and the third electrode layer TM3. It has a stacked electrode structure.

  The cathode contact portion for supplying a predetermined cathode voltage to the counter electrode 16p of the organic EL element OEL is, for example, as shown in FIG. 12D, the second electrode layer TM2 (FIGS. 1 and 6B). ), The third electrode layer TM3, and the counter electrode 16p are stacked.

  Here, in the external junction terminal and the cathode contact portion, the third electrode layer TM3 is formed to protect the second electrode layer TM2 connected to the lower layer side from etching damage. Specifically, as shown in FIG. 12A, when patterning the pixel electrode 14 made of ITO or the like on the insulating layer 13p including the planarizing film 13b, the inside of the opening formed in the insulating layer 13p. As shown in FIGS. 12B to 12D, the second electrode layer TM2 exposed to the transparent electrode such as ITO used for the pixel electrode 14 is transparent in each opening as shown in FIGS. The electrode material is filled and the second electrode layer TM2 is covered.

  On the other hand, as shown in the above-described embodiments, in a display panel having a bottom emission type light emitting structure, as a high work function thin film material having light reflection characteristics used for the counter electrode 16 of the organic EL element OEL, Aluminum-based metals are generally used.

  That is, as shown in FIG. 12D, in the cathode contact portion, a third electrode layer TM3 made of a transparent electrode material such as ITO formed on the second electrode layer TM2 that is a contact electrode; It has a connection structure in which counter electrodes 16p made of an aluminum-based metal are directly connected.

  However, in general, the contact resistance between the transparent electrode material such as ITO and the aluminum-based metal material is relatively high, and thus the voltage applied to the counter electrode of the organic EL element OEL varies, so that the organic EL element OEL is desired. In this case, there is a problem that the display operation of the display deteriorates because the light emission operation cannot be performed at a luminance of.

  On the other hand, in the display panel 10 according to the present embodiment, as the contact electrode Ect to which the counter electrode 16 of the organic EL element OEL is connected, a conductive material having a low contact resistance with aluminum, for example, molybdenum-niobium (MoNb ) And other alloys are applied, the contact resistance at the cathode contact portion can be made sufficiently low, the voltage applied to the counter electrode can be stabilized, and the display performance of the display can be improved. Has an advantageous effect.

  Further, in the method of manufacturing the display panel 10 according to the present embodiment, the source electrode and the drain metal layer of the contact electrode Ect are patterned, whereby the source electrodes Tr11s and Tr12s of the transistors Tr11 and Tr12 of the pixel drive circuit DC are drained. Since it can form simultaneously in the process of forming electrode Tr11d, Tr12d, favorable display performance can be implement | achieved, suppressing the increase in a manufacturing process.

<Modification of the first embodiment>
FIG. 13 is a cross-sectional view of an essential part showing another configuration example of the display panel according to the first embodiment.
In the same way as in FIG. 12, the display panel having the panel structure as shown in FIGS. 13 (a) and 13 (b) as the embodiment having the structure having the planarizing film 13b has the data line Ld. The following structure can be applied as a capacitor for holding a gradation signal (write voltage) corresponding to display data supplied via the. That is, as the capacitor, the pixel electrode 14 made of a transparent electrode material formed on the insulating layer 13p (planarization film 13b) is also used as one electrode (upper electrode), as shown in FIG. The gate electrode Tr101g of the transistor Tr101 formed in the lower layer of the gate insulating film 12, the wiring layer in the same layer as the power supply voltage line, etc. is used as the other electrode (lower electrode) Eca, and the insulation layer interposed between these electrodes is used. A structure in which the layer 13p and the gate insulating film 12 are also used as a dielectric layer can be applied.

  An external junction terminal for supplying the selection voltage Ssel for setting the display pixel PIX to the selection state to the selection line Ls and an external junction terminal for supplying the predetermined supply voltage Vdd to the power supply voltage line La are shown in FIG. As shown in b), it has an electrode structure in which a second electrode layer TM2 and a third electrode layer TM3 are sequentially laminated.

  The second electrode layer TM2 is formed by patterning the source and drain metal layers formed on the gate insulating film 12 that covers the insulating substrate 11, so that the source electrode Tr101s, the drain electrode Tr101d, and the data line Ld of the transistor Tr101 It is formed in the same process.

  The third electrode layer TM3 is formed by patterning a transparent electrode layer made of ITO or the like formed on the insulating layer 13p (planarization film 13b) covering the gate insulating film 12 to thereby form the pixel electrode 14 of the organic EL element OEL. It is formed in the same process. The third electrode layer TM3 is connected to the second electrode layer TM2 through an opening provided in the insulating layer 13p.

  The external junction terminals for supplying the gradation signal Vpix corresponding to the display data to the data line Ld are, for example, as shown in FIG. 13C, the first electrode layer TM1 and the second electrode layer TM2. It has an electrode structure in which a third electrode layer TM3 is laminated. The first electrode layer TM1 is integrated with the selection line Ls and the power supply voltage line La in the same process as the gate electrode Tr101g of the transistor Tr101, for example, by patterning a gate metal layer formed on the insulating substrate 11. Formed. The first electrode layer TM1 is connected to the second electrode layer TM2 through an opening provided in the gate insulating film 12.

  The cathode contact portion for supplying a predetermined cathode voltage to the counter electrode 16p of the organic EL element OEL is, for example, as shown in FIG. 13D, the second electrode layer TM2 (FIG. 1, FIG. 6B). ), The third electrode layer TM3, and the counter electrode 16p are stacked.

  A wiring layer in the same layer as the source electrode Tr101s, drain electrode Tr101d, etc. of the transistor Tr101 formed on the gate insulating film 12 is used as the other electrode (lower electrode) Eca, and an insulating layer 13p (between these electrodes) A planarization film 13b) or a structure in which the insulating layer 13p and the gate insulating film 12 are also used as a dielectric layer can be applied.

  In such a capacitor structure, since the insulating layer 13p (planarization film 13b) needs to be formed relatively thick in order to reduce the undulations on the surface of the insulating substrate 11, the capacitance of the capacitor is reduced. Cheap.

  On the other hand, in the display panel 10 according to the present embodiment shown in FIG. 5, the gate insulating film 12 formed thinly on the surface of the insulating substrate 11 is used as a dielectric layer, and the gate insulating film 12 is interposed through the gate insulating film 12. It has a capacitor Cs composed of an opposing pixel electrode 14 (upper electrode Ecb) and a lower electrode Eca formed in the same layer as the gate electrodes Tr11g and Tr12g. As a result, the thickness of the gate insulating film 12 can be formed to approximately 200 nm to 400 nm, so that the dielectric layer can be set relatively thin and the capacitance of the capacitor Cs can be set sufficiently large. It is possible to achieve good display characteristics while improving the yield. In other words, since molybdenum-niobium (MoNb) is used for the gate electrodes Tr11g and Tr12g, hillocks generated when an aluminum alloy is used are not generated, and thus the thickness of the gate insulating film 12 can be 400 nm or less. In addition, since the voltage between the upper electrode Ecb and the lower electrode Eca is about several volts, a sufficient breakdown voltage can be obtained if the thickness of the gate insulating film 12 is 200 nm or more.

<Other modifications of the first embodiment>
In this embodiment, the contact electrode Ect connected to the counter electrode (for example, cathode electrode) 16 of the organic EL element OEL and for supplying a predetermined cathode voltage is composed of a single layer of molybdenum-niobium (MoNb). Although the case where the source and drain metal layers are formed by patterning has been described, the present invention is not limited to this. That is, the contact electrode Ect has a two-layer structure of molybdenum-niobium, or a three-layer structure in which a molybdenum-niobium (MoNb) alloy lower layer, an aluminum alloy middle layer, and a molybdenum-niobium (MoNb) alloy upper layer are sequentially stacked. May be.

  In this way, the contact electrode Ect, the routing wiring Lh formed integrally with the contact electrode Ect, and the source electrodes Tr11s and Tr12s of the transistors Tr11 and Tr12 formed simultaneously by patterning the source and drain metal layers. Moreover, the resistance of the wiring can be reduced by forming the drain electrodes Tr11d, Tr12d, the external junction terminals TMi, and the like in a laminated structure.

<Second embodiment>
Next, a second embodiment of the display device according to the present invention will be described.
In the first embodiment described above, the case where the gate insulating film 12 is applied as the dielectric layer constituting the capacitor Cs has been described. However, in the second embodiment, it extends to the formation region of the capacitor Cs. The gate insulating film 12 is removed, and an insulating film 13 that functions as a protective insulating film or an interlayer insulating film is applied as a dielectric layer.

  FIG. 14 is a cross-sectional view of a principal part showing a second embodiment of the display panel according to the present invention. Here, the same components as those in the first embodiment (see FIGS. 1 to 6) are denoted by the same reference numerals, and the equivalent manufacturing method is appropriately referred to FIGS. The description is simplified or omitted. FIG. 14A is a schematic cross-sectional view corresponding to a cross section taken along line VA-VA of the planar layout shown in FIG. FIG. 14B is a schematic cross-sectional view corresponding to a cross section taken along the line VID-VID in the display panel having the planar layout shown in FIG.

  Specifically, as shown in FIG. 14A, the display panel according to the second example includes a gate insulating film 12 interposed between the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12 and the semiconductor layer SMC. Are removed at least in the region corresponding to the EL element formation region Rel of each pixel formation region Rpx. The lower electrode Eca is exposed in the opening 12e from which the gate insulating film 12 has been removed. In addition, an insulating film 13 that functions as a protective insulating film or an interlayer insulating film is formed on the entire area of one surface side of the insulating substrate 11. Here, unlike the first embodiment described above, the insulating film 13 is also formed on the lower electrode Eca exposed in the opening 12e of the gate insulating film 12. A pixel electrode 14 also serving as the upper electrode Ecb is formed on the insulating film 13 in a region corresponding to the lower electrode Eca. That is, the capacitor Cs is formed by disposing the lower electrode Eca and the upper electrode Ecb to face each other with the insulating film 13 interposed therebetween. Similarly to the first embodiment described above, the insulating film 13 and the partition layer 17 formed so as to continuously protrude from the surface of the insulating substrate 11 on which the insulating film 13 is formed are coated. An exposed region (EL element formation region Rel) is defined. A counter electrode 16 is formed on the pixel electrode 14 via an organic EL layer 15 (each of a hole transport layer 15a and an electron transport light emitting layer 15b).

  In other words, in the present embodiment, the dielectric layer is interposed between the lower electrode Eca constituting the capacitor Cs and the pixel electrode 14 which is the upper electrode Ecb so as to cover the entire area of the insulating substrate 11. The panel structure also serves as the insulating film 13. Note that the gate insulating film 12 in the display region 20 is not only in the capacitor Cs formation region (that is, the EL element formation region Rel) but also in the region where the contact holes CH1 to CH3 shown in FIG. 4 are formed. Has been removed. Further, the gate insulating film 12 is removed in the region where the external junction terminal TMi is formed in the peripheral region 30. Therefore, the gate insulating film 12 in the formation region of the capacitor Cs can be removed in the same process when, for example, the contact holes CH1 to CH3 are formed in the gate insulating film 12.

  As shown in FIG. 14A, the pixel electrode 14 is electrically connected to the source electrode Tr12s of the transistor Tr12 through a contact hole CH5 formed in the insulating film 13. An insulating film 19 made of silicon nitride is formed on the pixel electrode 14 and the insulating film 13. On the other hand, the contact electrode Ect for supplying the cathode voltage to the counter electrode 16 of the organic EL element OEL is formed by patterning the semiconductor film SMCx as in the transistors Tr11 and Tr12, as shown in FIG. Semiconductor layer Esmc, impurity layer Eohm formed by patterning an amorphous silicon layer containing n-type impurities for forming impurity layer OHM, and source and drain metal layers made of an alloy such as molybdenum-niobium (Electrode layer) It has an electrode structure in which Esd is sequentially laminated in the same pattern shape. The uppermost source / drain metal layer Esd of the contact electrode Ect is connected to the organic EL element OEL via the contact hole CH4 formed in the insulating film 13 and the insulating film 19, as in the first embodiment. The counter electrode 16 is electrically connected to a thin film 16b having a high work function such as aluminum.

A method for manufacturing the display panel shown in FIGS. 14A and 14B will be described below. About the part which has abbreviate | omitted description, it is the same as that of the above-mentioned Example.
First, after forming the semiconductor film SMCx of the transistors Tr11 and Tr12, an insulating film such as silicon nitride is deposited on the semiconductor film SMCx, and this insulating film is patterned to form the channel protective layer BL. Then, after depositing the amorphous silicon layer containing the impurity, the source and drain metal layers successively, the source, drain metal layer, the amorphous silicon layer containing the impurities, and the semiconductor film SMCx are continuously etched by photolithography, The source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 are formed, and the source / drain metal layer Esd, the impurity layer Eohm, and the semiconductor layer Esmc are formed as the contact electrodes Ect.

  Then, after forming the insulating film 13, a contact hole CH5 is formed in the insulating film 13, and an ITO film is formed. The ITO film is patterned by photolithography to form the pixel electrode 14. At this time, since the contact hole CH4 is not formed in the insulating film 13, the source / drain metal layer Esd is not likely to be eroded by the etchant for etching the ITO film. Subsequently, after the insulating film 19 is deposited, the insulating film 19 in the EL element formation region Rel, the insulating film 19 above the contact electrode Ect and the insulating film 13 therebelow are etched to expose the upper side of the pixel electrode 14 and to contact hole CH14. Form.

  Next, the partition wall layer 17 and the organic EL layer 15 are formed, and the counter electrode 16 is formed. At this time, in the contact electrode Ect, only the thin film 16b of high work function such as aluminum is deposited out of the counter electrode 16 and is in contact with the source / drain metal layer Esd of molybdenum-niobium. Since the layer Esd has a low contact resistance, it can be connected well.

<Modification of Second Embodiment>
FIG. 15 is a cross-sectional view of a main part showing another configuration example of the display panel according to the second embodiment. Here, components equivalent to those in the second embodiment described above are denoted by the same reference numerals, and the description thereof is simplified or omitted.
In the above-described embodiment, when polyimide or the like is applied as the partition wall layer 17, light emission inhibition on the organic EL layer 15 of the organic EL element OEL, such as moisture or by-product, in the partition wall layer 17 material or the partition layer 17 itself. Factors may be included, and thereafter, the characteristics of the formed organic EL layer 15 and the counter electrode 16 are deteriorated.

  On the other hand, as shown in FIGS. 15A and 15B, after the partition layer 17 is formed, the insulating film 19 having excellent shielding properties against light emission inhibiting factors such as silicon nitride or silicon oxide. Is coated on the surface of the partition wall layer 17. Next, the insulating film 19 formed in the EL element formation region Rel, the uppermost source of the contact electrode Ect, and the insulating film 19 and the insulating film 13 on the drain metal layer Esd are continuously etched to expose the pixel electrode 14. At the same time, a contact hole CH4 is formed.

  Then, after forming the organic EL layer 15 in the EL element formation region Rel, the counter electrode 16 is formed on the organic EL layer 15 and the insulating film 19. At this time, in the contact electrode Ect, only the high work function thin film 16b such as aluminum of the counter electrode 16 is deposited on the source / drain metal layer Esd and connected to each other. In such a structure in which the insulating film 19 shields the entire partition wall layer 17, the light emission inhibiting factor extracted from the partition wall layer 17 does not propagate to the organic EL layer 15 and the counter electrode 16, and thus a dark spot that is a non-light-emitting region. Etc., and the light can be emitted well over a long period of time.

Further, the side wall 17e of the partition layer 17 covers the end portion of the insulating film 19, but the end portion of the insulating film 19 protrudes from the side wall 17e of the partition layer 17, and the insulating film 19 sets the opening area of the pixel electrode 14. May be.
The insulating film 19 functions as a base layer that improves the adhesion to the partition wall layer 17, but may not be formed if the insulating film 13 has sufficient adhesion strength. In this case, the contact hole CH4 is formed immediately after the pixel electrode 14 is formed. Thereafter, as in the above embodiment, the partition wall layer 17 is formed, the surface of the pixel electrode 14 is subjected to lyophilic treatment, and the partition wall layer 17 is subjected to lyophobic treatment.

  In the display panel having such a panel structure, as shown in the first embodiment, the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 are formed in the process of forming the transistor Tr12. It is not necessary to pattern the source electrode Tr12s so as to extend over the pixel electrode 14 (see FIGS. 4 and 5A). That is, the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d can be formed in the same pattern shape as the lower impurity layer OHM and the semiconductor layer SMC. Therefore, since at least the amorphous silicon layer containing the n-type impurity to be the source and drain metal layers and the impurity layer OHM and the semiconductor layer SMCx can be patterned at once using the same mask, the number of masks in the manufacturing process The resistance can be further reduced. This manufacturing method can also be applied when forming the contact electrode Ect having the above-described laminated structure.

  Further, as described above, the gate insulating film 13 is limited in film thickness from the viewpoint of the operating characteristics of the transistors Tr11 and Tr12 and the prevention of short circuit between the wiring layers (product yield). When the insulating film 13 is applied as the dielectric layer of the capacitor Cs, the insulating film 13 can be formed thinner than the gate insulating film 12 without affecting the driving characteristics of the pixel driving circuit and the product yield. . Therefore, the capacitance of the capacitor Cs can be set larger, and the display performance of the display can be improved.

<Other Modifications of Second Embodiment>
FIG. 16 is a cross-sectional view of an essential part showing still another configuration example of the display panel according to the second embodiment. Here, components equivalent to those of the second embodiment described above are denoted by the same reference numerals, and description thereof is simplified or omitted.

  In the second embodiment described above, as in the first embodiment (see FIG. 6B), the source / drain metal layer Esd made of an alloy such as molybdenum-niobium is applied to the uppermost layer of the contact electrode Ect. Then, a contact structure in which a high work function thin film 16b such as aluminum constituting the counter electrode 16 of the organic EL element OEL is directly connected through a contact hole CH4 formed in the insulating film 13 is shown. However, the present invention is not limited to this.

  Specifically, as shown in FIG. 16B, the display panel according to this configuration example includes a source and drain metal layer Esd made of an alloy such as molybdenum-niobium of the contact electrode Ect, and the counter electrode 16. An ITO film Eito made of a transparent electrode material such as ITO and an auxiliary wiring layer (first wiring layer) Eass made of an aluminum alloy or the like are interposed between the high work function thin film 16b such as aluminum. Contact structure.

  Here, the ITO film Eito is formed simultaneously with the pixel electrode 14 by patterning the transparent electrode material layer, and is electrically connected to the source and drain metal layers Esd of the contact electrode Ect in the contact hole CH4. The auxiliary wiring layer Eass is made of, for example, a low-resistance aluminum alloy, and is formed so as not to be exposed by covering the ITO film Eito. As a result, the ITO film Eito can be prevented from directly contacting the high work function thin film 16b such as aluminum, and the contact resistance in the cathode contact portion can be lowered.

  Further, as the auxiliary wiring layer Eass connected to both the ITO film Eito and the counter electrode 16 (high work function thin film 16b), a low-resistance aluminum alloy or the like can be applied, so that the uppermost layer of the contact electrode Ect. Insulating substrate 11 as a wiring having a laminated structure in which source and drain metal layers (second wiring layers) Esd made of an alloy such as molybdenum-niobium used in the above are used as a lower wiring layer and the auxiliary wiring layer Eass is used as an upper wiring layer. Can be routed up. According to this, it is possible to realize the routing wiring with reduced wiring resistance, and to further improve the display characteristics of the display.

  In each of the above-described embodiments, the case where a molybdenum-niobium (MoNb) alloy is applied as the source and drain metal layers constituting the contact electrode Ect has been described. However, the present invention is not limited to this. Needless to say, other conductive materials may be used as long as the contact resistance of the counter electrode 16 with the high work function thin film 16b bonded to the upper layer can be lowered.

In each of the above-described embodiments, the case where ITO or zinc-doped indium oxide is applied as the pixel electrode 14 has been described. However, the present invention is not limited to this, and other transparent electrode materials are applied. It may be a thing.
Further, in each of the above-described embodiments, the display panel having the bottom emission type light emitting structure has been described. However, the present invention is not limited to this, and the display panel having the top emission type light emitting structure may be used. Alternatively, the electrode structure or the manufacturing method of the present invention may be applied to a display panel including a light emitting element other than the organic EL element.

  Furthermore, in each Example mentioned above, although the organic EL layer 15 of the organic EL element OEL demonstrated the case where it consists of the positive hole transport layer 15a and the electron transport light emitting layer 15b, this invention is limited to this. Instead, for example, only the hole transport / electron transport luminescent layer may be used, the hole transport luminescent layer and the electron transport layer may be used, the hole transport layer, the electron transport layer and the luminescent layer may be used, and between the layers. A carrier transport layer may be interposed as appropriate, or a combination of other carrier transport layers may be used.

In each of the above-described embodiments, the pixel electrode 14 is an anode electrode and the counter electrode 16 is a cathode electrode. However, the present invention is not limited thereto, and the pixel electrode 14 may be a cathode electrode and the counter electrode 16 may be an anode electrode. At this time, the organic EL layer 15 may be such that the carrier transporting layer in contact with the pixel electrode 14 is an electron transporting layer.
Further, in each of the above-described embodiments, the active drive display panel 10 including the pixel drive circuit DC is shown, but the present invention is not limited to this, and a passive drive display panel may be used.

DESCRIPTION OF SYMBOLS 10 Display panel 11 Insulating substrate 12 Gate insulating film 13 Insulating film 14 Pixel electrode 15 Organic EL layer 16 Counter electrode 16a Electron injection layer 16b High work function thin film 17 Partition layer 20 Display area 30 Peripheral area PIX Display pixel Rpx Pixel formation area Rel EL element formation region OEL Organic EL element Tr11, Tr12 Transistor Cs Capacitor Eca Lower electrode Ecb Upper electrode Ect Contact electrode TMi External junction terminal CH1-CH5 Contact hole

Claims (9)

In a display panel in which at least a display element and a functional element for driving the display element are formed on a substrate,
The functional element includes at least a first electrode and a second electrode provided on the first electrode via a first insulating film,
The display element includes at least a third electrode electrically connected to the second electrode of the functional element, a fourth electrode provided on the third electrode via a display functional layer, Have
The fourth electrode of the display element is the same layer as the second electrode of the functional element through an opening provided in a second insulating film formed so as to cover at least the functional element. Electrically connected to the fifth electrode provided in the
A display panel, wherein at least the second electrode and the fifth electrode have an electrode structure including a conductive layer made of molybdenum-niobium. The functional element is a thin film transistor, the first electrode is a gate electrode of the thin film transistor, and the second electrode is a source electrode and a drain electrode of the thin film transistor,
The display element is a light emitting element, the third electrode is a pixel electrode made of an electrode material having light transmission characteristics, and the fourth electrode is a counter electrode made of an electrode material having light reflection characteristics. The display panel according to claim 1, wherein the display panel is a display panel. The display panel according to claim 1, wherein the fourth electrode is a conductive layer containing aluminum. The fifth electrode is connected to a power supply wiring for applying a predetermined voltage to the fourth electrode, and includes a plurality of conductive layers including an electrode layer provided in the same layer as the second electrode. 4. The display panel according to claim 1, wherein the display panel has a structure. The fifth electrode has a stacked structure including at least the electrode layer provided in the same layer as the second electrode and a conductive layer provided in the same layer as the semiconductor layer of the thin film transistor. The display panel according to claim 4, wherein: The fifth electrode includes at least an electrode layer provided in the same layer as the third electrode, a first wiring layer formed so as to cover the electrode layer of the same layer as the third electrode, Is connected to the fourth electrode via
6. The first wiring layer according to claim 1, wherein the first wiring layer is formed by being laminated on a second wiring layer provided in the same layer as the second electrode. Display panel. In a method of manufacturing a display panel in which at least a display element and a functional element for driving the display element are formed on a substrate,
The functional element includes at least a first electrode and a second electrode provided on the first electrode via a first insulating film,
The display element includes at least a third electrode electrically connected to the second electrode of the functional element, a fourth electrode provided on the third electrode via a display functional layer, Have
Forming the first electrode of the functional element on the substrate;
Forming the third electrode of the display element on the first conductive layer via the first insulating film;
Forming the second electrode of the functional element at the same time as forming the fifth electrode so as to be connected to the third electrode of the display element;
Forming a second insulating film on the substrate so as to cover the second electrode, the third electrode, and the fifth electrode;
Forming an opening in the second insulating film through which at least the third electrode and the fifth electrode are exposed;
Forming the display functional layer on the third electrode of the display element;
The display element facing the third electrode of the display element via the display function layer and electrically connected to the fifth electrode via the opening of the second insulating film Forming the fourth electrode of:
Including
A method for manufacturing a display panel, wherein at least the second electrode and the fifth electrode have an electrode structure including a conductive layer made of molybdenum-niobium. In a method of manufacturing a display panel in which at least a display element and a functional element for driving the display element are formed on a substrate,
The functional element includes at least a first electrode and a second electrode provided on the first electrode via a first insulating film,
The display element includes at least a third electrode electrically connected to the second electrode of the functional element, a fourth electrode provided on the third electrode via a display functional layer, Have
Forming the first electrode of the functional element on the substrate;
Forming the second electrode of the functional element on the first conductive layer via the first insulating film and simultaneously forming the fifth electrode;
Forming a second insulating film on the substrate so as to cover the second electrode and the fifth electrode;
Forming an opening exposing at least the second electrode and the fifth electrode in the second insulating film;
Forming the third electrode of the display element so as to be connected to the second electrode of the functional element through the opening of the second insulating film;
Forming the display functional layer on the third electrode of the display element;
The display element facing the third electrode of the display element via the display function layer and electrically connected to the fifth electrode via the opening of the second insulating film Forming the fourth electrode of:
Including
A method for manufacturing a display panel, wherein at least the second electrode and the fifth electrode have an electrode structure including a conductive layer made of molybdenum-niobium. In a method of manufacturing a display panel in which at least a display element and a functional element for driving the display element are formed on a substrate,
The functional element includes at least a first electrode, and a second electrode provided on the first electrode via a first insulating film,
The display element includes at least a third electrode electrically connected to the second electrode of the functional element, a fourth electrode provided on the third electrode via a display functional layer, Have
Forming the first electrode of the functional element on the substrate;
Forming the second electrode of the functional element on the first conductive layer via the first insulating film and simultaneously forming the fifth electrode;
Forming a second insulating film on the substrate so as to cover the second electrode and the fifth electrode;
Forming an opening exposing at least the second electrode and the fifth electrode in the second insulating film;
The third electrode of the display element connected to the second electrode of the functional element and the electrode layer connected to the fifth electrode are simultaneously formed through the opening of the second insulating film. Forming, and
Forming a first wiring layer so as to cover at least the electrode layer connected to the fifth electrode;
Forming the display functional layer on the third electrode of the display element;
Opposite the third electrode of the display element through the display functional layer, and connect to the fifth electrode through the electrode layer and the first wiring layer connected to the fifth electrode. Forming the fourth electrode of the display element to be electrically connected;
Including
A method for manufacturing a display panel, wherein at least the second electrode and the fifth electrode have an electrode structure including a conductive layer made of molybdenum-niobium.

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