JP5201381B2 - Manufacturing method of display device - Google Patents

Description

The present invention relates to a method for manufacturing a display device, and more particularly to a method for manufacturing a display device including a display panel in which a plurality of display elements are arranged.

  2. Description of the Related Art In recent years, a display panel (organic EL display panel) in which organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”), which are self-luminous elements, are two-dimensionally arranged as display devices for electronic devices such as mobile phones and portable music players. ) Is known. In particular, the organic EL display panel using the active matrix drive system has a faster display response speed, less viewing angle dependency, and higher brightness and higher contrast than the widely used liquid crystal display devices. In addition to being able to increase the display image quality, it does not require a backlight or a light guide plate unlike a liquid crystal display device, so it has a very advantageous feature that it can be made thinner and lighter. . Therefore, application to various electronic devices is expected in the future.

FIG. 17 is a schematic diagram illustrating a configuration example of a main part of a display device including an active matrix display panel according to a conventional technique and a circuit configuration example of a display pixel.
For example, as shown in FIG. 17A, a display device corresponding to the active matrix driving method is provided on an insulating substrate such as a glass substrate in the row direction (left-right direction in the drawing) and the column direction (up-down direction in the drawing). A display panel 110 in which display pixels EMp are arranged in a matrix near each intersection of a plurality of scanning lines LPs and data lines LPd arranged in parallel, and a selection voltage Ssel at a predetermined timing with respect to each scanning line LPs. And a data driver (data line driving circuit) 130 for supplying a data voltage Vpix corresponding to display data to each data line LPd at a predetermined timing. Yes.

  Each display pixel EMp has an organic EL element OEL that is a current control type light emitting element and a light emission drive that has a current value corresponding to display data in the organic EL element OEL, as shown in FIG. A pixel driving circuit (or pixel circuit) DCP for supplying current. The pixel drive circuit DCP includes, for example, a transistor (select transistor) Tr111 having a gate terminal connected to the scan line LPs, a source terminal connected to the data line LPd, a drain terminal connected to the contact N111, and a gate terminal connected to the contact N111. A transistor (light emission drive transistor) Tr112 having a drain terminal connected to a contact N112, a source of the contact N111 and the transistor Tr112, a power supply voltage line LPv to which a power supply voltage Vdd whose terminal is higher than the ground potential GND is supplied The organic EL element OEL includes a capacitor Cx connected between terminals, and an anode terminal is connected to a contact N112 of the pixel driving circuit DCP, and a cathode terminal is connected to a common voltage electrode LPg to which a ground potential GND is supplied. ing.

  Desired image information is displayed by sequentially controlling the driving of every display pixel EMp two-dimensionally arranged in such a display panel 110 for each row. Such a display panel is described in detail in, for example, Patent Document 1 and the like.

JP-A-8-330600 (pages 3 to 4, FIGS. 3 and 4)

However, the display device including the display pixels (pixel drive circuit) as described above has the following problems.
That is, as described above, in a display panel in which a thin film wiring, a thin film transistor, or the like is formed on an insulating substrate, when studying high brightness, large screen, and high definition, the current flowing through each wiring increases. The signal delay and voltage drop due to the wiring resistance become remarkable. As a result, the voltage applied to each display pixel fluctuates, resulting in deterioration of various display image quality such as reduction in brightness, variation, and crosstalk. There was a problem that high definition was restricted. In particular, such a problem occurs remarkably in wiring such as a power supply voltage line and a common voltage line through which a large current flows.

  In order to avoid such a problem, it is conceivable to reduce the resistance of the wiring. Specifically, the wiring layer is formed in a layer different from the gate electrode, the source, and the drain electrode of the thin film transistor. However, in this case, the conductive material has poor adhesion to an insulating substrate, an insulating film as a base layer formed as necessary, or a resist for patterning. When forming a wiring pattern by wet etching, there is a problem that an etching solution enters between the layers, resulting in excessive thinning or peeling of the wiring width due to side etching.

The present invention has been made in view of the above problems, and an object thereof is to provide a method for producing excellent display device in the display quality.

The invention described in claim 1
In a method for manufacturing a display device including a pixel driving circuit having a transistor and a display element having a pair of electrodes,
A first opening that exposes at least part of the first electrode of the pair of electrodes of the display element; and a second opening that exposes at least part of one of the source and drain electrodes of the transistor. Forming an insulating film having,
A first metal thin film having a first metal material on the first electrode exposed in the first opening and on one of the source and drain electrodes of the transistor exposed in the second opening; A second metal thin film having a second metal material and a third metal thin film having the same material as the first metal material are sequentially laminated,
Etching the third metal thin film and the second metal thin film sequentially with an etching mask formed on the third metal thin film at a position corresponding to the second opening as a mask,
After removing the etching mask, the first metal thin film remaining on the first opening is removed to expose the first electrode,
An organic EL layer is formed on the first electrode .

In the step of removing the first metal thin film remaining on the first opening, the third metal thin film at a position corresponding to the etching mask is removed together with the first metal thin film.

The first metal material is chromium or an alloy thereof, and the second metal thin film is aluminum or an alloy thereof.

The display device has a scanning line connected to the pixel driving circuit,
In the step of sequentially laminating the first metal thin film, the second metal thin film, and the third metal thin film, the first metal thin film, the second metal thin film, and the scan line forming region, And sequentially stacking the third metal thin film,
In the step of sequentially etching the third metal thin film and the second metal thin film, the third metal thin film and the second metal thin film are sequentially etched using the second etching mask formed in the scan line formation region as a mask. ,
In the step of removing the first metal thin film and exposing the first electrode, the second metal thin film and the first metal thin film at positions corresponding to the second etching mask by etching the third metal thin film The scanning line consisting only of the second metal thin film and the first metal thin film is formed in the scanning line forming region by remaining the film.

The display device has a power supply voltage line connected to the pixel driving circuit,
In the step of sequentially laminating the first metal thin film, the second metal thin film, and the third metal thin film, the first metal thin film and the second metal thin film are also formed in a region where the power supply voltage line is formed. , Sequentially stacking the third metal thin film,
In the step of sequentially etching the third metal thin film and the second metal thin film, the third metal thin film and the second metal thin film are sequentially etched using the third etching mask formed in the power supply voltage line forming region as a mask. And
In the step of removing the first metal thin film and exposing the first electrode, the second metal thin film and the first metal thin film at positions corresponding to the third etching mask by etching the third metal thin film The power supply voltage line consisting only of the second metal thin film and the first metal thin film is formed in a region where the power supply voltage line is formed.

According to the manufacturing method of the display device according to the present invention, excellent connectivity, it is possible to realize a good display quality.

  Hereinafter, a display device and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments. Here, in the embodiment described below, a case where an organic EL element including an organic EL layer formed by applying an organic material is applied as a light emitting element constituting a display pixel will be described.

<First Embodiment>
(Display panel)
First, a display panel (organic EL panel) and display pixels applied to the display device according to the present invention will be described.

  FIG. 1 is a schematic plan view showing an example of a pixel arrangement state of a display panel applied to a display device according to the present invention, and FIG. 2 is a diagram of each two-dimensional array on the display panel of the display device according to the present invention. It is an equivalent circuit diagram which shows the circuit structural example of a display pixel (a light emitting element and a pixel drive circuit). In the plan view shown in FIG. 1, for the convenience of explanation, each display pixel (color) when a display panel having a bottom emission type light emitting structure that emits to the visual field side through the insulating substrate 11 is viewed from the upper surface side. Only the relationship of the arrangement (arrangement) between the pixel electrode provided in the pixel) and each wiring layer and the bank that defines the formation area of each display pixel is shown, and the organic EL element (light emitting element) of each display pixel is driven to emit light. Therefore, the display of the transistors and the like in the pixel driving circuit shown in FIG. 2 provided in each display pixel is omitted. Further, in FIG. 1, the pixel electrodes, the respective wiring layers, and the banks are hatched for the sake of convenience in order to clarify the arrangement. In FIG. 2, circuit elements, signals, and the like that are the same as those of the above-described prior art (see FIG. 17B) are denoted by the same or equivalent reference numerals.

  As shown in FIG. 1, the display device (display panel) according to the present invention has three colors of red (R), green (G), and blue (B) on one surface side of an insulating substrate 11 such as a glass substrate. A plurality of color pixels PXr, PXg, PXb are repeatedly arranged in the row direction (left-right direction in the drawing) and a plurality of color pixels PXr, PXg, PXb of the same color are arranged in the column direction (up-down direction in the drawing). Has been. Here, one display pixel PIX is formed by combining the adjacent RGB color pixels PXr, PXg, and PXb.

  The display panel 10 protrudes from one side of the insulating substrate 11 and has the same color arranged in the column direction by banks (partitions) 17 continuously arranged with a fence-like or grid-like plane pattern. Each color pixel region including a plurality of color pixels PXr or pixel formation regions of PXg and PXb is defined. In addition, a pixel electrode (for example, an anode electrode) 14 is formed in the pixel formation region of each color pixel PXr or PXg, PXb included in each color pixel region, and in parallel with the arrangement direction of the bank 17. A data line (signal line) Ld is arranged in the column direction (vertical direction in the drawing), and a scanning line (selection line) Ls and a power supply voltage line (for example, in the row direction (horizontal direction in the drawing) perpendicular to the data line Ld). An anode line (wiring layer for applying a power supply voltage) La is disposed. In addition, a counter electrode (for example, a cathode electrode) formed of a single planar electrode (solid electrode) so as to face a plurality of display pixels PIX (each pixel electrode 14) two-dimensionally arranged on the insulating substrate 11 in common. ) 16 is formed.

  As a specific circuit configuration of each color pixel PXr, PXg, and PXb of the display pixel PIX, for example, as shown in FIG. 2, a pixel drive composed of one to a plurality of transistors (for example, an amorphous silicon thin film transistor) on an insulating substrate 11 is performed. A circuit (or pixel circuit) DC, and an organic EL element (light emitting element) OEL that emits light when a light emission drive current controlled by the pixel drive circuit DC is supplied to the pixel electrode 14. .

  The power supply voltage line La is directly or indirectly connected to a predetermined high potential power supply, for example, and is a pixel electrode (for example, an anode electrode) 14 of the organic EL element OEL provided in each display pixel PIX (color pixels PXr, PXg, PXb). Since a light emission driving current corresponding to display data flows through the power supply voltage line, a predetermined high voltage (power supply voltage Vdd) higher than a reference voltage Vss described later is applied to the power supply voltage line La, and the counter electrode 16 has a predetermined low potential, for example. It is directly or indirectly connected to the power supply, and is set so that a predetermined low voltage (reference voltage Vss; for example, ground potential GND) is applied to the plurality of organic EL elements OEL.

  For example, as shown in FIG. 2, the pixel drive circuit DC has data in which the gate terminal is arranged on the scanning line Ls and the drain terminal is arranged in the column direction of the display panel 10 in the same manner as the circuit configuration shown in the related art described above. A transistor (select transistor) Tr11 having a source terminal connected to the contact N11, a gate terminal connected to the contact N11, a drain terminal connected to the power supply voltage line La, and a source terminal connected to the contact N12 are connected to the line Ld. A light emitting drive transistor (functional element) Tr12; and a capacitor Cs connected between the gate terminal and the source terminal of the transistor Tr12. Here, the transistors Tr11 and Tr12 are both n-channel thin film transistors. The capacitor Cs is a parasitic capacitance formed between the gate and the source of the transistor Tr12 and / or an auxiliary capacitance additionally provided between the gate and the source.

  The organic EL element OEL has an anode terminal (a pixel electrode 14 serving as an anode electrode) connected to the contact N12 of the pixel drive circuit DC, and a cathode terminal (a counter electrode 16 serving as a cathode electrode) common to each display pixel PIX. A reference voltage Vss (for example, ground potential GND) is supplied.

  In the display pixel PIX (pixel drive circuit DC and organic EL element OEL) shown in FIG. 2, the scanning line Ls is connected to, for example, a scanning driver (not shown) and arranged in the row direction of the display panel 10 at a predetermined timing. A selection voltage (scanning signal) Ssel for setting the plurality of display pixels PIX (color pixels PXr, PXg, PXb) to a selected state is applied. The data line Ld is connected to a data driver (not shown), and a data voltage (grayscale signal) Vpix corresponding to display data is applied at a timing synchronized with the selection state of the display pixel PIX.

  Further, as described above, the power supply voltage Vdd is applied to the power supply voltage line La, and the reference voltage Vss is applied to the counter electrode 16. That is, the power supply voltage Vdd and the reference voltage Vss are respectively applied to both ends of the pair of the transistor Tr12 and the organic EL element OEL connected in series, and the current value of the current to be passed through the organic EL element OEL by this potential difference The drive circuit DC is controlling.

  In the drive control operation in the display pixel PIX having such a circuit configuration, a selection voltage Ssel of a selection level (on level; for example, high level) is applied to the scanning line Ls, as in the conventional technique described above. As a result, the transistor Tr11 is turned on and set to the selected state. In synchronization with this timing, the data voltage Vpix having a voltage value corresponding to the display data is controlled to be applied to the data line Ld, so that the potential corresponding to the data voltage Vpix is connected to the contact N11 (via the transistor Tr11). That is, the voltage is applied to the gate terminal of the transistor Tr12.

  The current value of the drain-source current of the transistor Tr12 is determined by the potential difference between the drain and source and the potential difference between the gate and source. Here, since the power supply voltage Vdd and the reference voltage Vss are fixed values, the potential difference between the drain and source of the transistor Tr12 is fixed in advance by the power supply voltage Vdd and the reference voltage Vss. Since the potential difference between the gate and source of the transistor Tr12 is uniquely determined by the potential of the data voltage Vpix, the current value of the current flowing between the drain and source of the transistor Tr12 can be controlled by the data voltage Vpix. .

  In this way, the transistor Tr12 is turned on in a conductive state corresponding to the potential of the contact N11 (that is, a conductive state corresponding to the data voltage Vpix), and the transistor Tr12 and the organic EL element OEL are turned on from the power supply voltage Vdd on the high potential side. As a result, a predetermined light emission drive current flows through the reference voltage Vss (ground potential GND) on the low potential side, and the organic EL element OEL emits light with a luminance gradation corresponding to the data voltage Vpix (that is, display data). At this time, charges are accumulated (charged) in the capacitor between the gate and the source of the transistor Tr12 based on the data voltage Vpix applied to the contact N11.

  Next, by applying a selection voltage Ssel of a non-selection level (off level; for example, low level) to the scanning line Ls, the transistor Tr11 of the display pixel PIX is turned off and set to a non-selection state, and the data line Ld and the pixel The drive circuit DC is electrically disconnected. At this time, the electric charge accumulated in the capacitor Cs is held, whereby the potential difference between the gate and the source of the transistor Tr12 is held.

  Therefore, similarly to the light emission operation in the selected state, a predetermined light emission drive current flows from the power supply voltage Vdd to the organic EL element OEL via the transistor Tr12, and the light emission operation is continued. This light emission operation is controlled so as to continue, for example, for one frame period until the next data voltage Vpix is applied (written). Then, such a drive control operation is sequentially executed for every row, for example, for all the display pixels PIX (each color pixel PXr, PXg, PXb) two-dimensionally arranged on the display panel 10, thereby obtaining desired image information. An image display operation to be displayed can be executed.

  In FIG. 2, the pixel driving circuit DC provided in the display pixel PIX is written in each display pixel PIX (specifically, the gate terminal of the transistor Tr12 of the pixel driving circuit DC; the contact N11) according to display data. By adjusting the voltage value of the data voltage Vpix, the current value of the light emission drive current that flows through the organic EL element OEL is controlled to perform the light emission operation at a predetermined luminance gradation (or voltage gradation designation). Drive) circuit configuration is shown, but by adjusting the current value written to each display pixel PIX in accordance with the display data, the current value of the light emission drive current that flows through the organic EL element OEL is controlled to obtain a predetermined luminance scale. It may have a circuit configuration of a current gradation designation method (or current gradation designation drive) in which light emission operation is performed with a tone.

(Device structure of display pixel)
Next, a specific device structure (planar layout and cross-sectional structure) of the display pixel (light emission drive circuit and organic EL element) having the circuit configuration as described above will be described. Here, a display panel (organic EL panel) having a bottom emission type light emitting structure in which light emitted from the organic EL layer is emitted to the visual field side through an insulating substrate will be described.

  FIG. 3 is a plan layout diagram illustrating an example of display pixels applicable to the display device (display panel) according to the present embodiment. Here, a planar layout of one specific color pixel among the red (R), green (G), and blue (B) color pixels PXr, PXg, and PXb of the display pixel PIX shown in FIG. 1 is shown. In FIG. 3, the layer in which each transistor, wiring, and the like of the pixel driving circuit DC are formed is mainly shown. 4A and 4B show the IVA-IVA line (in this specification, the Roman numeral “4” shown in FIG. 3) in the display pixel PIX having the planar layout shown in FIG. 4 is a schematic cross-sectional view showing a cross section along the line IVB-IVB and a cross section along the line IVB-IVB.

  Specifically, the display pixels PIX (color pixels PXr, PXg, PXb) shown in FIG. 2 are pixel formation regions (organic EL elements in the color pixels PXr, PXg, PXb) set on one surface side of the insulating substrate 11. 4 (indicated as Rpx in FIG. 4), for example, the scanning line Ls and the power supply voltage extend in the row direction (horizontal direction in the drawing) to the upper and lower edge regions of the planar layout as shown in FIG. Each line La is arranged, and the data line Ld is arranged so as to extend in the column direction (vertical direction in the drawing) in the left edge region of the planar layout so as to be orthogonal to the lines Ls and La. It is installed. A bank (detailed later) 17 is disposed in the right edge region of the planar layout so as to extend in the column direction across the color pixels adjacent to the right side.

  Here, for example, as shown in FIGS. 3 and 4, the data line Ld is provided below the scanning line Ls and the power supply voltage line La (insulating substrate 11 side), and the gate electrodes Tr11g of the transistors Tr11 and Tr12. The signal wiring layer is formed through the contact hole Ch1 provided in the gate insulating film 12 formed on the gate insulating film 12 formed thereon by patterning the gate metal layer for forming the Tr12g. It is connected to the drain electrode Tr11d of the transistor Tr11 formed integrally with Ldx.

  Further, the scanning line Ls is formed by patterning the source and drain metal layers for forming the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12 located above the data line Ld. Are formed in the same process as the drain electrode, and are connected to the gate electrode Tr11g through contact holes Ch2 provided in the gate insulating film 12 located at both ends of the gate electrode Tr11g of the transistor Tr11.

Thus, for example, as shown in FIGS. 3, 4A, and 4B, the data line Ld is provided below the scanning line Ls and the power supply voltage line La (insulating substrate 11 side). Yes.
The scanning line Ls has a wiring structure in which a lower layer wiring portion Ls0 and an upper layer wiring portion (a wiring portion including a plurality of metal thin films Ls1 and Ls2 described later) are stacked.

The power supply voltage line La (including a power supply wiring layer La described later) has a wiring structure in which a lower layer wiring portion La0 and an upper layer wiring portion (a wiring portion including a plurality of metal thin films La1 and La2 described later) are stacked.
The lower layer wiring portions Ls0 and La0 are both provided in the same layer as or integrated with the source electrode Tr12s and the drain electrode (conductive layer) 12d of the transistor Tr12, and form the source electrode Tr12s and the drain electrode Tr12d. The source and drain metal layers are simultaneously formed in the patterning process.

  Here, the lower wiring portions Ls0 and La0 are respectively a transition metal layer for reducing migration of chromium (Cr), titanium (Ti), etc., and an aluminum simple substance or an aluminum alloy provided on the transition metal layer. And a low-resistance metal layer for reducing the wiring resistance.

The upper wiring portions Ls1 and La1 have transition metal layers for reducing migration of chromium (Cr), titanium (Ti), and the like. The upper layer wiring portions Ls2 and La2 provided above the upper layer wiring portions Ls1 and La1 each have a low resistance metal layer for reducing wiring resistance such as aluminum alone or aluminum alloy. The upper layer wiring portions Ls1 and La1 have a resistivity of 10 to 100 × 10 ⁻⁶ Ω · cm, and the upper layer wiring portions Ls2 and La2 have a resistivity of 2 to 20 × 10 ⁻⁶ Ω · cm. The upper layer wiring portions Ls1, La1 have better adhesion to the lower layer wiring portion Ls0 and the lower layer wiring portion La0 than the upper layer wiring portions Ls2, La2.

  More specifically, for example, as shown in FIG. 3, the pixel drive circuit DC is connected to the scanning line Ls (or the data line Ld) in which the transistor Tr11 shown in FIG. 2 is arranged in the row direction and extends in the row direction. The power supply wiring layer Lay (or the bank 17) is formed so as to extend along the signal wiring layer Ldx) formed so as to exist, and the transistor Tr12 is formed to protrude from the power supply voltage line La in the column direction. It is arrange | positioned so that it may extend along.

  Here, each of the transistors Tr11 and Tr12 has a well-known field effect type thin film transistor structure, and is formed in a region corresponding to each of the gate electrodes Tr11g and Tr12g via the gate electrodes Tr11g and Tr12g and the gate insulating film 12, respectively. And the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d formed so as to extend to both ends of the semiconductor layer SMC.

  A channel protective layer BL such as silicon oxide or silicon nitride for preventing etching damage to the semiconductor layer SMC is formed on the semiconductor layer SMC where the source electrode and the drain electrode of the transistors Tr11 and Tr12 face each other. An impurity layer OHM for realizing ohmic connection between the semiconductor layer SMC and the source and drain electrodes is formed on the semiconductor layer SMC where the source electrode and the drain electrode are in contact.

  Then, to correspond to the circuit configuration of the pixel driving circuit DC shown in FIG. 2, the transistor Tr11 scans through the contact hole Ch2 in which the gate electrode Tr11g is provided in the gate insulating film 12, as shown in FIG. The drain electrode Tr11d is connected to the line Ls and formed integrally with the signal wiring layer Ldx.

  As shown in FIGS. 3 and 4, the transistor Tr12 has a gate electrode Tr12g connected to the source electrode Tr11s of the transistor Tr11 through a contact hole Ch3 provided in the gate insulating film 12, and the drain electrode of the transistor Tr12. The Tr12d is connected to a power supply wiring layer La formed integrally with the power supply voltage line La, and the source electrode Tr12s of the transistor Tr12 is directly connected to the pixel electrode 14 of the organic EL element OEL.

  The organic EL element OEL is provided on the gate insulating film 12 of the transistors Tr11 and Tr12, and is directly connected to the source electrode Tr12s of the transistor Tr12 to be supplied with a predetermined light emission driving current (for example, an anode) Electrode) 14 and a pixel forming region Rpx (corresponding to a coating region of an organic compound material) defined by a bank 17 arranged in the column direction on the insulating substrate 11 (set between the banks 17). The organic EL layer (light emitting functional layer) 15 composed of the hole transport layer 15a (charge transport layer) and the electron transport light emitting layer 15b (charge transport layer), and a single pixel provided in common for each display pixel PIX A counter electrode 16 made of a planar electrode (solid electrode) is sequentially laminated. Here, since the display panel 10 according to the present embodiment has a bottom emission type light emitting structure, the pixel electrode 14 has light transmission characteristics using ITO or the like, and the counter electrode 16 reflects light. It has characteristics. The counter electrode 16 is provided so as to extend not only on each pixel formation region Rpx but also on the bank 17 that defines the pixel formation region Rpx.

  The bank 17 is a boundary region between a plurality of display pixels PIX (each color pixel PXr, PXg, PXb) two-dimensionally arranged on the display panel 10, and the column direction of the display panel 10 (the display panel 10 as a whole is shown in FIG. As shown, it has a fence-like or grid-like plane pattern). Here, as shown in FIG. 4A, in the boundary region, the transistor Tr12 is formed to extend in the column direction of the display panel 10 (insulating substrate 11). The transistor Tr12 is covered so that it continuously protrudes from the surface of the insulating substrate 11 on the insulating films 13a and 13b that function as an interlayer insulating film between the pixel electrodes 14 formed in each pixel formation region Rpx. It is formed by laminating a resin layer made of a photosensitive polyimide resin material. As a result, the region surrounded by the bank 17 (the pixel formation region Rpx of the plurality of display pixels PIX arranged in the column direction (vertical direction in FIG. 1)) becomes the organic EL layer 15 (the hole transport layer 15a and the electron transport layer). Is defined as an application region of the organic compound material when forming the light emitting layer 15b). For example, as shown in FIG. 4, a sealing layer 18 is formed on the entire area of the insulating substrate 11 on which the pixel driving circuit DC, the organic EL element OEL, and the bank 17 are formed.

  In such a display panel 10, in the pixel drive circuit DC including functional elements such as the transistors Tr11 and Tr12, wiring layers such as the scanning lines Ls, the data lines Ld, and the power supply voltage lines (anode lines) La, the data lines Based on the gradation signal Vpix corresponding to the display data supplied via Ld, a light emission drive current having a predetermined current value flows between the source and drain of the transistor Tr12 and is supplied to the pixel electrode 14 of the organic EL element OEL. Thus, the organic EL element OEL of each display pixel PIX (each color pixel PXr, PXg, PXb) emits light at a desired luminance gradation corresponding to the display data.

  At this time, the display panel 10 shown in the present embodiment, that is, the pixel electrode 14 has light transmission characteristics and the counter electrode 16 has light reflection characteristics (that is, the organic EL element OEL is a bottom emission type). Therefore, the light emitted from the organic EL layer 15 of each display pixel PIX (each color pixel PXr, PXg, PXb) is directly transmitted through the pixel electrode 14 having light transmission characteristics or the counter electrode having light reflection characteristics. 16, passes through the insulating substrate 11 (display panel 10), and is emitted to the other surface side of the insulating substrate 11 that is the visual field side (downward in FIG. 4).

(Manufacturing method of display device)
Next, a method for manufacturing the display device (display panel) according to the present embodiment will be described.
5 to 9 are process cross-sectional views illustrating an example of a method for manufacturing a display device (display panel) according to the present embodiment. Here, in order to clarify the characteristics of the manufacturing method of the display device according to the present embodiment, the cross section along the IVA-IVA line and the IVB-IVB line shown in FIGS. FIG. 4 shows a cross-sectional structure in which a part (transistor Tr12, scanning line Ls, data line Ld, power supply voltage line La) is extracted from the cross-sectional panel structure, and further described with reference to FIGS. 4 (a) and 4 (b) as appropriate. To do.

  In the manufacturing method of the display device (display panel) described above, first, as shown in FIGS. 5A to 5D, a display set on one surface side (the upper surface side of the drawing) of the insulating substrate 11 such as a glass substrate. For each pixel formation region Rpx of the pixel PIX (each color pixel PXr, PXg, PXb), the above-described pixel drive circuit (see FIGS. 2 and 3) DC transistors Tr11 and Tr12, data line Ld, signal wiring layer Ldx, scanning line A wiring layer such as a lower layer wiring portion Ls0 of Ls and a lower layer wiring portion La0 of the power supply voltage line La is formed, and a pixel electrode 14 which becomes an anode electrode of the organic EL element OEL is formed.

  Specifically, after forming a gate metal layer on the transparent insulating substrate 11, as shown in FIG. 5A, the gate metal layer is patterned to form gate electrodes Tr11g, Tr12g, and data lines. Ld is formed at the same time, and then a gate insulating film 12, a semiconductor film that becomes a semiconductor layer SMC made of amorphous silicon, and an insulating film such as silicon nitride that becomes a channel protective film layer BL are continuously formed over the entire area of the insulating substrate 11. To do.

  Next, as shown in FIG. 5B, the insulating film and the semiconductor film are appropriately patterned, and a channel protective layer BL and a semiconductor layer SMC are sequentially formed in a region corresponding to the gate electrode Tr12g on the gate insulating film 12. To do. Thereafter, impurity layers OHM for ohmic connection are formed at both ends of the semiconductor layer SMC.

Next, as shown in FIG. 5C, on the gate insulating film 12 and in the substantially central region of the pixel formation region Rpx of each display pixel PIX (in the planar layout shown in FIG. It has a rectangular planar pattern in the area excluding the peripheral part where the wiring is arranged, and tin-doped indium oxide (Indium
A pixel electrode 14 made of a transparent electrode material (having light transmission characteristics) such as Thin Oxide (ITO) or zinc-doped indium oxide (IZO) is formed. Thereafter, contact holes Ch1, Ch2, and Ch3 are formed in the gate insulating film 12.

  Then, as shown in FIG. 5D, the source electrode Tr12s and the drain electrode Tr12d are formed via the impurity layer OHM corresponding to the transistor Tr12, and the source electrode Tr11s and the drain electrode Tr12d via the impurity layer OHM corresponding to the transistor Tr11. The drain electrode Tr11d is formed, and the lower layer wiring portion Ls0 of the scanning line Ls, the lower layer wiring portion La0 of the power supply voltage line La (including the power supply wiring layer Lay), and the signal wiring layer Ldx are simultaneously formed.

  Here, the source electrodes Tr11s and Tr12s, the drain electrodes Tr11d and Tr12d, the lower layer wiring portion Ls0 of the scanning line Ls, the lower layer wiring portion La0 of the power supply voltage line La, and the signal wiring layer Ldx are formed after the step of FIG. The source and drain metal layers are formed and then patterned to form a package. Therefore, the signal wiring layer Ldx is connected to the data line Ld located below via the contact hole Ch1, and the scanning line Ls is connected to the gate electrode Tr11g located below via the contact hole Ch2, and the source electrode Tr11s. Is connected to the gate electrode Tr12g located below via the contact hole Ch3.

  Here, in other words, the source and drain metal layers are at least the source electrode Tr11s and drain electrode Tr11d of the transistor Tr11, the source electrode Tr12s and drain electrode Tr12d of the transistor Tr12, the lower layer wiring portion Ls0 of the scanning line Ls, and the power supply. The lower layer wiring portion La0 and the signal wiring layer Ldx of the voltage line La (including the power supply wiring layer Lay) include, for example, a lower metal layer made of chromium (Cr) alone or a chromium alloy, and aluminum (Al) alone or aluminum. A wiring structure in which an upper metal layer made of an aluminum alloy such as titanium (AlTi) or aluminum-neodymium-titanium (AlNdTi) is stacked, and the other end side of the source electrode Tr12s of the transistor Tr12 is the pixel electrode 14 Extends up and is electrically connected It is sea urchin formation.

  Next, as shown in FIG. 6A, the entire region of one surface side of the insulating substrate 11 including the transistor Tr12 (including Tr11), the scanning line Ls, and the lower layer wiring portions Ls0 and La0 of the power supply voltage line La is covered. In addition, after forming an insulating film made of an inorganic insulating material such as silicon nitride (SiN), the insulating film is etched to form upper surfaces of the lower wiring portions Ls0 and La0 of the scanning line Ls and the power supply voltage line La, and Then, an insulating film 13a having an opening through which the upper surface of the pixel electrode 14 is exposed is formed.

  Next, as shown in FIG. 6B, on the insulating substrate 11 on which the insulating film 13a is formed, for example, a metal thin film (hereinafter referred to as “chrome thin film”) made of chromium (Cr) alone or an alloy thereof; 1 metal thin film) Lx1, aluminum (Al) alone or a metal thin film made of aluminum alloy such as aluminum-titanium (AlTi), aluminum-neodymium-titanium (AlNdTi) (hereinafter referred to as “aluminum thin film”; second metal) A thin film (Lx2) and a metal thin film (chrome thin film; third metal thin film) Lx3 made of chromium (Cr) alone or an alloy thereof are sequentially laminated. Specifically, the above three-layered metal thin film is continuously formed using a metal material such as chromium, an alloy thereof, aluminum or an alloy thereof by sputtering, ion plating, vacuum deposition, plating, or the like. Film. Each metal thin film is formed with a film thickness of about 10 nm to 50 nm for each of the chromium thin films Lx1 and Lx3 and a film thickness of about 300 to 600 nm for the aluminum thin film Lx2.

  Here, the lowermost metal thin film (chromium thin film Lx1) is not limited to chromium, but a silicon nitride film to be the lower insulating film 13a, a scanning line Ls exposed in the opening of the insulating film 13a, and Any metal material may be used as long as it is a metal material having good adhesion (bonding) with the aluminum simple substance or aluminum alloy which is the upper metal layer of the lower layer wiring portions Ls0 and La0 of the power supply voltage line La, and the metal which is the uppermost layer. The thin film (chromium thin film Lx3) is not limited to chromium, and has good adhesion (bonding) with an etching mask MSK (photoresist) formed in a process described later (see FIG. 6C). Any metal material may be used, and each of the metal thin films (chromium thin films Lx1, Lx3) has an adhesion (bonding property) to the metal thin film (aluminum thin film Lx2) formed as an intermediate layer. If the good metal material, it may be for example those which apply other metals such as titanium.

  Next, as shown in FIG. 6 (c), a photoresist is formed on the insulating substrate 11 on which the three layers of metal thin films Lx1 to Lx3 are formed, and after pre-baking, exposure and development processes are performed to obtain a scanning line. Lower layer wiring portion of the region (for example, the above-described scanning line Ls and power supply voltage line La (including the power supply wiring layer Lay) corresponding to the plane pattern of the upper layer wiring portion of Ls and the power supply voltage line La (including the power supply wiring layer Lay) An etching mask MSK is formed by leaving the photoresist in a region having a planar pattern equivalent to Ls0 and La0.

  Next, as shown in FIG. 7A, the uppermost chromium thin film Lx3 is etched with a chromium etching solution (for example, C-1 etching solution manufactured by Nagase Chemical Co., Ltd.) using the etching mask MSK. The intermediate layer aluminum thin film Lx2 is etched with an etching solution (for example, Nagase Chemical A-1 etching solution) to expose the lowermost chromium thin film Lx1 other than the region where the etching mask MSK is formed. In other words, the pixel electrode 14 of each display pixel PIX is protected by the chrome thin film Lx1 on its upper surface.

  Next, as shown in FIG. 7B, the etching mask MSK is removed using a stripper (for example, N-303G manufactured by Nagase Chemical) to expose the uppermost chromium thin film Lx3. At this time, since the chromium thin film Lx1 is protected on the surface of the pixel electrode 14, the residue of the etching mask MSK is not directly attached.

  Next, the uppermost chromium thin film Lx3 exposed on the insulating substrate 11 with the above-described chromium etching solution (for example, C-1 etching solution manufactured by Nagase Chemical Co., Ltd.) and the uppermost region not located on the lower surface of the aluminum thin film Lx2. The lower chromium thin film Lx1 is etched. As a result, as shown in FIG. 7C, the lowermost chromium thin film Lx1 and the intermediate layer aluminum are formed only in the region corresponding to the plane pattern of the scanning line Ls and the power supply voltage line La (including the power supply wiring layer Lay). The thin film Lx2 remains, and an upper layer wiring portion is formed by laminating chromium thin films Ls1, La1 which are lower layer metal thin films and aluminum thin films Ls2, La2 which are upper layer metal thin films. A scanning line Ls and a power supply voltage line La (including a power supply wiring layer Lay) having a laminated wiring structure including the lower layer wiring portions Ls0 and La0 are formed. Here, the residue of the etching mask MSK attached to the upper surface of the exposed chromium thin film Lx1 and the etching mask MSK on the chromium thin film Ls3 are removed together with the chromium thin film Lx1 and the chromium thin film Ls3. There is almost no residue of the etching mask MSK on the surface and the surface of the pixel electrode 14 of each exposed display pixel PIX.

  Next, an insulating film made of, for example, silicon nitride is used by chemical vapor deposition (CVD) or the like so as to cover the entire area of the one surface side of the insulating substrate 11 including the scanning line Ls and the power supply voltage line La. After the formation, the insulating film is etched to cover the transistors Tr11 and Tr12, the scanning line Ls, and the power supply voltage line La (including the power supply wiring layer Lay) as shown in FIG. An insulating film 13b having an opening through which the upper surface of the pixel electrode 14 of the display pixel PIX is exposed is formed.

  Next, as shown in FIG. 8B, a bank 17 made of, for example, a photosensitive polyimide resin material is formed on the insulating film 13b formed in the boundary region between adjacent display pixels PIX. Specifically, the photosensitive polyimide film formed so as to cover the entire area of the one surface side of the insulating substrate 11 including the insulating film 13b is subjected to exposure and development processing, and the boundary between adjacent display pixels PIX. The region is formed by remaining so as to extend in the column direction of the display panel 10. Here, as a resin material, for example, a polyimide coating material “Photo Nice PW-1030” manufactured by Toray Industries, Inc. can be applied satisfactorily, and the film thickness of the bank 17 in this case is approximately 1 to 5 μm. To form. As a result, the pixel formation region (the formation region of the organic EL layer 15 of the organic EL element OEL) of the plurality of display pixels PIX of the same color arranged in the column direction of the display panel 10 is surrounded and defined by the bank (partition wall) 17. Thus, the upper surface of the pixel electrode 14 is exposed in the region.

  Next, after the insulating substrate 11 is washed with pure water, the surface of the pixel electrode 14 exposed to each pixel formation region Rpx defined by the bank 17 by performing, for example, oxygen plasma treatment or UV ozone treatment is described later. The organic EL-containing liquid of the hole transport material or the electron transporting light emitting material used in the step of forming the organic EL layer 15 is made lyophilic. If necessary, the surface of the bank 17 is made liquid repellent with respect to the organic compound-containing liquid.

  Thereby, on the same insulating substrate 11, the surface of the pixel electrode 14 exposed to each pixel formation region Rpx defined by the bank 17 is kept lyophilic. Thus, by defining the pixel formation region Rpx of each display pixel PIX (organic EL element OEL) by the bank 17, an organic EL layer is applied by applying a solution (including a dispersion) of a light emitting material in a process described later. Even when 15 light emitting layers (electron transporting light emitting layer 15b) are formed, the light emitting material is not mixed between adjacent display pixels PIX (color pixels PXr, PXg, PXb), and adjacent color pixels Mutual color mixing can be prevented. Here, the insulating films 13a and 13b formed in the boundary region between the display pixels PIX (pixel formation region Rpx) are in a state in which the organic compound-containing liquid is relatively familiar by the lyophilic process.

  Note that “liquid repellency” used in the present embodiment refers to an organic compound-containing liquid containing a hole transport material to be a hole transport layer, which will be described later, and an electron transport light-emitting material to be an electron transport light-emitting layer. When the contact angle is measured by dropping an organic compound-containing liquid or an organic solvent used in these solutions onto an insulating substrate or the like, the contact angle is determined to be 50 ° or more. To do. In addition, “lyophilic” as opposed to “liquid repellency” is defined as a state in which the contact angle is 40 ° or less in the present embodiment.

  Next, an ink jet method for ejecting a plurality of droplets separated from each other to a predetermined position or a nozzle coating method for ejecting a continuous solution to the pixel formation region (formation region of the organic EL element OEL) Rpx of each color. After applying and applying a solution or dispersion of the hole transport material in the same step, the hole transport layer (charge transport layer) 15a is formed by heating and drying. Subsequently, an inkjet method or a nozzle coating method is applied to apply a solution or dispersion of an electron transporting light emitting material on the hole transporting layer 15a, followed by drying by heating to form an electron transporting light emitting layer (charge transporting). Layer) 15b. As a result, as shown in FIG. 9A, an organic EL layer (light emitting functional layer) 15 composed of the hole transport layer 15a and the electron transport light emitting layer 15b is formed on the pixel electrode 14 in a stacked manner. Here, as described above, since the surfaces of the insulating films 13a and 13b are also lyophilic with respect to the organic compound-containing liquid, the hole transport layer 15a and the electron transporting property are also formed on the insulating films 13a and 13b14. The light emitting layer 15b is laminated.

  Specifically, as an organic compound-containing liquid containing an organic polymer-based hole transport material (charge transport material), for example, a polyethylene dioxythiophene / polystyrene sulfonic acid aqueous solution (PEDOT / PSS; polyethylene disulfide as a conductive polymer). After applying oxythiophene PEDOT and a dispersion of polystyrene sulfonate PSS, which is a dopant, in an aqueous solvent) on the pixel electrode 14, the stage on which the insulating substrate 11 is placed is heated to 100 ° C. or higher. The organic solvent type hole transport material is fixed on the pixel electrode 14 by heating and drying under temperature conditions to remove the residual solvent, and the hole transport layer 15a which is a charge transport layer is formed. Form.

  Here, since the surface of the pixel electrode 14 is lyophilic with respect to the organic compound-containing liquid (PEDOT / PSS) by the lyophilic process described above, the surface of the pixel electrode 14 is formed in the pixel formation region Rpx defined by the bank 17. The applied organic compound-containing liquid spreads sufficiently in the region (on the pixel electrode 14). On the other hand, since the bank 17 is set sufficiently high with respect to the height of the organic compound-containing liquid (PEDOT / PSS) to be applied, the leakage of the organic compound-containing liquid to the adjacent pixel formation region Rpx and overcoming it are avoided. Can be prevented.

  In addition, as an organic compound-containing liquid containing an organic polymer-based electron-transporting light-emitting material (charge-transporting material), for example, a light-emitting material containing a conjugated double bond polymer such as polyparaphenylene vinylene or polyfluorene is appropriately used. After applying a solution dissolved or dispersed in an aqueous solvent or an organic solvent such as tetralin, tetramethylbenzene, mesitylene, and xylene on the hole transport layer 15a, the stage is heated in a nitrogen atmosphere and dried. By removing the residual solvent, the organic polymer electron transporting light emitting material is fixed on the hole transporting layer 15a to form the electron transporting light emitting layer 15b which is both a charge transporting layer and a light emitting layer.

  Also in this case, the organic compound-containing liquid applied to the pixel formation region Rpx defined by the bank 17 is sufficiently familiar and spreads in the region (hole transport layer 15a), while the bank 17 contains the organic compound-containing liquid. Since it has liquid repellency with respect to the liquid, it is possible to prevent leakage and overcoming of the organic compound-containing liquid to the adjacent pixel formation region Rpx.

  Thereafter, as shown in FIG. 9B, the organic EL layer 15 (the hole transport layer 15a and the electron transporting light emitting layer) has light reflection characteristics on the insulating substrate 11 including at least each pixel formation region Rpx. A common counter electrode (for example, cathode electrode) 16 is formed to face the pixel electrodes 14 through 15b). Here, the counter electrode 16 includes, for example, an electron injection layer having a low work function such as calcium, barium, lithium, or indium having a thickness of 1 to 10 nm, and aluminum (Al), chromium (Cr), or silver (100 nm or more in thickness). A high work function thin film made of an alloy of Ag), palladium silver (AgPd), or the like can be used.

  Further, as shown in FIGS. 1, 4, and 9B, the counter electrode 16 includes not only a region facing the pixel electrode 14, but also each pixel formation region Rpx (formation region of the organic EL element OEL). It is formed as a single conductive layer (planar electrode; solid electrode) extending to the bank 17 to be defined and the insulating films 13a and 13b.

  Next, after the counter electrode 16 is formed, a sealing layer 18 made of a silicon oxide film, a silicon nitride film, or the like is formed over the entire surface of the one surface of the insulating substrate 11 by using a CVD method or the like, as shown in FIG. The display panel 10 having such a cross-sectional structure (bottom emission type light emitting structure) is completed. In addition to the sealing layer 18 or in place of the sealing layer 18, a sealing lid or a sealing substrate may be bonded using a UV curable or thermosetting adhesive.

  As described above, in the display device and the manufacturing method thereof according to the present embodiment, the wiring in which the lower wiring portion and the upper wiring portion are stacked as the wiring layers such as the power supply voltage line and the scanning line arranged in the display panel. Metal thin film (lower layer side) made of chromium or its alloy, etc. with good adhesion to the lower layer wiring part (lower layer side) as an upper layer wiring part, and aluminum or its alloy having a low resistivity It has a structure in which a metal thin film (upper layer side) made of, for example, is laminated.

  As a result, even when the display panel has a high brightness or a large screen, the wiring resistance of each wiring layer can be reduced to suppress signal delay and voltage drop. It is possible to prevent a decrease in luminance, variation, crosstalk, and the like by suppressing a change in voltage applied to the pixel. Therefore, the light emission operation can be performed with an appropriate luminance gradation corresponding to the display data, and a display device (display panel) excellent in display image quality can be realized.

  Even when metal materials such as low resistivity aluminum or its alloys are used for the upper wiring part, a metal thin film (such as a chromium thin film) with high adhesion between the insulating substrate and the lower wiring part is used. Since there are no gaps on the lower surface of the aluminum thin film in the intermediate layer of the upper layer wiring part, which is relatively easy to etch, and there is no gap between the upper layer wiring part and the lower layer wiring part, there is no gap in the lower layer of the intermediate layer. It can be suppressed that the etchant penetrates and the intermediate layer is side-etched. Accordingly, it is possible to form a wiring layer having a desired wiring width by suppressing the phenomenon of wiring width narrowing or delamination caused by side etching, in particular, it is possible to form a wiring layer having a short width, The aperture ratio of the display pixel PIX can be improved.

  Furthermore, in the present embodiment, as a method of manufacturing the upper layer wiring portion, the lowermost layer metal thin film (chromium thin film) having good adhesion to the lower layer wiring portion and the intermediate layer metal thin film (aluminum thin film) having a low resistivity are used. ) And the uppermost metal thin film (chromium thin film) having good adhesion to the etching mask (photoresist), and then wet etching using the etching mask formed in the wiring formation region. The uppermost layer and the intermediate layer metal thin film are sequentially patterned, the etching mask is removed, and then the lowermost layer metal thin film and the uppermost layer metal thin film in the wiring formation region are simultaneously etched away.

  The uppermost metal thin film (chromium thin film) has better adhesion to the etching mask than the intermediate layer (aluminum thin film) of the upper wiring portion, so that when etching the uppermost and intermediate metal thin films. Since the etching mask is prevented from peeling off, there is no gap on the upper surface of the aluminum thin film in the intermediate layer of the upper wiring part, which is relatively easy to etch, and the metal thin film and etching mask as the uppermost layer of the upper wiring part Therefore, it is possible to suppress the etchant from penetrating into the gap on the upper surface of the intermediate layer. Accordingly, it is possible to form a wiring layer having a desired wiring width by suppressing the phenomenon of wiring width narrowing or delamination caused by side etching, in particular, it is possible to form a wiring layer having a short width, The aperture ratio of the display pixel PIX can be improved.

  In addition, when the etching mask is removed, even if a resist residue remains on the uppermost metal thin film, the uppermost metal thin film is removed together with the lowermost metal thin film exposed outside the wiring formation region. Therefore, it is possible to improve the manufacturing yield of the panel by suppressing the deterioration of the display panel quality due to the resist residue.

<Second Embodiment>
Next, a second embodiment of the display device and the manufacturing method thereof according to the present invention will be described. Here, since the pixel arrangement state of the display panel, the circuit configuration of each display pixel, and the planar layout are the same as those of the first embodiment described above, the second embodiment will be described with reference to FIGS. A specific device structure (cross-sectional structure) according to the present invention will be described.

(Device structure of display pixel)
FIG. 10 is a schematic cross-sectional view showing an example of a cross-sectional structure of a display panel (display pixel) according to the second embodiment. Here, a cross section taken along line IVA-IVA and a cross section taken along line IVB-IVB are shown in a display pixel having a planar layout (FIG. 3) equivalent to that of the first embodiment described above. Also in the present embodiment, a display panel (organic EL panel) having a bottom emission type light emitting structure that emits light emitted from the organic EL layer to the view side through an insulating substrate will be described. In addition, about the structure equivalent to 1st Embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified.

  In the first embodiment described above, for the display pixel PIX (organic EL element OEL and pixel driving circuit DC) having the circuit configuration shown in FIG. 2, as shown in FIG. 4, the pixel electrode of the organic EL element OEL 14 is formed in the same layer (on the gate insulating film 12 formed on the insulating substrate 11) as the transistors Tr11 and Tr12, the scanning line Ls, and the power supply voltage line La of the pixel driving circuit DC, and the drain of the transistor Tr12 for driving light emission. The case of having a panel structure directly connected to the electrode Tr12d has been described, but in the second embodiment, the organic EL element OEL (pixel electrode 14) and the pixel drive circuit DC (transistors Tr11, Tr12 and various wirings) are different. The case of having a panel structure formed in layers will be described.

  That is, in the display panel 10 (display pixel PIX) according to the present embodiment, as shown in FIGS. 10A and 10B, a plurality of transistors Tr11 and Tr12 of the pixel drive circuit DC are formed on the insulating substrate 11. Various wirings such as a scanning line Ls and a power supply voltage line La are provided, and the insulating film 13c formed so as to cover the transistors Tr11 and Tr12 and the wiring and a flat surface so that the upper surface is flattened by relaxing the steps in the lower layer. A pixel electrode (for example, an anode electrode) 14, a positive electrode is formed in a pixel formation region Rpx that is an upper layer of the conversion film (insulating layer) 13 d and is defined by a bank 17 protruding from the planarization film 13 d. An organic EL layer (light emitting functional layer) 15 composed of a hole transport layer 15a (charge transport layer) and an electron transport light emitting layer 15b (charge transport layer), and a reference voltage Vss are applied. An organic EL element OEL composed of a counter electrode (for example, a cathode electrode) 16 is formed.

  Here, the source electrode Tr12s of the light emission driving transistor Tr12 provided in the pixel driving circuit DC on the lower layer side (insulating substrate 11 side) passes through the contact hole HL provided in the insulating film 13c and the planarizing film 13d. Thus, a predetermined light emission drive current that is electrically connected to the pixel electrode 14 of the organic EL element OEL on the upper layer side and is generated in the pixel drive circuit DC is supplied to the organic EL element OEL.

  The scan line Ls and the power supply voltage line La (including the power supply wiring layer Lay) are each formed by stacking the lower layer wiring portions Ls0 and La0 and the upper layer wiring portion made of a plurality of metal thin films, as in the first embodiment. The lower wiring portions Ls0 and La0 are provided in the same layer as or integrally with the signal wiring layer Ldx, the source electrode Tr11s and drain electrode Tr11d of the transistor Tr11, and the source electrode Tr12s and drain electrode Tr12d of the transistor Tr12. The source and drain metal layers are simultaneously formed in the patterning process.

  Here, in other words, the source and drain metal layers are at least the signal wiring layer Ldx, the source electrode Tr11s and drain electrode Tr11d of the transistor Tr11, the source electrode Tr12s and drain electrode Tr12d of the transistor Tr12, and the lower layer wiring portion Ls0 of the scanning line Ls. The lower wiring portion La0 of the power supply voltage line La (including the power supply wiring layer Lay) includes, for example, a lower metal layer (transition metal layer for reducing migration) made of chromium (Cr) alone and aluminum-titanium (AlTi And an upper metal layer (low resistance metal layer for reducing the wiring resistance) made of a wiring structure.

  On the other hand, the upper wiring portion of the scanning line Ls and the power supply voltage line La (including the power supply wiring layer Lay) is provided in the same layer as a contact buffer portion BF, which will be described later, formed on the source electrode Tr12s of the transistor Tr12. , Lower wiring lines Ls0 and La0 of the scanning line Ls and the power supply voltage line La, the source electrode Tr11s and the drain electrode Tr11d of the transistor Tr11, the source electrode Tr12s and the drain electrode Tr12d of the transistor Tr12 (aluminum-titanium which is a metal layer on the upper layer side, etc. ) And a lowermost metal thin film (for example, titanium thin film Ls1, La1, Lb1; first metal thin film) made of a metal material having good adhesion to a metal thin film formed as an intermediate layer described later, and a low resistivity. Intermediate layer metal thin film (for example, copper thin films Ls2, La2) for reducing wiring resistance , Lb2; second metal thin film) and the upper layer wiring portion of the scanning line Ls and the power supply voltage line La, the etching mask when patterning the contact buffer portion BF, and the metal thin film formed as an intermediate layer An uppermost metal thin film (for example, a titanium thin film Ls3, La3, Lb3; a third metal thin film) made of a metal material that is good and has a function of preventing oxidation of the metal thin film formed as an intermediate layer; The wiring structure is formed by stacking layers.

  In the organic EL element OEL, similarly to the first embodiment described above, the pixel electrode 14 is formed of a transparent electrode material such as ITO, and the counter electrode 16 is formed of aluminum (Al) or chromium ( It is made of an electrode material having light reflection characteristics such as Cr) and silver (Ag). Here, as shown in FIG. 10A, the pixel electrode 14 extends on the planarizing film 13d in the pixel formation region Rpx, is formed in the contact hole HL, and has a plurality of metal thin films (as described above). For example, it is connected to the source electrode Tr12s of the transistor Tr12 of the pixel drive circuit DC via a contact buffer portion (intervening layer) BF having a structure in which a titanium thin film Lb1, a copper thin film Lb2, and a titanium thin film Lb3) are laminated.

  Further, the bank 17 that defines the pixel formation region Rpx of each display pixel PIX functions as an interlayer insulating film between the pixel electrodes 14 formed in each pixel formation region Rpx, for example, as shown in FIG. The lower insulating layer 17a and the upper metal layer 17b that functions to define the application region of the organic compound material when forming the organic EL layer 15 (the hole transporting layer 15a and the electron transporting light emitting layer 15b). Are stacked in the thickness direction.

  The insulating layer 17a is formed of an inorganic insulating material such as a silicon nitride film (SiN), and the metal layer 17b is formed of a low resistance metal material such as copper or silver. The metal layer 17 b functions as a wiring that applies the reference voltage Vss to the counter electrode 16. Even if the data line Ld overlaps the metal layer 17b in a plan view, the data line Ld depends on the voltage applied to the metal layer 17b because the gate insulating film 12, the insulating film 13c, the planarizing film 13d, and the insulating layer 17a are interposed. The current value of the current flowing through Ld is not easily interfered with. The metal layer 17b may have a triazine thiol compound having water repellency attached to the surface as necessary.

  Such a bank 17 (insulating layer 17a and metal layer 17b) is formed so as to partition the pixel forming regions Rpx along the row direction, and is not formed between the pixel forming regions Rpx along the column direction. As shown in FIG. 1, the uppermost part and the lowermost part of the pixel formation region Rpx are provided so as to be partitioned.

  In such a display panel 10, in the pixel drive circuit DC provided in the lower layer (the layer on the insulating substrate 11 side of the organic EL element OEL), a light emission drive current having a predetermined current value according to display data is generated. The generated light is supplied from the transistor Tr12 for driving light emission (drain electrode Tr12d) to the pixel electrode 14 on the flattening film 13d through the contact hole HL (contact buffer portion BF), whereby the organic pixel of each display pixel PIX is supplied. The EL element OEL emits light with a desired luminance gradation corresponding to display data.

(Manufacturing method of display device)
Next, a method for manufacturing the display device (display panel) according to the present embodiment will be described.
11 to 15 are process cross-sectional views illustrating an example of a method for manufacturing a display device (display panel) according to the present embodiment. Here, in order to clarify the characteristics of the manufacturing method of the display device according to the present embodiment, each of the panel structures of the cross section along the IVA-IVA line and the cross section along the IVB-IVB line (transistor Tr12). , The scanning line Ls, the data line Ld, and the power supply voltage line La) are shown in cross section, and will be described with reference to FIGS. 10A and 10B as appropriate.

  In the manufacturing method of the display device (display panel) described above, first, as shown in FIG. 11A, the gate electrodes Tr11g and Tr12g and the data line Ld are patterned on the transparent insulating substrate 11 with the same gate metal layer. Then, the gate insulating film 12, the semiconductor layer SMC, and the channel protective layer BL are continuously formed. Next, after forming the channel protection layer BL and the semiconductor layer SMC sequentially in the regions corresponding to the gate electrodes Tr11g and Tr12g on the gate insulating film 12, the impurity layers OHM are respectively formed at both ends of the semiconductor layer SMC. Form. Thereafter, contact holes Ch1, Ch2, and Ch3 are formed in the gate insulating film.

  Next, source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d are formed through the impurity layer OHM. At this time, after forming the source and drain metal layers, the source electrodes Tr11s and Tr12s, the drain electrodes Tr11d and Tr12d, the lower layer wiring portion La0 of the power supply voltage line La, the lower layer wiring portion La0 of the power supply wiring layer Lay, and the signal are patterned. The wiring layer Ldx and the lower layer wiring portion Ls0 of the scanning line Ls are simultaneously formed. Here, as in the first embodiment, the source and drain metal layers are a lower metal layer made of chromium (Cr) or the like, and an upper metal layer made of aluminum-titanium (AlTi) or the like. And a wiring structure in which are stacked.

  Next, as shown in FIG. 11B, the insulating substrate including the transistors Tr11 and Tr12, the scanning line Ls and the lower layer wiring portions Ls0 and La0 of the power supply voltage line La (including the power supply wiring layer Lay) and the signal wiring layer Ldx. 11, an insulating film made of silicon nitride (SiN) or the like is formed so as to cover the entire area of one surface side, and then the insulating film is etched to form a contact buffer portion BF (contact connected to the source electrode Tr12s of the transistor Tr12) (Corresponding to the formation portion of the hole HL), the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12, the scanning line Ls, and the insulating film formed by opening the upper surface of the lower layer wiring portions Ls0 and La0 of the power supply voltage line La 13c is formed.

Next, as shown in FIG. 11C, on the insulating substrate 11 on which the insulating film 13c is formed, a metal thin film (hereinafter referred to as “titanium thin film”) Ly1 made of, for example, titanium (Ti) alone or an alloy thereof. Then, a metal thin film (hereinafter referred to as “copper thin film”) Ly2 made of copper (Cu) alone or an alloy thereof, and a metal thin film (titanium thin film) Ly3 made of titanium (Ti) alone or an alloy thereof are sequentially laminated. Specifically, the above three-layered metal thin film is continuously formed using a metal material such as titanium, an alloy thereof, copper or an alloy thereof by sputtering, ion plating, vacuum deposition, plating, or the like. Film. Each metal thin film is, for example, a copper thin film Ly2 having a resistivity of 50 to 100 × 10 ⁻⁶ Ω · cm as a titanium thin film Ly1 or Ly3 of about 10 to 50 nm and a resistivity of 2 to 10 × 10 ⁻⁶ Ω · cm. As a film thickness of about 300 nm to 1 μm.

  Here, the lowermost metal thin film (titanium thin film Ly1) is not limited to titanium, and is exposed at the lower insulating film (silicon nitride film) 13c or the opening of the insulating film 13c as described above. Transistors Tr11, Tr12 source electrodes Tr11s, Tr12s, drain electrodes Tr11d, Tr12d, scan line Ls and lower layer wiring portions Ls0, La0 of power supply voltage line La (a single aluminum layer or an alloy thereof or the like) and intermediate Any metal material may be used as long as the metal film (copper thin film Ly2) formed as a layer has good adhesion (bondability), and the uppermost metal thin film (titanium thin film Ly3) is also limited to titanium. Not an etching mask, but formed as an etching mask MSK and an intermediate layer formed in a process described later (see FIG. 12A) Any metal material having good adhesion (bondability) to the metal thin film (copper thin film Ly2) to be formed and having a function of preventing oxidation of the metal thin film formed as the intermediate layer may be used. The metal thin film (copper thin film Ly2) of the intermediate layer is not limited to copper, but has a low resistivity and adhesion (bonding) to the metal thin films (titanium thin films Ly1, Ly3) of the lowermost layer and the uppermost layer. Any metal material having good properties) may be used.

  Next, as shown in FIG. 12A, a photoresist is formed on the three layers of metal thin films Ly1 to Ly3, exposed and developed, and then contact buffer portion BF, drain electrodes Tr11d and Tr12d, and scanning lines. An etching mask MSK is formed by leaving the photoresist in a region corresponding to the planar pattern of the upper layer wiring portion of Ls and the power supply voltage line La (including the power supply wiring layer Lay).

  Next, using the etching mask MSK, the uppermost titanium thin film Ly3 is etched with a titanium etchant (for example, Adeka Tech WTI / W-A12, B19, etc., manufactured by Asahi Denka Kogyo Co., Ltd.), and subsequently a copper etchant (for example, Asahi Denka Co., Ltd.). The intermediate layer copper thin film Ly2 is etched by an industrial Adeka Super Chemical WAD-5011), and the lowermost layer titanium thin film Ly1 is etched by the above-described titanium etchant.

  Accordingly, as shown in FIG. 12B, the contact buffer portion BF (corresponding to the formation portion of the contact hole HL connected to the source electrode Tr12s of the transistor Tr12), the scanning line Ls, and the power supply voltage line La (feeding wiring) The lower layer titanium thin film Ly1, the intermediate layer copper thin film Ly2, and the uppermost layer titanium thin film Ly3 remain only in the region corresponding to the planar pattern of the layer (including the layer Lay), and the titanium thin film Lb1, the copper thin film Lb2, and the titanium thin film Contact buffer portion BF made of Lb3, upper wiring portion of scanning line Ls made of titanium thin film Ls1, copper thin film Ls2 and titanium thin film Ls3, and upper layer of power supply voltage line La made of titanium thin film La1, copper thin film La2 and titanium thin film La3 And a wiring portion. The titanium thin films Ls1, La1, and Lb1 have better adhesion to the lower layer wiring portion Ls0 and the lower layer wiring portion La0 than the copper thin films Ls2, La2, and Lb2.

  Next, as shown in FIG. 13A, a contact buffer BF, a scanning line Ls, and a power supply voltage line using a stripping solution (for example, R-100 manufactured by Mitsubishi Gas Chemical Co., Ltd., Adeka Remover manufactured by Asahi Denka Kogyo Co., Ltd.). The etching mask MSK remaining on La (including the power supply wiring layer Lay) is removed.

  Next, light made of, for example, a photosensitive organic material is used by using a spin coating method or the like so as to cover the entire area of one surface of the insulating substrate 11 including the contact buffer unit BF, the scanning line Ls, and the power supply voltage line La. After the planarization film 13d having a high transmittance is formed, the planarization film 13d is developed and etched, and as shown in FIG. 13B, the contact buffer portion BF formed on the source electrode Tr12s of the transistor Tr12. A contact hole HL is formed to expose the upper surface of.

  Thus, when the contact hole is formed by etching the planarizing film 13d, the contact buffer portion BF is formed on the source electrode Tr12s of the transistor Tr12 (that is, the source electrode is formed in the contact hole HL). By preventing the Tr12s from being exposed), it is possible to prevent the surface of the drain electrode Tr12d from being damaged by the etching solution of the planarizing film 13d. Further, when copper (Cu) alone or an alloy thereof is applied as the metal thin film Ly2 of the intermediate layer, oxidation is facilitated by the planarization film 13d, but titanium (Ti), chromium (Cr), etc. that are less likely to be oxidized than copper. Since the uppermost metal thin film Ly3 protects the upper surface of the metal thin film Ly2, oxidation over time of the metal thin film Ly2 (copper thin films Ls2, La2, Lb2, etc.) can be suppressed.

  Next, as shown in FIG. 13 (c), on the planarizing film 13d, a substantially central region of the pixel formation region Rpx of each display pixel PIX (the transistors Tr11 and Tr12 and various types in the planar layout shown in FIG. 3). A pixel electrode 14 having a rectangular planar pattern (in a region excluding the peripheral portion where the wiring is disposed) and made of a transparent electrode material such as ITO (having light transmission characteristics) is formed. Here, a part of the pixel electrode 14 is embedded and formed so as to be connected to the contact buffer portion BF exposed in the contact hole HL, whereby the pixel electrode 14 is formed in the contact buffer portion BF in the contact hole HL. Is electrically connected to the source electrode Tr12s of the transistor Tr12.

  Next, an insulating layer made of an inorganic insulating material such as a silicon oxide film or a silicon nitride film is formed using a CVD method or the like so as to cover the entire area of one surface side of the insulating substrate 11 including the pixel electrode 14. Thereafter, as shown in FIG. 14A, the pixel formation region Rpx of each display pixel PIX has an opening through which the upper surface of the pixel electrode 14 is exposed, and a space between the pixel electrodes 14 of the display pixels PIX adjacent in the row direction. An insulating layer 17a to be insulated is formed.

  Next, as shown in FIG. 14B, an etching process is performed on the metal film formed so as to cover the entire area of the one surface side of the insulating substrate 11 including the insulating layer 17a. And the metal layer 17b which protrudes continuously in the column direction of the display panel 10 is formed. Here, the metal layer 17b is preferably a low-resistivity metal such as copper, silver, or gold, and copper is particularly preferable in terms of etching processability and side etching. The metal layer 17b is formed to have a thickness of about 0.3 to 5 μm. Although not shown, an adhesion layer may be provided below the metal layer 17b. Thereby, the pixel formation region of the plurality of display pixels PIX of the same color arranged in the column direction of the display panel 10 is surrounded and defined by the bank (partition wall) 17, and the upper surface of the pixel electrode 14 is exposed in the region. It becomes.

  Next, after cleaning the insulating substrate 11 with pure water, the surface of the pixel electrode 14 exposed in each pixel formation region Rpx defined by the bank 17 is made lyophilic by performing, for example, oxygen plasma treatment or the like, The insulating substrate 11 is immersed in a liquid repellent treatment solution of, for example, a triazine thiol compound to make the surface of the bank 17 liquid repellent.

  Next, after applying a solution or dispersion of a hole transport material in the same process by applying an inkjet method, a nozzle coating method, or the like, to each color pixel formation region (formation region of the organic EL element OEL) Rpx, A hole transport layer (charge transport layer) 15a is formed by heating and drying. Subsequently, an inkjet method or a nozzle coating method is applied to apply a solution or dispersion of an electron transporting light emitting material on the hole transporting layer 15a, followed by drying by heating to form an electron transporting light emitting layer (charge transporting). Layer) 15b. As a result, as shown in FIG. 15A, an organic EL layer (light emitting functional layer) 15 composed of a hole transport layer 15a and an electron transport light emitting layer 15b is formed on the pixel electrode 14 in a stacked manner.

Next, as shown in FIG. 15B, the organic EL layer 15 (the hole transport layer 15a and the electron transport light emitting layer 15b) has light reflection characteristics on the insulating substrate 11 including each pixel formation region Rpx. ) To form a counter electrode (for example, a cathode electrode) 16 composed of a single planar electrode (solid electrode) that faces each pixel electrode 14. Here, the counter electrode 16 may be a thin film made of, for example, aluminum (Al), chromium (Cr), silver (Ag), palladium silver (AgPd), or the like.
Thereafter, after forming the counter electrode 16, a sealing layer 18 made of a silicon oxide film, a silicon nitride film, or the like is formed on the entire surface of the one surface side of the insulating substrate 11, so that the cross-sectional structure (as shown in FIG. A display panel 10 having a bottom emission type light emitting structure is completed.

  As described above, in the display device and the manufacturing method thereof according to the present embodiment, the adhesiveness (bondability) with the lower layer wiring unit as the upper layer wiring unit such as the power supply voltage line and the scanning line disposed in the display panel. ) Is a metal thin film (bottom layer titanium thin film) made of titanium or an alloy thereof, a metal thin film (copper thin film serving as an intermediate layer) made of copper or an alloy thereof having a low resistivity, a power supply voltage line, It consists of titanium or its alloy to suppress the phenomenon that oxygen contained in the planarizing film formed to cover the scanning line is combined (oxidized) with the metal thin film (copper thin film) as an intermediate layer to expand. It has a structure in which a metal thin film (uppermost titanium thin film; antioxidant film) is laminated.

  As a result, as in the first embodiment described above, even when a metal material such as copper or an alloy thereof having a low resistivity is used for the upper wiring portion, the insulating substrate or the lower wiring portion is interposed between the insulating substrate and the lower wiring portion. Since a metal thin film (titanium thin film, etc.) with high adhesion is interposed, there is no gap on the lower surface of the copper thin film in the middle layer of the upper wiring portion that is relatively easy to etch, and there is no gap between the upper wiring portion and the lower wiring portion. Since there is no gap, it can be suppressed that the etchant penetrates into the gap on the lower surface of the intermediate layer and the intermediate layer is side-etched. Therefore, it is possible to suppress a phenomenon in which the wiring width is narrowed or delaminated due to side etching, and a wiring layer having a desired wiring width can be formed.

The uppermost metal thin film (titanium thin film) has better adhesion to the etching mask than the intermediate layer (copper thin film) in the upper wiring part, and etches the upper and lower metal thin films in the upper wiring part. In this case, the phenomenon that the etching mask is peeled off is suppressed, so that there is no gap on the upper surface of the copper thin film in the intermediate layer of the upper wiring portion, which is relatively easily etched, and the metal thin film (the uppermost layer of the upper wiring portion) ( Since there are no gaps between the titanium thin film and the etching mask and the etching mask, it is possible to prevent the etchant from penetrating into the gaps on the upper surface of the intermediate layer.
Therefore, it is possible to suppress a phenomenon in which the wiring width is thinned or delaminated due to the side etching of the intermediate layer, thereby forming a wiring layer having a desired wiring width. In particular, a wiring layer having a short width (for example, 15 μm or less). Can be formed.

  Even when the display panel has a high brightness or a large screen, the wiring resistance of each wiring layer can be reduced to suppress signal delay and voltage drop, so that it is applied to each display pixel. By suppressing voltage fluctuations, it is possible to prevent the occurrence of brightness reduction, variation, crosstalk, etc. In addition, the uppermost metal thin film (titanium) as an antioxidant film for the intermediate metal thin film (copper thin film) Thin film), it is possible to suppress the occurrence of delamination and cracks due to the expansion of the metal thin film (copper thin film) of the intermediate layer, thereby realizing a display panel with high product yield and high reliability.

In addition, as a contact buffer portion in the contact portion (in the contact hole) for electrically connecting the pixel driving circuit and the organic EL element, the lower layer titanium thin film and the intermediate layer copper thin film as the upper layer wiring portion. And the uppermost titanium thin film.
Thus, a step of forming a contact hole in the planarization film for electrically connecting the pixel electrode of the organic EL element and the light emission driving transistor of the pixel driving circuit, and a step of patterning ITO or the like to be the pixel electrode In the above, the drain electrode of the transistor is damaged by etching or a battery reaction (a reduction reaction occurs on the ITO surface and an oxidation reaction occurs on the aluminum surface serving as the source electrode in contact with the ITO to increase the resistance. Can be prevented from occurring due to corrosion and peeling, so that an increase in contact resistance and disconnection at the contact portion can be prevented. Furthermore, since transparent electrode materials such as ITO used for the pixel electrode have poor bondability with aluminum or its alloy used for the source electrode of the light emission driving transistor, it is preferable to use the contact buffer portion as an intervening layer. An electrical connection can also be realized.

  By the way, in this embodiment, in order to prevent the oxidation of the metal thin film (copper thin film) which is an intermediate layer of the wiring layer which is low resistance and relatively easily oxidized, a metal material which is not easily oxidized on the metal thin film of the intermediate layer. The structure in which the uppermost metal thin film (titanium thin film) is formed is shown. As a specific dimension example of the wiring layer that becomes the upper wiring portion of the scanning line and the power supply voltage line, the thickness of the copper thin film that is the metal thin film of the intermediate layer is set to 1 μm, and the wiring width is set to several tens to several tens of μm In this case, the copper thin film exposed on the side surface of the wiring layer is very small compared to the upper surface (wiring width). Therefore, as described above, even with a wiring structure in which only the upper surface is covered with the uppermost metal thin film (titanium thin film), oxidation due to the factor (oxygen) that promotes oxidation contained in the planarization film is sufficiently prevented. Generation of delamination and cracks can be effectively prevented.

  Here, since the film thickness and wiring width of the metal thin film (copper thin film) serving as the intermediate layer described above are determined by the size of the display panel, the exposure amount on the side surface of the wiring layer may be relatively large. In such a case, as shown in FIG. 16, for example, the uppermost metal thin film (titanium thin films Ls3, La3, Lb3) and at least the upper surface of the metal thin film (copper thin films Ls2, La2, Lb2) and the intermediate layer A wiring structure that covers the side surfaces may be applied to prevent the metal thin film in the intermediate layer from being oxidized almost completely.

  In this case, in the manufacturing method shown in the present embodiment, the lowermost metal thin film Ly1 and the intermediate metal thin film Ly2 are sequentially stacked, and then wiring layers such as scan lines and power supply voltage lines, contact buffers, etc. Using the first etching mask corresponding to the planar pattern of the part, the intermediate layer metal thin film Ly2 and the lowermost layer metal thin film Ly1 are patterned, and then the uppermost layer metal thin film Ly3 is formed by coating. Each step of patterning and forming the uppermost metal thin film (titanium thin films Ls3, La3, Lb3) covering at least the upper surface and the side surface of the intermediate metal thin film using the etching mask can be applied.

  In each of the embodiments described above, the display panel having a bottom emission type light emitting structure has been described. However, the present invention is not limited to this, and the display panel may have a top emission type light emitting structure. Good. In this case, the pixel electrode may be formed of a conductive material having a light reflection characteristic such as aluminum or chromium, and the counter electrode may be formed of a conductive material having a light transmission characteristic such as ITO.

  Further, in each of the embodiments described above, an intermediate layer metal thin film (for example, a copper thin film) made of a low-resistance metal material is sandwiched between the structure of the wiring layer that becomes the scanning line and the power supply voltage line and in the manufacturing process. As described above, the case where the lowermost layer and the uppermost metal thin film (for example, a titanium thin film) made of the same metal material are formed has been described. However, the present invention is not limited to this, and the metal thin film or the etching that is the intermediate layer Different metal materials may be applied as long as they have good adhesion to the mask and the lower wiring part, and moreover are less susceptible to oxidation than the metal thin film serving as the intermediate layer. Note that if different metal materials are used as the lowermost and uppermost metal thin films, the etchant will change for each metal thin film in the patterning process of the wiring layer. More preferably, the lower and uppermost metal thin films are formed of the same metal material.

Further, in each of the embodiments described above, the case where the organic EL layer is composed of a hole transport layer and an electron transporting light emitting layer has been described. However, the present invention is not limited to this, for example, hole transport / electron Only the transporting light emitting layer may be used, the hole transporting light emitting layer and the electron transporting layer may be used, or a charge transporting layer may be appropriately interposed therebetween, or a combination of other charge transporting layers may be used.
In each of the above-described embodiments, the pixel electrode is an anode. However, the pixel electrode is not limited to this and may be a cathode. At this time, in the organic EL layer, the charge transport layer in contact with the pixel electrode may be an electron transport layer.

It is a schematic plan view which shows an example of the pixel arrangement state of the display panel applied to the display apparatus which concerns on this invention. FIG. 6 is an equivalent circuit diagram illustrating a circuit configuration example of each display pixel (light emitting element and pixel driving circuit) two-dimensionally arranged on the display panel of the display device according to the present invention. It is a plane layout figure which shows an example of the display pixel applicable to the display apparatus (display panel) which concerns on this embodiment. It is a schematic sectional drawing which shows the AA cross section and BB cross section in the display pixel which has the planar layout which concerns on this embodiment. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 4) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 5) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is a schematic sectional drawing which shows an example of the cross-section of the display panel (display pixel) which concerns on 2nd Embodiment. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 4) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 5) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is a schematic sectional drawing which shows the other example of sectional structure of the display panel (display pixel) which concerns on 2nd Embodiment. It is the schematic which shows the principal part structural example of the display apparatus provided with the active matrix type display panel in a prior art, and the circuit structural example of a display pixel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display panel 11 Insulating substrate 13a-13c Insulating film 13d Flattening film 14 Pixel electrode 15 Organic EL layer 15a Hole transport layer 15b Electron transport light emitting layer 16 Counter electrode 17 Bank 17a Insulating layer 17b Metal layer Ls Scan line La Power supply Voltage line Ls0, La0 Lower layer wiring part Ls1, La1, Lb1, Ls3, La3, Lb3 Chrome thin film, Titanium thin film Ls2, La2, Lb2 Aluminum thin film, Copper thin film BF Contact buffer part PIX Display pixel Rpx Pixel formation area

Claims (5)

In a method for manufacturing a display device including a pixel driving circuit having a transistor and a display element having a pair of electrodes,
A first opening that exposes at least part of the first electrode of the pair of electrodes of the display element; and a second opening that exposes at least part of one of the source and drain electrodes of the transistor. Forming an insulating film having,
A first metal thin film having a first metal material on the first electrode exposed in the first opening and on one of the source and drain electrodes of the transistor exposed in the second opening; A second metal thin film having a second metal material and a third metal thin film having the same material as the first metal material are sequentially laminated,
Etching the third metal thin film and the second metal thin film sequentially with an etching mask formed on the third metal thin film at a position corresponding to the second opening as a mask,
After removing the etching mask, the first metal thin film remaining on the first opening is removed to expose the first electrode,
A method of manufacturing a display device, comprising forming an organic EL layer on the first electrode.   The step of removing the first metal thin film remaining on the first opening portion removes the third metal thin film at a position corresponding to the etching mask together with the first metal thin film. A manufacturing method of the display device according to 1.   3. The method of manufacturing a display device according to claim 1, wherein the first metal material is chromium or an alloy thereof, and the second metal thin film is aluminum or an alloy thereof. The display device has a scanning line connected to the pixel driving circuit,
In the step of sequentially laminating the first metal thin film, the second metal thin film, and the third metal thin film, the first metal thin film, the second metal thin film, and the scan line forming region, And sequentially stacking the third metal thin film,
In the step of sequentially etching the third metal thin film and the second metal thin film, the third metal thin film and the second metal thin film are sequentially etched using the second etching mask formed in the scan line formation region as a mask. ,
In the step of removing the first metal thin film and exposing the first electrode, the second metal thin film and the first metal thin film at positions corresponding to the second etching mask by etching the third metal thin film 4. The display device according to claim 1, wherein the scanning line formed only of the second metal thin film and the first metal thin film is formed in a region where the scanning line is formed by remaining the film. 5. Manufacturing method. The display device has a power supply voltage line connected to the pixel driving circuit,
In the step of sequentially laminating the first metal thin film, the second metal thin film, and the third metal thin film, the first metal thin film and the second metal thin film are also formed in a region where the power supply voltage line is formed. , Sequentially stacking the third metal thin film,
In the step of sequentially etching the third metal thin film and the second metal thin film, the third metal thin film and the second metal thin film are sequentially etched using the third etching mask formed in the power supply voltage line forming region as a mask. And
In the step of removing the first metal thin film and exposing the first electrode, the second metal thin film and the first metal thin film at positions corresponding to the third etching mask by etching the third metal thin film 5. The power supply voltage line including only the second metal thin film and the first metal thin film is formed in a region where the power supply voltage line is formed. Manufacturing method of display device.

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