JP5648395B2 - LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE - Google Patents

Description

  The present invention relates to a light emitting device, a method for manufacturing a light emitting device, and an electronic apparatus, and more particularly, to a light emitting apparatus in which a plurality of pixels including a light emitting element are arranged, a method for manufacturing the same, and an electronic apparatus mounted with the light emitting device.

In recent years, an EL display device using an EL (Electro Luminescence) element as a light emitting element is known (for example, see Patent Document 1).
An EL display device, which is a light emitting device, includes a plurality of EL elements. For example, the EL display apparatus displays various images and videos by an active matrix driving method that controls a current supplied to each EL element. An EL display device to which an active matrix driving method is applied includes a thin film transistor as a switching element that controls light emission of an EL element for each of a plurality of pixels.

  In such an EL display device, an EL element constituting a pixel, a thin film transistor, various wirings, and the like are formed on one side of the substrate, and further, the EL element is protected from being deteriorated by moisture, oxygen, or the like. Therefore, a structure is employed in which a sealing substrate is bonded to one surface of the substrate and an EL element or the like is sealed between the substrate and the sealing substrate.

JP 2001-147659 A

However, in the case of the above prior art, when the sealing substrate is bonded to the substrate, when the sealing substrate is pressed against the substrate, or in the EL display device manufactured by bonding the substrate and the sealing substrate, the external When a force is applied to the sealing substrate from the side, the sealing substrate may press one side of the substrate.
If the wiring is damaged by the pressing of the sealing substrate, there is a problem in that the EL element is deteriorated due to a defect in light emission of the EL element.

  An object of the present invention is to improve the quality of a light emitting device.

In order to solve the above problems, one embodiment of the present invention is a light-emitting device, which is a first substrate, a plurality of pixels arranged on one surface of the first substrate, and one surface side of the first substrate. And a second substrate that seals each pixel between the first substrate and each pixel, wherein each pixel includes a light emitting element and a transistor that controls light emission of the light emitting element. The at least two wirings connected to the transistor and intersecting each other, and at least the four regions divided by the two wirings crossing each other as a boundary line, is disposed at the corner portion serving as mutual nearest neighbor in the two regions in the vertical angle of the relationship between wiring crossing region where two wires intersect, the wiring intersection toward the second substrate from the one surface of the first substrate a plurality of wires crossing in the region It is formed so as to protrude, and the feature that it has a plurality of protrusions at least one wiring of the at least two of the wiring is formed between the passing Ru position, respectively.
Preferably, the transistor includes an electrode, an insulating film, and a semiconductor film, and the protruding portion has a stacked structure in which layers made of the same material as the electrode, the insulating film, and the semiconductor film are stacked. .
Preferably, the stacked structure of the protruding portion includes a layer made of the same material as the wiring.
An electronic device in which the light emitting device is mounted functions well.

Another aspect of the present invention is a method for manufacturing a light-emitting device, which includes a light-emitting element, a transistor that controls light emission of the light-emitting element, and at least two wirings that are connected to the transistor and intersect each other. A method of manufacturing a light emitting device in which a plurality of pixels are arranged, the step of forming the transistor having an electrode, an insulating film, and a semiconductor film on one surface of a first substrate, and at least for each of the plurality of pixels , Of the four regions divided by the two wires intersecting each other with the two wires as a boundary line, two regions having a vertical angle relationship of the wire intersecting region where the two wires intersect at the corner portion serving as mutual nearest neighbor protrudes than the plurality of lines that intersect at the wiring crossing region from one surface side of the first substrate, small of the at least two wires A step of Kutomo single wires to form a plurality of protrusions formed on the passing Ru position between, the plurality of pixels so as to seal between the first substrate, said first substrate Bonding the second substrate to the one surface side, and the step of forming the projecting portion is the same as the step of forming the transistor, the same as the electrode, the insulating film, and the semiconductor film forming the transistor The method includes a step of stacking layers made of materials to form a stacked structure that forms at least a part of the protruding portion.
Preferably, the step of forming the protruding portion includes a step of forming a layer made of the same material as the wiring and forming a part of the stacked structure.

  According to the present invention, it is possible to improve the quality of the light emitting device.

It is a schematic block diagram which shows the display apparatus which concerns on this embodiment. It is an equivalent circuit diagram of a pixel applied to the display device according to the present embodiment. It is a schematic plan view which shows the structure of the display panel of the display apparatus which concerns on this embodiment. It is sectional drawing of the surface along the IV-IV line of FIG. It is a top view which shows an example of the pixel applied to the display apparatus which concerns on this embodiment. It is sectional drawing of the surface along the VI-VI line of FIG. It is sectional drawing of the surface along the VII-VII line of FIG. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the manufacturing process of the display apparatus which concerns on this embodiment. It is explanatory drawing which shows the state which gave the pressing force to the opposing board | substrate of the display apparatus which concerns on this embodiment. It is a front view which shows an example of the mobile telephone which mounted the display apparatus. They are the front side perspective view (a) which shows an example of the digital camera which mounted the display apparatus, and a rear side perspective view (b). It is a perspective view which shows an example of the personal computer which mounted the display apparatus.

  Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

(Display device)
FIG. 1 is a schematic block diagram illustrating a display device according to the present embodiment, and FIG. 2 is an equivalent circuit diagram of a pixel applied to the display device according to the present embodiment.
FIG. 3 is a schematic plan view showing the overall configuration of the display panel of the display device according to the present embodiment, and FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG.

  As shown in FIG. 1, a display device 100 as a light emitting device generally includes a display panel 110 in which a plurality of pixels PIX are two-dimensionally arranged, and a selection driver (selection drive circuit) for setting each pixel PIX to a selected state. ) 120, a data driver (signal driving circuit) 130 for supplying gradation signals corresponding to image data to each pixel PIX, and a controller 140.

Here, in the display panel 110 (display device 100) applied to the present embodiment, as shown in FIGS. 3 and 4, the substrate 11 as the first substrate and the counter substrate 20 as the second substrate face each other. Are arranged.
A pixel array 111 in which a plurality of pixels PIX is two-dimensionally arranged is provided on one surface side (the upper surface side in FIG. 4) of the substrate 11, and each pixel PIX is driven in the peripheral region of the pixel array 111. A lead line Lr is provided for supplying the above signal. The lead line Lr has one end connected to the pixel array 111 (each pixel PIX) and the other end connected to a connection terminal TM provided at an end of the substrate 11, for example. The connection terminal TM is connected to a selection driver 120 and a data driver 130 provided outside the substrate 11 or a driver chip having these driver functions via a film substrate (flexible printed circuit board) FPC or the like. .
Then, as shown in FIGS. 3 and 4, the substrate 11 and the counter substrate 20 that are arranged to face each other are bonded via a sealing material 30 provided in a peripheral region of the pixel array 111, and the pixel array 111 (each The pixel PIX) is sealed between the substrate 11 and the counter substrate 20 to be protected from the influence of the external environment. A gap material (not shown) for setting a gap (gap) between the substrate 11 and the counter substrate 20 is provided in the sealing material 30. As a result, the gap between the one surface side of the substrate 11 and the counter substrate 20 is set to such a value that the counter surface of the counter substrate 20 (the lower surface facing the substrate 11 in FIG. 4) does not contact the upper surface of the pixel array 111. Has been.

Further, the pixels PIX arranged in the display panel 110 (display device 100) of the present embodiment include, for example, a light emission drive circuit DC and an organic EL element OEL which is a current drive type light emitting element, as shown in FIG. It is equipped with.
The light emission drive circuit DC generates a light emission drive current having a current value corresponding to the image data and supplies the light emission drive current to the organic EL element OEL.
The organic EL element OEL emits light at a luminance gradation corresponding to image data based on the light emission drive current supplied from the light emission drive circuit DC.

For example, as shown in FIG. 2, the light emission drive circuit DC includes transistors Tr11 and Tr12, which are switching elements, and a capacitor Cs.
The transistor (select transistor) Tr11 has a gate terminal connected to the selection line Ls, a drain terminal connected to the data line Ld, and a source terminal connected to the contact N11.
The transistor (drive transistor) Tr12 has a gate terminal connected to the contact N11, a drain terminal connected to the power supply line La (high potential power supply voltage Vsa), and a source terminal connected to the contact N12.
The capacitor Cs is connected between the gate terminal (contact N11) and the source terminal (contact N12) of the transistor Tr12.
The selection line Ls, the data line Ld, and the power supply line La are connected to the transistors Tr11 and Tr12, respectively, and function as wirings for transmitting various signals for causing the organic EL element OEL to emit light.

  Further, the organic EL element OEL has an anode (a pixel electrode serving as an anode electrode described later) connected to a contact N12 of the light emission drive circuit DC, and a cathode (a counter electrode serving as a cathode electrode described later) having a predetermined low potential power source (reference). Voltage Vsc; for example, ground potential Vgnd).

  Here, an n-channel thin film transistor can be applied to both the transistors Tr11 and Tr12. If the transistors Tr11 and Tr12 are P-channel type, the source terminal and the drain terminal are opposite to each other. The capacitor Cs is a parasitic capacitance formed between the gate and the source of the transistor Tr12, an auxiliary capacitance additionally provided between the gate and the source, or a capacitance component composed of the parasitic capacitance and the auxiliary capacitance. .

  For example, the selection line Ls connected to the pixel PIX is arranged in the row direction (left-right direction in FIG. 1) of the display panel 110 (display device 100) and is connected to the selection driver 120. A selection voltage (selection signal) Vsel of a selection level or a non-selection level is applied to the selection line Ls from the selection driver 120. Further, the data line Ld connected to the pixel PIX is disposed in the column direction (vertical direction in FIG. 1) of the display panel 110 (display device 100) and connected to the data driver 130, for example. A gradation voltage (selection signal) Vdata corresponding to image data is applied from the data driver 130 to the data line Ld. A power supply voltage (voltage signal) Vsa is applied to the power supply line La connected to the pixel PIX.

  The controller 140 generates display data composed of digital data including luminance gradation data based on image data supplied from the outside of the display device 100, and supplies the display data to the data driver 130. The controller 140 controls the operation state of the selection driver 120 and the data driver 130 based on a timing signal generated or extracted based on the image data, and displays a predetermined image on the display panel 110 (display device 100). A selection control signal and a data control signal for executing the operation are generated and output.

  Accordingly, the selection driver 120 applies the selection voltage Vsel of the selection level to the selection line Ls of each row based on the selection control signal, thereby setting the pixel PIX of each row to the selected state. The data driver 130 generates a gradation voltage Vdata corresponding to the image data based on the data control signal, and supplies it to the pixel PIX set to the selected state via each data line Ld.

  In the display drive operation of the display device 100 including the pixel PIX having such a circuit configuration, first, a selection level (high level) is selected from the selection driver 120 to the selection line Ls in a predetermined selection period. By applying the voltage Vsel, the transistor Tr11 is turned on to set the pixel PIX to a selected state. In synchronization with this timing, the gradation voltage Vdata having a voltage value corresponding to the image data is applied from the data driver 130 to the data line Ld, whereby the potential corresponding to the gradation voltage Vdata is applied to the contact N11 via the transistor Tr11. Is applied.

  As a result, the transistor Tr12 is turned on in a conductive state corresponding to the gradation voltage Vdata, a light emission drive current having a predetermined current value flows between the drain and the source, and the organic EL element OEL has the gradation voltage Vdata (that is, an image). Light emission at a luminance gradation corresponding to the data. At this time, charges are accumulated (charged) in the capacitor Cs connected between the gate and source of the transistor Tr12 based on the gradation voltage Vdata applied to the contact N11.

Next, in a non-selection period after the end of the selection period, the selection driver 120 applies a selection voltage Vsel of a non-selection level (low level) to the selection line Ls, thereby turning off the transistor Tr11, thereby causing the pixel PIX. Is set to the non-selected state. At this time, the charge accumulated in the capacitor Cs (that is, the potential difference between the gate and the source) is held, and a voltage corresponding to the gradation voltage Vdata is applied to the gate terminal of the transistor Tr12. Therefore, a light emission drive current having a current value equivalent to that in the light emission operation state (selection period) flows between the drain and source of the transistor Tr12, and the organic EL element OEL continues to emit light.
Then, the desired image information is displayed by sequentially executing such a display driving operation for every pixel PIX two-dimensionally arranged on the display panel 110 (display device 100), for example, for each row.

(Pixel device structure)
Next, a specific device structure of a pixel (light emission drive circuit and organic EL element) having the circuit configuration as described above will be described. Here, a display panel 110 having a bottom emission type light emitting structure in which light emitted from the organic EL layer of the organic EL element OEL is transmitted through the transparent substrate 11 and emitted to the viewing side (the lower surface side of the substrate 11). A display device 100) will be described.

  FIG. 5 is a plan view illustrating an example of a pixel applied to the display device according to the present embodiment. 6 is a cross-sectional view of the plane along line VI-VI in FIG. 5, and FIG. 7 is a cross-sectional view of the plane along line VII-VII in FIG.

  As shown in FIGS. 5 to 7, the pixel PIX is provided for each pixel formation region Rpx set on one surface side (upper surface side in FIG. 6) of a transparent insulating substrate (first substrate) 11 such as glass. Is provided. In this pixel formation region Rpx, at least a boundary region between the formation region (EL element formation region) Rel of the organic EL element OEL and the adjacent pixel PIX is set. Further, the pixel formation region Rpx includes a wiring intersection region Rx that three-dimensionally intersects with various wirings (selection line Ls, data line Ld, power supply line La) insulated.

  In the pixel PIX shown in FIG. 5, a selection line Ls and a power supply line La are provided on the edge (lower side in the drawing) of the pixel formation region Rpx so as to extend in the row direction (left and right direction in the drawing). It is arranged. A data line Ld is arranged on the edge (right side in the figure) of the pixel formation region Rpx so as to extend in the column direction (vertical direction in the figure) perpendicular to the selection line Ls and the power supply line La. Has been.

  Further, in the display device 100 (pixel PIX) shown in FIG. 5, for example, as shown in FIG. 6, a partition layer 15 having an opening provided in the EL element formation region Rel in the pixel formation region Rpx is provided. Yes. That is, in the display device 100 (pixel PIX) shown in FIG. 5, in the boundary region between the pixels PIX arranged adjacent to each other in the row direction (left and right direction in the figure) and the column direction (up and down direction in the figure), As shown in FIG. 6, a partition wall layer 15 having a continuous thickness is provided on the surface of the substrate 11. A region surrounded by the partition layer 15 and from which the pixel electrode 16 is exposed (that is, an opening of the partition layer 15) is defined as an EL element formation region Rel.

  As shown in FIGS. 5 to 7, the selection line Ls is provided on the upper surface of the substrate 11 on the lower layer side than the data line Ld and the power supply line La. The selection line Ls is collectively formed in the same process as the gate electrodes Tr11g and Tr12g by patterning the gate metal layer for forming the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12. In particular, the selection line Ls is formed integrally with the gate electrode Tr11g of the transistor Tr11 as shown in FIG.

  Further, as shown in FIGS. 5 to 7, the data line Ld is provided on the upper surface of the gate insulating film 12 on the lower layer side than the power supply line La. The data line Ld is provided so as to be covered with the interlayer insulating film 13 like the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12. That is, the data line Ld is formed by patterning the source-drain metal layer for forming the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the transistors Tr11 and Tr12, thereby forming the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d. Are formed in the same process. In particular, the data line Ld is formed integrally with the drain electrode Tr11d of the transistor Tr11 as shown in FIG.

  5 to 7, the power supply line La is provided on the upper layer side of the data line Ld and the power supply line La and on the upper surface of the interlayer insulating film 13 covering the transistors Tr11 and Tr12. As shown in FIG. 5, the power supply line La is connected to the drain electrode Tr12d of the transistor Tr12 through a contact hole HL12 provided in the interlayer insulating film 13.

  In the pixel PIX shown in FIG. 5, the transistors Tr11 and Tr12 provided in the light emission drive circuit DC are arranged side by side in the column direction (vertical direction in the figure) along the data line Ld, for example. Yes. Specifically, the channel width direction of the transistors Tr11 and Tr12 is provided in a direction extending in parallel with the data line Ld. Each of the transistors Tr11 and Tr12 has a field effect thin film transistor structure as shown in FIG. In the following description of the transistor Tr11, for the sake of illustration, the description will be made with reference to the cross-sectional structure of the transistor Tr12 shown in FIG.

  As shown in FIGS. 5 and 6, the transistors Tr11 and Tr12 are provided with a gate insulating film 12 so as to cover the gate electrodes Tr11g and Tr12g formed on the substrate 11, and on the gate insulating film 12, A semiconductor film SMC (not shown in FIG. 5) is provided in a region corresponding to the gate electrodes Tr11g and Tr12g. In addition, a channel protective film BL which is an insulating film is provided on a channel region formed in the semiconductor film SMC, and source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d are provided so as to face each other with the channel protective film BL interposed therebetween. It has been. An impurity semiconductor film OHM is provided between the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d and the semiconductor film SMC, so that the semiconductor film SMC, the source electrodes Tr11s and Tr12s, and the drain electrodes Tr11d and Tr12d are in ohmic contact, respectively. doing.

  In the transistor Tr11, the gate electrode Tr11g is formed integrally with the selection line Ls so as to correspond to the circuit configuration of the light emission drive circuit DC shown in FIG. Further, the drain electrode Tr11d is formed integrally with the data line Ld as shown in FIG. Further, as shown in FIG. 5, the source electrode Tr11s is connected to the gate electrode Tr12g of the transistor Tr12 through a contact hole HL11 provided in the gate insulating film 12. Here, the contact hole HL11 corresponds to the contact N11 of the light emission drive circuit DC shown in FIG.

  Further, as shown in FIG. 5, the transistor Tr12 is connected to the source electrode Tr11s of the transistor Tr11 through the contact hole HL11 in which the gate electrode Tr12g is provided in the gate insulating film 12. Further, as shown in FIG. 5, the drain electrode Tr12d is connected to the power supply line La via a contact hole HL12 provided in the interlayer insulating film 13. The source electrode Tr12s is connected to the pixel electrode 16 of the organic EL element OEL as shown in FIGS.

  As shown in FIGS. 5 and 6, the organic EL element OEL is an element in which a pixel electrode (anode electrode) 16, an organic EL layer (light emitting functional layer) 17, and a counter electrode (cathode electrode) 18 are sequentially stacked. It has a structure. Here, in the present embodiment, since the organic EL element OEL has a bottom emission type light emitting structure, the pixel electrode 16 is light-transmitting (high light transmittance) such as tin-doped indium oxide (ITO). ) And a transparent electrode material. On the other hand, the counter electrode 18 is formed to include an electrode material having a high light reflectance such as aluminum alone or an aluminum alloy.

As shown in FIGS. 5 and 6, the pixel electrode 16 is connected to the source electrode Tr12s of the transistor Tr12.
As shown in FIGS. 5 and 6, the organic EL layer 17 is formed on the pixel electrode 16 exposed in the EL element formation region Rel defined by the opening provided in the partition wall layer 15 formed on the substrate 11. Is done. The organic EL layer 17 is formed of, for example, a hole injection layer 17a and an electron transporting light emitting layer 17b.

  The counter electrode 18 is formed of a single electrode layer (solid electrode) so as to face the pixel electrode 16 of each pixel PIX two-dimensionally arranged on the substrate 11 in common. Further, as shown in FIGS. 5 and 6, the counter electrode 18 extends not only to the EL element formation region Rel of each pixel PIX but also to the partition layer 15 that defines the EL element formation region Rel. Is provided. Further, the counter electrode 18 is connected to a low potential power supply (reference voltage Vsc) through a contact portion and a lead line (not shown).

  As shown in FIGS. 5 and 6, the partition layer 15 covers the interlayer insulating film 13 formed in the boundary region between the pixels PIX arranged on the substrate 11, and the power supply line La on the interlayer insulating film 13. The surface of the substrate 11 is provided with a thickness so as to cover the protective insulating film 14. The partition layer 15 is provided with an opening through which the pixel electrode 16 of the organic EL element OEL is exposed. Here, the partition wall layer 15 is formed of an insulating material that can be patterned using, for example, a dry etching method, for example, a polyimide resin material that is a photosensitive insulating material.

  Then, on one surface side of the substrate 11 on which the light emission drive circuit DC, the organic EL element OEL, and the partition wall layer 15 are formed, a counter substrate (second substrate) 20 such as glass has a predetermined gap from the one surface side of the substrate 11. Thus, the pixels PIX and the like are sealed.

  In the pixel PIX having such a device structure, in this embodiment, as shown in FIGS. 5 and 7, in the vicinity of the selection line Ls, the data line Ld, and the power supply line La in each pixel formation region Rpx, A plurality (four in this embodiment) of projecting portions PLA so as to surround a wiring intersection region Rx (intersections and vertices of wiring) that three-dimensionally intersect with the selection line Ls, the data line Ld, and the power supply line La insulated. , PLB, PLC, and PLD are provided. Here, the height (projection dimension) of the protrusions PLA, PLB, PLC, and PLD from the surface of the substrate 11 is formed to be higher than other elements (for example, transistors Tr11 and Tr12) in the pixel formation region Rpx. ing. The region where the protrusions PLA, PLB, PLC, and PLD are provided is formed thicker than the wiring intersection region Rx where the selection line Ls, the data line Ld, and the power supply line La intersect, and the protrusions PLA, The region where the PLB, PLC, and PLD are provided is the region closest to the counter substrate 20.

Accordingly, when the counter substrate 20 is pressed toward the substrate 11 in order to bond the counter substrate 20 to the substrate 11, or when a pressing force is applied to the counter substrate 20 from the outside when the display device 100 is used, Even if the protruding portions PLA, PLB, PLC, and PLD in the pixel formation region Rpx come into contact with the counter substrate 20, no pressing force is applied to the selection line Ls, the data line Ld, and the power supply line La. Therefore, the pressing force applied when the counter substrate 20 is bonded to the substrate 11 and the pressing force applied from the outside to the counter substrate 20 when the display device 100 is used are concentrated on the protrusions PLA, PLB, PLC, and PLD. Since the pressing force is not applied to the selection line Ls, the data line Ld, and the power supply line La, the selection line Ls, the data line Ld, and the power supply line La are prevented from being damaged (disconnected) or short-circuited. can do.
Note that at least one of the four protrusions PLA, PLB, PLC, and PLD may be provided in the vicinity of the wiring intersection region Rx. Preferably, it may be provided in at least two places (for example, the projecting portions PLB and PLD, or the projecting portions PLA and PLC) along the direction sandwiching the wiring intersection region Rx. And it is more preferable to provide the protrusions PLA, PLB, PLC, and PLD at four places surrounding the wiring intersection region Rx.

Specifically, the protrusions PLA, PLB, PLC, and PLD are formed on the substrate 11, as shown in FIG. 5 and FIG. 7, on the protrusion layer PL11, the gate insulating film 12, the protrusion layers PL12 to PL16, and the interlayer insulating film 13. The protrusion layer PL17 and the protective insulating film 14 are sequentially stacked.
Here, the projecting layer PL11 is composed of a gate metal layer (conductive layer) that forms the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12. By patterning the gate metal layer, the same as the gate electrodes Tr11g and Tr12g and the selection line Ls. It is formed at a time in the process. Further, the projecting layers PL12 to PL14 are made of the same material as the semiconductor film SMC, the channel protective film BL, and the impurity semiconductor film OHM of the transistors Tr11 and Tr12, respectively, and are collectively formed in the same process. Further, the projecting layer PL15 is composed of a source-drain metal layer (conductive layer) that forms source electrodes Tr11s, Tr12s and drain electrodes Tr11d, Tr12d of the transistors Tr11, Tr12, and the source electrode is patterned by patterning the source-drain metal layer. Tr11s and Tr12s, drain electrodes Tr11d and Tr12d, and data line Ld are formed together in the same process. Further, the protruding layer PL16 is made of the same material as the pixel electrode 16 of the organic EL element OEL, and is formed in a lump in the same process. Further, the projecting layer PL17 is made of a wiring metal layer that forms the power supply line La, and is formed in the same process as the power supply line La by patterning the wiring metal layer.
As described above, each of the projecting portions PLA, PLB, PLC, and PLD has a stacked structure in which each protruding layer including a gate metal layer, a source-drain metal layer, a wiring metal layer, a semiconductor layer, and an insulating layer is included in a part thereof. Have. The protrusion layers PL11 to 17 that form the protrusions PLA, PLB, PLC, and PLD are electrically connected to the transistors Tr11 and Tr12, the capacitor Cs, the various wirings La, Ls, and Ld, and the organic EL element OEL that constitute the light emission drive circuit DC. Is not connected.

In the display panel 110 (display device 100) having the device structure as described above, a light emission drive current having a predetermined current value corresponding to the image data (gradation voltage Vdata) flows between the drain and source of the transistor Tr12. By being supplied to the pixel electrode 16, the organic EL element OEL emits light at a predetermined luminance gradation corresponding to the image data.
At this time, since the pixel electrode 16 of the display panel 110 (display device 100) has a high light transmittance and the counter electrode 18 has a high light reflectance, the light emitted from the organic EL layer 17 of each pixel PIX is Then, the light passes through the pixel electrode 16 directly, or after being reflected by the counter substrate 18, passes through the substrate 11 and is emitted from the lower surface side of the substrate 11 which is the visual field side.

(Manufacturing method of display device)
Next, a method for manufacturing the display device according to the present embodiment will be described.
8 to 20 are process cross-sectional views illustrating a display device manufacturing method (manufacturing process). The left side of the drawing is a cross-sectional portion of the transistor Tr12 corresponding to FIG. 6, and the right side of the drawing is a cross-sectional portion of a wiring intersection region corresponding to FIG.

First, a gate metal layer is formed on one surface of the substrate 11 by using, for example, a PVD method (Physical Vapor Deposition) such as an evaporation method or a sputtering method. Thereafter, a resist having a desired planar pattern is formed by using a photolithography method, and the gate metal layer is patterned by using a wet etching method or a dry etching method, whereby the gate electrode Tr12g ( Tr11g), the selection line Ls, and the projecting layer PL11 are formed simultaneously.
The gate metal layer for forming the gate electrodes Tr12g and Tr11g and the selection line Ls is, for example, a single metal such as aluminum, titanium, chromium, nickel, copper, niobium, molybdenum, silver, tantalum, or tungsten, or any one of these. A metal material made of an alloy containing or a compound material containing any of these can be used. This gate metal layer is formed to a thickness of about 100 nm (1000 mm), for example.

Next, silicon nitride (SiN) or the like is formed on the substrate 11 on which the gate electrode Tr12g (Tr11g), the selection line Ls, and the projection layer PL11 are formed by using, for example, a plasma CVD method (Chemical Vapor Deposition). A gate insulating film 12 made of, a semiconductor layer SMCx containing amorphous silicon, and an insulating film made of silicon nitride (SiN) or the like are successively formed. The gate insulating film 12 is formed to a thickness of, for example, about 400 nm (4000 mm), the semiconductor layer SMCx is formed to a thickness of, for example, about 50 nm (500 mm), and the insulating film on the semiconductor layer SMCx is, for example, 200 nm The film is formed to a thickness of about 2000 mm.
Then, the insulating film on the semiconductor layer SMCx is patterned by a photolithography method, an etching method or the like to form a channel protective film (etching stopper) BL as shown in FIG. When the channel protective film BL is formed by patterning this insulating film, the projecting layer PL13 is formed at the same time. The channel protective film BL is formed at a position that covers a channel region in the semiconductor layer SMCx, and the protruding layer PL13 is formed at a position corresponding to the upper side of the protruding layer PL11.

  Next, as shown in FIG. 10, an impurity layer OHMx containing n-type amorphous silicon is formed on the semiconductor layer SMCx of the substrate 11 on which the channel protective film BL and the protruding layer PL13 are formed by using, for example, a plasma CVD method. To do. The impurity layer OHMx is formed to a thickness of about 20 nm (200 mm), for example.

Next, as illustrated in FIG. 11, the impurity layer OHMx and the semiconductor layer SMCx are collectively patterned by a photolithography method, an etching method, or the like to form the impurity semiconductor film OHM and the semiconductor film SMC. When the impurity semiconductor film OHM and the semiconductor film SMC are formed by this patterning, the protrusion layer PL14 and the protrusion layer PL12 are formed at the same time. The protrusion layer PL14 is formed on the protrusion layer PL13, and the protrusion layer PL12 is formed below the protrusion layer PL13.
Further, by this patterning, a contact hole HL11 (see FIG. 5) is formed at a predetermined position of the gate insulating film 12 on the gate electrode Tr12g of the transistor Tr12, and a part of the gate electrode Tr12g is exposed.

  Next, as shown in FIG. 12, a source / drain metal layer SDx is formed on the gate insulating film 12 of the substrate 11 on which the impurity semiconductor film OHM and the semiconductor film SMC are formed by using, for example, a PVD method. The source / drain metal layer SDx is formed to a thickness of, for example, about 200 nm (2000 mm). For this source / drain metal layer SDx, a metal material equivalent to the gate metal layer described above can be used. The source / drain metal layer SDx is also formed in the contact hole HL11 and is electrically connected to the gate electrode Tr12g of the transistor Tr12.

Next, as shown in FIG. 13, the source / drain metal layer SDx is patterned by photolithography, etching, or the like, thereby forming the source electrodes Tr11s, Tr12s, the drain electrodes Tr11d, Tr12d, and the data line Ld at the same time. .
Then, transistors Tr11 and Tr12 including gate electrodes Tr11g and Tr12g, a semiconductor film SMC, a channel protective film BL, an impurity semiconductor film OHM, source electrodes Tr11s and Tr12s, and drain electrodes Tr11d and Tr12d are formed on the substrate 11. Note that the source electrode Tr11s of the transistor Tr11 is electrically connected to the gate electrode Tr12g of the transistor Tr12 through the contact hole HL11 (see FIG. 5).
At the same time as the formation of the source electrodes Tr11s and Tr12s, the drain electrodes Tr11d and Tr12d, and the data line Ld, the projection layer PL15 is formed on the projection layer PL14.

Next, after forming a transparent electrode film made of, for example, tin-doped indium oxide (ITO) on the gate insulating film 12 of the substrate 11 on which the transistors Tr11 and Tr12 and the data line Ld are formed, a photolithography method or the like is used. As shown in FIG. 14, the pixel electrode (anode electrode) 16 having, for example, a substantially rectangular shape is formed on the gate insulating film 12 in the EL element formation region Rel of each pixel PIX. The pixel electrode 16 is formed so as to partially overlap the source electrode Tr12s of the transistor Tr12, and is directly connected to the source electrode Tr12s.
Simultaneously with the formation of the pixel electrode 16, the protrusion layer PL16 is formed on the protrusion layer PL15. The transparent electrode film for forming the pixel electrode 16 is formed to a thickness of about 200 nm (2000 mm), for example.

Next, after an insulating film made of silicon nitride (SiN) or the like is formed on the upper surface side of the substrate 11, the insulating film is patterned to thereby form an EL element formation region Rel of each pixel PIX as shown in FIG. An interlayer insulating film 13 having an opening through which the pixel electrode 16 is exposed is formed. The film thickness of the insulating film for forming the interlayer insulating film 13 is, for example, about 400 nm (4000 mm).
Further, by this patterning, a contact hole HL12 (see FIG. 5) is formed at a predetermined position of the interlayer insulating film 13 on the drain electrode Tr12d of the transistor Tr12, and a part of the drain electrode Tr12d is exposed.

Next, a wiring metal layer is formed on the upper surface side of the substrate 11 on which the interlayer insulating film 13 is formed by using, for example, a PVD method. The wiring metal layer is formed to a thickness of about 400 nm (4000 mm), for example. For this wiring metal layer, a metal material equivalent to the above-described gate metal layer or source / drain metal layer can be used. The wiring metal layer is also formed in the contact hole HL12 and is electrically connected to the drain electrode Tr12d of the transistor Tr12.
By patterning the wiring metal layer by a photolithography method, an etching method or the like, a power supply line La is formed on the interlayer insulating film 13 as shown in FIG. The power supply line La is electrically connected to the drain electrode Tr12d of the transistor Tr12 through the contact hole HL12 (see FIG. 5).
Simultaneously with the formation of the power supply line La, the projecting layer PL17 is formed on the interlayer insulating film 13 corresponding to the upper side of the projecting layers PL11 to PL16. These projecting layers PL11 to PL17 constitute main parts of the projecting portions PLA to PLD.

  Next, after an insulating film made of silicon nitride (SiN) or the like is formed on the upper surface side of the substrate 11, the insulating film is patterned to thereby form an EL element formation region Rel of each pixel PIX as shown in FIG. A protective insulating film (overcoat insulating film) 14 having an opening through which the pixel electrode 16 is exposed is formed. In addition, the film thickness of the insulating film for forming the protective insulating film 14 is, for example, about 200 nm (2000 mm).

  Next, after applying a photosensitive organic resin material such as polyimide or acrylic on the upper surface side of the substrate 11 to form a resin layer, the resin layer is patterned, as shown in FIG. A partition wall layer 15 having an opening 15h through which the pixel electrode 16 is exposed is formed in the EL element formation region Rel of each pixel PIX. Thereby, in each pixel formation region Rpx, a region where the pixel electrode 16 is exposed in the opening 15h formed in the partition wall layer 15 is defined as the EL element formation region Rel of each pixel PIX. The partition layer 15 is formed with a thickness (height) of about 1.5 μm, for example.

Next, after the substrate 11 on which the partition wall layer 15 is formed is washed with pure water, the upper surface side of the substrate 11 is subjected to, for example, oxygen plasma treatment or UV ozone treatment to expose the pixels exposed to each EL element formation region Rel. The surface of the electrode 16 is subjected to a treatment for making it lyophilic with respect to the organic compound-containing liquid described later.
As described above, the partition layer 15 defines an area (EL element formation area Rel) to which the organic compound-containing liquid is applied, and in addition, the surface of the pixel electrode 16 of each pixel PIX (organic EL element OEL) is made lyophilic. Thus, as will be described later, the organic compound-containing liquid is applied using a nozzle printing method or an ink jet method to form a light emitting layer (hole injection layer 17a, electron transporting light emitting layer 17b) of the organic EL layer 17. Even in such a case, it is possible to suppress leakage or overcoming of the organic compound-containing liquid into the EL element formation region Rel of the pixels PIX of different colors arranged adjacent to each other. Therefore, even when the display panel 110 (display device 100) corresponding to color display is manufactured, color mixing between adjacent pixels is prevented, and red (R), green (G), and blue (B) colors are prevented. The light-emitting material can be applied separately.

  Next, as shown in FIG. 19, for example, a hole injection layer (carrier transport layer) 17a is formed on the pixel electrode 16 exposed in the opening 15h of the partition wall layer 15 in the EL element formation region Rel of each pixel PIX. And an organic EL layer (light emitting functional layer) 17 in which the electron transporting light emitting layer (carrier transport layer) 17b is laminated.

First, a nozzle printing (or nozzle coating) method that discharges a continuous solution to an EL element formation region Rel of each pixel PIX, or an inkjet method that discharges a plurality of discontinuous droplets separated from each other to a predetermined position. Then, after applying a solution or dispersion of the hole transporting material using the above, etc., the hole injection layer 17a is formed on the pixel electrode 16 by heating and drying.
Specifically, as an organic compound-containing liquid containing an organic polymer-based hole transport material (carrier transport material), for example, a polyethylene dioxythiophene / polystyrene sulfonic acid aqueous solution (PEDOT / PSS: polyethylene disulfide which is a conductive polymer). Oxythiophene PEDOT and a dispersion obtained by dispersing polystyrene sulfonate PSS as a dopant in an aqueous solvent are applied to the EL element formation region Rel. After that, the stage on which the substrate 11 is placed is heated under a temperature condition of 100 ° C. or higher to perform a drying process, and the residual solvent is removed, whereby the pixel electrode 16 exposed to each EL element formation region Rel is removed. The hole injection layer 17a is formed by fixing the organic polymer hole transport material.
Further, after applying a solution or dispersion of an electron transporting luminescent material on the hole injection layer 17a formed on the pixel electrode 16 in each EL element formation region Rel by using a nozzle printing method or an ink jet method or the like. Then, it is heated and dried to form the electron transporting light emitting layer 17b overlaid on the hole injection layer 17a.
Specifically, as an organic compound-containing liquid containing an organic polymer-based electron-transporting light-emitting material (carrier-transporting material), for example, red containing a conjugated double bond polymer such as polyparaphenylene vinylene-based or polyfluorene-based ( R), green (G), and blue (B) luminescent materials are dissolved or dispersed in an aqueous solvent or an organic solvent such as tetralin, tetramethylbenzene, mesitylene, xylene, or the like in a 0.1 wt% to 5 wt% solution. Is applied on the hole injection layer 17a. Thereafter, the stage is heated in a nitrogen atmosphere and dried to remove the residual solvent, thereby fixing the organic polymer electron-transporting light-emitting material on the hole injection layer 17a, thereby providing an electron transporting property. The light emitting layer 17b is formed.

Next, as shown in FIG. 20, on the upper surface side of the substrate 11 on which the partition wall layer 15 and the organic EL layer 17 (the hole injection layer 17a and the electron transporting light emitting layer 17b) are formed, the light reflectance is high and each A counter electrode (cathode electrode) 18 facing the pixel electrode 16 in common via the organic EL layer 17 of the pixel PIX is formed. The counter electrode 18 is formed by forming an electrode layer made of pure aluminum on the upper surface of the substrate 11 through a vapor deposition mask, for example, using a vacuum vapor deposition method.
Next, after sealing the substrate surface by forming a sealing layer made of, for example, a silicon oxide film or a silicon nitride film on the one surface side of the substrate 11 directly on the one surface side of the substrate 11 on which the counter electrode 18 is formed. The display panel 110 (display device 100) is completed by bonding the counter substrate 20 such as glass so as to face the one surface side (upper surface side) of the substrate 11.

As described above, in the display device 100 according to the present embodiment, the protruding portions PLA, PLB, PLC, and PLD are provided in the vicinity of the wiring intersection region Rx in the pixel formation region Rpx.
The projecting portions PLA to PLD are made of the same material as the gate electrodes Tr11g and Tr12g, the semiconductor film SMC, the channel protective film BL, the impurity semiconductor film OHM, the source electrodes Tr11s and Tr12s, and the drain electrodes Tr11d and Tr12d constituting the transistors Tr11 and Tr12. The projecting layers PL11 to PL15, the projecting layer PL16 made of the same material as the pixel electrode 16, the projecting layer PL17 made of the same material as the power supply line La, the gate insulating film 12 provided between the projecting layers, the interlayer insulating film 13, and the protection The insulating film 14, the partition wall layer 15, and the like are stacked.
That is, in the process of manufacturing the display device 100, a plurality of protrusion layers PL11 to PL11 at the same time in the process of forming the transistors Tr11, Tr12, the organic EL element OEL, and various wirings (selection line Ls, data line Ld, power supply line La). Protrusions PLA to PLD in which PL17 is laminated can be formed.
Therefore, the protrusions PLA to PLD can be formed in the pixel formation region Rpx of the display device 100 without changing the manufacturing process of the display device 100 or increasing the number of steps.

The region where the projecting portions PLA, PLB, PLC, and PLD are provided is formed thicker than the wiring intersecting region Rx where the selection line Ls, the data line Ld, and the power supply line La intersect, and the projecting portions PLA, PLB The area where the PLC and the PLD are provided is the area closest to the counter substrate 20.
When the counter substrate 20 is pressed against the substrate 11 in order to join the counter substrate 20 to the substrate 11 or when a pressing force is applied to the counter substrate 20 from the outside when the display device 100 is used, for example, As shown in FIG. 21, the height from the surface of the substrate 11 is maintained even when the counter substrate 20 close to the substrate 11 side comes into contact with the protruding portions PLA, PLB, PLC, and PLD by pressing force (indicated by an arrow in the drawing). The pressing force concentrates on the region where the protrusions PLA, PLB, PLC, and PLD where the maximum value is provided, and the pressing force is not applied to the selection line Ls, the data line Ld, and the power supply line La.
Accordingly, the pressing force applied when the counter substrate 20 is bonded to the substrate 11 and the pressing force applied from the outside to the counter substrate 20 when the display device 100 is used are applied to the protrusions PLA, PLB, PLC, and PLD. Since the concentrated pressure does not apply to the selection line Ls, the data line Ld, and the power supply line La, the selection line Ls, the data line Ld, and the power supply line La are damaged (disconnected) or short-circuited. Can be prevented.
Thus, by preventing damage to various wirings (selection line Ls, data line Ld, and power supply line La) in the display device 100, the light emission display performance of the display device 100 is not deteriorated, and the quality of the display device 100 is improved. Can do.

The display device 100 formed and manufactured as described above is mounted on various electronic devices and used as a display panel of the electronic device.
For example, the display panel 1a of the mobile phone 200 shown in FIG. 22, the display panel 1b of the digital camera 300 shown in FIGS. 23A and 23B, the display panel 1c of the personal computer 400 shown in FIG. The display device 100 can be applied.

  The application of the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present invention.

11 Substrate (first substrate)
12 Gate insulating film 13 Interlayer insulating film 14 Protective insulating film 15 Partition layer 16 Pixel electrode 20 Counter substrate (second substrate)
100 Display device (light emitting device)
110 display panel Tr11, Tr12 transistor Tr11g, Tr12g gate electrode Tr11s, Tr12s source electrode Tr11d, Tr12d drain electrode SMC semiconductor film BL channel protective film OHM impurity semiconductor film Ls selection line (wiring)
Ld data line (wiring)
La power line (wiring)
PLA, PLB, PLC, PLD Protrusion part PL11-PL17 Protrusion layer OEL Organic EL element (light emitting element)
PIX pixel Rpx pixel formation area Rx wiring intersection area (intersection, vertex)

Claims (6)

A first substrate;
A plurality of pixels arranged on one surface of the first substrate;
A second substrate provided opposite to the one surface side of the first substrate and sealing each of the pixels with the first substrate;
With
Each pixel is
A light emitting element;
A transistor for controlling light emission of the light emitting element;
At least two wirings connected to the transistor and intersecting each other;
At least two of the four regions divided by the two wires intersecting each other with the two wires intersecting each other as a boundary line are in the relationship of the vertical angle of the wire intersecting region where the two wires intersect. The two regions are arranged at the corners that are closest to each other, and are formed so as to protrude from the one surface side of the first substrate toward the second substrate, more than a plurality of wires intersecting at the wire intersection region, a plurality of protrusions at least one wiring of the at least two of the wiring is formed on passing Ru position between,
Each of the light-emitting devices includes: The transistor includes an electrode, an insulating film, and a semiconductor film,
The light emitting device according to claim 1, wherein the protrusion has a stacked structure in which layers made of the same material as the electrode, the insulating film, and the semiconductor film are stacked.   The light emitting device according to claim 1, wherein the stacked structure of the protruding portion includes a layer made of the same material as the wiring.   An electronic apparatus comprising the light-emitting device according to claim 1 mounted thereon. A method of manufacturing a light emitting device in which a plurality of pixels each having a light emitting element, a transistor that controls light emission of the light emitting element, and at least two wirings that are connected to the transistor and intersect each other are arranged,
Forming the transistor having an electrode, an insulating film, and a semiconductor film on one surface of the first substrate;
Of each of the plurality of pixels, at least a wiring crossing region where the two wirings intersect among four regions divided by the two wirings intersecting each other with the two wirings intersecting each other. The corners of the two regions in the relationship of the vertical angle that are closest to each other protrude from the one surface side of the first substrate more than a plurality of wires intersecting at the wiring intersection region, and of the at least two wires a step in which at least one of the wires to form a plurality of protrusions formed on the passing Ru position between,
Bonding a second substrate to one side of the first substrate so as to seal the plurality of pixels with the first substrate;
Including
In the step of forming the protruding portion, at the same time as the step of forming the transistor, a layer made of the same material as that of the electrode, the insulating film, and the semiconductor film is stacked, and at least one of the protruding portions is formed. The manufacturing method of the light-emitting device characterized by including the process of forming the laminated structure which comprises a part.   6. The method of manufacturing a light emitting device according to claim 5, wherein the step of forming the protruding portion includes a step of forming a layer made of the same material as the wiring to form a part of the stacked structure. .

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