JP2011191434A - Light emitting device and method for manufacturing the same, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting device and a method for manufacturing the device, which can suppress photo-degradation or erroneous operations of a thin film transistor that controls light emission of a light emitting element to achieve favorable display quality, and can improve the flexibility of layout design of pixels, and to provide electronic equipment. <P>SOLUTION: Each pixel PIX arranged on a display panel 110 includes a light emitting drive circuit (pixel circuit) DC and an organic EL element OEL which is a current driving type light emitting element. The light emitting drive circuit DC includes a double-gate type transistor Tr 11 being a selecting transistor, a thin film transistor Tr 12 being a driving transistor, and a capacitor Cs. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a light-emitting device, a method for manufacturing the same, and an electronic device, and more particularly, includes a light-emitting panel in which pixels composed of pixel circuits and light-emitting elements for emitting light-emitting elements with luminance gradations according to image data are arranged. The present invention relates to a light emitting device, a method for manufacturing the same, and an electronic device in which the light emitting device is mounted.

  2. Description of the Related Art Recently, a display panel (light emitting element type display panel) in which light emitting elements such as organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”) are two-dimensionally arranged as display devices for electronic devices such as mobile phones and portable music players. ) Is known. In particular, a light-emitting element type display panel to which an active matrix driving method is applied has a faster display response speed and less viewing angle dependency than a widely used liquid crystal display device. And the display image quality can be increased. In addition, the light emitting element type display panel does not require a backlight or a light guide plate unlike a liquid crystal display device, and thus has a feature that it can be further reduced in thickness and weight.

  In such a light emitting element type display, various drive control mechanisms and control methods for controlling light emission of the light emitting elements have been proposed. For example, as described in Patent Literature 1 and Patent Literature 2, a device having a drive circuit (pixel circuit) including a plurality of switching means (thin film transistors) is known for each pixel arranged in a display panel. Yes. A specific example of the drive circuit will be described in detail in an embodiment described later.

JP 2002-156923 A JP 2001-147659 A

  By the way, in a display panel in which pixels having light emitting elements such as organic EL elements are arranged, light emitted from the light emitting elements of each pixel is emitted to the field of view, and part of the light is reflected in the panel substrate. And scattering. This is because light generated in a light emitting layer of a light emitting element such as an organic EL element has a complete radiation characteristic and is emitted in the entire circumferential direction. For this reason, part of the light reflected or scattered in the panel substrate is incident on the thin film transistor that constitutes the pixel circuit, which deteriorates the element characteristics of the thin film transistor (light deterioration) or causes a malfunction. Was.

  Further, when designing the layout of a pixel including such a pixel circuit, it is necessary to set a wide light emitting element formation region (light emitting region) in order to increase the aperture ratio. In order to increase the driving capability of the thin film transistor of the pixel circuit that performs light emission control, it is also necessary to set a large transistor size. That is, since the two are in a trade-off relationship, the aperture ratio cannot be sufficiently increased. In addition, when a wiring layer or a metal layer is provided above the thin film transistor, the thin film transistor malfunctions due to a so-called back gate effect, and the light emitting element cannot emit light with a desired luminance gradation. Therefore, it is necessary to form a thick insulating film between the upper wiring layer or metal layer and the thin film transistor, or to restrict the arrangement of both. As described above, the pixel layout design has various problems and has a problem of low design freedom.

  Therefore, in view of the above-described problems, the present invention can realize a good display quality by suppressing light deterioration and malfunction of a thin film transistor that performs light emission control of a light emitting element, and has a degree of freedom in pixel layout design. An object of the present invention is to provide a light emitting device and a method for manufacturing the same, and an electronic device.

  The invention according to claim 1 is a light-emitting device including a light-emitting panel in which a plurality of pixels are arranged. Each of the plurality of pixels includes a light-emitting element and a predetermined luminance gradation based on a gradation signal. A pixel circuit that performs a light emission operation at least, and the pixel circuit includes at least a selection transistor for setting the pixel to a selected state in order to write the gradation signal, and a current value corresponding to the gradation signal. A drive transistor that generates a light emission drive current and supplies the light emission element to the light emitting element, wherein the selection transistor includes a semiconductor layer that forms a channel region, and one side and the other side of the semiconductor layer across the semiconductor layer A gate electrode and a conductive layer disposed on each side, and a source electrode and a drain electrode connected to the semiconductor layer and disposed to face each other, the conductive layer comprising: Is formed of an opaque conductive material, characterized in that it is formed simultaneously with the part of the signal line connected to the pixel circuit.

According to a second aspect of the present invention, in the light emitting device according to the first aspect, the light emitting device is disposed at least in a plurality of selection lines disposed in a row direction of the light emitting panel and in a column direction of the light emitting panel. A plurality of data lines, a power supply line that applies a power supply voltage of a light emission level to the light emitting element of the pixel, a selection signal applied to the selection line, and the pixel connected to the selection line to the pixel, A selection driving circuit for setting the selection state to enable writing of the gradation signal, and generating the gradation signal based on image data, and supplying the gradation signal to the pixel set to the selection state via the data line And a data driving circuit.
According to a third aspect of the present invention, in the light emitting device according to the second aspect, the signal line formed simultaneously with the conductive layer is at least a part of the power supply line.
According to a fourth aspect of the present invention, in the light emitting device according to any one of the first to third aspects, the light emitting panel includes at least a partition layer provided in a region between the pixels, and includes at least the selection transistor and the drive. The transistor is provided below the partition wall layer.
According to a fifth aspect of the present invention, in the light emitting device according to any one of the first to third aspects, the light emitting panel has a stripe-shaped opening through which pixel electrodes of the plurality of pixels arranged in a specific direction are exposed. And the selection transistor is provided in a region between the pixel electrodes in the opening.
A sixth aspect of the present invention is the light emitting device according to any one of the first to fifth aspects, wherein the selection transistor has the conductive layer electrically connected to the gate electrode.
According to a seventh aspect of the present invention, in the light emitting device according to any one of the first to fifth aspects, the selection transistor has the conductive layer electrically connected to either the source electrode or the drain electrode. It is characterized by that.
According to an eighth aspect of the present invention, in the light-emitting device according to any one of the first to fifth aspects, the selection transistor has the conductive layer set in an electrically floating state.
According to a ninth aspect of the present invention, in the light emitting device according to any one of the first to eighth aspects, the pixel circuit is characterized in that at least the semiconductor layer of the selection transistor is made of amorphous silicon.
An electronic apparatus according to a tenth aspect of the invention is characterized in that the light emitting device according to any one of the first to ninth aspects is mounted.

  The invention according to claim 11 is a method of manufacturing a light emitting device including a light emitting panel in which a plurality of pixels having a light emitting element and a pixel circuit having a transistor for controlling the light emitting element are arranged. Forming a layer, a gate electrode disposed on one side of the semiconductor layer with the semiconductor layer interposed therebetween, and a source electrode and a drain electrode connected to the semiconductor layer and disposed to face each other And a step of forming a conductive layer on the other side of the semiconductor layer simultaneously with a part of the signal line made of an opaque conductive material connected to the pixel.

  According to the present invention, it is possible to realize good display quality by suppressing light deterioration and malfunction of a thin film transistor that performs light emission control of a light emitting element, and to improve the degree of freedom of pixel layout design.

It is a schematic block diagram which shows an example of the display apparatus to which the light-emitting device which concerns on the 1st Embodiment of this invention is applied. FIG. 3 is an equivalent circuit diagram illustrating a circuit configuration example of a pixel including the pixel circuit according to the first embodiment. It is a figure which shows the double gate type transistor applied to the pixel circuit which concerns on 1st Embodiment. It is a schematic plan view which shows an example of the display panel applied to the display apparatus which concerns on 1st Embodiment. It is a plane layout figure showing an example of a pixel applied to a 1st embodiment. It is a principal part enlarged view of the pixel applied to 1st Embodiment. It is principal part sectional drawing (the 1) of the display panel applied to the display apparatus which concerns on 1st Embodiment. It is principal part sectional drawing (the 2) of the display panel applied to the display apparatus which concerns on 1st Embodiment. It is process sectional drawing (the 1) which shows the manufacturing method of the display panel which concerns on 1st Embodiment. It is process sectional drawing (the 2) which shows the manufacturing method of the display panel which concerns on 1st Embodiment. It is process sectional drawing (the 3) which shows the manufacturing method of the display panel which concerns on 1st Embodiment. It is process sectional drawing (the 4) which shows the manufacturing method of the display panel which concerns on 1st Embodiment. It is process sectional drawing (the 5) which shows the manufacturing method of the display panel which concerns on 1st Embodiment. It is process sectional drawing (the 6) which shows the manufacturing method of the display panel which concerns on 1st Embodiment. It is process sectional drawing (the 7) which shows the manufacturing method of the display panel which concerns on 1st Embodiment. It is a schematic block diagram which shows an example of the display apparatus to which the light-emitting device which concerns on the 2nd Embodiment of this invention is applied. It is an equivalent circuit diagram which shows the circuit structural example of the pixel provided with the pixel circuit which concerns on 2nd Embodiment. It is a schematic sectional drawing which shows the problem of the display panel used as a comparison object. It is a schematic sectional drawing which shows the effect of the display panel which concerns on 1st and 2nd embodiment. FIG. 6 is a diagram (No. 1) for comparing and verifying element characteristics of a double gate transistor applied to the first and second embodiments and a general thin film transistor. FIG. 6 is a diagram (No. 2) for comparing and verifying element characteristics of a double gate transistor applied to the first and second embodiments and a general thin film transistor. It is a schematic sectional drawing which shows the connection structure of the double gate type transistor applied to the pixel circuit which concerns on 3rd Embodiment. It is FIG. (1) for verifying the relationship between the connection structure of the conductive layer of the double gate type transistor applied to 3rd Embodiment, and element characteristics. It is FIG. (2) for verifying the relationship between the connection structure of the conductive layer of the double gate type transistor applied to 3rd Embodiment, and element characteristics. It is FIG. (3) for verifying the relationship between the connection structure of the conductive layer of the double gate type transistor applied to 3rd Embodiment, and element characteristics. It is FIG. (4) for verifying the relationship between the connection structure of the conductive layer of the double gate type transistor applied to 3rd Embodiment, and element characteristics. It is the schematic of the display panel to which the pixel circuit which concerns on 4th Embodiment is applied. 10 is an equivalent circuit illustrating an example of a pixel circuit according to a fifth embodiment. It is a perspective view which shows the structural example of the digital camera to which the light-emitting device which concerns on this invention is applied. It is a perspective view which shows the structural example of the thin-type television to which the light-emitting device based on this invention is applied. 1 is a perspective view illustrating a configuration example of a mobile personal computer to which a light emitting device according to the present invention is applied. It is a figure which shows the structural example of the mobile telephone to which the light-emitting device which concerns on this invention is applied.

Hereinafter, a pixel circuit, a light emitting device, a manufacturing method thereof, and an electronic device according to the present invention will be described in detail with reference to embodiments.
<First Embodiment>
First, a schematic configuration of a light emitting device including a light emitting panel in which a plurality of pixels having a pixel circuit according to a first embodiment of the present invention is arranged will be described with reference to the drawings. Here, a case where the light-emitting device according to the present invention is applied as a display device will be described.

(Display device)
FIG. 1 is a schematic block diagram showing an example of a display device to which the light emitting device according to the first embodiment of the present invention is applied.
As shown in FIG. 1, a display device (light emitting device) 100 according to the first embodiment schematically includes a display panel (light emitting panel) 110, a scanning driver (selection drive circuit) 120, and a data driver (data drive circuit). ) 130 and a controller 140.

  As schematically shown in FIG. 1, the display panel 110 includes a plurality of pixels PIX, a plurality of signal lines (selection lines (scanning lines) Ls, a plurality of data lines Ld) connected to the pixels PIX on the panel substrate. ) And. The plurality of pixels PIX are two-dimensionally arranged (for example, n rows × m columns; n and m are positive integers) in a row direction (horizontal direction in the drawing) and a column direction (vertical direction in the drawing) on the panel substrate. As will be described later, each pixel PIX includes a light emission drive circuit (pixel circuit) and a current drive type light emitting element. The plurality of selection lines Ls are connected to the pixels PIX arranged in the row direction of the panel substrate for each row. The plurality of data lines Ld are connected to the pixels PIX arranged in the column direction of the panel substrate for each column.

  The scanning driver 120 is connected to each selection line Ls arranged in the row direction of the display panel 110 described above. The scan driver 120 applies the selection voltage Vsel of a selection level to the selection line Ls of each row at a predetermined timing based on a selection control signal supplied from the controller 140 described later, thereby bringing the pixel PIX of each row into a selected state. Set.

  The data driver 130 is connected to each data line Ld of the display panel 110 and generates a gradation signal (gradation voltage Vdata) corresponding to image data based on a data control signal supplied from a controller 140 described later. , And supplied to the pixel PIX via each data line Ld.

  The controller 140 generates display data including digital data including luminance gradation data based on image data supplied from the outside of the display device 100 and supplies the display data to the data driver 130. Further, the controller 140 controls the operation states of the scan driver 120 and the data driver 140 described above based on a timing signal generated or extracted based on the image data, and executes a predetermined drive control operation on the display panel 110. A selection control signal and a data control signal are generated and output.

(Pixel)
FIG. 2 is an equivalent circuit diagram illustrating a circuit configuration example of a pixel including the pixel circuit according to the first embodiment.
Each pixel PIX arranged in the display panel 110 described above includes, for example, as shown in FIG. 2, a light emission drive circuit (pixel circuit) DC and an organic EL element OEL which is a current drive type light emitting element. . The light emission drive circuit DC has a circuit configuration including one or more transistors and capacitors. Further, the light emission drive circuit DC generates a light emission drive current having a current value corresponding to the image data, and supplies the light emission drive current to the organic EL element OEL. The organic EL element OEL emits light at a luminance gradation corresponding to image data based on the light emission drive current supplied from the light emission drive circuit DC.

  Specifically, the light emission drive circuit DC includes, for example, as shown in FIG. 2, a double gate transistor (selection transistor) Tr11, a transistor Tr12 (drive transistor), and a capacitor Cs (capacitance element). . In the double gate transistor Tr11, the top gate terminal TG and the bottom gate terminal BG are connected to the selection line Ls via the contact N14, the drain terminal is connected to the data line Ld via the contact N13, and the source terminal is connected to the contact N11. It is connected. The transistor Tr12 has a gate terminal connected to the contact N11, a drain terminal connected to the power supply line Lv via the contact N15, and a source terminal connected to the contact N12. The capacitor Cs is connected between the gate terminal (contact N11) and the source terminal (contact N12) of the transistor Tr12.

  Further, the organic EL element OEL has an anode (a pixel electrode serving as an anode electrode described later) connected to a contact N12 of the light emission driving circuit DC, and a cathode (a counter electrode serving as a cathode electrode described later) connected to a predetermined low potential power source ( Reference voltage Vsc; for example, ground potential Vgnd).

  Here, each of the double-gate transistor Tr11 and the transistor Tr12 has, for example, an element structure including an n-channel semiconductor layer as a channel region. These double gate transistors Tr11 and Tr12 may be made of, for example, amorphous silicon or polysilicon as a semiconductor layer. In particular, when amorphous silicon is applied as the semiconductor layer of the double gate transistor Tr11 and the transistor Tr12, a polycrystalline or single crystal silicon thin film transistor can be formed by a simple manufacturing process using an already established manufacturing technique. In comparison, a transistor with uniform and stable operating characteristics (such as electron mobility) can be realized. Note that if the double-gate transistor Tr11 and the transistor Tr12 are p-channel transistors, the source terminal and the drain terminal are opposite to each other. The capacitor Cs may be a parasitic capacitance formed between the gate and the source of the transistor Tr12, or in addition to the parasitic capacitance, a separate capacitive element is connected in parallel between the contact N11 and the contact N12. There may be.

  Thus, in the light emission drive circuit DC according to the present embodiment, a general field effect transistor (thin film transistor) is used as a switching element (Tr11) for setting the pixel PIX to a selected state based on the selection voltage Vsel. Rather, it has a circuit configuration to which a double-gate thin film transistor having an element structure as described later is applied.

  FIG. 3 is a diagram showing a double gate type transistor applied to the pixel circuit according to the present embodiment. FIG. 3A is a schematic cross-sectional view showing the element structure of a double gate type transistor, and FIG. 3B is an equivalent circuit symbol showing the double gate type transistor. Here, configurations common to the device structure of the pixel PIX described later will be described with the same or equivalent reference numerals.

As shown in FIG. 3A, the double gate transistor DGT applied to the selection transistor of the light emission drive circuit according to the present embodiment is roughly composed of a semiconductor layer (channel region) SMC and a source electrode Es (source terminal S). ) And a drain electrode Ed (drain terminal D), a conductive layer Etg (top gate terminal TG), and a bottom gate electrode Ebg (bottom gate terminal BG; gate electrode). The semiconductor layer SMC is made of, for example, amorphous silicon. The source electrode Es and the drain electrode Ed are provided at both ends of the semiconductor layer SMC so as to face each other through an impurity layer (ohmic contact layer) OHM made of n ⁺ silicon. A channel protective layer (etching stopper film) BL is provided on the semiconductor layer SMC between the source electrode Es and the drain electrode Ed. The conductive layer Etg is provided above (above the drawing) the semiconductor layer SMC via the channel protective layer BL and the insulating film 13 serving as a top gate insulating film. Further, the bottom gate electrode Ebg is provided below the semiconductor layer SMC (downward in the drawing) via an insulating film 12 serving as a bottom gate insulating film.

  Further, the double gate transistor DGT having such a configuration is formed on a transparent insulating substrate 11 such as a glass substrate, as shown in FIG. In the element structure shown in FIG. 3A, the channel protection layer BL provided on the semiconductor layer SMC is subjected to an etching process in which the source electrode Es and the drain electrode Ed provided on the semiconductor layer SMC are patterned. It has a function as an etching stopper and a function for preventing damage to the semiconductor layer SMC due to the etching. The double gate transistor DGT having such an element structure is generally represented by an equivalent circuit as shown in FIG.

  Thus, the double gate type transistor DGT is provided with the gate electrodes (conductive layer Etg, bottom gate electrode Ebg) on the upper side and the lower side of the single semiconductor layer SMC. Therefore, by electrically connecting these gate electrodes and applying the same gate voltage, the driving capability of the transistor can be improved compared to a general thin film transistor having the gate electrode only on one side. It has the feature of being able to. In other words, this means that the element size of a double-gate transistor can be reduced or the gate voltage can be lowered when a driving capability equivalent to that of a general thin film transistor is realized.

  Further, since the conductive layer Etg and the bottom gate electrode Ebg are formed of an opaque metal material (conductive material), light incident on the semiconductor layer SMC from the outside of the double gate transistor DGT can be blocked. Degradation (light degradation) of element characteristics of the double gate transistor DGT can be suppressed. Note that element characteristics of the double-gate transistor will be described in detail later.

  In the drive control operation in the pixel PIX having such a circuit configuration, first, a selection level (high level) selection voltage Vsel is applied from the scan driver 120 to the selection line Ls in a predetermined selection period. . As a result, the double gate transistor Tr11 provided in the light emission drive circuit DC is turned on, and the pixel PIX is set to the selected state. In synchronization with this timing, the gradation voltage Vdata corresponding to the image data is applied from the data driver 130 to the data line Ld. As a result, the contact N11 (that is, the gate terminal of the transistor Tr12) is connected to the data line Ld via the double gate transistor Tr11, and a potential corresponding to the gradation voltage Vdata is applied to the contact N11.

  Here, the current value of the drain-source current of the transistor Tr12 (that is, the light emission drive current flowing through the organic EL element OEL) is determined by the potential difference between the drain and source and the potential difference between the gate and source. That is, in the light emission drive circuit DC shown in FIG. 2, the current value of the current flowing between the drain and source of the transistor Tr12 is controlled by the gradation voltage Vdata.

  Therefore, the transistor Tr12 is turned on in a conductive state according to the potential of the contact N11 (that is, the gradation voltage Vdata), and the transistor Tr12 and the organic EL element OEL are connected from the power supply line Lv to which the high-potential-side power supply voltage Vsa is applied. Through this, a light emission driving current having a predetermined current value flows in the reference voltage Vsc (ground potential Vgnd) on the low potential side. Thereby, the organic EL element OEL emits light with a luminance gradation corresponding to the gradation voltage Vdata (that is, image data). At this time, charges are accumulated (charged) in the capacitor Cs between the gate and the source of the transistor Tr12 based on the gradation voltage Vdata applied to the contact N11.

  Next, in the non-selection period after the end of the selection period, the selection voltage Vsel of the non-selection level (low level) is applied from the scan driver 120 to the selection line Ls. As a result, the double gate transistor Tr11 of the light emission drive circuit DC is turned off and set to a non-selected state, and the data line Ld and the contact N11 are electrically disconnected. At this time, the electric charge accumulated in the capacitor Cs is held, whereby the potential difference between the gate and the source of the transistor Tr12 is held, and a voltage corresponding to the gradation voltage Vdata is applied to the gate terminal (contact N11) of the transistor Tr12. Applied.

  Accordingly, as in the above selection state, the light emission driving current having the same current value as the light emission operation state flows from the power supply voltage Vsa to the organic EL element OEL via the transistor Tr12, and the light emission operation state is continued. This light emitting operation state is controlled so as to continue, for example, for one frame period until the gradation voltage Vdata corresponding to the next image data is written. Then, an operation for displaying desired image information is executed by sequentially executing such a drive control operation for every pixel PIX two-dimensionally arranged on the display panel 110 for each row.

(Specific example of display panel)
Next, a specific example of a display panel (light-emitting panel) including pixels having the above-described circuit configuration will be described.

  FIG. 4 is a schematic plan view illustrating an example of a display panel applied to the display device according to the above-described embodiment. Here, in the plan views shown in FIGS. 4A and 4B, for convenience of explanation, the pixel electrode of each pixel viewed from one side of the display panel (the surface on which the organic EL element is formed on the substrate) and The arrangement relation of the partition walls (banks) is mainly shown. FIG. 4A shows an example of a display panel to which a partition having a striped planar pattern is applied, and FIG. 4B shows an example of a display panel to which a partition having a box-like planar pattern is applied. In FIG. 4, hatching is shown for convenience in order to clarify the arrangement of the pixel electrodes and the partition walls.

  As shown in FIGS. 4A and 4B, each pixel PIX has a boundary between adjacent pixels formed by continuous partition walls formed on one surface side of the display panel (panel substrate). A region where the pixel electrode of each pixel PIX is exposed is defined. Here, as shown in FIGS. 4A and 4B, the partition has a stripe-like or box-like plane pattern. Also, for example, as shown in FIGS. 4A and 4B, the display panel has a plurality of external junction terminals for electrical connection with the outside of the display panel at the edge along a specific side. Are arranged.

  As shown in FIG. 4, for example, the display panel 110 to which the circuit board according to the present invention is applied has a display area 20 and a peripheral area around the display area 20 on one side of the transparent substrate 11 such as a glass substrate. 30 is set. In the display area 20, a plurality of pixels PIX are arranged in a matrix in the row direction (horizontal direction in the drawing) and the column direction (vertical direction in the drawing). Here, when the display panel 110 supports color display, each pixel PIX is each color pixel of three colors of red (R), green (G), and blue (B) arranged adjacent to each other in the row direction. (Sub-pixel) is formed as a set. In this case, the same color pixels are arranged in the column direction of the display panel 110.

  In addition, in the display region 20 of the display panel 110, for example, as shown in FIG. 4A, a partition layer having a slit-like opening that exposes pixel electrodes of pixels arranged in the column direction is continuous. Provided. And between the pixel electrodes of each pixel in the opening, for example, insulating films 13 and 14 are provided so as to be exposed. That is, the partition layer shown in FIG. 4A has a planar pattern in which striped partition layers are continuously formed in the column direction in the boundary region between the pixels arranged in the row direction. A region where the pixel electrode 16 of each pixel PIX is exposed is defined by the partition layer and the insulating films 13 and 14 formed in the slit-shaped opening. The region where the pixel electrode 16 is exposed is a region where an organic EL element is formed in each pixel PIX (EL element formation region Rel).

  Note that the planar pattern of the partition layer provided in the display panel 110 is not limited to the stripe pattern as shown in FIG. In the display panel according to the present embodiment, for example, as shown in FIG. 4B, the partition layer 15 having a planar pattern continuous in a box shape (or a lattice shape) so that only the pixel electrode 16 of each pixel is exposed. It may have. In this case, the partition wall layer 15 is provided so as to surround the four sides of each pixel electrode 16 and is continuously formed in each boundary region between the pixels PIX arranged in the row direction and the column direction.

  In addition, in the peripheral region 30 of the display panel 110, external joint terminals TM are arranged at predetermined positions (for example, along a specific side of the substrate). Each external junction terminal TM is connected to a selection line Ls, a data line Ld, a power supply line Lv, and a counter electrode described later, which are shown in the above-described pixel PIX, through a routing wire (not shown) or directly. . For example, the IC chip (driver chip) of the scan driver 120 and the data driver 130 as shown in FIG. 1 is connected to the external junction terminal TM to which the selection line Ls and the data line Ld are connected. In addition, a predetermined high potential power source or a low potential power source is directly or indirectly connected to the external junction terminal TM connected to the power line Lv or the counter electrode.

  Next, a specific device structure (planar layout and cross-sectional structure) of the pixel (light emission drive circuit and organic EL element) having the circuit configuration as described above will be described. Here, an organic EL display panel having a bottom emission type light emitting structure in which light emitted from the organic EL layer is transmitted through a transparent substrate and emitted to the viewing side (the other surface side of the substrate) is described. Note that the present invention is not limited to this, and has a top emission type light emitting structure in which light emitted from the organic EL layer is emitted directly to the visual field side (one surface side of the substrate) without passing through the substrate. It may be a thing.

  FIG. 5 is a plan layout diagram illustrating an example of a pixel applied to the present embodiment. FIG. 6 is an enlarged view of a main part of a pixel applied to this embodiment. 5 and 6 mainly show layers in which the transistors and wirings of the light emission drive circuit DC shown in FIG. 2 are formed. In order to clarify the electrodes and wiring layers of the transistors, Shown with hatching for convenience. Here, the electrode and wiring layer which gave the same hatching are provided in the same layer.

  7 and 8 are cross-sectional views of a main part of a display panel applied to the display device according to the present embodiment. Here, FIGS. 7A, 7B and 8A are respectively the VIIA-VIIA lines in the pixel having the planar layout shown in FIG. 5 (in this specification, the Roman shown in FIG. 5). For convenience, "VII" is used as a symbol corresponding to the numeral "7". The same applies hereinafter), VIIB-VIIB line, and VIIIC-VIIIC line (in this specification, the Roman numeral " For convenience, “VIII” is used as a symbol corresponding to “8”. The same applies hereinafter). FIG. 8B is a schematic cross-sectional view showing a cross section taken along line VIIID-VIIID in the main part plane layout shown in FIG.

  Specifically, as shown in FIGS. 7A and 7B, the pixel PIX shown in FIG. 5 is provided for each pixel formation region Rpx set on one surface side (the upper surface side in the drawing) of the substrate 11. ing. In this pixel formation region Rpx, at least a boundary region between the formation region (EL element formation region) Rel of the organic EL element OEL and the adjacent pixel PIX is set.

  In the pixel PIX shown in FIG. 5, a selection line Ls and a power supply line Lv are arranged in the upper and lower edge regions of the pixel formation region Rpx so as to extend in the row direction (left-right direction in the drawing), respectively. ing. On the other hand, a data line Ld is arranged in the edge region on the right side of the pixel formation region Rpx in the drawing so as to extend in the column direction (vertical direction in the drawing) perpendicular to the selection line Ls and the power supply line Lv. . In the present embodiment, the power supply line (anode line) Lv is disposed so as to overlap the voltage supply line La and the upper layer of the voltage supply line La in a plane and in a predetermined position. 2 has a double wiring structure consisting of auxiliary wirings Lb electrically connected. Here, the auxiliary wiring Lb is a wiring layer for compensating the power supply voltage Vsa applied to the voltage supply line La. That is, in the present embodiment, the power supply voltage Vsa is supplied to the anode (pixel electrode) side of the organic EL element OEL of each pixel PIX by the power supply line Lv including the voltage supply line La and the auxiliary wiring Lb.

  In the display panel shown in FIG. 4A, partition walls 15 extending in the column direction (vertical direction in the drawing) are provided in the left and right edge regions of the pixel formation region Rpx. That is, as shown in FIG. 5, FIG. 7 (a), and FIG. 8 (a), the boundary region between the pixels PIX arranged adjacent to each other in the row direction (left and right direction in the drawing) is continuously formed from the surface of the substrate 11. A partition wall layer 15 is provided so as to protrude from the surface. On the other hand, in the upper and lower edge regions of the pixel formation region Rpx, as shown in FIGS. 5 and 7B, in the boundary region between the pixels PIX arranged adjacent to each other in the column direction (up and down direction in the drawing), Insulating films 13 and 14 are provided so as to cover the selection line Ls and the power supply line Lv. A region surrounded by the partition layer 15 and the insulating films 13 and 14 and from which the pixel electrode 16 is exposed is defined as an EL element formation region Rel. In the display panel shown in FIG. 4B, the partition wall layer 15 is provided between the pixels PIX arranged adjacent to each other in the row direction and the column direction so that only the pixel electrode 16 of each pixel PIX is exposed. May be provided so as to surround the four sides of the pixel electrode 16.

  The data line Ld is provided on the lower layer side (substrate 11 side) than the selection line Ls and the power supply line Lv, for example, as shown in FIGS. 5, 6, 7 (a), and 8 (a). The data line Ld is formed in the same process as the bottom gate electrode Tr11bg and the gate electrode Tr12g by patterning the gate metal layer for forming the bottom gate electrode Tr11bg of the double gate transistor Tr11 and the gate electrode Tr12g of the transistor Tr12. Formed. The data line Ld is directly connected to the drain electrode Tr11d of the double-gate transistor Tr11 through the conductor layer CV21 and the contact hole CH2 provided in the insulating film 12. The conductor layer CV21 is formed in a lump in the same process as the lower electrode Eca by patterning a transparent electrode layer for forming a lower electrode Eca of the capacitor Cs described later, for example. Also good. Further, the contact hole CH2 corresponds to the contact N13 of the light emission drive circuit DC shown in FIG.

  Further, the voltage supply line La of the selection line Ls and the power supply line Lv is, for example, as shown in FIGS. 5, 6, 7 (b), and 8 (b), the source electrodes of the double gate type transistors Tr 11 and Tr 12. It is provided in the same layer as Tr11s, Tr12s and drain electrodes Tr11d, Tr12d. The selection line Ls and the voltage supply line La are formed by patterning the source and drain metal layers for forming the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d of the double gate transistor Tr11 and the transistor Tr12, thereby forming the source electrode Tr11s. , Tr12s and the drain electrodes Tr11d, Tr12d are formed together in the same process.

  The selection line Ls is directly connected to the conductor layer CL2 through a contact hole HL3 provided in the lower insulating film 12, as shown in FIGS. 5, 6, and 8C. The conductor layer CL2 is directly connected to a bottom gate electrode Tr11bg of a double gate transistor Tr11 described later. Thereby, the selection line Ls is electrically connected to the bottom gate electrode Tr11bg of the double gate transistor Tr11 via the conductor layer CL2. Here, the conductor layer CL2 is formed in the same process as the lower electrode Eca by patterning a transparent electrode layer for forming the lower electrode Eca of the capacitor Cs described later, for example. May be. The contact hole HL3 corresponds to the contact N14 of the light emission drive circuit DC shown in FIG.

  The power supply line Lv is connected to the lower voltage supply line La via a contact hole HL5 in which the upper auxiliary wiring Lb is provided in the insulating film 13, as shown in FIGS. Connected directly to. Thus, the auxiliary wiring Lb is provided in parallel on the voltage supply line La via the insulating film 13 and both are electrically connected, so that the wiring resistance of the power supply line Lv is substantially reduced. can do. Here, the auxiliary wiring Lb is collectively formed in the same process as the conductive layer Tr11tg by patterning the gate metal layer for forming the conductive layer Tr11tg of the double gate transistor Tr11. In other words, the conductive layer Tr11tg of the double gate transistor Tr11 is formed simultaneously with the formation of the auxiliary wiring Lb.

  Although not shown, the external junction terminals (see FIG. 4) TM arranged at the end of the display panel 110 (substrate 11) also have, for example, the data line Ld and the bottom gate of the double gate transistor Tr11 described above. By patterning the gate metal layer for forming the electrode Tr11bg and the gate electrode Tr12g of the transistor Tr12, the data lines Ld, the bottom gate electrode Tr11bg, and the gate electrode Tr12g are formed in the same process.

  Further, in the pixel PIX shown in FIG. 5, the double gate transistor Tr11 and the transistor Tr12 provided in the light emission drive circuit DC are extended in the column direction (vertical direction in the drawing) along the data line Ld, for example. Has been placed. Specifically, the width direction of the channels of the double gate type transistors Tr11 and Tr12 is set to extend in parallel to the data line Ld.

  The double gate transistor Tr11 has an element structure equivalent to that of the double gate transistor DGT shown in FIG. That is, as shown in FIGS. 5, 6, 7A, and 8C, the double gate transistor Tr11 has a semiconductor layer SMC in a region corresponding to the bottom gate electrode Tr11bg formed on the substrate 11. And a conductive layer Tr11tg is provided in a region corresponding to the semiconductor layer SMC. Further, a source electrode Tr11s and a drain electrode Tr11d are provided so as to face each other with a channel region formed in the semiconductor layer SMC interposed therebetween. An insulating film 12 serving as a bottom gate insulating film is provided between the bottom gate electrode Tr11bg and the semiconductor layer SMC. An insulating film 13 serving as a top gate insulating film is provided between the conductive layer Tr11tg and the semiconductor layer SMC. Note that an impurity layer OHM is provided between the source electrode Tr11s and the drain electrode Tr11d and the semiconductor layer SMC, so that the semiconductor layer SMC and the source electrode Tr11s or the drain electrode Tr11d are ohmically connected.

  In order to correspond to the circuit configuration of the light emission drive circuit DC shown in FIG. 2, the double gate type transistor Tr11 has a bottom gate electrode Tr11bg as shown in FIGS. 5, 6, and 8C. Connected to the layer CL2. The conductive layer Tr11tg of the double-gate transistor Tr11 is connected to the conductor layer CL2 through a contact hole HL4 provided in the insulating films 13 and 12, as shown in FIGS. 5, 6, and 8C. Yes. The conductor layer CL2 is connected to the selection line Ls through a contact hole HL3 provided in the insulating film 12. That is, the bottom gate electrode Tr11bg and the conductive layer Tr11tg of the double gate transistor Tr11 are electrically connected via the conductor layer CL2 and electrically connected to the selection line Ls via the conductor layer CL2. Yes.

  Further, the drain electrode Tr11d of the double gate transistor Tr11 is connected to the data via the contact hole HL2 provided in the insulating film 12 and the conductor layer CL1, as shown in FIGS. 5, 6, and 7A. It is electrically connected to the line Ld. The source electrode Tr11s of the double gate transistor Tr11 is directly connected to the lower electrode Eca of the capacitor Cs through the contact hole HL1 provided in the insulating film 12, as shown in FIGS. It is connected. Here, as shown in FIGS. 5 and 6, the lower electrode Eca is directly connected to the gate electrode Tr12g of the transistor Tr12. Accordingly, the source electrode Tr11s of the double gate transistor Tr11 is electrically connected to the gate electrode Tr12g of the transistor Tr12 via the lower electrode Eca. Here, the contact hole HL1 corresponds to the contact N11 of the light emission drive circuit DC shown in FIG.

  The transistor Tr12 has a known field effect thin film transistor structure. That is, in the transistor Tr12, as shown in FIGS. 5 and 8A, the semiconductor layer SMC is provided in a region corresponding to the gate electrode Tr12g formed on the substrate 11. Further, a source electrode Tr12s and a drain electrode Tr12d are provided so as to face each other with a channel region formed in the semiconductor layer SMC interposed therebetween. An insulating film 12 serving as a gate insulating film is provided between the gate electrode Tr12g and the semiconductor layer SMC. Note that an impurity layer OHM is provided between the source electrode Tr12s and the drain electrode Tr12d and the semiconductor layer SMC, whereby the semiconductor layer SMC and the source electrode Tr12s or the drain electrode Tr12d are ohmically connected.

  In the transistor Tr12, the gate electrode Tr12g is directly connected to the lower electrode Eca of the capacitor Cs as described above. Further, as shown in FIG. 5, the drain electrode Tr12d of the transistor Tr12 is formed integrally with the voltage supply line La constituting the power supply line Lv. Further, the source electrode Tr12s of the transistor Tr12 is directly connected to the pixel electrode 16 that also serves as the upper electrode Ecb of the capacitor Cs, as shown in FIGS. Further, the drain electrode Tr12d of the transistor Tr12 formed integrally with the voltage supply line La of the power supply line Lv substantially corresponds to the contact N15 of the light emission drive circuit DC shown in FIG.

  As shown in FIGS. 5, 7, and 8A, the capacitor Cs includes a lower electrode Eca made of a transparent electrode material, an upper electrode Ecb made of a transparent electrode material facing the lower electrode Eca, and a lower electrode Eca. And the insulating film 12 interposed between the upper electrodes Ecb. Here, the insulating film 12 is also used as a dielectric layer of the capacitor Cs. The upper electrode Ecb also serves as the pixel electrode 16 of the organic EL element OEL described later. That is, the capacitor Cs is provided on the lower layer side (substrate 11 side) of the organic EL element OEL.

  As shown in FIGS. 5, 7, and 8A, the organic EL element OEL includes a pixel electrode (anode electrode) 16 that also serves as the upper electrode Ecb of the capacitor Cs, an organic EL layer (light emitting functional layer) 17, and And a counter electrode (cathode electrode) 18 are sequentially stacked. Here, since the organic EL element OEL according to the present embodiment has a bottom emission type light emitting structure, the pixel electrode 16 is formed of a transparent electrode material having a high light transmittance such as ITO. On the other hand, the counter electrode 18 contains an electrode material having a high light reflectance such as aluminum alone or an aluminum alloy.

  As shown in FIG. 8A, the pixel electrode 16 is directly connected to the source electrode Tr12s of the transistor Tr12. A predetermined light emission drive current is supplied to the pixel electrode 16 from the light emission drive circuit DC. As shown in FIGS. 7 and 8A, the organic EL layer 17 is a pixel exposed to an EL element formation region Rel defined by the side wall 15e of the partition wall layer 15 formed to protrude continuously on the substrate 11. It is formed on the electrode 16. The organic EL layer 17 is formed of, for example, a hole injection layer (or a hole transport layer including a hole injection layer) 17a and an electron transport light emitting layer 17b. Here, the organic EL layer 17 refers to a carrier transport layer such as a hole injection layer, a light emitting layer, or an electron injection layer in which a layer functioning as a light emitting layer is formed of an organic material.

  The counter electrode 18 is provided so as to face the pixel electrode 16 of each pixel PIX arranged two-dimensionally on the substrate 11 in common. The counter electrode 18 is formed of a single electrode layer (solid electrode) so as to correspond to the display region 20 of the substrate 11 shown in FIG. Further, as shown in FIGS. 7 and 8, the counter electrode 18 extends not only to the EL element formation region Rel of each pixel PIX but also to the partition layer 15 and the insulating film 14 that define the EL element formation region Rel. It is provided to exist. Further, the counter electrode 18 is provided so as to partially extend to the peripheral region 30 outside the display region 20, and via a contact portion and lead wiring (both not shown) arranged in the peripheral region 30. The external junction terminal TM is electrically connected.

  As shown in FIGS. 4, 5, 7 (a), and 8, the partition layer 15 is continuous from the surface of the substrate 11 at least in a boundary region between a plurality of pixels PIX two-dimensionally arranged on the display panel 110. Is provided so as to protrude. Here, the partition wall layer 15 is formed of an insulating material that can be patterned using, for example, a dry etching method, for example, a polyimide resin material that is a photosensitive insulating material.

  Note that the light emitting drive circuit DC, the organic EL element OEL (pixel electrode 16, organic EL layer 17, counter electrode 18), the insulating films 13 and 14, and the one side of the substrate 11 on which the partition wall layer 15 is formed are sealed on one side. The stop layer 19 is formed and the display panel 110 is sealed. Here, in the peripheral region 30, an opening is formed in the sealing layer 19 so that at least the external joint terminal TM is exposed. The display panel 110 applies a sealing structure in which a sealing substrate such as a metal cap (sealing lid) or glass is bonded in addition to the sealing layer 19 or instead of the sealing layer 19. It may be.

  In the display panel having the device structure as described above, a light emission driving current having a predetermined current value corresponding to image data (gradation voltage Vdata) flows between the drain and source of the transistor Tr12 and is supplied to the pixel electrode 16. Thus, the organic EL element OEL emits light with a predetermined luminance gradation corresponding to the image data.

  At this time, since the pixel electrode 16 of the display panel 110 has a high light transmittance and the counter electrode 18 has a high light reflectance, light emitted from the organic EL layer 17 of each pixel PIX passes through the pixel electrode 16. Directly transmitted or reflected by the counter electrode 18 and then transmitted through the substrate 11 and emitted to the other side of the substrate 11 that is the visual field side (the lower side of the drawings in FIGS. 7 and 8).

(Display panel manufacturing method)
Next, a method for manufacturing a display panel according to this embodiment will be described.
9 to 15 are process cross-sectional views illustrating the display panel manufacturing method according to the present embodiment. Here, for convenience of illustration, a part of the cross section of each part of the display panel 110 shown in FIGS. 7 and 8 is extracted and arranged so as to be adjacent for convenience. In the drawing, (VIIA-VIIA), (VIIIC-VIIIC), (VIIID-VIIID), and (VIIIE-VIIIE) show process cross sections in the respective cross sections shown in FIGS.

  First, as shown in FIGS. 9A to 10C, the above-described manufacturing method of the display panel is arranged such that the light emission driving circuit DC (FIGS. 2 and 5) is formed on one side of the substrate 11 such as a glass substrate. Transistor Tr12, selection line Ls, power supply line Lv, and data line Ld are formed.

  Specifically, first, as shown in FIG. 9A, the same gate metal layer formed on one surface side (upper surface side of the drawing) of the transparent substrate 11 is patterned using a photolithography method. In the pixel formation region Rpx of each pixel PIX in the display region 20, the bottom gate electrode Tr11bg, the gate electrode Tr12g, and the data line Ld made of an opaque conductive material (light-shielding metal film) are formed at the same time. The gate metal layer for forming the bottom gate electrode Tr11bg, the gate electrode Tr12g, and the data line Ld is, for example, a sputtering method using an aluminum-nickel alloy (hereinafter abbreviated as “Al—Ni alloy”) as a target. It is formed by.

  Next, as shown in FIGS. 5 and 9B, the lower electrode Eca of the capacitor Cs is formed for each region corresponding to the EL element formation region Rel of each pixel PIX set on the one surface side of the substrate 11. . Here, the lower electrode Eca is formed by depositing an electrode layer made of a transparent electrode material such as ITO on the substrate 11 and then patterning it using a photolithography method. At this time, simultaneously with the lower electrode Eca, a conductor layer CL1 directly connected to a predetermined position of the data line Ld and a conductor layer CL2 directly connected to the bottom gate electrode Tr11bg are also formed in a lump.

  Next, as shown in FIG. 9C, the insulating film 12 made of silicon nitride, the semiconductor film SMCx made of intrinsic amorphous silicon, etc., and the insulating film made of silicon nitride, etc. are continuously formed over the entire substrate 11. . Thereafter, the uppermost insulating film such as silicon nitride is patterned by using a photolithography method, so that the bottom gate electrode Tr11bg and the gate electrode Tr12g are formed on the semiconductor film SMCx as shown in FIG. 9C. A channel protective layer BL is formed in a region corresponding to.

  Next, as shown in FIG. 10A, an impurity layer OHMx made of n-type amorphous silicon or the like is formed over the entire substrate 11. Thereafter, as shown in FIG. 10B, by using the photolithography method, the impurity layer OHMx and the semiconductor film SMCx are patterned at once, thereby forming the formation regions (outer shapes) of the double-gate transistor Tr11 and the transistor Tr12 described later. Shape). Next, by patterning the impurity layer OHM, the semiconductor layer SMC, and the insulating film 12 in regions serving as the source and drain of the double gate transistor Tr11, the upper surfaces of the lower electrode Eca and the conductor layer CL1 at predetermined positions can be obtained. Exposed contact holes HL1 and HL2 are formed. At this time, by simultaneously patterning the insulating film 12 at a predetermined position in the vicinity of the formation region of the double gate transistor Tr11, the contact hole HL3 exposing the upper surface of the conductor layer CL2 is formed.

  Next, after forming a source / drain metal layer on one surface side of the substrate 11, the source / drain metal layer is patterned by photolithography. As a result, as shown in FIG. 10C, at least the channel protection layer BL is interposed between the two ends of the region that becomes the semiconductor layer SMC of the double-gate transistor Tr11 and the transistor Tr12 for ohmic connection. Source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d are formed through the impurity layer OHM. That is, the transistor Tr12 having the thin film transistor structure shown in FIG. Here, the source electrode Tr11s and the drain electrode Tr11d of the double gate transistor Tr11 are directly connected to the lower electrode Eca through the contact hole HL1, and the drain electrode Tr11d is connected to the conductor layer CL1 through the contact hole HL2. Connected directly.

  In the step of forming the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d, the selection line Ls and the voltage supply line La that constitutes the power supply line Lv are also formed at the same time. Here, the selection line Ls is directly connected to the conductor layer CL2 through the contact hole HL3 described above. Further, as shown in FIG. 5, the voltage supply line La is formed integrally with the drain electrode Tr12d of the transistor Tr12. Note that the source and drain metal layers for forming the source electrodes Tr11s and Tr12s, the drain electrodes Tr11d and Tr12d, the selection line Ls, and the voltage supply line La are made of, for example, an Al—Ni alloy as a target in the same manner as the gate metal layer. Formed by the sputtering method or the like.

  Next, after depositing a transparent electrode layer made of ITO or the like over the entire area of the substrate 11, patterning is performed using a photolithography method, thereby forming at least EL elements of each pixel PIX as shown in FIGS. A pixel electrode 16 having, for example, a rectangular planar pattern is formed on the insulating film 12 in the region Rel. Here, the pixel electrode 16 is formed so that a part thereof extends on the source electrode Tr12s of the transistor Tr12, and is directly connected to the source electrode Tr12s.

  Thus, as shown in FIG. 11A, in the EL element formation region Rel of each pixel PIX, the capacitor Cs is formed in which the lower electrode Eca and the pixel electrode 16 are arranged to face each other with the insulating film 12 interposed therebetween. Is done. That is, the pixel electrode 16 is an anode electrode of the organic EL element OEL, and is also used as the upper electrode Ecb facing the lower electrode Eca, and the insulating film 12 is also used as a dielectric layer.

  Next, an insulating film 13 made of silicon nitride or the like is formed over the entire area of the substrate 11. Thereafter, the insulating film 13 is patterned to form an opening through which the pixel electrode 16 is exposed, as shown in FIG. At this time, contact holes HL4 and HL5 from which the conductor layer CL2 and the voltage supply line La are exposed are formed. At this time, the contact holes HL4 exposing the upper surface of the conductor layer CL2 are formed by simultaneously patterning the insulating films 13 and 12 at predetermined positions in the vicinity of the formation region of the double gate transistor Tr11. Further, by simultaneously patterning the insulating film 13 at a predetermined position on the voltage supply line La, a contact hole HL5 exposing the upper surface of the voltage supply line La is formed.

  Next, after forming a wiring layer on one surface side of the substrate 11 by, for example, a sputtering method using an Al—Ni alloy as a target, the wiring layer is patterned by using a photolithography method, thereby FIG. ), A conductive layer Tr11tg made of an opaque conductive material (light-shielding metal film) is formed in a region corresponding to the semiconductor layer SMC of the double gate transistor Tr11. That is, the transistor Tr11 having the double gate type thin film transistor structure shown in FIG. Here, the conductive layer Tr11tg of the double gate transistor Tr11 is directly connected to the conductor layer CL2 through the contact hole HL4 described above.

  Further, in the step of forming the conductive layer Tr11tg, the auxiliary wiring Lb constituting the power supply line Lv is also formed at the same time. Here, as shown in FIG. 5, the auxiliary wiring Lb is arranged so as to be parallel to the voltage supply line La and overlap in a plane. The auxiliary wiring Lb is directly connected to the voltage supply line La through the contact hole HL5 described above. Thereby, a power supply line Lv having a double wiring structure including the voltage supply line La and the auxiliary wiring Lb is formed. According to such a wiring structure, for example, in a large-screen display panel, it is possible to reduce a voltage drop of the power supply voltage Vsa caused by an increase in wiring resistance of the power supply line Lv.

  Next, after forming an insulating film 14 made of silicon nitride or the like over the entire area of the substrate 11, the insulating film 14 is patterned to form an EL element forming region Rel of each pixel PIX as shown in FIG. An opening through which the pixel electrode 16 is exposed is formed.

  Next, a photosensitive organic resin material such as polyimide or acrylic is applied on the substrate 11 to form a resin layer, and then the resin layer is patterned to obtain a display region as shown in FIG. A partition wall layer 15 is formed on 20. Here, the partition layer 15 continuously protrudes to one surface side of the substrate 11, and has an opening 15h through which the pixel electrode 16 of each pixel PIX is exposed. Thereby, in each pixel formation region Rpx, an opening 15h formed in the partition wall layer 15, that is, a region surrounded by the side wall 15e of the partition layer 15 and the pixel electrode 16 exposed is defined as an EL element formation region Rel of each pixel PIX. Defined.

  Next, after cleaning the substrate 11 with pure water, the surface of the pixel electrode 16 exposed in each EL element formation region Rel is subjected to, for example, oxygen plasma treatment or UV ozone treatment, so that a hole transport material or an electron to be described later is formed. A process for making the organic compound-containing liquid of the transportable luminescent material lyophilic is performed. In this way, the partition layer 15 defines an area (EL element formation area Rel) to which the organic compound-containing liquid is applied, and in addition, the surface of the pixel electrode 16 of each pixel PIX (organic EL element OEL) is made lyophilic. As will be described later, even when the organic compound-containing liquid is applied using a nozzle printing method or an inkjet method to form the light emitting layer of the organic EL layer 17 (electron transporting light emitting layer 17b), It is possible to suppress leakage and overcoming of the organic compound-containing liquid into the EL element formation region Rel of the pixels PIX of different colors arranged. Therefore, even when the display panel 110 corresponding to color display is manufactured, color mixture between adjacent pixels is prevented and the light emitting materials of red (R), green (G), and blue (B) are separately applied. Can be performed satisfactorily.

  Next, as shown in FIG. 14, for example, a hole transport layer (carrier transport layer) 17 a and an electron transport light-emitting layer (carrier) are formed on the pixel electrode 16 exposed in the EL element formation region Rel of each pixel PIX of the display region 20. An organic EL layer (light emitting functional layer) 17 in which a transport layer) 17b is laminated is formed.

  First, a nozzle printing (or nozzle coating) method that discharges a continuous solution (liquid flow) to the EL element formation region Rel of each pixel PIX or a plurality of discontinuous droplets separated from each other at a predetermined position. A solution or dispersion of a hole transport material is applied using an inkjet method or the like to be discharged, and then heated and dried to form the hole transport layer 17 a on the pixel electrode 16.

  Specifically, as an organic compound-containing liquid (organic solution) containing an organic polymer-based hole transport material (carrier transport material), for example, a polyethylenedioxythiophene / polystyrene sulfonic acid aqueous solution (PEDOT / PSS; conductive polymer) (Polyethylene dioxythiophene PEDOT and dispersion of polystyrene sulfonate PSS as a dopant in an aqueous solvent) are applied to the EL element formation region Rel. After that, the stage on which the substrate 11 is placed is heated under a temperature condition of 100 ° C. or higher and dried to remove the residual solvent, so that only the pixel electrode 16 exposed to each EL element formation region Rel is removed. The hole transport layer 17a is formed by fixing the organic polymer hole transport material.

  Next, a solution or dispersion of an electron transporting luminescent material is applied onto the hole transport layer 17a formed in each EL element formation region Rel using a nozzle printing method or an inkjet method, and then dried by heating. An electron transporting light emitting layer (carrier transporting layer) 17b is formed.

  Specifically, as an organic compound-containing liquid (organic solution) containing an organic polymer-based electron transporting light emitting material (carrier transporting material), for example, a conjugated double bond polymer such as polyparaphenylene vinylene or polyfluorene. 0.1 wt% to 5 wt% of red (R), green (G), and blue (B) luminescent materials containing benzene, dissolved or dispersed in an aqueous solvent or an organic solvent such as tetralin, tetramethylbenzene, mesitylene, and xylene as appropriate. % Solution is applied on the hole transport layer 17a. Thereafter, the above stage is heated in a nitrogen atmosphere and dried to remove the residual solvent, thereby fixing the organic polymer electron transporting light-emitting material on the hole transporting layer 17a, thereby transporting electrons. The light emitting layer 17b is formed.

  Next, as shown in FIG. 15, the region including the display region 20 in which the partition layer 15 and the organic EL layer 17 (the hole transport layer 17a and the electron transporting light emitting layer 17b) are formed has light reflection characteristics. A common counter electrode (cathode electrode) 18 facing the pixel electrode 16 through the organic EL layer 17 of each pixel PIX is formed. Here, the counter electrode 18 is formed by forming an electrode layer made of pure aluminum on the substrate 11 through a vapor deposition mask, for example, using a vacuum vapor deposition method.

  Next, as shown in FIGS. 7 and 8, a sealing layer 19 made of, for example, a silicon oxide film or a silicon nitride film is formed on one surface side of the substrate 11 on which the counter electrode 18 is formed, and the substrate surface is formed. The display panel 110 is completed by sealing. Here, the sealing layer 19 is formed with an opening so that the upper surface of the external joint terminal TM formed in the peripheral region 30 is exposed. In addition to the sealing layer 19 or in place of the sealing layer 19, a sealing substrate such as a metal cap (sealing lid) or glass may be bonded to face the substrate 11. .

  Thus, in this embodiment, the selection transistor provided in the light emission drive circuit DC of each pixel PIX has a double-gate thin film transistor structure, and each layer constituting the double-gate transistor is provided on the display panel 110. They are formed at the same time in the process of forming other elements and wirings to be provided. Therefore, according to the present embodiment, the double gate transistor can be applied as the selection transistor without changing the manufacturing process or increasing the number of processes.

  In the present embodiment, the opaque metal layer for forming the conductive layer Tr11tg, the bottom gate electrode Tr11bg, the gate electrode Tr12g, the source electrodes Tr11s and Tr12s, and the drain electrodes Tr11d and Tr12d of the double gate transistor Tr11 and the transistor Tr12. However, the present invention is not limited to this. For example, a molybdenum-niobium alloy (Mo-Nb alloy) or the like may be applied.

<Second Embodiment>
Next, a display device including a display panel in which a plurality of pixels having a pixel circuit according to a second embodiment of the present invention is arranged will be described with reference to the drawings.

(Display device)
FIG. 16 is a schematic block diagram showing an example of a display device to which the light emitting device according to the second embodiment of the present invention is applied. FIG. 17 is an equivalent circuit diagram illustrating a circuit configuration example of a pixel including the pixel circuit according to the second embodiment. Here, about the structure equivalent to 1st Embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified.

  As shown in FIG. 16, a display device (light emitting device) 100 according to the second embodiment is schematically shown as a display panel (light emitting panel) 110, a scan driver 120, a data driver 130, a controller 140, and a power supply driver. 150. That is, the display device shown in this embodiment has a configuration including the power supply driver 150 in addition to the configuration shown in the first embodiment.

  As shown in FIG. 16, the display panel 110 includes a plurality of selection lines (scanning lines) Ls connected to a plurality of pixels PIX two-dimensionally arranged on the panel substrate, a plurality of power supply lines Lv, and a plurality of data. Line Ld. Here, the plurality of power supply lines Lv are arranged in parallel with the selection line Ls, and are connected to the pixels PIX arranged in the row direction of the panel substrate for each row.

  The power driver 150 is connected to each power line Lv disposed in the row direction of the display panel 110. The power supply driver 150 causes each pixel PIX to perform a light emission operation by applying a power supply voltage Vsa of a light emission level to the power supply line Lv of each row at a predetermined timing based on the power supply control signal supplied from the controller 140 described above.

  The pixel PIX applied to the present embodiment includes a light emission driving circuit DC having three transistors and an organic EL element OEL as shown in FIG. 17, for example. Specifically, the light emission drive circuit DC includes double gate transistors (selection transistors) Tr21 and Tr22, a transistor (drive transistor) Tr23, and a capacitor (capacitance element) Cs. In the double-gate transistor Tr21, the top gate terminal TG and the bottom gate terminal BG are connected to the selection line Ls via the contact N24, the drain terminal is connected to the power supply line Lv via the contact N25, and the source terminal is connected to the contact N21. It is connected. In the double gate transistor Tr22, the top gate terminal TG and the bottom gate terminal BG are connected to the selection line Ls via the contact N24, the source terminal is connected to the data line Ld via the contact N23, and the drain terminal is connected to the contact N22. It is connected. The transistor Tr23 has a gate terminal connected to the contact N21, a drain terminal connected to the power supply line Lv via the contact N25, and a source terminal connected to the contact N22. The capacitor Cs is connected between the gate terminal (contact N21) and the source terminal (contact N22) of the transistor Tr23.

  The organic EL element OEL has an anode (a pixel electrode serving as an anode electrode) connected to the contact N22 of the light emission drive circuit DC, similarly to the pixel (see FIG. 2) shown in the first embodiment. A cathode (a counter electrode serving as a cathode electrode) is connected to a predetermined low potential power source (reference voltage Vsc; for example, ground potential Vgnd).

  As described above, also in the light emission drive circuit DC according to the present embodiment, a circuit in which a double-gate thin film transistor is applied as the switching elements (Tr21, Tr22) for setting the pixel PIX to the selected state based on the selection voltage Vsel. It has a configuration. Note that the same configuration and method as those of the first embodiment described above can be applied to the specific configuration of the display panel 110 including the light emission drive circuit DC according to the present embodiment and the manufacturing method thereof.

  The drive control operation in the pixel PIX having such a circuit configuration includes a write operation (selection period) for holding a voltage component corresponding to image data within a predetermined processing cycle period, and after the write operation is completed. The organic EL element OEL is controlled to perform a light emission operation (non-selection period) that causes the organic EL element OEL to emit light at a luminance gradation corresponding to the image data.

  First, in the writing operation (selection period) to the pixel PIX, the pixel PIX is set to the selected state by applying the selection voltage Vsel of the selection level (high level) to the selection line Ls. The level set to a negative voltage value corresponding to the image data on the data line Ld in a state where the power supply voltage Vsa of a non-light emission level (voltage level equal to or lower than the reference voltage Vsc; for example, a negative voltage) is applied to the power supply line Lv A regulated voltage Vdata is supplied. Thereby, the double gate transistors Tr21 and Tr22 and the transistor Tr23 provided in the light emission driving circuit DC are turned on, and a write current corresponding to the potential difference generated between the gate and the source of the transistor Tr23 is supplied from the power supply line Lv. It flows in the direction of the data line Ld through the transistor Tr23, the contact N22, the double gate type transistor Tr22, and the contact N23.

  At this time, charges corresponding to the potential difference generated between the contacts N21 and N22 are accumulated in the capacitor Cs and held as a voltage component. Further, the power supply line Lv is applied with a power supply voltage Vsa equal to or lower than the reference voltage Vsc, and the write current is set to be extracted from the pixel PIX in the direction of the data line Ld. As a result, the potential applied to the anode (contact N22) of the organic EL element OEL is lower than the cathode potential (reference voltage Vsc). Therefore, no current flows through the organic EL element OEL, and the organic EL element OEL Does not emit light (non-emission operation). Such a writing operation is sequentially executed for each row for all the pixels PIX two-dimensionally arranged on the display panel 110.

  Next, in the light emission operation (non-selection period) after the end of the write operation, the pixel PIX is set to the non-selection state by applying the selection voltage Vsel of the non-selection level (low level) to the selection line Ls. Thereby, the double gate transistors Tr11 and Tr12 are turned off, and the connection between the data line Ld and the pixel PIX (light emission drive circuit DC) is cut off. At this time, since the charge accumulated in the above-described write operation is held in the capacitor Cs, the transistor Tr23 maintains the on state. Then, when a power supply voltage Vsa having a light emission level (a voltage level higher than the reference voltage Vsc) is applied to the power supply line Lv, a predetermined light emission from the power supply line Lv to the organic EL element OEL via the transistor Tr23 and the contact N22. Drive current flows.

  At this time, the voltage component held by the capacitor Cs corresponds to a potential difference when a write current corresponding to the gradation voltage Vdata is caused to flow in the transistor Tr23. Therefore, the light emission drive current flowing through the organic EL element OEL The current value is approximately the same as the current. As a result, the organic EL element OEL of each pixel PIX emits light with a luminance gradation corresponding to the image data (gradation voltage Vdata) written during the writing operation, so that desired image information is displayed.

  Note that the pixel circuits shown in the first and second embodiments (FIGS. 2 and 17) described above apply an image voltage to the light emitting element of each pixel by applying a gradation voltage having a voltage value corresponding to the image data. The case has been described in which a circuit configuration corresponding to a voltage designation type gradation control method in which a light emission driving current according to data is supplied to perform light emission operation (display operation) at a desired luminance gradation has been described. The pixel circuit applicable to the present invention is not limited to this, and for example, by supplying a gradation current having a current value corresponding to the image data, the image data is supplied to the light emitting element provided in each pixel. It may be provided with a circuit configuration corresponding to a current designation type gradation control method in which a corresponding light emission driving current is supplied to perform light emission operation at a desired luminance gradation.

(Verification of effects)
Next, operational effects of the display device to which the pixel circuit according to each of the above-described embodiments is applied will be described in detail with reference to a comparison target.

  FIG. 18 is a schematic cross-sectional view showing the problems of the display panel to be compared with the first and second embodiments described above. FIG. 19 is a schematic cross-sectional view showing effects of the display panel according to the first and second embodiments described above. In FIGS. 18 and 19, a part of hatching showing a cross section is omitted for convenience of illustration.

  The display panel to be compared shown in FIG. 18 is the same as the display panel 110 according to the first embodiment shown in FIG. 7 except that the double gate transistor Tr11 is replaced with a general thin film transistor Tr11x having only one gate electrode. It has a cross-sectional structure. In the display panel having such a cross-sectional structure, when the organic EL element OEL provided on one surface side (upper surface side of the drawing) of the substrate 11 emits light, most of the light is emitted to the visual field side on the other surface side of the substrate 11. However, a part of the light is reflected at the layer boundary or interface inside the display panel and propagates inside the layer or is scattered. Therefore, such light (reflected light or scattered light) is incident on the channel region of the thin film transistor Tr11x constituting the pixel circuit, thereby degrading the element characteristics (light deterioration) of the thin film transistor Tr11x or causing a malfunction. Has the problem. Such a phenomenon remarkably occurs when amorphous silicon is applied as the semiconductor layer of the thin film transistor.

  On the other hand, in the display panel 110 according to each of the above-described embodiments, as shown in FIG. 19, the reflected light and scattered light inside the display panel are blocked by the conductive layer Tr11tg of the double-gate transistor Tr11, and the channel Incidence of light to the region is suppressed. That is, the conductive layer Tr11tg can be made to function as a light-shielding film by being formed of a light-shielding metal film (an opaque conductive material) such as an aluminum alloy. The results of comparison and verification of device characteristics (degree of photodegradation) between a double gate transistor using amorphous silicon as a semiconductor layer and a general thin film transistor are shown below.

  20 and 21 are diagrams for comparing and verifying the element characteristics of the double gate transistor applied to the first and second embodiments described above and a general thin film transistor. FIGS. 20A and 20B are simulations showing voltage-current characteristics (Vg-Id characteristics; relation of drain-source current Ids to gate-source voltage Vgs) in a double gate transistor and a general thin film transistor. It is a result. FIG. 20B shows a change in the drain-source current Ids in a specific voltage range (gate-source voltage Vgs = 10 to 15 V) in the simulation result shown in FIG. is there. FIG. 21A is a simulation result showing voltage-carrier mobility (Vg-μ characteristic; relationship of carrier mobility μ to gate-source voltage Vgs) between a double gate transistor and a general thin film transistor. is there. FIG. 21B is a simulation result showing voltage-current characteristics (Vd-Id characteristics; relation of drain-source current Ids to drain-source voltage Vds) in a double gate transistor and a general thin film transistor. 20 and 21A, the drain-source voltage Vds was set to 10V. In the simulation experiment of FIG. 21B, the gate-source voltage Vgs was set to 5V.

  As shown in FIGS. 20 and 21, the characteristics of a general thin film transistor (denoted as “SingleGate” in the figure) change due to the incidence of light on the channel region. Specifically, as shown in FIGS. 20A and 20B, for a Vg-Id characteristic line in a dark state not affected by light (SingleGate (dark); indicated by a thin dotted line in the figure). Thus, the Vg-Id characteristic line in the bright state affected by light (SingleGate (bright); indicated by a thin broken line in the figure) showed a tendency for the drain-source current Ids to increase.

  In contrast, a double gate transistor (denoted as “DoubleGate” in the figure) has a very small change in element characteristics due to the incidence of light on the channel region. Specifically, as shown in FIGS. 20A and 20B, a Vg-Id characteristic line in a dark state (DoubleGate (dark); indicated by a thick broken line in the figure) and a Vg-Id characteristic in a bright state. In the line (DoubleGate (bright); indicated by a thick solid line in the figure), no significant change was observed in the drain-source current Ids.

  In FIG. 20A, when the gate-source voltage Vgs is in a negative range (Vgs <0), a slight difference is observed in the drain-source current Ids. However, in the gate-source voltage Vgs (= −12 to −15 V) corresponding to the use range of the double gate transistors Tr11, Tr21, Tr22 in the light emission drive circuit DC, the difference is 1 pA or less. It has no effect on the driving of

  As for the Vg-μ characteristic, as shown in FIG. 21A, in a general thin film transistor, the Vg-μ characteristic line in a dark state (SingleGate (dark); indicated by a thin dotted line in the figure). Thus, the Vg-μ characteristic line in the bright state (SingleGate (bright); indicated by a thin broken line in the figure) showed a tendency to change the carrier mobility μ.

  On the other hand, in the double gate type transistor, the Vg-μ characteristic line in the dark state (DoubleGate (dark); indicated by a thick broken line in the figure) and the Vg-μ characteristic line in the bright state (DoubleGate (bright); In the figure, a large change was not recognized in the carrier mobility μ.

  As for the Vd-Id characteristic, as shown in FIG. 21B, in a general thin film transistor, the Vd-Id characteristic line in a dark state (SingleGate (dark); indicated by a thin dotted line in the figure). Thus, the Vd-Id characteristic line in the bright state (SingleGate (bright); indicated by a thin broken line in the figure) showed a tendency for the drain-source current Ids to be remarkably increased.

  On the other hand, in the double gate type transistor, the Vd-Id characteristic line in the dark state (DoubleGate (dark); indicated by a thick broken line in the figure) and the Vd-Id characteristic line in the bright state (DoubleGate (bright); In the figure, a large change in the drain-source current Ids was not recognized.

  Therefore, according to each of the above-described embodiments, even when the double gate transistor Tr11 using amorphous silicon is applied as the selection transistor constituting the light emission drive circuit DC of the pixel PIX, the device characteristics are deteriorated. In addition to being able to suppress, malfunction of the light emission drive circuit DC can be prevented.

  In addition, since the double gate type transistor has a gate electrode for forming an electric field in the channel region above and below, it is generally possible to connect the conductive layer and the bottom gate electrode and apply the same gate voltage. Compared with a typical thin film transistor, the driving capability can be improved.

  That is, according to the double gate type transistor, the element size of the transistor required for realizing the driving capability equivalent to that of a general thin film transistor can be reduced, or the gate voltage can be lowered. Can do. Therefore, by applying a double gate type transistor as the selection transistor that constitutes the light emission drive circuit DC of the pixel PIX, the element area of the transistor occupying the formation region of each pixel can be reduced, so that the degree of freedom in layout design is improved. In addition, the aperture ratio can be relatively increased.

<Third Embodiment>
Next, a pixel circuit according to a third embodiment of the present invention will be described with reference to the drawings. Here, a connection structure of conductive layers in a double gate type transistor applied as a selection transistor of a light emission driving circuit will be described.

  In the first and second embodiments described above, as shown in FIGS. 2 and 17, the top gate terminal of the double gate transistor applied as the selection transistor (Tr11, Tr21, Tr22) of the light emission drive circuit DC. The case where the same gate voltage is applied by connecting TG (conductive layer) to the bottom gate terminal BG (bottom gate electrode) has been described. The third embodiment has an element structure in which the conductive layer of the double gate type transistor is in an electrically floating state (floating state) or an element structure in which the conductive layer is connected to either the drain electrode or the source electrode. is doing.

  FIG. 22 is a schematic cross-sectional view showing a connection structure of double gate type transistors applied to the pixel circuit according to the third embodiment. Here, the same reference numerals as those of the cross-sectional structure of the double gate transistor shown in FIG.

  The double gate transistor DGT shown in FIG. 22A is set in a floating state (floating state) in which the conductive layer Etg is not connected to another conductive layer and a specific voltage is not applied. It has an element structure. Further, the double gate transistor DGT shown in FIGS. 22B and 22C has an element structure in which the conductive layer Etg is connected to the drain electrode Ed and the source electrode Es, respectively. In this embodiment, such a double gate transistor DGT has a circuit configuration applied to the selection transistors (Tr11, Tr21, Tr22) of the light emission drive circuit DC.

  Next, element characteristics of the double gate transistor having the connection structure as described above will be described. Here again, the results of a simulation experiment on a double gate transistor using amorphous silicon as the semiconductor layer are shown.

  23 to 26 are diagrams for verifying the relationship between the connection structure of the conductive layer of the double-gate transistor applied to this embodiment and the element characteristics. FIGS. 23A and 23B are simulation results showing the relationship between the connection structure of the conductive layers of the double-gate transistor and the Vg-Id characteristics in the bright state. FIG. 23B shows a change in the drain-source current Ids in a specific voltage range (gate-source voltage Vgs = 4 to 6 V) in the simulation result shown in FIG. is there. FIG. 24A is a simulation result showing the relationship between the connection structure of the conductive layer of the double gate transistor and the Vg-μ characteristic in the dark state. FIG. 24B is a simulation result showing the relationship between the connection structure of the conductive layer of the double gate transistor and the Vd-Id characteristic in the dark state. In the simulation experiments of FIGS. 23 and 24A, the drain-source voltage Vds is set to 10V, and in the simulation experiment of FIG. 24B, the gate-source voltage Vgs is set to 5V. .

  FIGS. 25A and 25B are simulation results showing the relationship between the connection structure of the conductive layer of the double gate transistor and the Vg-Id characteristic in the bright state. FIG. 25B shows a change in the drain-source current Ids in a specific voltage range (gate-source voltage Vgs = 4 to 6 V) in the simulation result shown in FIG. 25A. is there. FIG. 26A is a simulation result showing the relationship between the connection structure of the conductive layer of the double gate transistor and the Vg-μ characteristic in the bright state. FIG. 26B is a simulation result showing the relationship between the connection structure of the conductive layer of the double-gate transistor and the Vd-Id characteristic in the bright state. In the simulation experiments of FIGS. 25 and 26A, the drain-source voltage Vds is set to 10V, and in the simulation experiment of FIG. 26B, the gate-source voltage Vgs is set to 5V. .

  As shown in FIGS. 23 to 26, the device characteristics of the double gate transistor DGT applied to the present embodiment vary depending on the connection structure of the conductive layer Etg. First, element characteristics in a dark state where the double gate transistor DGT is not affected by light will be described. As shown in FIGS. 23A and 23B, the Vg-Id characteristic in the dark state is obtained when the conductive layer Etg is connected to the bottom gate electrode Ebg (G connection; indicated by a thick solid line in the figure). The drain-source current Ids is either connected to the source electrode Es (S connection; indicated by a thick broken line in the figure) or connected to the drain electrode Ed (D connection; indicated by a thin broken line in the figure). Showed almost the same change trend.

  As for the Vg-μ characteristic in the dark state, as shown in FIG. 24A, when the conductive layer Etg is connected to the drain electrode Ed (D connection), the gate-source voltage Vgs is approximately 2 to 2. In the range of 10 V, the carrier mobility μ becomes somewhat lower, and when the conductive layer Etg is connected to the source electrode Es (S connection), the carrier mobility μ changes relatively, but the conductive layer Etg The change tendency was almost the same as when connected to the bottom gate electrode Ebg (G connection).

  As for the Vd-Id characteristics in the dark state, as shown in FIG. 24B, when the conductive layer Etg is connected to the drain electrode Ed (D connection), the drain-source current Ids is somewhat smaller. Further, when the conductive layer Etg is connected to the source electrode Es (S connection), the drain-source current Ids changes relatively greatly, but the conductive layer Etg is connected to the bottom gate electrode Ebg (G The trend of change was almost the same as that of connection.

  Next, element characteristics in a bright state in which the double gate transistor DGT is affected by light will be described. As shown in FIGS. 25 and 26, the Vg-Id characteristic, Vg-μ characteristic, and Vd-Id characteristic in the bright state are obtained when the conductive layer Etg is connected to the bottom gate electrode Ebg (G connection; In either case of connecting to the source electrode Es (indicated by a thick solid line) (S connection; indicated by a thick broken line in the figure) or connecting to the drain electrode Ed (D connection; indicated by a thin broken line in the figure) Changes substantially equal to the Vg-Id characteristics, Vg-μ characteristics, and Vd-Id characteristics in the case where the conductive layer Etg is connected to the bottom gate electrode Ebg in the dark state described above (dark G connection; indicated by a thick dotted line in the figure). Showed a trend.

  Next, element characteristics when the conductive layer Etg of the double-gate transistor DGT is set in a floating state will be described with reference to FIGS. 23 and 24 again. As shown in FIGS. 23 and 24B, the Vg-Id characteristic and the Vd-Id characteristic when the conductive layer Etg of the double gate transistor DGT is set in a floating state (floating; indicated by a thick dotted line in the figure). Are Vg-Id characteristics and Vd-Id in a general thin film transistor (SingleGate; indicated by a thin dotted line in the figure) and other connection structures (G connection, S connection, D connection) in the double gate type transistor DGT described above. The change tendency was almost the same as the characteristic.

  On the other hand, as shown in FIG. 24A, when the conductive layer Etg of the double gate transistor DGT is set in a floating state (floating; indicated by a thick dotted line in the figure), (SingleGate; indicated by a thin dotted line in the figure) showed almost the same change tendency. Further, the Vg-μ characteristics in this case showed a change tendency almost in the middle when the conductive layer Etg is connected to the drain electrode Ed (D connection) or when it is connected to the source electrode Es (S connection).

  In FIG. 24A, the Vg-μ characteristic when the conductive layer Etg is connected to the bottom gate electrode Ebg (G connection; indicated by a thick solid line in the figure) is higher than that of a general thin film transistor. It has been found that the mobility μ increases by about 18%. On the other hand, the Vg-μ characteristic when the conductive layer Etg is connected to the source electrode Es (S connection) has been found to be about 15% lower than the general thin film transistor.

  Therefore, in the display panel 110 as shown in each of the above-described embodiments, the conductive layer Etg of the double gate transistor provided in the pixel PIX is connected to any one of the bottom gate electrode Ebg, the source electrode E, and the drain electrode Ed. Even when a structure or a structure set in a floating state is applied, light degradation of element characteristics of a double gate transistor (select transistor) to which amorphous silicon is applied can be suppressed, and a light emission driving circuit ( Pixel circuit) DC malfunction can be prevented.

<Fourth Embodiment>
Next, a display panel to which a pixel circuit according to a fourth embodiment of the present invention is applied will be described with reference to the drawings.

  In the first embodiment described above, the selection transistor (double gate type transistor Tr11) and the drive transistor (transistor Tr12) constituting the light emission drive circuit DC of the pixel PIX are arranged so as to overlap the formation region of the partition wall layer 15. A planar layout (see FIGS. 4 to 8) is shown. The fourth embodiment has a planar layout in which double-gate transistors are arranged in the boundary region between the pixels PIX where the partition layer 15 is not formed.

  FIG. 27 is a schematic view of a display panel to which the pixel circuit according to the fourth embodiment is applied. FIG. 27A is a plan view of a main part of a display panel to which the pixel circuit according to this embodiment is applied. In FIG. 27A, an insulating film and a partition layer formed on each transistor and wiring of the light emission driving circuit DC are mainly shown, and hatched for convenience of illustration. . FIG. 27B is a cross-sectional view of a main part of a display panel to which the pixel circuit according to this embodiment is applied. Here, the line XXVIIF-XXVIIF in the pixel having the planar layout shown in FIG. 27A (in this specification, “XXVII” is conveniently used as a symbol corresponding to the Roman numeral “27” shown in FIG. 27). It is a schematic sectional drawing which shows the cross section along line. In addition, about the structure equivalent to each embodiment mentioned above, the same code | symbol is attached | subjected and description is simplified.

  First, a transistor layout method (see FIGS. 5 to 8) as shown in the first embodiment will be described. In the first embodiment, as shown in FIG. 5, since the EL element formation region Rel is defined by the arrangement of the partition layer 15, the transistor (double gate) overlaps the formation region of the partition layer 15 in a plane. By disposing a type transistor and a thin film transistor), the aperture ratio of the pixel PIX can be improved. Further, in such a layout method, the counter electrode 18 provided substantially over the entire display area 20 so as to face the pixel electrode 16 of each pixel PIX is formed on the thick insulating layer including the partition wall layer 15 above the transistor. Will be. Therefore, in the case where a general thin film transistor is disposed in the formation region of the partition wall layer 15, the counter electrode 18 functions as a back gate electrode of the thin film transistor, and a phenomenon such as malfunction of the thin film transistor (back gate effect) can be suppressed.

  On the other hand, in the method for forming the organic EL layer 17 as shown in the first embodiment (see FIG. 14), in recent years, wet printing methods such as a nozzle printing method and an ink jet method are frequently used. In particular, according to the nozzle printing method, an organic compound can be appropriately and efficiently applied to the EL element formation region Rel of the pixel PIX by using the partition layer 15 having a stripe-like planar pattern as shown in FIG. By applying the containing liquid, the substantially uniform organic EL layer 17 can be easily formed. In this case, in order to suppress the uneven application of the organic compound-containing liquid and form the organic EL layer 17 having a uniform thickness on the pixel electrode 16, the unevenness of the surface of the application region between the partition walls 15 is as small as possible ( High flatness is desirable.

  For these reasons, there are significant restrictions on the pixel layout and the partition layer layout. For example, in the display panel 110 to which the partition wall layer 15 having a striped planar pattern is applied, a region such as a transistor is disposed in a boundary region between the pixels PIX arranged in the column direction and the insulating film 14 is exposed. It is necessary to design the layout so that the flatness of the surface is deteriorated and an element that is likely to malfunction due to the back gate effect is not arranged as much as possible.

  In the present embodiment, as shown in FIG. 27A, for example, in the boundary region between the pixels PIX, which is an area exposed to the slit-like opening 15h provided in the partition wall layer 15, for example, a selection transistor A double gate type transistor DGT is arranged. According to this, as shown in FIG. 27B, even when the counter electrode 18 is provided on the double gate type transistor DGT with the insulating film 14 interposed therebetween, the conductive layer is provided on the double gate type transistor DGT. By providing Etg, the back gate effect by the counter electrode 18 can be suppressed. In particular, the double gate transistor DGT is formed using the same conductive layer as the electrodes and wiring layers of other elements provided in the display panel 110 as shown in the above-described embodiment. Unevenness on the substrate surface can be minimized.

  Therefore, according to the display panel 110 as shown in the present embodiment, the partition layer 15 having a striped planar pattern is formed, and the nozzle printing method is applied, so that the EL element formation region Rel of each pixel PIX is applied. By applying an organic compound-containing liquid appropriately and efficiently, a substantially homogeneous organic EL layer can be easily formed. Further, according to the present embodiment, the degree of freedom in the layout design of the transistors (double gate type transistors) and partition walls constituting the light emission drive circuit DC can be improved, and the aperture ratio of the pixel PIX can be improved. .

<Fifth Embodiment>
Next, a pixel circuit according to a fifth embodiment of the present invention will be described with reference to the drawings.
In each of the above-described embodiments, the case where the double gate type transistor is applied to the selection transistors (Tr11, Tr21, Tr22) constituting the light emission drive circuit DC of each pixel PIX has been described. The fifth embodiment has a circuit configuration that is applied not only to the selection transistor constituting the light emission drive circuit DC but also to the drive transistors (Tr12, Tr23).

  FIG. 28 is an equivalent circuit illustrating an example of a pixel circuit according to the fifth embodiment. Here, the same components as those of the light emission drive circuit (pixel circuit) shown in each of the above-described embodiments are denoted by the same reference numerals, and description thereof is simplified. FIG. 28A shows a circuit configuration in which the present embodiment is applied to the pixel PIX (light emission drive circuit DC) shown in FIG. 2, and FIG. 28B shows the pixel PIX shown in FIG. 17 (light emission drive circuit). A circuit configuration in which the present embodiment is applied to a circuit DC).

  As shown in FIGS. 28A and 28B, the pixel circuit according to the fifth embodiment includes a transistor Tr12, which is a drive transistor, in addition to the selection transistors (Tr11, Tr21, Tr22) of the light emission drive circuit DC. Tr23 is also composed of a double gate type transistor. Even in this case, as shown in each of the above-described embodiments, as in the case where the double gate type transistor is applied to the selection transistor, it is possible to obtain the same effects such as suppression of light degradation and improvement of driving capability. it can.

  28A and 28B, a connection structure in which the top gate terminal TG (conductive layer Etg) of the double gate type transistors Tr12 and Tr23 is connected to the bottom gate terminal BG (bottom gate electrode Ebg). Indicated. The present invention is not limited to this, and as shown in the third embodiment (see FIG. 22), the conductive layer Etg is connected to the source electrode Es or the drain electrode Ed. Alternatively, it may be set in a floating state.

  In FIGS. 28A and 28B, double gate transistors are provided for all of the selection transistors (Tr11, Tr21, Tr22) and the drive transistors (Tr12, Tr23) constituting the light emission drive circuit DC of the pixel PIX. Although the applied circuit configuration is shown, a double gate transistor may be applied to at least one of the selection transistors and the driving transistor.

<Application examples of electronic devices>
Next, an electronic apparatus to which the display panel according to the above-described embodiment (a light-emitting panel including the pixel circuit according to the invention) is applied will be described with reference to the drawings.

  As shown in the embodiments described above, the display device 100 including the display panel 110 in which the pixels PIX having the organic EL elements OEL are two-dimensionally arranged includes, for example, a digital camera, a thin television, a mobile personal computer, It can be favorably applied as a display device for various electronic devices such as mobile phones.

  FIG. 29 is a perspective view illustrating a configuration example of a digital camera to which the light emitting device according to the present invention is applied, and FIG. 30 is a perspective view illustrating a configuration example of a thin television to which the light emitting device according to the present invention is applied. 31 is a perspective view showing a configuration example of a mobile personal computer to which the light emitting device according to the present invention is applied, and FIG. 32 is a diagram showing a configuration example of a mobile phone to which the light emitting device according to the present invention is applied. It is.

  29, the digital camera 210 is roughly divided into a main body unit 211, a lens unit 212, an operation unit 213, a display unit 214 including the display device 100 described in each of the above-described embodiments, and a shutter button 215. I have. According to this, it is possible to prevent deterioration of element characteristics and malfunction of the pixel (light emission drive circuit) in the display unit 214, and it is possible to improve the degree of freedom of pixel layout design and increase the aperture ratio. The display image quality can be improved.

  In FIG. 30, the thin television 220 is broadly divided into a main body 221, a display unit 222 including the display device 100 described in the above-described embodiment, and an operation controller (remote controller) 223. . According to this, it is possible to prevent deterioration of element characteristics and malfunction of the pixel (light emission drive circuit) in the display unit 222, and it is possible to improve the degree of freedom of pixel layout design and increase the aperture ratio. The display image quality can be improved.

  In FIG. 31, the personal computer 230 roughly includes a main body 231, a keyboard 232, and a display unit 233 including the display device 100 described in the above embodiment. Even in this case, it is possible to prevent deterioration of element characteristics and malfunction of the pixel (light emission drive circuit) in the display portion 233, and it is possible to improve the degree of freedom in pixel layout design and increase the aperture ratio. The display image quality can be improved.

  In FIG. 32, the mobile phone 240 is roughly provided with an operation unit 241, an earpiece 242, a mouthpiece 243, and a display unit 244 including the display device 100 described in the above-described embodiment. . Even in this case, it is possible to prevent deterioration of element characteristics and malfunction of the pixel (light emission drive circuit) in the display portion 244, and to improve the degree of freedom in pixel layout design and increase the aperture ratio. The display image quality can be improved.

  In each electronic device described above, the case where the light-emitting panel to which the pixel circuit according to the present invention is applied is applied as a display panel has been described in detail. However, the present invention is not limited to this. A pixel circuit and a light-emitting device according to the present invention include, for example, a light-emitting element array in which a plurality of pixels each having a light-emitting element are arranged in one direction, and irradiates light emitted from the light-emitting element array on a photosensitive drum according to image data Then, it may be applied to an exposure apparatus that performs exposure.

11 Substrate 12, 13, 14 Insulating film 15 Partition layer 16 Pixel electrode 17 Organic EL layer 18 Counter electrode 20 Display area 30 Peripheral area 110 Display panel PIX pixel Rpx Pixel formation area Rel EL element formation area OEL Organic EL element Tr11, Tr21, Tr22 Double-gate transistor Tr12, Tr23 Transistor Cs Capacitor Ls Selection line Lv Power supply line La Voltage supply line Lb Auxiliary wiring Ld Data line

Claims (11)

In a light emitting device including a light emitting panel in which a plurality of pixels are arranged,
Each of the plurality of pixels includes a light emitting element, and a pixel circuit that causes the light emitting element to emit light at a predetermined luminance gradation based on a gradation signal,
The pixel circuit includes at least
A selection transistor for setting the pixel to a selected state in order to write the gradation signal;
A drive transistor that generates a light emission drive current having a current value corresponding to the gradation signal and supplies the light emission drive current to the light emitting element;
The selection transistor is connected to the semiconductor layer, a semiconductor layer forming a channel region, a gate electrode and a conductive layer disposed on one side and the other side of the semiconductor layer with the semiconductor layer interposed therebetween, and A source electrode and a drain electrode disposed so as to face each other,
The light-emitting device, wherein the conductive layer is formed of an opaque conductive material and is formed at the same time as a part of a signal line connected to the pixel circuit. The light emitting device is at least
A plurality of selection lines arranged in a row direction of the light emitting panel;
A plurality of data lines arranged in a column direction of the light emitting panel;
A power supply line for applying a power supply voltage of an emission level to the light emitting element of the pixel;
A selection drive circuit configured to apply a selection signal to the selection line and set the selection state to enable writing of the gradation signal to the pixel connected to the selection line;
A data driving circuit that generates the gradation signal based on image data and supplies the gradation signal to the pixel set in the selected state via the data line;
The light-emitting device according to claim 1.   3. The light emitting device according to claim 2, wherein the signal line formed simultaneously with the conductive layer is at least a part of the power supply line. The light-emitting panel includes a partition layer provided at least in a region between the pixels,
4. The light emitting device according to claim 1, wherein at least the selection transistor and the driving transistor are provided in a lower layer of the partition wall layer. The light emitting panel includes a partition layer having a stripe-shaped opening through which pixel electrodes of the plurality of pixels arranged in a specific direction are exposed,
4. The light emitting device according to claim 1, wherein the selection transistor is provided in a region between the pixel electrodes in the opening.   6. The light emitting device according to claim 1, wherein the selection transistor has the conductive layer electrically connected to the gate electrode.   The light emitting device according to claim 1, wherein the selection transistor has the conductive layer electrically connected to either the source electrode or the drain electrode.   The light emitting device according to claim 1, wherein the selection transistor has the conductive layer set in an electrically floating state.   The light emitting device according to claim 1, wherein at least the semiconductor layer of the selection transistor is made of amorphous silicon.   An electronic apparatus comprising the light emitting device according to claim 1 mounted thereon. In a method for manufacturing a light-emitting device including a light-emitting panel in which a plurality of pixels having a light-emitting element and a pixel circuit including a transistor that controls the light-emitting element are arranged.
A semiconductor layer of the transistor; a gate electrode disposed on one side of the semiconductor layer across the semiconductor layer; a source electrode and a drain electrode connected to the semiconductor layer and disposed to face each other; Forming a
Forming a conductive layer on the other side of the semiconductor layer simultaneously with a part of a signal line made of an opaque conductive material connected to the pixel;
A method for manufacturing a light-emitting device, comprising:

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