JP4712156B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device using a crystalline semiconductor film. Note that the semiconductor device of the present invention is not limited to an element such as a thin film transistor or a MOS transistor, but also an electronic apparatus having a semiconductor circuit formed of these insulated gate semiconductor elements, or an electro-optic display device including an active matrix substrate (typically The category also includes electronic devices such as personal computers and digital cameras equipped with liquid crystal display devices and EL display devices.
[0002]
[Prior art]
Currently, a thin film transistor (TFT) is known as a semiconductor element using a semiconductor film. The TFT is used as a switching element in the pixel portion of the active matrix liquid crystal display device. In recent years, a TFT can be manufactured using a polycrystalline silicon film having a higher mobility than an amorphous silicon film as a semiconductor layer, and the mobility of the TFT has been increased. As a result, not only the pixel portion but also the driver circuit can be manufactured on the same substrate.
[0003]
Conventionally, in order to form a polycrystalline silicon film, a method of directly forming a polycrystalline silicon film by raising the substrate temperature by a CVD method and a method of forming amorphous silicon by a CVD method or a sputtering method, There are known a method of crystallizing in a solid phase by heating at a temperature of 1100 ° C. for 20 to 48 hours, and a method of melting and recrystallizing an amorphous silicon film by irradiation with an excimer laser. The polycrystalline silicon film obtained by crystallizing the amorphous silicon film has larger crystal grains than the polycrystalline silicon film formed directly on the substrate, and the characteristics of the manufactured semiconductor element are also good.
[0004]
When crystallization is performed by heat treatment, when a glass substrate is used, the upper limit of the crystallization process temperature is about 600 ° C., and the crystallization process takes a long time. Further, the temperature of 600 ° C. is close to the lowest temperature for crystallizing silicon, and if it becomes 500 ° C. or less, it cannot be crystallized in industrial time.
[0005]
In order to shorten the crystallization time, it is sufficient to use a quartz substrate having a high strain point and raise the heating temperature to about 1000 ° C. However, the quartz substrate is very expensive compared to the glass substrate, and the area is increased. It is difficult. On the other hand, glass substrates have the advantages of being inexpensive and easy to increase in area, but having the disadvantage of low heat resistance. Corning 7059 glass widely used in active matrix liquid crystal display devices has a glass strain point of 593 ° C., and heating at a temperature of 600 ° C. or higher for several hours may cause the substrate to warp or bend. It is. For this reason, the crystallization process is required to have a low temperature and a short time so that a glass substrate such as Corning 7059 glass can be used.
[0006]
Crystallization technology using an excimer laser is one of the technologies that enables process temperature reduction and time reduction. Excimer laser light can give a semiconductor film energy in a short period of time comparable to thermal annealing at around 1000 ° C. with little thermal effect on the substrate, and can form a highly crystalline semiconductor film. it can. However, since the excimer laser varies in energy distribution on the irradiated surface, it is difficult to make the crystallinity of the obtained crystalline semiconductor film uniform, and it is difficult to make the characteristics of each TFT element uniform. .
[0007]
Therefore, the present applicant has intensively studied a technique for lowering the crystallization temperature using heat treatment, and disclosed the results in JP-A-6-232059, JP-A-7-321339, and the like. Yes. The technique of the above publication obtains a crystalline silicon film by thermal annealing in a state where a metal element for promoting crystallization is slightly added to an amorphous silicon film. With this crystallization technique, it has become possible to form crystalline silicon by thermal annealing at 450 to 600 ° C. for 4 to 12 hours.
[0008]
[Problems to be solved by the invention]
However, this crystallization technique has a problem that the metal element used for promoting crystallization remains in the crystalline silicon film. Since the metal element impairs the semiconductor characteristics of the silicon film, it becomes a cause of impairing the stability and reliability of the TFT characteristics.
[0009]
In order to solve this problem, the present inventor has developed a technique (gettering technique) for removing a crystallization promoting element from a crystalline silicon film, and disclosed in Japanese Patent Laid-Open No. 10-270363. That technique is to selectively add phosphorus to the crystalline silicon film and perform thermal annealing. By thermal annealing, nickel in the region where phosphorus is not added diffuses into the phosphorus-added region and is captured in this region, and as a result, the metal element concentration in the region where the additive is not added is lowered. The thermal annealing temperature could be 600 ° C. or lower that the glass substrate can withstand. However, there is a drawback that the processing time is more than 10 hours. In addition, since the phosphorus-added region is formed, a region where an element can be formed is limited, which prevents high integration.
[0010]
An object of the present invention is to provide a technique for solving the above-described problems and improving the removal efficiency of a metal element and realizing high integration in a technique of forming a crystalline silicon film using a metal element. It is to provide.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problems, in the present invention, after crystallizing a semiconductor film using a metal element that promotes crystallization, a group 15 element, specifically phosphorus, is selectively added to the crystallized semiconductor film. Alternatively, antimony is added and thermal annealing is performed, and the metal element contained in the region to which the group 15 element is not added is diffused and captured (gettering) in the region to which the group 15 element is added.
[0012]
Since the diffusion distance of the metal element becomes longer as the region (gettering region) added with the group 15 element that absorbs and captures the metal element is separated from the region where the metal element should be reduced (gettering region), the removal is performed. It will take time. Therefore, in the present invention, one of the features is to make the gettering region as close as possible to the gettering region.
[0013]
In the present invention, a semiconductor crystallized using a metal element that promotes crystallization is a semiconductor having an amorphous portion. The semiconductor is specifically a semiconductor containing silicon as a main component, a semiconductor containing germanium as a main component, or a compound semiconductor of silicon and germanium, and its crystallinity is amorphous or microcrystalline. The microcrystal is a mixed phase of microcrystal and amorphous including crystal grains having a size of several nm to several tens of nm. The semiconductor film may be formed to a thickness of 10 to 150 nm, and is formed by a chemical vapor phase method such as a plasma CVD method or a low pressure CVD method, or a physical vapor phase method such as a sputtering method.
[0014]
The metal element that promotes crystallization is an element having a catalytic action that particularly promotes crystallization of silicon. From Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. One selected element or a plurality of elements can be used. Ni (nickel) has the highest effect of promoting crystallization.
[0015]
In order to introduce a metal element that promotes crystallization into the semiconductor film, a method of adding the metal element to the semiconductor film by an ion doping method, an ion implantation method, a diffusion method, or the like can be used. Alternatively, a film containing a metal element may be formed on the upper surface or the lower surface of the semiconductor film. In order to form a film containing a metal element, a coating method using a CVD method, a sputtering method, a vapor deposition method, a spinner, or the like may be used. The metal element film may be a metal element film, a film made of the metal compound thereof, typically a film made of silicide. For example, when Ni is used for the metal element, a nickel film or a nickel silicide film may be formed.
[0016]
In the case of using the coating method, nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, nickel sulfate, etc. as a solute, water, alcohol, acid, A solution containing ammonia as a solvent or a solution containing nickel element as a solute and a solvent selected from benzene, toluene, xylene, carbon tetrachloride, chloroform and ether can be used. Alternatively, a material such as an emulsion in which nickel is dispersed in a solvent may be used even if nickel is not completely dissolved.
[0017]
Alternatively, a method of forming an oxide film containing nickel by dispersing nickel alone or a nickel compound in a solution for forming an oxide film may be used. As such a solution, Oka (Ohka Diffusion Source) manufactured by Tokyo Ohka Kogyo Co., Ltd. can be used. If this OCD solution is used, a silicon oxide film can be easily formed by coating on the surface to be formed and baking at about 200 ° C. The same applies to other metal elements.
[0018]
Here, either the film containing the metal element or the semiconductor film may be formed first. If the semiconductor film is formed first, the film containing the metal element that promotes crystallization is formed on the semiconductor film. After that, a film containing a metal element that promotes crystallization is formed under the semiconductor film.
[0019]
The film containing the metal element is not only formed in contact with the semiconductor film, but an oxide film having a thickness of about several nm to 10 nm, a natural oxide film, or the like is provided between the semiconductor film and the film containing the metal element film. May be present. In the crystallization process of the semiconductor film described below, it is sufficient that the metal element can be diffused from the film containing the metal element into the semiconductor film. The thickness of the oxide film or the natural oxide film is about several nm to 10 nm. That is no problem with crystallization.
[0020]
In order to crystallize a semiconductor film including an amorphous part, the semiconductor film is heated by thermal annealing or light annealing, and the metal element moves within the semiconductor film while reacting silicon or germanium (nucleic acid). Let While the metal element moves, it exerts a catalytic action on the molecular chain in an amorphous state to crystallize the semiconductor film. Regarding the action of the metal element, the present applicant discloses in Japanese Patent Laid-Open Nos. 6-244103 and 6-244104.
[0021]
Silicon in contact with the metal element is bonded to the metal element, and silicide is formed. It was found that the crystallization proceeds due to the reaction between the silicide and the amorphous silicon bond. This is because the interatomic distance between the metal element that promotes crystallization and silicon is very close to the interatomic distance of single crystal silicon, and the Ni—Si distance is closest to the single crystal Si—Si distance. 6% shorter.
[0022]
When the reaction of crystallizing an amorphous silicon film using Ni is modeled, Si [a] -Ni (silicide) + Si [b] -Si [c] (amorphous)
→ Si [a] -Si [b] (crystallinity) + Ni-Si [c] (silicide). In the reaction formula, the indices [a], [b], and [c] represent Si atom positions.
[0023]
This reaction formula shows that the Ni [a] -Si [b] distance is almost the same as that of the single crystal because the Ni atom in the silicide is replaced with the Si [b] atom of the amorphous silicon. ing. Further, it is shown that Ni is crystal-grown while diffusing in the semiconductor film.
[0024]
In order to give energy for advancing the crystallization reaction, thermal annealing at 450 ° C. or higher may be performed in a heating furnace. The upper limit of the thermal annealing temperature is 650 ° C. When the temperature exceeds 650 ° C., the crystallization of the semiconductor film proceeds even in a portion that does not react with the metal element that promotes crystallization, and the crystal grains cannot be increased, and the grain size also varies.
[0025]
Further, as a method for solid phase growth equivalent to the heat treatment in the heating furnace, light annealing that irradiates infrared light can be used. As light annealing using infrared light, an RTA method is known in which infrared light having a peak at a wavelength of 0.6 to 4 μm, more preferably 0.8 to 1.4 μm, is irradiated for several tens to several hundreds of seconds. Since the absorption coefficient for infrared light is high, the semiconductor film is heated to 800 to 1100 ° C. in a short time by irradiation with infrared light. However, in the RTA method, since the irradiation time becomes long, heat is easily absorbed by the substrate. When a glass substrate is used, attention must be paid to the warpage of the substrate.
[0026]
By the way, the reaction formula showing the above crystallization model shows that when crystallization is completed, Ni is bonded to Si and is localized at the terminal end (or the tip of crystal growth). Show. That is, NiSi _x In the silicidated state represented by the formula, the film is irregularly distributed in the crystallized film. The presence of such silicide is due to FPM (50% HF and 50% H ₂ O ₂ Can be confirmed by etching the crystallized silicon film in about 30 seconds. A portion where silicide is formed by etching becomes a hole.
[0027]
In the present invention, in order to remove (getter) the metal element present in the crystallized semiconductor film, the group 15 element is added by selectively adding the group 15 element to the semiconductor film and performing thermal annealing. Reduce the metal element concentration in the areas that were not. The annealing temperature is 500 to 850 ° C., more preferably 550 to 650 ° C., and the annealing time is 1 to 12 hours.
[0028]
A region where a metal element that promotes crystallization is reduced (a gettering region) includes at least a region that serves as a channel formation region. Switching characteristics and mobility values are greatly affected by the characteristics of the channel formation region. If the metal element that promotes crystallization remains in the channel formation region, the characteristics of the semiconductor are impaired, which causes the stability and reliability of the device to be impaired.
[0029]
Further, it is preferable that the gettering region includes a low-concentration impurity region that is bonded to the channel formation region in addition to the region to be the channel formation region. The low-concentration impurity region is a region formed in order to reduce a leakage current when a reverse bias voltage is applied or to suppress deterioration due to hot carriers. Therefore, by reducing the metal element that promotes crystallization remaining in the low-concentration impurity region, it is possible to manufacture an element that is stable and reliable with respect to reduction of leakage current. Note that the low concentration impurity region is a region in which the impurity concentration that determines the conductivity type of the source / drain is lower than that of the source region or the drain region, and the impurity concentration is 1 × 10 6. ¹⁶ ~ 1x10 ¹⁹ atoms / cm ^Three It is.
[0030]
The concentration of the group 15 element added to the gettering region is about 10 times the concentration of the metal element that promotes crystallization remaining in the semiconductor film. Metal element concentration is 10 ¹⁸ -10 ²⁰ atoms / cm ^Three If it is in order, crystallization can be performed with good reproducibility. Since metal elements that promote crystallization remain in this order, the concentration of phosphorus or antimony in the gettering region is 10 ¹⁹ -10 ^{twenty two} atoms / cm ^Three Any order is acceptable. Phosphorus (P) and antimony (As) are n-type impurities for imparting n-type conductivity to a semiconductor made of silicon or germanium, and are contained in the gettering region in the above concentration range. A gettering region made of an added semiconductor can be used as an n-type impurity region of a semiconductor element.
[0031]
Therefore, in the present invention, a region to which phosphorus or antimony for capturing a metal element is added is included in the semiconductor film of the semiconductor element. With this configuration, the gettering region approaches the channel formation region, and at the same time, the region in which the element can be formed in the semiconductor film is widened, so that integration is facilitated.
[0032]
For example, in an n-channel TFT, at least one of an n-type source region and a drain region may include a group 15 element-added region serving as a gettering region. As long as the gettering region has at least the size of a region to be a source region or a region to be a drain region, the metal element in the channel formation region and the low concentration impurity region can be sufficiently removed. Of course, the wider the gettering region, the lower the temperature and the shorter the time for thermal annealing.
[0033]
In order to add phosphorus and antimony to the semiconductor film, a gas phase method such as a plasma doping method without mass separation or an ion implantation method with mass separation can be given. When such an addition method is used, the crystallinity of the region to which the element is added is impaired. As described above, the region used for gettering the metal element is included in the n-type high-concentration impurity region and the p-type high-concentration impurity region provided in the semiconductor film of the semiconductor element. It is necessary to restore the property (recrystallization). In the present invention, since the step of recovering crystallinity is combined with the step of thermal annealing for gettering the metal element, phosphorus annealing is performed so that the n-type impurity region can be recrystallized by thermal annealing at about 500 to 650 ° C. Add antimony.
[0034]
Since the crystallinity is impaired as the concentration of the impurity to be added becomes higher, the recrystallization becomes difficult. Therefore, in the present invention, the concentration distribution of phosphorus or antimony in the thickness direction of the semiconductor film is defined in the gettering region so as to be recrystallized. FIG. 1 is an example of the concentration profile (concentration distribution in the depth direction) of the group 15 element in the gettering region of the present invention, the vertical axis indicates the concentration, and the horizontal axis indicates the depth of the semiconductor film. The surface of the semiconductor film is set to zero.
[0035]
The maximum concentration of the group 15 element is set to 5 × 10 so that the metal element can be gettered and can function as a source or drain. ¹⁹ atoms / cm ^Three More specifically, 1 × 10 ²⁰ ~ 1x10 ^{twenty two} atoms / cm ^Three It is in the range. At the same time, for recrystallization, the concentration (thickness from the interface with the base film) is 5 nm or more, typically 5 nm to 20 nm, and the concentration is 1 × 10 10. ²⁰ atoms / cm ^Three Make sure that: That is, in the gettering region, 1 × 10 ²⁰ atoms / cm ^Three The thickness d of the layer to be described below (a region indicated by hatching in FIG. 1) may be 5 nm or more, typically 5 nm to 20 nm.
Group 15 element concentration is 1 × 10 ²⁰ atoms / cm ^Three Since the crystallinity of the semiconductor is not significantly impaired in the following part, the entire gettering region can be recrystallized using this part as a nucleus. In order to function as a crystal nucleus, the thickness d of this region is set to 5 nm or more and 5 nm to 20 nm.
[0036]
Furthermore, in the present invention, it has been found that a gettering effect higher than that of only phosphorus or antimony can be obtained by adding not only a group 15 element such as phosphorus but also a group 13 element to the gettering region. . The present inventor has disclosed this gettering technique in JP-A-11-54760. A higher gettering effect can be obtained by adding the group 13 element at a higher concentration than the group 15 element. However, when the concentration of the group 13 element is lower than that of the group 15 element, the metal element cannot be gettered. Further, the metal element could not be gettered only by the group 13 element. A semiconductor in which the concentration of a group 13 element is higher than that of a group 15 element is a semiconductor having a p-type conductivity, and can be used as a p-type impurity region of a semiconductor element.
[0037]
Therefore, at least one of the source region and the drain region of the p-channel TFT can include a p-type impurity region for gettering the metal element. The group 13 element used to form the p-type source / drain is boron, which has a high gettering effect.
[0038]
In the p-type impurity region used as a gettering region in the present invention, boron is added to both phosphorus (or antimony), but since the atomic weight of boron is smaller than that of silicon or germanium, a crystallized semiconductor is formed by doping boron. It is considered that the crystallinity of the film is not significantly impaired. Therefore, the boron concentration profile in the gettering region may be higher than that of the group 15 element so that the gettering effect can be obtained. On the other hand, the concentration profile of the group 15 element satisfies the condition of the concentration profile of the group 15 element in the n-type impurity region described with reference to FIG.
[0039]
SIMS (mass secondary ion analysis) may be used to measure the concentration profiles of phosphorus, antimony, and boron. FIG. 2 shows phosphorus and boron concentration profiles measured by SIMS. FIG. 2 shows an example of the phosphorus and boron concentration profiles in the p-type silicon film used for the gettering region. The thickness of the silicon film is about 50 nm. Phosphorus and boron were added by an ion doping method. As the doping gas, phosphine was used for phosphorus and diborane was used for boron. Both gases are diluted with hydrogen. The acceleration voltage is 10 keV for both phosphorus and boron, and the set dose is 1.5 × 10 5 for phosphorus. ¹³ ions / cm ² Boron is 7.8 × 10 ¹⁴ ions / cm ² It was.
[0040]
By the thermal annealing for gettering, the metal element is removed from the region where the group 15 element is not added. For example, when nickel was used as the metal element, the above-described FPM treatment was performed after gettering, but no hole was generated in the region where the group 15 element was not added. Also, in the measurement by SIMS, the concentration of the metal element is 5 × 10 ¹⁷ atoms / cm ^Three Below, further 2 × 10 ¹⁷ atoms / cm ^Three It can be reduced to the following.
[0041]
Currently, the lower limit of detection by SIMS is 2 × 10. ¹⁷ atoms / cm ^Three Therefore, it is not possible to examine the concentration below that. However, the gettering process described herein at least 1 × 10 ¹⁴ ~ 1x10 ¹⁵ atoms / cm ^Three It is estimated that the metal elements that promote crystallization are reduced to a certain extent. By forming the channel formation region using a semiconductor with reduced metal elements in this manner, the reliability of the TFT can be increased.
[0042]
On the other hand, in an n-type impurity region or a p-type impurity region gettered with a metal element, the concentration of the metal element is 1 × 10 5. ¹⁸ atoms / cm ^Three 1 × 10 ¹⁸ ~ 1x10 ^{twenty one} atoms / cm ^Three It becomes. The metal concentration is defined by the maximum value measured by SIMS.
[0043]
For example, when a metal element that promotes crystallization is Ni and an n-type impurity region in which phosphorus (P) is added to the gettering region is used, nickel gettered in the n-type impurity region is NiP. ₁ , NiP ₂ Ni ₂ ... exists in a combined state. Since this bonding state is very stable, even if a region where the metal element is gettered is included in the source region or the drain region, the operation of the TFT is hardly affected.
[0044]
Further, since the n-type or p-type impurity region gettered with the metal element is doped with the group 15 element or the group 13 element in the above-described concentration profile, the crystallinity is recovered by thermal annealing at 500 to 650 ° C. The
[0045]
In the present invention, the laser light or strong light having the same intensity as the laser light (e.g., emitted from a halogen lamp) is applied to the crystallized crystalline semiconductor film before the thermal annealing for reducing the metal element for promoting crystallization. By performing light annealing using infrared light or ultraviolet light emitted from an ultraviolet lamp, this thermal annealing can be performed at a low temperature and with a shorter time.
[0046]
Metal element is NiSi _x As described above, they are distributed in the semiconductor film in a state of being bonded to molecules. The molecular bond is broken by the energy of light annealing, and the metal element that promotes crystallization is put into an atomic state, or the molecular bond energy is lowered, so the metal element remaining in the semiconductor film is crystalline. It is considered that the semiconductor film is easily moved.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
[0048]
[Embodiment 1]
The present embodiment will be described with reference to FIGS. 3 and 4. This embodiment relates to a manufacturing process of an n-channel TFT, and an n-type high-concentration impurity region serving as a source region and a drain region is used as a gettering region.
[0049]
As shown in FIG. 3A, a substrate 10 is prepared, and a base film 11 is formed on the surface of the substrate 10. The substrate 10 includes an insulating substrate such as a glass substrate, a quartz substrate, a ceramic (also referred to as crystalline glass), a single crystal silicon substrate, a Cu substrate, a refractory metal material such as Ta, W, Mo, Ti, Cr, or the like. A conductive substrate such as a substrate made of an alloy or a compound containing these metal elements (for example, a nitrogen-based alloy such as tantalum nitride or a silicide such as tungsten silicide) can be used.
[0050]
The base film 11 has a function of preventing impurities from diffusing from the substrate into the semiconductor element, and a function of improving the adhesion of the semiconductor film and metal film formed on the substrate 10 to prevent peeling. As the base film 11, an inorganic insulating film such as a silicon oxide film formed by a CVD method or the like, or a silicon nitride film or a silicon nitride oxide film can be used. For example, when a single crystal silicon substrate is used, the base film can be formed by oxidizing the surface by thermal oxidation. When a heat resistant substrate such as a quartz substrate or a single crystal silicon substrate is used, an amorphous silicon film may be formed and thermally oxidized.
[0051]
Further, as the base film 11, a coating film of a high melting point metal such as tungsten, chromium, tantalum or the like, or a coating film having high conductivity such as aluminum nitride, boron nitride, DLC (Diamond Like Carbon), alumina or the like is used as the inorganic insulating film. A coated multilayer film may be used. In this case, since the heat generated in the semiconductor device is radiated by the base film 11, the operation of the semiconductor device becomes stable.
[0052]
A semiconductor film having an amorphous part is formed in contact with the surface of the base film 11. Here, the amorphous silicon film 12 is formed to a thickness of 55 nm by low pressure CVD. (Fig. 3 (A))
[0053]
Next, a metal element that promotes crystallization is introduced into the semiconductor film having an amorphous portion. Here, nickel is used as the metal element, and a film 13 containing nickel is formed on the surface of the amorphous silicon film 12 by a coating method using a spinner.
[0054]
A nickel acetate solution is applied to the surface of the amorphous silicon film 12 by a spinner, and this state is maintained for several minutes. By drying using a spinner, a film 13 containing nickel is formed as a film containing a metal element. Although the film 13 containing nickel is not necessarily a complete film, there is no problem even if it is not a film, and it is practical if the nickel concentration in the nickel acetate solution is 1 ppm or more, more preferably 10 ppm or more.
[0055]
Here, before applying the nickel acetate solution, in order to improve the wettability of the surface of the amorphous silicon film, a very thin silicon oxide film of about several nm is formed by irradiation with UV light. Since the silicon oxide film is thin, nickel can pass through the silicon oxide film and react with amorphous silicon from the film 13 containing nickel. (Fig. 3 (B))
[0056]
In the heating furnace, the amorphous silicon film 12 introduced with nickel is thermally annealed to crystallize to form a crystalline silicon film 14. Here, thermal annealing is performed at 550 ° C. for 8 hours in a nitrogen atmosphere. Since the nickel element is in contact with the entire surface of the amorphous silicon film 12, the nickel moves from the silicon film surface toward the base film substantially perpendicularly to the substrate surface. Crystallization of the silicon film 12 proceeds with the movement of nickel, and crystals grow in that direction. (Figure 3 (C))
[0057]
Next, in the crystalline silicon film 14, a group 15 element, here phosphorus (P), is added to a region including a region which becomes a source region and a drain region of the TFT. In FIG. 3D, a rectangular region 18 surrounded by a dotted line is an element formation region which becomes a semiconductor layer of the TFT.
[0058]
Here, in the element formation region 18, a region that becomes a channel formation region and a low concentration impurity region of the semiconductor layer is covered with a mask 15. As the mask 15, an inorganic insulating film such as silicon oxide or silicon nitride silicon oxynitride film, a resist, or the like can be used. However, an inorganic insulating film is preferable because it is in contact with the channel formation region. Here, a silicon oxide film having a thickness of 100 nm is formed and patterned to form the mask 15. Here, before the mask 15 is formed, the crystalline silicon film 14 is optically annealed by an excimer laser.
[0059]
A phosphorus addition region 16 is formed in the crystalline silicon film 14 by selectively adding phosphorus with an ion doping apparatus. In order for the phosphorus concentration profile to be included in the profile described with reference to FIG. 1, the doping condition is phosphine diluted to 5% with hydrogen as the doping gas, the acceleration voltage is 10 kV, and the set dose is 1.5. × 10 ¹⁴ ions / cm ² And Here, the region where phosphorus is not added is referred to as a non-added region 17 for convenience. (Fig. 3 (D))
[0060]
Next, the crystalline silicon film 14 is thermally annealed, and nickel in the non-added region 17 is gettered to the phosphorus-added region 16. Here, the annealing temperature is 600 ° C. and the annealing time is 8 hours. As a result of the thermal annealing, nickel in the non-added region 17 moves toward the phosphorus-added region as indicated by an arrow, and bonds with phosphorus in the phosphorus-added region 16. The nickel concentration in the non-added region 17 is 2 × 10 ¹⁷ atoms / cm ^Three It becomes the following. Furthermore, the crystallinity damaged at the time of doping is recovered in the phosphorus added region 16 by thermal annealing, and the added phosphorus is activated. (Fig. 4 (A))
[0061]
After removing the mask 15, the crystalline silicon film 14 is patterned into an island shape to form an island-shaped semiconductor film. Note that the mask may be removed before thermal annealing for gettering. The phosphorus-added region 16 is patterned so as to become the n-type impurity regions 20 and 21 of the TFT, and the non-added region 17 becomes a region 23 in which a channel forming region and a low concentration impurity region are formed. (Fig. 4 (B))
[0062]
Next, a gate insulating film 24 is formed so as to cover the island-shaped semiconductor film 19, and phosphorus is added to the island-shaped semiconductor film 19 using the gate wiring 25 as a mask on the gate insulating film 24 to form a low concentration impurity region. Form. As the doping gas, phosphine diluted to 5% with hydrogen is used. Using ion doping equipment, acceleration voltage 90kV, set dose 3 × 10 ¹³ ions / cm ² It was.
[0063]
As a result of doping, a source region 26, a drain region 27, a channel formation region 28, and low-concentration impurity regions 29 and 30 are formed in a self-aligned manner. In this doping step, phosphorus is 10% in the low concentration impurity regions 29 and 30. ¹⁶ -10 ¹⁹ atoms / cm ^Three It is added in order. For this reason, the concentration profile of phosphorus in the source / drain regions 26 and 27 is not so different from that of the n-type impurity regions 20 and 21, and the conditions of the concentration profile capable of recrystallization are maintained.
[0064]
After doping, excimer laser irradiation is performed to activate phosphorus added to the source / drain regions 26 and 27 and the low-concentration impurity regions 29 and 30. Then, an interlayer insulating film 31 is formed, contact holes reaching the source / drain regions 26 and 27 are formed therein, and a source wiring 32 and a drain wiring 33 are formed. (Fig. 4 (D))
[0065]
[Embodiment 2]
The present embodiment will be described with reference to FIG. This embodiment is different from the first embodiment in the nickel introduction method, and the rest is the same as the first embodiment.
[0066]
A base film 51 is formed on the surface of the substrate 50. As a semiconductor film including an amorphous portion, an amorphous silicon film is formed by a low pressure thermal CVD method. The film thickness of the amorphous silicon film is 55 nm.
[0067]
A 120 nm thick silicon oxide film is formed on the amorphous silicon film 52 and an opening is formed as a mask 53. The opening of the mask defines the nickel addition region. As the mask 53, a resist or a silicon oxide film can be used.
[0068]
Next, a solution in which nickel acetate containing nickel of 10 ppm by weight is dissolved in ethanol is applied by spin coating and dried to form a film 54 containing nickel. (Fig. 5 (A))
[0069]
Next, thermal annealing is performed at 570 ° C. for 8 hours in a nitrogen atmosphere to crystallize the amorphous silicon film 52 and form a crystalline silicon film 56. When the amorphous silicon film 52 is exposed at the opening, the reaction between nickel and silicon starts in the region 55. By thermal annealing, crystallization is performed while diffusing in the silicon film 52 with nickel as schematically shown by an arrow with the region 55 as a base point. Here, heat treatment is performed at 570 ° C. for 8 hours, so that the crystalline semiconductor film 56 containing nickel is formed. (Fig. 5 (B))
[0070]
As described above, the crystallization of silicon proceeds preferentially from the nickel silicide reacted in the region 55 and grows almost parallel to the surface of the substrate 50, so that the crystal grains can be grown greatly and the crystal The growth direction is aligned and the overall crystallinity is excellent.
[0071]
According to TEM (transmission electron microscopy) observation, the crystal grains in the crystalline silicon film 56 were rod-shaped or flat rod-shaped, and the orientations of these crystal grains were almost uniform. Almost all of these crystal grains are roughly {110} oriented, the directions of the <100> axis and the <111> axis are the same for each crystal grain, and the <110> axis is slightly less than 2 ° between the crystal grains. It is shaking. Thus, since the orientations of the crystal axes are uniform, the bonding of atoms at the crystal grain boundary becomes smooth and there are few unpaired bonds.
[0072]
Since conventional polycrystalline silicon has irregular crystal axis directions for each crystal grain, there are many atoms that cannot be bonded at grain boundaries. In this respect, the crystalline structure of the crystalline silicon film of this embodiment is completely different from that of the conventional polycrystalline silicon film. The crystalline silicon film has almost no atomic bonds at the crystal grain boundary, and the two crystal grains are joined together with extremely good consistency, so that the crystal lattice is continuously connected at the crystal grain boundary, resulting in crystal defects. It is very difficult to generate trap levels due to the above.
[0073]
After removing the mask 53, a mask 58 for selectively adding phosphorus is formed. In the present embodiment, the mask 58 is wider than the element formation region 61 and formed in a strip shape. Of course, the mask 58 covers the channel forming region and the portion to be the low concentration impurity region. Further, since nickel is first added in the region 55 and nickel remains at a high concentration, it is desired that the region 55 is not included in the element formation region 61.
[0074]
Phosphorus is added by an ion doping apparatus to selectively form a phosphorus addition region. The doping conditions are phosphine diluted to 5% with hydrogen as doping gas, acceleration voltage 10 kV, set dose amount 1.5 × 10 ¹³ ions / cm ² And Here, a region where phosphorus is not added is referred to as a non-added region 60 for convenience. (Fig. 5 (C))
[0075]
Then, after forming the phosphorus-added region 59, thermal annealing is performed at 600 ° C. for 12 hours to getter the nickel contained in the non-added region 60 into the phosphorus-added region 59. (Fig. 5 (C))
[0076]
After thermal annealing for gettering, the silicon film is patterned into an island shape to form an island-shaped semiconductor film 61. The island-like semiconductor film 61 is made up of n-type impurity regions 63 and 64 made up of a phosphorus-added region 56 containing nickel at a high concentration, and a region 65 made up of an undoped region 60 having a lowered nickel concentration. A TFT channel formation region and a low concentration impurity region may be formed in the region 65. (Fig. 5 (D))
[0077]
[Embodiment 3]
This embodiment will be described with reference to FIGS. This embodiment relates to a process for forming a CMOS circuit by forming an n-channel TFT and a p-channel TFT on the same substrate, and the source / drain region of each TFT is made a region for gettering a metal element. An example used is shown.
[0078]
A 300 nm-thick silicon oxide film is formed as a base film 101 on the substrate 100, and a crystalline silicon film 102 is formed according to the method of Embodiment 1 or 2. A mask 103 for selectively adding phosphorus is formed using a silicon oxide film having a thickness of 120 nm. Then, phosphorus is added to crystalline silicon by an ion doping apparatus to form a phosphorus-added region 102a. The region 102b where phosphorus is not added is defined as a non-added region 102b. The non-added region 102b includes a region that becomes a channel formation region of a TFT, and in the case of an n-channel TFT, a region that becomes a low-concentration impurity region is also included.
[0079]
Phosphorous concentration is carried out using phosphine diluted to 5% with hydrogen as a doping gas, an acceleration voltage of 10 kV, and a set dose of 1.5 × 10. ¹³ ions / cm ² And
[0080]
The crystalline silicon film 102 is patterned into an island shape to form island-like semiconductor films 105 and 106. The island-like semiconductor films 105 and 106 are formed of n-type impurity regions 107 to 110 each including a phosphorus-added region 102a containing nickel at a high concentration, and regions 105 and 106 each including a non-added region 102b whose nickel concentration is decreased. In the region 105 where the nickel concentration is lowered, a channel formation region and a low concentration impurity region of the n-channel TFT are formed. In the region 106, a channel formation region of a p-channel TFT and a p-type high-concentration impurity region to be a source / drain region are formed. (Fig. 6 (B))
[0081]
Next, SiH is performed by plasma CVD. _Four And N ₂ A gate insulating film 111 made of a silicon oxynitride film is formed using O as a source gas. A mask 112 for forming a low concentration impurity in the island-like semiconductor film 105 is formed using a resist. In order to form a low concentration impurity region, phosphine diluted to 5% with hydrogen is used as a doping gas, an acceleration voltage is 90 kV, and a set dose is 5.4 × 10. ¹¹ ions / cm ² And A source region 113, a drain region 114, a channel formation region 115, and low-concentration impurity regions 116 and 117 are formed in the island-like semiconductor film 105 in a self-aligning manner. (Fig. 6 (C))
[0082]
After the mask 112 is removed, a stacked film of a tantalum nitride film and a tantalum film is formed on the gate insulating film 111 by sputtering, and a gate wiring 119 is formed by patterning. The gate wiring 119 is common to the n-channel and p-channel TFTs, and is formed so as to partially overlap the n-channel low-concentration impurities 116 and 117. Further, before the gate wiring 119 is formed, the island-shaped semiconductor films 105 and 106 are optically annealed with an excimer laser. (Fig. 6 (D))
[0083]
A mask 120 for adding boron to the island-shaped semiconductor film 106 is formed using a resist. Diborane diluted to 5% with hydrogen is used as a doping gas. Acceleration voltage 10kV, set dose amount 7.8 × 10 ¹⁴ ions / cm ² And
[0084]
The p-type high concentration impurity regions 121 and 122 and the channel formation region 123 are formed in a self-aligned manner. The region 121 becomes a source region, and the region 122 becomes a drain region. Both phosphorus and boron are added to the regions 121a and 122a and function as gettering regions. Only boron is added to the regions 121b and 122b. (Fig. 7 (A))
[0085]
The mask 120 is removed and thermal annealing is performed at 600 ° C. for 8 hours. By thermal annealing, nickel in the channel formation region 115 and the low-concentration impurity regions 116 and 117 is diffused to the source region 113 and the drain region 114 as shown by arrows, and gettering is performed there. Further, nickel in the channel formation region 123 diffuses into the source region 121 and the drain region 122 and is gettered to the regions 121a and 122b. (Fig. 7 (B))
[0086]
An interlayer insulating film 124 made of a silicon oxide film is formed. After forming contact holes in the interlayer insulating film 124, a laminated film made of titanium / aluminum / titanium is formed as an electrode material and patterned to form wirings 125 to 127. Here, an n-channel TFT and a p-channel TFT are connected by a wiring 127 to form a CMOS circuit. (Fig. 7 (C))
[0087]
[Embodiment 4]
8 to 10, this embodiment relates to an active matrix liquid crystal display device, and describes a method for manufacturing an active matrix substrate in which a pixel portion and a driving circuit for driving TFTs in the pixel portion are formed on the same substrate. To do. However, in order to simplify the description, in the driver circuit, a manufacturing process of a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit and an n-channel TFT forming a sampling circuit will be described.
[0088]
A base film in which a silicon oxynitride film having a thickness of 50 nm and a silicon oxide film having a thickness of 150 nm are stacked is formed on the surface of the glass substrate 200. An amorphous silicon film 202 having a thickness of 50 nm is formed on the base film 201 by a plasma CVD method. After oxidizing the surface of the amorphous silicon film 202 with UV light, a nickel acetic acid solution is applied by a spinner and dried to form a film 203 containing nickel. (Fig. 8 (A))
[0089]
Thermal annealing is performed at 600 ° C. for 8 hours to crystallize the amorphous silicon film 202 to form a crystalline silicon film 204. By thermal annealing, nickel in the film 203 reacts with silicon in the amorphous silicon film 202 to form nickel silicide, while nickel diffuses toward the base film 201 to promote crystallization.
[0090]
A protective film 205 is formed over the crystalline silicon film 204. The protective film 205 is formed using a silicon nitride oxide film or a silicon oxide film having a thickness of 100 to 200 nm (preferably 130 to 170 nm). The protective film 205 is meaningful to prevent the crystalline silicon film 204 from being directly exposed to plasma during doping and to enable fine concentration control.
[0091]
A mask 206 made of a resist is formed on the protective film 205. Boron is selectively added through the protective film 205. Diborane (B ₂ H ₆ Was excited by plasma without mass separation, and boron was added. Boron is 1 × 10 ¹⁵ ~ 1x10 ¹⁸ atoms / cm ^Three Typically 5 × 10 ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three ). (FIG. 8C) This step is a step of adding an impurity imparting p-type conductivity to a semiconductor to a channel region in order to control the threshold voltage of the n-channel TFT. This process is called. (Fig. 8 (C))
[0092]
The mask 206 was removed, and a resist mask 208 was newly formed. Then, phosphorus is added to form n-type low concentration impurity regions 209 to 211. These low-concentration impurity regions 209 to 211 become LDD regions of the n-channel TFTs of the CMOS circuit and the sampling circuit. In an ion doping apparatus, phosphine diluted to 5% is added by plasma excitation. The doping condition is that the concentration of phosphorus in the low-concentration impurity regions 209 to 211 is 2 × 10. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three Typically 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three ). (Fig. 8 (D))
[0093]
The mask 207 and the protective film 205 are removed, and light annealing is performed with laser light. Pulsed excimer laser light is shaped into a line and irradiated. The laser annealing conditions are as follows: KrF gas is used as the excitation gas, the processing temperature is room temperature, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 300 mJ / cm. ² (Typically 150-250mJ / cm ² ). (Fig. 8 (E))
[0094]
The optical annealing is for activating the added phosphorus and boron and for recrystallizing the amorphous semiconductor film at the time of doping, so that nickel remaining in the crystalline silicon film 204 can be easily diffused. It is.
[0095]
Next, the crystalline silicon film 204 is patterned into an island shape to form island-shaped semiconductor films 212 to 215. The semiconductor films 212 and 213 constitute a CMOS circuit, the semiconductor film 214 constitutes an n-channel TFT of a sampling circuit, and the semiconductor film 215 constitutes an n-channel TFT of a pixel portion. (Fig. 8 (F))
[0096]
Next, a gate insulating film 216 is formed so as to cover the semiconductor films 212 to 215. As the gate insulating film 216, N is formed by plasma CVD. ₂ O and SiH _Four A silicon oxynitride film with a thickness of 115 nm is formed as a raw material. (Fig. 9 (A))
[0097]
A 50-nm-thick tungsten nitride (WN) film 217 and a 350-nm-thick tungsten film 218 are stacked over the gate insulating film 216 by sputtering. Although not shown, it is effective to form a silicon film with a thickness of about 2 to 20 nm under the tungsten nitride film 217. The silicon film can improve the adhesion of the tungsten nitride film and prevent oxidation.
[0098]
The tungsten nitride film 217 and the tungsten film 218 are etched together to form gate wirings 219 to 221 having a thickness of 400 nm. The gate wiring 219 formed in the CMOS circuit is formed so as to partially overlap the n-type low concentration impurity region 209 of the semiconductor film 213, and the TFT gate wiring 220 of the sampling circuit is connected to the n-type low concentration impurity regions 210 and 211. It forms so that it may overlap partially. (Figure 9 (C))
[0099]
Using the gate wirings 219 to 220 as masks, phosphorus is added to form n-type low concentration impurity regions 222 to 227 in a self-aligning manner. In the low-concentration impurity regions 222 to 227, the phosphorus concentration is 1/2 to 1/10 (typically 1/3 to 1/4) of the n-type low-concentration impurity regions 209 to 210. However, the concentration is 5 to 10 times higher than the boron concentration added in the channel doping step. This is because the regions 224 to 227 have n-type conductivity because boron is added in advance. Specifically, 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three , Typically 3x10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three And In this doping process, the island-like semiconductor film is formed on the island-like semiconductor film except for the portion hidden by the gate wiring. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three Phosphorus is added at a concentration of (Figure 9 (D))
[0100]
The gate insulating film 216 is etched in a self-aligning manner using the gate wirings 219 to 221 as a mask. Etching uses a dry etching method and the etching gas is CHF. _Three Gas was used. However, the etching gas is not necessarily limited to this. Thus, gate insulating films 228 to 230 were formed under the gate wiring. (Fig. 9 (E))
[0101]
By exposing the active layer in this way, the acceleration voltage can be lowered in the next impurity element addition step. As a result, the throughput is improved because the required dose is small. The gate insulating film may be left without etching, and the impurity region may be formed by through doping.
[0102]
Next, a resist mask 231 is formed, and phosphorus is added to form source / drain regions of the n-channel TFT. N-type high concentration impurity regions 233 to 241 are formed by ion doping using phosphine diluted with hydrogen. The doping conditions are an acceleration voltage of 10 kV and a set dose of 1.5 × 10 ¹³ ions / cm ² And
[0103]
The n-type high-concentration impurity region produced in this phosphorus doping process functions as a gettering region for gettering nickel contained in the channel formation region and the low-concentration impurity region of the TFT. (Fig. 9 (F))
[0104]
Next, the mask 231 is removed, and a new mask 242 is formed. Diborane diluted with hydrogen is plasma-excited by an ion doping apparatus, and boron is added to the semiconductor film. P-type high concentration impurity regions 243 and 244 are formed in the semiconductor film 212. Boron doping conditions include an acceleration voltage of 10 kV and a set dose of 7.8 × 10 ¹⁴ ions / cm ² And (Fig. 10 (A))
[0105]
After removing the mask 242, SiH is formed by plasma CVD. _Four , N ₂ O, NH _Three As a source gas, a 200 nm thick silicon nitride oxide film (nitrogen concentration of 25 to 50 atomic%) is formed to form a first interlayer insulating film 245. Then, thermal annealing is performed at 600 ° C. for 6 hours in a nitrogen atmosphere. Phosphorus and boron added to the semiconductor film of each TFT are activated, and nickel remaining in the channel formation region and low-concentration impurity region of each TFT contains phosphorus and boron at a high concentration as indicated by arrows. The p-type impurity regions 243a and 244a and the n-type impurity regions 236 to 241 containing phosphorus at a high concentration are diffused and captured. Furthermore, this thermal annealing activates phosphorus and boron added to the semiconductor film, and recovers crystallinity damaged by doping and recrystallization. (Fig. 10 (B))
[0106]
Further, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor film. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0107]
After the thermal annealing for activation and gettering is completed, a silicon oxide film having a thickness of 800 nm is formed on the first interlayer insulating film 245 by a plasma CVD method to form a second interlayer insulating film 246. Thus, a 1 μm-thick interlayer insulating film composed of a laminated film of the first interlayer insulating film (silicon nitride oxide film) 245 and the second interlayer insulating film (silicon oxide film) 246 is formed.
[0108]
Contact holes reaching the source region or drain region of each TFT are formed in the interlayer insulating films 245 and 246, and source wirings 248 to 251 and drain wirings 252 to 255 are formed. Although not shown, the drain wirings 252 and 253 are connected as the same wiring in order to form a CMOS circuit. These wirings are formed by a three-layer film in which a Ti film is formed by 100 nm, an aluminum film containing Ti of 300 nm, and a Ti film of 150 nm are continuously formed by sputtering.
[0109]
As the passivation film 256, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed with a thickness of 50 to 500 nm (typically 200 to 300 nm). A third interlayer insulating film 257 made of an organic resin is formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Note that organic resin films other than those described above, organic SiO compounds, and the like can also be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C.
[0110]
In the pixel portion, an aluminum film containing 1 wt% titanium is formed on the third interlayer insulating film 257 to a thickness of 125 nm and patterned to form a shielding film 258. In this specification, the term “shielding film” is used in the sense of shielding light and electromagnetic waves.
[0111]
It is possible to form not only the shielding film but also other connection wirings by the aluminum film containing titanium. For example, a connection wiring that connects the circuits in the control circuit can be formed. However, in that case, it is necessary to form a contact hole in the third interlayer insulating film in advance before forming the material for forming the shielding film or the connection wiring.
[0112]
Next, an aluminum oxide 259 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the shielding film 258 by anodic oxidation or plasma oxidation (in this embodiment, anodic oxidation). First, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration is prepared. This is a solution of 15% ammonium tartrate aqueous solution and ethylene glycol mixed at 2: 8, and ammonia water is added to this to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, the substrate on which the shielding film 258 is formed is immersed in the solution, and a constant direct current (several mA to several tens mA) is passed through the shielding film 258 as an anode. On the surface of the shielding film 258, an aluminum oxide 259 having a thickness of about 50 nm is formed. The film thickness of the shielding film 258 becomes 90 nm by anodic oxidation.
[0113]
Next, a contact hole reaching the drain wiring 255 is formed in the third interlayer insulating film 257 and the passivation film 256, and the pixel electrode 260 is formed. Note that the pixel electrodes 261 and 262 are pixel electrodes of different adjacent pixels. The pixel electrodes 260 to 262 may be made of a transparent conductive film when a transmissive liquid crystal display device is used, and a metal film when a reflective liquid crystal display device is used. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 110 nm by sputtering.
[0114]
At this time, the pixel electrode 260 and the shielding film 258 overlap with each other through the alumina 259 to form the storage capacitor 263. Note that the shielding film 258 is desirably set to a floating state (electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal input to the source wiring).
[0115]
Thus, an active matrix substrate having a drive circuit and a pixel circuit is completed on the same substrate. In FIG. 10C, a p-channel TFT 301 and n-channel TFTs 302 and 303 are formed in the driver circuit, and a pixel TFT 304 including an n-channel TFT is formed in the pixel portion.
[0116]
A channel formation region 311, a source region 312 and a drain region 313 made of a p-type high concentration impurity region are formed in the island-shaped semiconductor film of the p-channel TFT 301 in the driver circuit. The source / drain regions 312 and 313 include a region containing phosphorus and boron to be a gettering region. In this region, gettered nickel is 5 × 10 5. ¹⁸ atoms / cm ^Three Above (typically 1 × 10 ¹⁹ ~ 5x10 ²⁰ atoms / cm ^Three ) Present in concentration.
[0117]
The island-shaped semiconductor film of the n-channel TFT 302 in the driver circuit overlaps with the gate wiring through the gate insulating film on the channel formation region 314, the source region 315, the drain region 316, and the drain region side of the channel formation region) A region 317 (such a region is referred to as a Lov region, where ov is used for overlap) is formed.
[0118]
In the island-shaped semiconductor film of the n-channel TFT 303, a channel formation region 318, a source region 319, a drain region 320, and n-type low-concentration impurity regions 321 and 322 are formed on both sides of the channel formation region. The regions 321 and 322 are a region that overlaps the gate wiring through the gate insulating film (Lov region) and a region that does not overlap the gate wiring (in this specification, such a region is referred to as an Loff region. ).
[0119]
The island-shaped semiconductor film of the TFT 304 in the pixel portion includes channel formation regions 323 and 324, n-type high-concentration impurity regions 325 to 327, and n-type low-concentration impurities that are regions that do not overlap with the gate wiring (Loff region). Regions 328 to 331 are formed.
[0120]
In this embodiment, the structure of the TFT forming each circuit can be optimized according to the circuit specifications required by the pixel circuit and the control circuit, and the operation performance and reliability of the semiconductor device can be improved. Specifically, n-channel TFTs place high importance on high-speed operation or hot carrier countermeasures on the same substrate by changing the arrangement of n-type low-concentration impurity regions according to circuit specifications and using Lov regions or Loff regions. This makes it possible to manufacture TFTs and TFTs that emphasize low-off current operation.
[0121]
For example, in the case of an active matrix liquid crystal display device, this structure of the n-channel TFT 302 is suitable for a control circuit such as a shift register circuit, a frequency dividing circuit, a signal dividing circuit, a level shifter circuit, or a buffer circuit that places importance on high speed operation. . That is, by arranging the Lov region only on one side (drain region side) of the channel formation region, a structure in which the resistance component is reduced as much as possible and the hot carrier countermeasure is emphasized. This is because in the case of the above circuit group, the functions of the source region and the drain region are not changed and the direction in which carriers (electrons) move is constant. However, the Lov region can be formed so as to be bonded to both sides of the channel formation region as necessary.
[0122]
The structure of the n-channel TFT 303 is suitable for a sampling circuit (sample hold circuit) that places importance on both hot carrier countermeasures and low off-current operation. That is, the arrangement of the Lov region provides a countermeasure against hot carriers, and further the arrangement of the Loff region realizes a low off-current operation. In addition, since the functions of the source region and the drain region are inverted and the carrier moving direction is changed by 180 °, the sampling circuit must be structured so as to be symmetric with respect to the gate wiring. Depending on the characteristics required for the TFT, only the Lov region may be used.
[0123]
The structure of the n-channel TFT 304 in the pixel portion is suitable for a pixel circuit and a sampling circuit (sample hold circuit) that place importance on low off-current operation. That is, a low off-current operation is realized by arranging only the Loff region without arranging the Lov region that can increase the off-current value. Further, by using a low-concentration impurity region having a lower phosphorus concentration than the n-type low-concentration impurity region of the control circuit as the Loff region, the off-current value is thoroughly reduced even if the on-current value is somewhat reduced. It is possible.
[0124]
The length (width) of the Lov region 317 of the n-channel TFT 302 may be 0.5 to 3.0 μm, typically 1.0 to 1.5 μm, with respect to the channel length of 3 to 7 μm. Further, the length (width) of the Lov region of the n-channel TFT 303 is 0.5 to 3.0 μm, typically 1.0 to 1.5 μm, and the length (width) of the Loff region is 1.0 to 3 μm. 0.5 μm, typically 1.5 to 2.0 μm. In addition, the length (width) of the Loff regions 329 to 330 provided in the pixel TFT 304 may be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.
[0125]
Further, in the present embodiment, an alumina film having a high relative dielectric constant of 7 to 9 is used as the dielectric of the storage capacitor, thereby making it possible to reduce the area for forming the necessary capacitance. Furthermore, by using the shielding film formed on the pixel TFT as one electrode of the storage capacitor as in this embodiment, the aperture ratio of the image display unit of the active matrix liquid crystal display device can be improved.
[0126]
Note that the present invention is not necessarily limited to the structure of the storage capacitor shown in this embodiment. For example, the storage capacitor structure described in Japanese Patent Application Laid-Open No. 11-133463 and Japanese Patent Application No. 10-254097 by the applicant can be used.
[0127]
[Embodiment 5] In this embodiment, a process for manufacturing an active matrix liquid crystal panel from an active matrix substrate will be described.
[0128]
As shown in FIG. 11, an alignment film 401 is formed on an active matrix substrate manufactured according to the manufacturing process of Embodiment 4. In this embodiment, a polyimide film is used as the alignment film. Further, a counter electrode 403 and an alignment film 404 are formed over the counter substrate 402. Note that a color filter or a shielding film may be formed on the counter substrate as necessary.
[0129]
Next, the alignment film is rubbed so that the liquid crystal molecules are aligned with a certain pretilt angle. Then, the active matrix substrate on which the pixel circuit and the control circuit were formed and the counter substrate were bonded to each other through a sealing material, a spacer (both not shown) and the like by a known cell assembling process. Thereafter, liquid crystal 405 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal. Thus, the active matrix type liquid crystal display device shown in FIG. 11 is completed.
[0130]
Next, the configuration of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. Note that FIG. 12 is denoted by the same reference numeral in order to correspond to the cross-sectional structure diagrams of FIGS. The active matrix substrate includes a pixel circuit 601, a scanning (gate) signal control circuit 602, and an image (source) signal control circuit 603 formed on the glass substrate 101. A pixel TFT 304 of the pixel circuit is an n-channel TFT, and a control circuit provided in the periphery is configured based on a CMOS circuit. The scanning signal control circuit 602 and the image signal control circuit 603 are connected to the pixel circuit 601 through a gate wiring 124 and a source wiring 152, respectively. In addition, connection wirings 606 and 607 from the external input / output terminal 605 to which the FPC 604 is connected to the input / output terminal of the control circuit are provided.
[0131]
Embodiment 6 FIG. 13 shows an example of a circuit configuration of the active matrix substrate shown in Embodiment 4. The active matrix substrate of this embodiment includes an image signal control circuit 701, a scanning signal control circuit (A) 707, a scanning signal control circuit (B) 711, a precharge circuit 712, and a pixel circuit 706. In this specification, the control circuit is a generic name including the image signal processing circuit 701 and the scanning signal control circuit 707.
[0132]
The image signal control circuit 701 includes a shift register circuit 702, a level shifter circuit 703, a buffer circuit 704, and a sampling circuit 705. The scanning signal control circuit (A) 707 includes a shift register circuit 708, a level shifter circuit 709, and a buffer circuit 710. The scanning signal control circuit (B) 711 has a similar configuration.
[0133]
Here, the shift register circuits 702 and 708 have a driving voltage of 5 to 16 V (typically 10 V), and the n-channel TFT used in the CMOS circuit forming the circuit has the structure of the TFT 302 shown in the fourth embodiment. Is suitable.
[0134]
In addition, the level shifter circuits 703 and 709 and the buffer circuits 704 and 710 have a drive voltage as high as 14 to 16 V. Like the shift register circuit, a CMOS circuit including the n-channel TFT 302 described in Embodiment 4 is suitable. Yes. In addition, it is effective in improving the reliability of each circuit that the gate wiring has a multi-gate structure such as a double gate structure or a triple gate structure.
[0135]
The sampling circuit 705 has a driving voltage of 14 to 16 V. However, since the source region and the drain region are inverted and the off-current value needs to be reduced, the CMOS including the n-channel TFT 303 described in Embodiment 4 is used. A circuit is suitable. Note that only an n-channel TFT is shown in FIG. 10C, but when a sampling circuit is actually formed, an n-channel TFT and a p-channel TFT are combined.
[0136]
Further, since the pixel circuit 706 requires a driving voltage of 14 to 16 V and a lower off-current value than the sampling circuit 705, the pixel circuit 706 preferably has a structure in which the Lov region is not disposed, as illustrated in FIG. It is desirable to use the n-channel TFT 304 as the pixel TFT.
[0137]
Note that the structure of this embodiment mode can be easily realized by manufacturing a TFT in accordance with the manufacturing process shown in Embodiment Mode 1. Further, in the present embodiment, only the configuration of the pixel circuit and the control circuit is shown. However, according to the manufacturing process of the first embodiment, in addition, a signal dividing circuit, a frequency divider circuit, a D / A converter circuit, an operational amplifier circuit, γ It is also possible to form a correction circuit, and further a signal processing circuit (also referred to as a logic circuit) such as a memory circuit or a microprocessor circuit on the same substrate.
[0138]
As described above, the present invention provides a semiconductor device including at least a pixel circuit and a control circuit for controlling the pixel circuit on the same substrate, for example, a semiconductor including a signal processing circuit, a control circuit, and a pixel circuit on the same substrate. An apparatus can be realized.
[0139]
[Embodiment 7] Various liquid crystals can be used in addition to the TN liquid crystal in the liquid crystal display device manufactured by the above example. For example, 1998, SID, "Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability" by H. Furue et al., 1997, SID DIGEST, 841, "A Full -Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time "by T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 671-673," Thresholdless antiferroelectricity in liquid crystals and its application to The liquid crystal disclosed in "displays" by S. Inui et al. or US Pat. No. 5,945,569 can be used.
[0140]
A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal. Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a V-shaped electro-optic response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) is also found. ing.
[0141]
Here, FIG. 14 shows an example of the light transmittance characteristics of the thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optic response with respect to the applied voltage. The vertical axis of the graph shown in FIG. 14 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. The transmission axis of the polarizing plate on the incident side of the liquid crystal display device is set to be substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal that substantially coincides with the rubbing direction of the liquid crystal display device. . Further, the transmission axis of the output-side polarizing plate is set to be substantially perpendicular (crossed Nicols) to the transmission axis of the incident-side polarizing plate.
[0142]
As shown in FIG. 14, it can be seen that when such a thresholdless antiferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible.
[0143]
When such a low-voltage thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having an analog driver, the power supply voltage of the image signal sampling circuit is suppressed to about 5V to 8V, for example. Is possible. Therefore, the operating power supply voltage of the driver can be lowered, and low power consumption and high reliability of the liquid crystal display device can be realized.
[0144]
Further, even when such a low-voltage thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having a digital driver, the output voltage of the D / A conversion circuit can be lowered. The operating power supply voltage of the A conversion circuit can be lowered, and the operating power supply voltage of the driver can be lowered. Therefore, low power consumption and high reliability of the liquid crystal display device can be realized.
[0145]
Therefore, using such a thresholdless antiferroelectric mixed liquid crystal driven at a low voltage makes it possible to use a TFT (for example, 0 nm to 500 nm or 0 nm to 200 nm) having a relatively small LDD region (low concentration impurity region). It is also effective when used.
[0146]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. Further, the driving method of the liquid crystal display device may be line-sequential driving, so that the period of writing the gradation voltage to the pixel (pixel feed period) may be lengthened to compensate for the small storage capacity. .
[0147]
In addition, since low voltage drive is implement | achieved by using such a thresholdless antiferroelectric mixed liquid crystal, the low power consumption of a liquid crystal display device is implement | achieved.
[0148]
Any liquid crystal having electro-optical characteristics as shown in FIG. 14 can be used as the display medium of the liquid crystal display device of the present invention.
[0149]
[Embodiment 8] The method for manufacturing a TFT of Embodiment 4 can be applied to manufacture of an active matrix EL display. Examples thereof are shown in FIGS.
[0150]
In this embodiment, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described. 15A is a top view of the EL display device of the present invention, and FIG. 15B is a cross-sectional view thereof.
[0151]
In FIG. 15A, reference numeral 4001 denotes a substrate, 4002 denotes a pixel portion, 4003 denotes a source side driver circuit, and 4004 denotes a gate side driver circuit. Each driver circuit reaches an FPC (flexible printed circuit) 4006 through a wiring 4005. Connected to an external device.
[0152]
At this time, a first sealant 4101, a cover material 4102, a filler 4103, and a second sealant 4104 are provided so as to surround the pixel portion 4002, the source side driver circuit 4003, and the gate side driver circuit 4004.
[0153]
FIG. 15B corresponds to a cross-sectional view taken along line AA ′ of FIG. 15A. A driving TFT included in the source side driver circuit 4003 on the substrate 4001 (here, an n-channel type is used here). TFTs and p-channel TFTs are shown.) 4201 and a current control TFT (TFT for controlling current to the EL element) 4202 included in the pixel portion 4002 are formed.
[0154]
In the present embodiment, a TFT having the same structure as the p-channel TFT or n-channel TFT in FIG. 11 is used as the driving TFT 4201, and a TFT having the same structure as the p-channel TFT in FIG. It is done. Further, the pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the current control TFT 4202.
[0155]
An interlayer insulating film (planarization film) 4301 made of a resin material is formed on the driving TFT 4201 and the pixel TFT 4202, and a pixel electrode (anode) 4302 electrically connected to the drain of the pixel TFT 4202 is formed thereon. As the pixel electrode 4302, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.
[0156]
An insulating film 4303 is formed over the pixel electrode 4302, and an opening is formed in the insulating film 4303 over the pixel electrode 4302. In this opening, an EL (electroluminescence) layer 4304 is formed on the pixel electrode 4302. A known organic EL material or inorganic EL material can be used for the EL layer 4304. The organic EL material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0157]
As a method for forming the EL layer 4304, a known vapor deposition technique or coating technique may be used. The EL layer may have a stacked structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0158]
A conductive film containing an element belonging to Group 1 or 2 of the periodic table (typically, a conductive film in which an alkali metal element or an alkaline earth metal element is included in aluminum, copper, or silver) over the EL layer 4304 A cathode 4305 made of is formed. In addition, it is preferable to remove moisture and oxygen present at the interface between the cathode 4305 and the EL layer 4304 as much as possible. Therefore, it is necessary to devise such that the both are continuously formed in vacuum, or the EL layer 4304 is formed in a nitrogen or rare gas atmosphere, and the cathode 4305 is formed without being exposed to oxygen or moisture. In the present embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0159]
The cathode 4305 is electrically connected to the wiring 4005 in a region indicated by 4306. A wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305 and is electrically connected to the FPC 4006 through the anisotropic conductive film 4307.
[0160]
As described above, an EL element including the pixel electrode (anode) 4302, the EL layer 4304, and the cathode 4305 is formed. This EL element is surrounded by a first sealing material 4101 and a cover material 4102 bonded to the substrate 4001 by the first sealing material 4101, and is enclosed by a filler 4103.
[0161]
As the cover material 4102, a glass material, a metal material (typically stainless steel), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0162]
However, when the emission direction of light from the EL element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0163]
As the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) is used. Can be used. When a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen is provided in the filler 4103, deterioration of the EL element can be suppressed.
[0164]
Further, the filler 4103 may contain a spacer. At this time, if the spacer is formed of barium oxide, the spacer itself can be hygroscopic. In the case where a spacer is provided, it is also effective to provide a resin film on the cathode 4305 as a buffer layer that relieves pressure from the spacer.
[0165]
The wiring 4005 is electrically connected to the FPC 4006 through the anisotropic conductive film 4307. The wiring 4005 transmits a signal transmitted to the pixel portion 4002, the source side driver circuit 4003, and the gate side driver circuit 4004 to the FPC 4006, and is electrically connected to an external device by the FPC 4006.
[0166]
In this embodiment, the second sealing material 4104 is provided so as to cover the exposed portion of the first sealing material 4101 and a part of the FPC 4006, and the EL element is thoroughly shielded from the outside air. Thus, an EL display device having the cross-sectional structure of FIG.
[0167]
Here, a more detailed cross-sectional structure of the pixel portion is shown in FIG. 16, a top structure is shown in FIG. 17A, and a circuit diagram is shown in FIG. In FIG. 16, FIG. 17 (A), and FIG.
[0168]
In FIG. 16, a switching TFT 4402 provided over a substrate 4401 is formed using the n-channel TFT 304 in FIG. Therefore, the description of the n-channel TFT 304 may be referred to for the structure of the TFT 4402. A wiring indicated by 4403 is a gate wiring that electrically connects the gate electrodes 4404 a and 4404 b of the switching TFT 4402.
[0169]
In this embodiment, a double gate structure in which two channel formation regions are formed is used, but a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed may be used.
[0170]
Further, the drain wiring 4405 of the switching TFT 4402 is electrically connected to the gate electrode 4407 of the current control TFT 4406. Note that the current control TFT 4406 is formed using the p-channel TFT 301 of FIG. Therefore, the description of the structure may be referred to the description of the p-channel TFT 301. In the present embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.
[0171]
A first passivation film 4408 is provided on the switching TFT 4402 and the current control TFT 4406, and a planarizing film 4409 made of resin is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 4409. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0172]
Reference numeral 4410 denotes a pixel electrode (EL element anode) made of a transparent conductive film, which is electrically connected to the drain wiring 4411 of the current control TFT 4406. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.
[0173]
An EL layer 4411 is formed over the pixel electrode 4410. Although only one pixel is shown in FIG. 16, in the present embodiment, EL layers corresponding to R (red), G (green), and B (blue) colors are separately created. In this embodiment, the low molecular weight organic EL material is formed by a vapor deposition method. Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a tris-8-quinolinolato aluminum complex (Alq) having a thickness of 70 nm is formed thereon as a light emitting layer. _Three ) A laminated structure provided with a film. Alq _Three The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1.
[0174]
However, the above example is an example of an organic EL material that can be used as an EL layer, and is not necessarily limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in the present embodiment, an example in which a low molecular weight organic EL material is used as the EL layer is shown, but a high molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0175]
Next, a cathode 4412 made of a conductive film is provided over the EL layer 4411. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (magnesium and silver alloy film) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or Group 2 of the periodic table or a conductive film added with these elements may be used.
[0176]
When the cathode 4412 is formed, the EL element 4413 is completed. Note that the EL element 4413 here refers to a capacitor formed by a pixel electrode (anode) 4410, an EL layer 4411, and a cathode 4412.
[0177]
Next, the top surface structure of the pixel in this embodiment is described with reference to FIG. The source of the switching TFT 4402 is connected to the source wiring 4415, and the drain is connected to the drain wiring 4405. The drain wiring 4405 is electrically connected to the gate electrode 4407 of the current control TFT 4406. The source of the current control TFT 4406 is electrically connected to the current supply line 4416, and the drain is electrically connected to the drain wiring 4417. The drain wiring 4417 is electrically connected to a pixel electrode (anode) 4418 indicated by a dotted line.
[0178]
At this time, a storage capacitor is formed in the region indicated by 4419. The storage capacitor 4419 is formed between the semiconductor film 4420 electrically connected to the current supply line 4416, an insulating film (not shown) in the same layer as the gate insulating film, and the gate electrode 4407. Further, a capacitor formed by the gate electrode 4407, the same layer (not shown) as the first interlayer insulating film, and the current supply line 4416 can also be used as the storage capacitor.
[0179]
[Embodiment 9]
In this embodiment, an EL display device having a pixel structure different from that in Embodiment 8 will be described. FIG. 18 is used for the description. In addition, what is necessary is just to refer description of Embodiment 8 about the part to which the code | symbol same as FIG. 17 is attached | subjected.
[0180]
In FIG. 18, a TFT having the same structure as that of the n-channel TFT 302 in FIG. Needless to say, the gate electrode 4502 of the current control TFT 4501 is electrically connected to the drain wiring 4405 of the switching TFT 4402. Further, the drain wiring 4503 of the current control TFT 4501 is electrically connected to the pixel electrode 4504.
[0181]
In this embodiment, the pixel electrode 4504 made of a conductive film functions as a cathode of the EL element. Specifically, an alloy film of aluminum and lithium is used, but a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film added with these elements may be used.
[0182]
An EL layer 4505 is formed over the pixel electrode 4504. Although only one pixel is shown in FIG. 18, an EL layer corresponding to G (green) is formed by an evaporation method and a coating method (preferably a spin coating method) in this embodiment. Specifically, a 20 nm thick lithium fluoride (LiF) film is provided as an electron injection layer, and a 70 nm thick PPV (polyparaphenylene vinylene) film is provided thereon as a light emitting layer.
[0183]
Next, an anode 4506 made of a transparent conductive film is provided over the EL layer 4505. In the present embodiment, a conductive film made of a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide is used as the transparent conductive film.
[0184]
When the anode 4506 is formed, the EL element 4507 is completed. Note that the EL element 4507 here refers to a capacitor formed of a pixel electrode (cathode) 4504, an EL layer 4505, and an anode 4506.
[0185]
When the voltage applied to the EL element is a high voltage of 10 V or more, the current control TFT 4501 becomes prominent due to the hot carrier effect. In such a case, it is effective to use an n-channel TFT having the structure of the present invention as the current control TFT 4501.
[0186]
Further, the current control TFT 4501 of this embodiment forms a parasitic capacitance called a gate capacitance between the gate electrode 4502 and the LDD region 4509. By adjusting the gate capacitance, a function equivalent to that of the storage capacitor 4418 shown in FIGS. 17A and 17B can be provided. In particular, when the EL display device is operated by the digital driving method, the holding capacitor can be replaced with a gate capacitor because the capacitance of the holding capacitor is smaller than that when the EL display device is operated by the analog driving method.
[0187]
Note that when the voltage applied to the EL element is 10 V or less, preferably 5 V or less, the deterioration due to the hot carrier effect is not a serious problem. Therefore, an n-channel TFT having a structure in which the LDD region 4509 is omitted in FIG. It may be used.
[0188]
[Embodiment 10] In this embodiment, examples of a pixel structure that can be used for the pixel portion of the EL display device described in Embodiment 8 or Embodiment 9 are illustrated in FIGS. In this embodiment, 4601 is a source wiring of the switching TFT 4602, 4603 is a gate wiring of the switching TFT 4602, 4604 is a current control TFT, 4605 is a capacitor, 4606 and 4608 are current supply lines, and 4607 is an EL element. .
[0189]
FIG. 19A shows an example in which the current supply line 4606 is shared between two pixels. That is, there is a feature in that the two pixels are formed so as to be symmetrical with respect to the current supply line 4606. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0190]
FIG. 19B illustrates an example in which the current supply line 4608 is provided in parallel with the gate wiring 4603. In FIG. 19B, the current supply line 4608 and the gate wiring 4603 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, the current supply line 4608 and the gate wiring 4603 can share an exclusive area, so that the pixel portion can be further refined.
[0191]
In FIG. 19C, a current supply line 4608 is provided in parallel with the gate wiring 4603 similarly to the structure of FIG. 19B, and two pixels are symmetrical with respect to the current supply line 4608. It is characterized in that it is formed. It is also effective to provide the current supply line 4608 so as to overlap with any one of the gate wirings 4603. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0192]
[Embodiment Mode 11] In this embodiment mode, an example of a pixel structure of an EL display device in which the present invention is implemented is shown in FIGS. In this embodiment, 4701 is a source wiring of the switching TFT 4702, 4703 is a gate wiring of the switching TFT 4702, 4704 is a current control TFT, 4705 is a capacitor (can be omitted), 4706 is a current supply line, 4707. Is a power control TFT, 4709 is a power control gate wiring, and 4708 is an EL element. Refer to Japanese Patent Application No. 11-341272 for the operation of the power supply control TFT 4707.
[0193]
In this embodiment, the power control TFT 4707 is provided between the current control TFT 4704 and the EL element 4708. However, the current control TFT 4704 is provided between the power control TFT 4707 and the EL element 4708. Also good. The power supply control TFT 4707 preferably has the same structure as the current control TFT 4704 or is formed in series with the same active layer.
[0194]
FIG. 20A shows an example in which the current supply line 4706 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 4706. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0195]
FIG. 20B shows an example in which a current supply line 4710 is provided in parallel with the gate wiring 4703 and a power supply control gate wiring 4711 is provided in parallel with the source wiring 4701. In FIG. 20B, the current supply line 4710 and the gate wiring 4703 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, the current supply line 4710 and the gate wiring 4703 can share an exclusive area, so that the pixel portion can be further refined.
[0196]
[Embodiment 12] In this embodiment, an example of a pixel structure of an EL display device in which the present invention is implemented is shown in FIGS. In this embodiment, 4801 is a source wiring of the switching TFT 4802, 4803 is a gate wiring of the switching TFT 4802, 4804 is a current control TFT, 4805 is a capacitor (can be omitted), 4806 is a current supply line, 4807 Denotes an erasing TFT, 4808 denotes an erasing gate wiring, and 4809 denotes an EL element. For the operation of the erasing TFT 4807, refer to Japanese Patent Application No. 11-338786.
[0197]
The drain of the erasing TFT 4807 is connected to the gate of the current control TFT 4804 so that the gate voltage of the current control TFT 4804 can be forcibly changed. Note that the erasing TFT 4807 may be either an n-channel TFT or a p-channel TFT, but preferably has the same structure as the switching TFT 4802 so that the off-state current can be reduced.
[0198]
FIG. 21A illustrates an example in which the current supply line 4806 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 4806. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0199]
FIG. 21B shows an example in which a current supply line 4810 is provided in parallel with the gate wiring 4803 and an erasing gate wiring 4811 is provided in parallel with the source wiring 4801. In FIG. 21B, the current supply line 4810 and the gate wiring 4803 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, the current supply line 4810 and the gate wiring 4803 can share an exclusive area, so that the pixel portion can be further refined.
[0200]
[Embodiment 13] The EL display device of the present invention may have a structure in which any number of TFTs are provided in a pixel. For example, four to six or more TFTs may be provided. The present invention can be practiced without being limited to the pixel structure of an EL display device.
[0201]
[Embodiment 14] An active matrix display device manufactured by using the present invention, for example, all electronic devices in which the liquid crystal panel shown in Embodiment 5 or the organic EL display shown in Embodiments 8 to 15 is mounted as a display medium. The present invention can be applied to.
[0202]
Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones or electronic books). Etc.). Examples of these are shown in FIGS.
[0203]
FIG. 22A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display device 2003, and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.
[0204]
FIG. 22B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the voice input unit 2103, and other signal control circuits.
[0205]
FIG. 22C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.
[0206]
FIG. 22D illustrates a goggle type display which includes a main body 2301, a display device 2302, and an arm portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.
[0207]
FIG. 22E shows a player using a recording medium (hereinafter referred to as a recording medium) in which a program is recorded. The main body 2401, a display device 2402, a speaker unit 2403, a recording medium 2404, an operation switch 2405, an external input unit (illustrated). Not). This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 2402 and other signal control circuits.
[0208]
FIG. 22F illustrates a digital camera which includes a main body 2501, a display device 2502, an eyepiece unit 2503, an operation switch 2504, and an image receiving unit (not shown). The present invention can be applied to the display device 2502 and other signal control circuits.
[0209]
FIG. 23A illustrates a front projector, which includes a light source optical system, a display device 2601, and a screen 2602. The present invention can be applied to display devices and other signal control circuits.
[0210]
FIG. 23B shows a rear projector, which includes a main body 2701, a light source optical system and display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.
[0211]
Note that FIG. 23C is a diagram illustrating an example of the structure of the light source optical system and the display devices 2601 and 2702 in FIGS. 23A and 23B. The light source optical system and display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2804 to 2806, a dichroic mirror 2803, an optical system 2807, a display device 2808, a phase difference plate 2809, and a projection optical system 2810. The projection optical system 2810 is composed of a plurality of optical lenses provided with a projection lens. In this embodiment, an example of a three-plate type using three display devices 2808 is shown, but there is no particular limitation, and a single-plate type may be used, for example. In addition, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like in the optical path indicated by an arrow in FIG.
[0212]
FIG. 23D shows an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 23D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like in the light source optical system.
[0213]
FIG. 23 shows an example of a three-plate projector, but a single-plate projector may be used. In this case, color display may be performed by forming a color filter on the liquid crystal panel.
[0214]
【The invention's effect】
According to the present invention, since a semiconductor film having an amorphous portion is crystallized using a metal element, a film with extremely excellent crystallinity can be formed, so that a TFT with high electrolytic effect mobility can be manufactured. In addition, since the metal element used for crystallization is gettered, the reliability and stability of the TFT are excellent. In addition, since the region for gettering the metal element is included in the n-type or p-type impurity region functioning as a source or drain, the integration of the elements is facilitated. In addition, by defining the phosphorus and antimony concentration profiles in the gettering region, each crystal can be recrystallized effectively, leading to an improvement in yield.
[Brief description of the drawings]
FIG. 1 is a concentration distribution chart of a group 15 element in an n-type impurity region (gettering region) of the present invention.
FIG. 2 is a concentration distribution diagram of phosphorus and boron in the gettering region of the present invention.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.
FIG. 4 is a cross-sectional view showing a manufacturing process of a TFT of the present invention.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.
FIG. 6 is a cross-sectional view showing a manufacturing process of a TFT of the present invention.
7 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention. FIG.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.
FIG. 9 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.
FIG. 10 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.
FIG. 11 is a cross-sectional view of a liquid crystal panel of the present invention.
FIG. 12 is a schematic perspective view of a modularized liquid crystal panel.
FIG. 13 is a block diagram of an active matrix substrate.
FIG. 14 is a characteristic diagram of thresholdless antiferroelectric mixed liquid crystal.
15A and 15B are a top view and a cross-sectional view of an EL display device of the present invention.
FIG. 16 is a cross-sectional view of a pixel portion of an EL display device of the present invention.
FIG. 17 is a top view of a pixel portion of an EL display device of the present invention and a circuit diagram thereof.
FIG. 18 is a cross-sectional view of an EL display device of the present invention.
FIG. 19 is a circuit diagram of a pixel portion of an EL display device of the present invention.
FIG. 20 is a circuit diagram of a pixel portion of an EL display device of the present invention.
FIG. 21 is a circuit diagram of a pixel portion of an EL display device of the present invention.
FIG. 22 shows an application example of an electronic device.
FIG. 23 shows an application example to a projector.

Claims (1)

A method for manufacturing a semiconductor device having a thin film transistor,
Forming a base film,
Forming a semiconductor film on the base film;
Introducing a metal element that promotes crystallization of the semiconductor into the semiconductor film, and performing heat treatment to crystallize the semiconductor film,
Wherein the semiconductor film, after forming a mask in a region to be a channel formation region and the low concentration impurity regions of the thin film transistor, by doping the Group 15 element, the maximum value of the concentration of the group 15 element is 5 × 10 ¹⁹ atoms / cm ³ or more, and the impurity regions concentration of the group 15 element is 1 × ¹⁰ 20 atoms / cm ³ or less in the thickness direction, is formed below the base film with a thickness of 5nm or 20nm from the interface ,
By performing heat treatment on the semiconductor film, the metal element is gettered from the channel formation region to the impurity region, and the concentration of the metal element in the channel formation region is 5 × 10 ¹⁷ atoms / cm ³ or less and The method for manufacturing a semiconductor device, wherein the impurity region has a concentration of the metal element of 1 × 10 ¹⁸ atoms / cm ³ or more.

Images