JP4472082B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor film having a crystal structure and a method for manufacturing a semiconductor device manufactured using the semiconductor film. Note that in this specification, a semiconductor device includes an electro-optical device such as a liquid crystal display device or an EL display device using an electroluminescence (EL) material, and an electronic device including the electro-optical device as a component.
[0002]
[Prior art]
A thin film transistor (hereinafter referred to as TFT) can be manufactured using a semiconductor film formed over a substrate. A TFT can form various integrated circuits as an active element. In particular, as a switching element provided in a pixel portion of an active matrix type liquid crystal display device or as an element forming a drive circuit provided in the periphery of the pixel portion. Can be used.
[0003]
A TFT using an amorphous silicon film as a semiconductor film has a low process temperature and is easy to produce, but has a drawback of low electrical characteristics. Therefore, although there is a usage form as a switching element provided in each pixel, a driving circuit for the pixel portion cannot be formed. On the other hand, it is known that when a TFT is formed using a semiconductor film having a crystal structure (hereinafter referred to as a crystalline semiconductor film), electrical characteristics can be improved. A silicon film is typically used as the semiconductor film, but a silicon film having a crystal structure is also known as a polycrystalline silicon film, a polysilicon film, a microcrystalline silicon film, or the like. In the technical field of TFT, a crystalline silicon film obtained by crystallizing an amorphous silicon film with light or heat energy is used.
[0004]
However, the thermal crystallization method using thermal energy requires heat treatment at a temperature of 600 ° C. or higher, and the processing time is about 10 hours. Therefore, when mass-producing a product using TFT such as an active matrix type liquid crystal display device, there is a problem that the productivity is lowered. On the other hand, a laser crystallization method using excimer laser light or YAG laser light is known as a crystallization technique using light energy, but the electrical characteristics are inferior to TFTs manufactured by thermal crystallization. There is.
[0005]
In addition, a technique for forming a crystalline semiconductor film by a thermal crystallization method using a catalytic element is known. For example, the techniques disclosed in Japanese Patent Laid-Open Nos. 7-130652 and 8-78329 can be used. According to the thermal crystallization method using a catalytic element, a crystalline silicon film can be formed by introducing a catalytic element such as nickel into an amorphous silicon film and performing a heat treatment at 550 ° C. for 4 hours.
[0006]
[Problems to be solved by the invention]
It is obtained by forming a base film made of silicon oxide, silicon nitride, silicon oxynitride, etc. on a substrate such as glass and crystallizing the amorphous semiconductor film deposited thereon by thermal crystallization or laser crystallization. The crystalline semiconductor film is preferentially oriented to <111> in consideration of the magnitude relationship of the interfacial energy between the base film and the semiconductor film, and there are many crystal grains having random orientations in other directions. This is known from the analysis of electron diffraction. On the other hand, in the crystalline semiconductor film manufactured by the thermal crystallization method using a catalytic element such as nickel, most of the crystal grains are oriented in <110>. However, as described above, other orientations such as <111> are slightly mixed in consideration of the interfacial energy between the base film and the semiconductor film.
[0007]
In a crystalline semiconductor film composed of a plurality of crystal grains, if the orientation is low, a large number of dangling bonds are formed at the crystal grain boundaries, and the transport properties of carriers (electrons and holes) in the crystalline semiconductor film are degraded. That is, since carriers are scattered or trapped, a TFT having a high field effect mobility cannot be manufactured even when a TFT is manufactured using such a crystalline semiconductor film. Further, since crystal grain boundaries exist randomly, it becomes a factor of variation in electrical characteristics of individual TFTs.
[0008]
An object of the present invention is to provide means for solving such problems, and to enhance the orientation of a crystalline semiconductor film produced by using a thermal crystallization method or a laser crystallization method for an amorphous semiconductor film. For the purpose. It is another object of the present invention to improve TFT characteristics and reduce characteristic variations by using such a crystalline semiconductor film.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the configuration of the present invention includes a first step of forming a first insulating film on a substrate and a second step of forming an amorphous semiconductor film on the first insulating film. And a third step of injecting fluorine from the surface of the amorphous semiconductor film, and adding a catalytic element in the amorphous semiconductor film or in contact with the amorphous semiconductor film to promote crystallization of the amorphous semiconductor film A fourth step of performing a first heat treatment on the amorphous semiconductor film to form a crystalline semiconductor film, and further irradiating the crystalline semiconductor film with laser light to provide the crystal A sixth step for increasing the crystallinity of the crystalline semiconductor film may be added.
[0010]
According to another aspect of the invention, there is provided a first step of forming a first insulating film on a substrate, a second step of fluorinating the surface of the first insulating film, and a first step on the first insulating film. A third step of forming an amorphous semiconductor film, and a fourth step of adding a catalyst element in the amorphous semiconductor film or in contact with the amorphous semiconductor film to promote crystallization of the amorphous semiconductor film And a fifth step of performing a first heat treatment on the amorphous semiconductor film to form a crystalline semiconductor film, and further irradiating the crystalline semiconductor film with laser light to crystallize the crystalline semiconductor film. It is also effective to perform the sixth step for improving the property.
[0011]
According to another aspect of the invention, there is provided a first step of forming a first insulating film on a substrate, a second step of fluorinating the surface of the first insulating film, and a first step on the first insulating film. A third step of forming an amorphous semiconductor film from a reaction gas containing at least fluorine and hydrogen; and crystallization of the amorphous semiconductor film in or in contact with the amorphous semiconductor film A fourth step of adding a catalytic element to be formed, and a fifth step of heat-treating the amorphous semiconductor film to form a crystalline semiconductor film, and further irradiating the crystalline semiconductor film with laser light It is also possible to perform a sixth step for increasing the crystallinity of the crystalline semiconductor film.
[0012]
According to another aspect of the invention, there is provided a first step of forming a first insulating film on a substrate, a second step of fluorinating the surface of the first insulating film, and a first step on the first insulating film. A third step of forming an amorphous semiconductor film, and a fourth step of adding a catalytic element in the amorphous semiconductor film or in contact with the amorphous semiconductor film to promote crystallization of the amorphous semiconductor film; A fifth step of forming a crystalline semiconductor film by first heat-treating the amorphous semiconductor film, and a sixth step of forming a region to which phosphorus is added in a selected region of the crystalline semiconductor film Process,
And a seventh step of performing a second heat treatment after the sixth step.
[0013]
According to another aspect of the invention, there is provided a first step of forming a first insulating film on a substrate, a second step of fluorinating the surface of the first insulating film, and a first step on the first insulating film. A third step of forming an amorphous semiconductor film from a reaction gas containing at least fluorine and hydrogen; and crystallization of the amorphous semiconductor film in or in contact with the amorphous semiconductor film Phosphorus is added to a selected region of the crystalline semiconductor film, a fourth step of adding a catalytic element to be added, a fifth step of heat-treating the amorphous semiconductor film to form a crystalline semiconductor film, and It has a sixth step of forming a region and a seventh step of performing a second heat treatment after the sixth step.
[0014]
In the structure of the present invention, the step of fluorinating the surface of the first insulating film may be performed by exposing to a plasma containing fluorine atoms or fluorine radicals, or using silicon tetrafluoride or nitrogen trifluoride as the plasma. It may be done by exposing it to a tempered atmosphere.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
In FIG. 1A, an alkali-free glass substrate such as barium borosilicate glass or alumino borosilicate glass is used for the substrate 1001. For example, Corning # 7059 glass or # 1737 glass base can be preferably used. In addition to the quartz substrate, a ceramic substrate or a stainless steel substrate on which an insulating film such as a silicon oxide film or a silicon nitride film is formed can be used.
[0016]
An insulating surface containing silicon such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride (SiOxNy) film is formed on the surface of the substrate 1101 on the side where the semiconductor film is formed in order to prevent diffusion of impurities such as an alkali metal element from the substrate 1101. A film is formed. Such an insulating film is referred to as a base film in this specification.
[0017]
The base film 1102 may be formed of one layer of the above material or a stacked structure of two or more layers. In any case, it is formed to have a thickness of about 100 to 300 nm. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A first silicon oxynitride film 1102a made of O is formed to a thickness of 10 to 100 nm, and SiH _Four , N ₂ A base film 1102 is formed as a two-layer structure in which a second silicon oxynitride film 1102b formed from O is stacked to a thickness of 100 to 200 nm.
[0018]
The first silicon oxynitride film 1102a is formed by using a conventional parallel plate type plasma CVD method. An example of the production conditions is SiH _Four 10SCCM, NH _Three To 100 SCCM, N ₂ O was introduced into the reaction chamber as 20 SCCM, the substrate temperature was 325 ° C., the reaction pressure was 40 Pa, and the discharge power density was 0.41 W / cm. ² The discharge frequency is 60 MHz. On the other hand, an example of conditions for forming the second silicon oxynitride film 1102b is SiH _Four 4SCCM, N ₂ O was introduced into the reaction chamber as 400 SCCM, the substrate temperature was 400 ° C., the reaction pressure was 40 Pa, and the discharge power density was 0.41 W / cm. ² The discharge frequency is 60 MHz. These films can be formed continuously only by changing the substrate temperature and switching the reaction gas. The first silicon oxynitride film is formed so that the internal stress becomes a tensile stress with the substrate as the center. The second silicon oxynitride film is also given an internal stress in the same direction, but the stress is smaller than the first silicon oxynitride film in terms of absolute value.
[0019]
After the base film 1102 is formed, the surface treatment is performed. This is a surface treatment using a halogen element, and is intended to expose the surface of the base film 1102 in an atmosphere of fluorine or fluorine radicals and coat the surface with fluorine. In addition, chlorine, bromine, etc. can be used as the halogen element.
[0020]
Specifically, silicon tetrafluoride (SiF _Four ) Or nitrogen trifluoride (NF) _Three ) To form plasma and generate fluorine atoms or fluorine radicals. For example, a plasma CVD apparatus can be applied. As the plasma CVD apparatus, any type of apparatus such as a capacitively coupled type or an inductively coupled type, an ECR (electron cycloton resonance) plasma CVD apparatus, or a microwave CVD apparatus may be applied. In particular, since ECR plasma and microwave plasma have high gas decomposition efficiency, fluorine radicals can be generated efficiently.
[0021]
In the example of FIG. 1A, since the first silicon oxynitride film 1102a and the second silicon oxynitride film 1102b are formed as the base film 1102, in this case, the surface of the second silicon oxynitride film Is surface treated with fluorine. Since the electronegativity of fluorine is larger than that of oxygen on the outermost surface of the second silicon oxynitride film, it can be substituted with oxygen to terminate dangling bonds on the surface with fluorine. Such an effect is not limited to the silicon oxynitride film, but can be similarly realized by using a silicon oxide film or a silicon nitride film.
[0022]
Then, as shown in FIG. 1B, a semiconductor film 1103 having an amorphous structure is formed with a thickness of 25 to 100 nm. As typical examples of the semiconductor film having an amorphous structure, an amorphous silicon (a-Si) film, an amorphous silicon-germanium (a-SiGe) film, an amorphous silicon carbide (a-SiC) film, A crystalline silicon tin (a-SiSn) film or the like can be applied. These amorphous semiconductor films are preferably formed so as to contain about 0.1 to 40 atomic% of hydrogen. These semiconductor films having an amorphous structure are formed by a plasma CVD method, a sputtering method, a low pressure CVD method, or the like. For example, SiH by plasma CVD method _Four Or SiH _Four And H ₂ An amorphous silicon film prepared from the above is formed with a thickness of 55 nm. SiH _Four Instead of Si ₂ H ₆ May be used.
[0023]
Then, a layer 1104 containing the catalyst element is formed by a spin coating method in which an aqueous solution containing 10 ppm of the catalyst element in terms of weight is applied by rotating the substrate with a spinner. Catalyst elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold (Au). The catalyst element-containing layer 1104 is formed by forming the catalyst element layer to a thickness of 1 to 5 nm by a printing method, a spray method, a bar coater method, a sputtering method or a vacuum deposition method in addition to the spin coating method. Also good.
[0024]
In the crystallization step shown in FIG. 1C, first, heat treatment is performed at 400 to 500 ° C. for about 1 hour, so that the amount of hydrogen contained in the amorphous silicon film is 5 atom% or less. When the amount of hydrogen contained in the amorphous silicon film is this value from the beginning after the film formation, this heat treatment is not necessarily required. Then, thermal crystallization is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours using a furnace annealing furnace. Preferably, heat treatment is performed at 550 ° C. for 4 hours. Thus, a crystalline semiconductor film 1105 made of a crystalline silicon film can be obtained.
[0025]
However, when the crystalline semiconductor film 1105 manufactured by this thermal crystallization is observed with an optical microscope, it may be observed that an amorphous region remains locally. In such a case, the Raman spectroscopy is similarly 480 cm. ^-1 An amorphous component having a broad peak is observed. The laser crystallization method is suitable for the purpose of crystallizing the remaining amorphous region.
[0026]
Laser light sources used in the laser crystallization method include excimer laser, YAG laser, YVO _Four Laser, YAlO _Three A laser, a YLF laser, or the like can be used. An excimer laser can radiate light having a wavelength of 400 nm or less with high output, and thus can be suitably used for crystallization of a semiconductor film. On the other hand, YAG laser, YVO _Four Laser, YAlO _Three A solid laser such as a laser or a YLF laser uses the second harmonic (532 nm), the third harmonic (355 nm), and the fourth harmonic (266 nm). Due to the penetration depth of light, the second harmonic (532 nm) is used from the surface and inside of the semiconductor film, and the third harmonic (355 nm) and the fourth harmonic (266 nm) are used in the same manner as the excimer laser. Crystallization can be performed by heating from the surface of the semiconductor film.
[0027]
FIG. 1D shows such a state. For example, an Nd: YAG laser is used, its pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is 100 to 500 mJ / cm. ² (Typically 100-400mJ / cm ² ), The linear laser beam 1107 formed by an optical system including a cylindrical lens is scanned in a direction perpendicular to the longitudinal direction (or the substrate is relatively moved). The line width of the linear laser beam 1107 is 100 to 1000 μm, for example, 400 μm. In this way, by using the thermal crystallization method and the laser crystallization method in combination, the crystalline semiconductor film 1108 with high crystallinity can be formed.
[0028]
A crystalline semiconductor film manufactured by a thermal crystallization method or a laser crystallization method has low interface energy between silicon oxide or silicon oxynitride and silicon formed as a base film. Electron diffraction analysis shows that when crystallizing a crystalline silicon film by thermal crystallization or laser crystallization, <111> is preferentially oriented and there are many other grains with random orientations. Known from. On the other hand, a crystalline silicon film manufactured by a thermal crystallization method using a catalytic element such as nickel has a structure in which a plurality of needle-like or rod-like crystals are aggregated when viewed microscopically. However, it is expected that the continuity of adjacent crystal grains is high and almost no dangling bonds are formed. Most of the crystal grains are oriented to <110>. One reason is that the crystal growth process using a catalyst element such as nickel is considered to involve the silicide of the catalyst element, and the semiconductor film is as thin as 25 to 100 nm. Among the initial nuclei, those whose (111) plane is substantially perpendicular to the substrate surface preferentially grow, so it is considered that the <110> orientation is substantially increased. However, as described above, since the interface energy between silicon oxide and silicon is low, other plane orientations included in the <111> crystal zone can be taken. Accordingly, other orientations are mixed slightly.
[0029]
However, in the thermal crystallization method using a catalytic element, the surface of the silicon oxide film, silicon nitride film, silicon oxynitride film, etc. formed as the base film is terminated with fluorine, so that the influence of the interface with the base is affected. Can be reduced and the effect can be substantially ignored. As a result, the crystal orientation is influenced only by the surface energy, but the <110> orientation is enhanced in crystal growth using a catalytic element. Such an effect can be realized by a normal thermal crystallization method, a laser crystallization method, or the like, but can be obtained more significantly by a thermal crystallization method using a catalytic element.
[0030]
A TFT can be manufactured using the crystalline semiconductor film 1108 manufactured as described above. The crystalline semiconductor film 1108 can be preferably used for forming a channel formation region, a source region, a drain region, an LDD region, and the like. If necessary, the island-shaped semiconductor layer 1109 may be formed by etching the crystalline semiconductor film 1108 into a predetermined shape as shown in FIG. In any case, by using a crystalline semiconductor film with uniform orientation by using the present invention, it is possible to manufacture a TFT with less electrical characteristics and variation.
[0031]
[Embodiment 2]
In the crystalline semiconductor film manufactured in Embodiment 1, the catalyst element used in the thermal crystallization is 1 × 10. ¹⁷ ~ 1x10 ²⁰ atoms / cm ^Three It remains in the film at a certain concentration. Of course, an element such as a TFT can be manufactured and operated even in this state, but it is more preferable to remove the catalytic element from the film. In this embodiment, in the thermal crystallization method using the catalyst element shown in Embodiment 1, the catalyst element is crystallized after the crystalline semiconductor film is formed. quality An example of performing a step of removing from a semiconductor film is shown. As the method, techniques described in JP-A-10-247735, JP-A-10-135468, JP-A-10-135469, etc. can be used.
[0032]
The technique described in Japanese Patent Laid-Open No. 10-247735 is a technique for removing a catalyst element used for crystallization of an amorphous semiconductor film by using a gettering action of phosphorus after crystallization. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film is reduced to 1 × 10. ¹⁷ atoms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atoms / cm ^Three It can be reduced to.
[0033]
First, the steps shown in FIGS. 1A to 1D are performed in the same manner as in Embodiment 1 to form the crystalline semiconductor film 1108. The subsequent steps will be described with reference to FIG. Then, a mask insulating film (eg, silicon oxide film) 1110 is formed on the surface of the crystalline semiconductor film 1108 to a thickness of 50 to 200 nm, eg, 150 nm. Then, an opening 1111 is formed in the insulating film 1110 by etching treatment to expose the surface of the crystalline semiconductor film 1108 in that portion.
[0034]
Then, a phosphorus doping step is performed by an ion doping method or the like, so that a region 1112 to which phosphorus is added is formed in the crystalline semiconductor film 1108. The phosphorus concentration in this region is not particularly limited, but 1 × 10 ¹⁸ ~ 1x10 ²⁰ atoms / cm ^Three It is good to make it about.
[0035]
In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, the region 1112 to which phosphorus is added to the crystalline semiconductor film 1108 functions as a gettering site, The catalytic element remaining in the crystalline semiconductor film 1108 can be segregated in the region 1112 to which phosphorus is added.
[0036]
Then, the mask insulating film 1110 is removed by etching. Further, by removing the region 1112 to which phosphorus is added by etching, the concentration of the catalytic element used in the thermal crystallization method is 1 × 10 5. ¹⁷ atoms / cm ^Three The crystalline semiconductor film 1113 which has been reduced to the following can be formed.
[0037]
[Embodiment 3]
In Embodiment 1, a semiconductor film 1103 having an amorphous structure is formed by SiH using a plasma CVD method. _Four Or SiH _Four And H ₂ An example of manufacturing from is shown. In this embodiment mode, a case of using another gas is described.
[0038]
A feature of the manufacturing method of this embodiment is that the semiconductor film 1103 having an amorphous structure is formed using a reaction gas containing a halogen element and hydrogen. Specifically, for example, when an amorphous silicon film is formed as a semiconductor film having an amorphous structure, a halogen element and hydrogen are mixed. Fluorine is particularly preferably used as the halogen element, and fluorine has an action of etching silicon, so that a weakly bonded portion can be preferentially etched in the film deposition process. Further, the concentration of fluorine remaining in the film can be reduced by supplying hydrogen. A dense amorphous silicon film with few voids and voids can be produced by utilizing the action of fluorine and hydrogen. Such effects include amorphous silicon / germanium (a-SiGe) film, amorphous silicon carbide (a-SiC) film, amorphous silicon / tin (a-SiSn) film in addition to amorphous silicon film. It can also be applied.
[0039]
As a method for supplying fluorine and hydrogen, when an amorphous silicon film is formed as an amorphous semiconductor film, silicon tetrafluoride (SiF) is used as a reactive gas. _Four ) And hydrogen (H ₂ ) Or SiF _Four And SiH _Four Or SiF _Four And SiH _Four And H ₂ Can be selected. SiF _Four Instead of trifluorosilane (SiHF _Three ), Difluorosilane (SiH) ₂ F ₂ ), Monofluorosilane (SiH) _Three F) can also be applied. SiH _Four And F ₂ May be reacted directly. Further, when an amorphous silicon / germanium film is formed, germane (GeH _Four ) And germanium tetrafluoride (GeF) _Four ) In the case of producing amorphous silicon carbide, methane (CH _Four ) And tetrafluoromethane (CF _Four ), Etc., when forming an amorphous silicon / tin film, tin hydride (SnH) _Four ) May be added as appropriate.
[0040]
The semiconductor film 1103 having an amorphous structure is formed with a thickness of 25 to 100 nm. In the initial stage of film deposition, the surface of the base film 1102 can be fluorinated by the effect of fluorine.
[0041]
As described above, the semiconductor film 1103 having an amorphous structure manufactured using a reaction gas containing fluorine and hydrogen has a hydrogen content of 0.1 to 20 atomic% in the film, depending on the substrate temperature at the time of film formation. The film is formed so as to contain 0.1 to 10 atomic% of fluorine. Fluorine and hydrogen remaining in the film are released from the film in the subsequent thermal crystallization process, and the concentration remaining in the film is further reduced, but the dense amorphous semiconductor film and the outermost surface are made of fluorine. The <110> orientation can be further enhanced by the interaction with the terminated base film.
[0042]
[Embodiment 4]
As a method for fluorinating the surface of the base film or the interface between the base film and the amorphous semiconductor film, the base film 1102 is formed on the substrate 1101 as shown in FIG. 1, and the amorphous semiconductor film 1103 is formed as it is. Later, fluorine may be implanted from the surface of the amorphous semiconductor film 1103. As the technique, an ion doping method or an ion implantation method is used.
[0043]
In the ion doping method, SiF is used as the ion source. _Four Or helium (He) diluted F ₂ Is ionized and implanted from the surface of the amorphous semiconductor film. The acceleration voltage is set high so that a peak of the concentration distribution of fluorine implanted exists at or near the interface between the amorphous semiconductor film 1103 and the base film 1102. In that case, the peak concentration is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three To be. Since mass separation is not performed by the ion doping method, elements other than fluorine are implanted at the same time, but this is suitable for processing a large area substrate such as a liquid crystal display device. Further, fluorine can be implanted at a similar concentration into the interface between the amorphous semiconductor film 1103 and the base film 1102 or in the vicinity thereof by an ion implantation method.
[0044]
In this way, the same effect can be obtained by crystallizing a layer containing a catalytic element in contact with the amorphous semiconductor film 1103 in the same manner as in Embodiment Mode 1 in a state where fluorine is implanted.
[0045]
【Example】
[Example 1]
In this embodiment, an example of a method for manufacturing a TFT using a crystallized semiconductor film manufactured according to the present invention will be described. 3 to 5 show an example of a display device. A method for simultaneously manufacturing a pixel TFT and a storage capacitor of a pixel portion and a TFT of a driver circuit provided in the periphery of the display region will be described with reference to FIGS. It demonstrates in detail according to a process.
[0046]
In FIG. 3A, a glass substrate such as barium borosilicate glass or alumino borosilicate glass typified by Corning # 7059 glass or # 1737 glass is used for the substrate 101. The glass substrate may be preheated at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, in order to prevent impurity diffusion from the substrate 101, a base film 102 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 101 where the TFT is formed. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film 102a made of O is 10 to 200 nm (preferably 50 to 100 nm), similarly SiH. _Four , N ₂ A silicon oxynitride silicon film 102b formed from O is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm).
[0047]
After that, the surface treatment of the silicon oxynitride silicon film 102b formed as the base film is performed to fluorinate the surface. For example, using a plasma CVD apparatus in which the base film 102 is formed, SiF _Four Gas or NF _Three A gas is introduced, high frequency power is applied, and the gas is turned into plasma to generate fluorine atoms or fluorine radicals. By exposing the surface of the silicon oxynitride silicon film 102b to the plasma thus formed, fluorine or fluorine radicals are supplied to the surface, and the electronegativity of fluorine is higher than that of oxygen. Hands can be terminated.
[0048]
Then, according to Embodiment 1 or 3, an amorphous semiconductor film is formed on the base film 102 and crystallized to form a crystalline semiconductor film. As shown in FIG. 1A, island-shaped semiconductor films 104 to 108 are formed from the crystalline semiconductor film. In this embodiment, a crystalline silicon film is formed from an amorphous silicon film having a thickness of 55 nm formed by plasma CVD. The amorphous silicon film is SiH _Four Or SiH _Four And H ₂ Is used as a reactive gas and formed by plasma CVD. Alternatively, SiF as the reaction gas _Four And water H ₂ Or SiF _Four And SiH _Four Or SiF _Four And SiH _Four And H ₂ It is also possible to select a combination. In addition, the formation of the base film 102, the surface treatment, and the amorphous semiconductor film can be continuously performed using a plasma CVD apparatus. Furthermore, this continuous treatment can be carried out in the same reaction chamber. In this way, by continuously performing the treatment without being exposed to the air atmosphere, it is possible to prevent the surface of the silicon oxynitride silicon film 102b from being contaminated. Can be reduced.
[0049]
After the island-like semiconductor film is formed, a mask layer 194 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by plasma CVD or sputtering.
[0050]
In this state, an impurity element imparting p-type is added to the island-like semiconductor film for the purpose of controlling the threshold voltage (Vth) of the TFT. ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three You may add to the whole surface of an island-like semiconductor film with a density | concentration of a grade. As an impurity element imparting p-type to a semiconductor, elements of Group 13 of the periodic table such as boron (B), aluminum (Al), and gallium (Ga) are known. As the method, an ion implantation method or an ion doping method can be used, but an ion doping method is suitable for processing a large-area substrate. In the ion doping method, diborane (B ₂ H ₆ ) As a source gas and boron (B) is added. Such implantation of the impurity element is not always necessary and may be omitted. However, this is a technique that is particularly suitable for keeping the threshold voltage of the n-channel TFT within a predetermined range.
[0051]
Next, an impurity element imparting n-type conductivity is selectively added to the island-shaped semiconductor films 105 and 107 in order to form an LDD region of the n-channel TFT of the driver circuit. Resist masks 195a to 195e are formed in advance. As the impurity element imparting n-type conductivity, phosphorus (P) or arsenic (As) may be used. Here, phosphorous (PH) is added to add phosphorus (P). _Three The ion doping method using) is applied. The formed impurity regions are low-concentration n-type impurity regions 196 and 197, and this phosphorus (P) concentration is 2 × 10. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three It may be in the range. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 196 and 197 formed here is (n ^- ). The impurity region 198 is a semiconductor film for forming a storage capacitor of the pixel portion, and phosphorus (P) is added to this region at the same concentration (FIG. 3B).
[0052]
Thereafter, a treatment for activating the added impurity element is performed. The activation process is performed by the laser annealing method described in the seventh embodiment. An example of the conditions is a laser pulse oscillation frequency of 1 kHz and a laser energy density of 100 to 300 mJ / cm. ² (Typically 150-250mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear beam at this time is 80 to 99% (preferably 95 to 99%). Laser oscillators used for laser annealing include gas laser excimer laser, solid laser YAG laser, YVO _Four Laser, YAlO _Three A laser, a YLF laser, or the like can be used. In the case of a solid-state laser such as the YAG laser, the second harmonic (532 nm) and the third harmonic (355 nm) can be used in addition to the fundamental wave (1064 nm).
[0053]
The gate insulating film 109 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. For example, it is preferable to form a silicon oxynitride film with a thickness of 120 nm. SiH _Four And N ₂ O to O ₂ A silicon oxynitride film manufactured by adding N is a preferable material for this application because the fixed charge density in the film is reduced. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0054]
Then, as shown in FIG. 3E, a heat resistant conductive layer for forming a gate electrode is formed over the gate insulating film 109. Although the heat-resistant conductive layer may be formed as a single layer, it may have a laminated structure including a plurality of layers such as two layers or three layers as necessary. The conductive layer 111 is formed using such a heat-resistant conductive material. The conductive layer 111 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined (typically May be formed of a Mo—W alloy film or a Mo—Ta alloy film. Under the conductive layer 111 made of such a material, nitrides such as tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, molybdenum nitride (MoN), tungsten silicide, titanium silicide, molybdenum silicide A silicide such as the above may be formed. It is preferable to reduce the concentration of impurities contained in the conductive layer 111 in order to reduce the resistance. In particular, the oxygen concentration is preferably 30 ppm or less. For example, tungsten (W) can realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.
[0055]
The conductive layer 111 is formed to a thickness of 200 to 400 nm (preferably 250 to 350 nm). For example, in order to form the conductive layer 111 with W, an argon (Ar) gas is introduced into a thickness of 250 nm by sputtering using W as a target. As another method, W film is tungsten hexafluoride (WF ₆ Can also be formed by a thermal CVD method. In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. Therefore, in the case of sputtering, the resistivity is obtained by using a W target with a purity of 99.9999% and forming a W film with sufficient consideration so that impurities are not mixed in the gas phase during film formation. 9 to 20 μΩcm can be realized (FIG. 3A).
[0056]
Next, resist masks 112 to 117 are formed using a photolithography technique, and the conductive layer 111 is etched to form gate electrodes 118 to 122 and a capacitor wiring 123 (FIG. 4A).
[0057]
A method for etching the conductive layer 111 may be selected as appropriate by the practitioner. However, in the case where the conductive layer 111 is formed of a material containing W as a main component as described above, the etching is performed at high speed and with high accuracy. It is desirable to apply a dry etching method using high-density plasma. As one method for obtaining high-density plasma, an inductively coupled plasma (ICP) etching apparatus may be used. The etching method of W using an ICP etching apparatus uses CF as an etching gas. _Four And Cl ₂ These gases are introduced into the reaction chamber, the pressure is set to 0.5 to 1.5 Pa (preferably 1 Pa), and 200 to 1000 W of high frequency (13.56 MHz) power is applied to the inductive coupling portion. At this time, high-frequency power of 20 W is applied to the stage on which the substrate is placed, and the negative ions are charged by self-bias, whereby positive ions are accelerated and anisotropic etching can be performed. By using an ICP etching apparatus, a hard metal film such as W can obtain an etching rate of 2 to 5 nm / second. Further, in order to perform etching without leaving a residue, overetching is preferably performed by increasing the etching time at a rate of about 10 to 20%. However, it is necessary to pay attention to the etching selectivity with the base at this time. For example, since the selection ratio of the silicon oxynitride film (gate insulating film 109) to the W film is 2.5 to 3, the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by such over-etching treatment. Being substantially thinner.
[0058]
Then, in order to form an LDD region in the n-channel TFT of the pixel TFT, an impurity element addition step (n ^- Doping step) is performed. An impurity element imparting n-type in a self-aligning manner is added by ion doping using the gate electrodes 118 to 122 as a mask. The concentration of phosphorus (P) added as an impurity element imparting n-type is 1 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three Add in the concentration range of. In this manner, low-concentration n-type impurity regions 124 to 129 are formed in the island-shaped semiconductor film as shown in FIG.
[0059]
Next, a high-concentration n-type impurity region that functions as a source region or a drain region is formed for the n-channel TFT (n ⁺ Doping process). First, resist masks 130 to 134 are formed, and an n-type impurity element is added to form high-concentration n-type impurity regions 135 to 140. Phosphorus (P) is used for the impurity element imparting n-type, and its concentration is 1 × 10. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three The phosphine (PH _Three (FIG. 4C).
[0060]
Then, high-concentration p-type impurity regions 144 and 145 serving as a source region and a drain region are formed in the island-like semiconductor films 104 and 106 forming the p-channel TFT. Here, an impurity element imparting p-type is added using the gate electrodes 118 and 120 as a mask, and a high-concentration p-type impurity region is formed in a self-aligning manner. At this time, resist masks 141 to 143 are formed to cover the entire surface of the island-shaped semiconductor films 105, 107, and 108 forming the n-channel TFT. The high-concentration p-type impurity regions 144 and 145 are diborane (B ₂ H ₆ ) Using an ion doping method. The boron (B) concentration in this region is 3 × 10 ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (FIG. 4D).
[0061]
The high-concentration p-type impurity regions 144 and 145 are doped with phosphorus (P) in the previous step, and the high-concentration p-type impurity regions 144a and 145a are 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three 1 × 10 in the high-concentration p-type impurity regions 144b and 145b. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three However, there is no problem in functioning as a source region and a drain region of a p-channel TFT by increasing the concentration of boron (B) added in this step from 1.5 to 3 times. Does not occur.
[0062]
After that, as shown in FIG. 5A, a protective insulating film 146 is formed over the gate electrode and the gate insulating film. The protective insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film including a combination thereof. In any case, the protective insulating film 146 is formed from an inorganic insulating material. The thickness of the protective insulating film 146 is 100 to 200 nm. When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² It is formed by discharging with. When using a silicon oxynitride film, SiH is formed by plasma CVD. _Four , N ₂ O, NH _Three Silicon oxynitride film manufactured from SiH or SiH _Four , N ₂ A silicon oxynitride film formed from O may be used. The production conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm. ² Can be formed. SiH _Four , N ₂ O, H ₂ Alternatively, a silicon oxynitride silicon film manufactured from the above may be used. Similarly, the silicon nitride film is made of SiH by plasma CVD. _Four , NH _Three It is possible to make from.
[0063]
Thereafter, a step of activating the impurity element imparting n-type or p-type added at each concentration is performed. This step can be performed by a thermal annealing method using a furnace annealing furnace, but may be activated by the heat treatment method using laser light described in the seventh embodiment. The heat treatment conditions in this case are the same as those described above. On the other hand, when the thermal annealing method is used, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. Heat treatment was performed at 550 ° C. for 4 hours. In the case where a plastic substrate having a low heat resistant temperature is used for the substrate 101, it is preferable to apply the heat treatment method using laser light of the present invention (FIG. 5B).
[0064]
After the heat treatment, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor film. This process is performed on the island-like semiconductor film 10 by thermally excited hydrogen. ¹⁶ -10 ¹⁸ /cm ^Three This is a step of terminating the dangling bond. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0065]
Then, an interlayer insulating film 147 made of an organic insulating material is formed with an average film thickness of 1.0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, when using a type of polyimide that is thermally polymerized after being applied to the substrate, it is formed by baking at 300 ° C. in a clean oven. When acrylic is used, a two-component type is used, and after mixing the main material and the curing agent, applying the entire surface of the substrate using a spinner, preheating at 80 ° C. for 60 seconds with a hot plate. It can be formed by baking at 250 ° C. for 60 minutes in a clean oven.
[0066]
Thus, the surface can be satisfactorily flattened by forming the interlayer insulating film with an organic insulating material. In addition, since the organic resin material generally has a low dielectric constant, parasitic capacitance can be reduced. However, it is hygroscopic and is not suitable as a protective film, and thus needs to be used in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the protective insulating film 146 as in this embodiment.
[0067]
Thereafter, a resist mask having a predetermined pattern is formed, and contact holes reaching the source region or the drain region formed in each island-shaped semiconductor film are formed. Contact holes are formed by dry etching. In this case, CF is used as an etching gas. _Four , O ₂ First, the interlayer insulating film made of an organic resin material is etched using a mixed gas of He, and then the etching gas is changed to CF. _Four , O ₂ The protective insulating film 146 is etched as follows. Further, in order to increase the selectivity with the island-shaped semiconductor film, the etching gas is changed to CHF. _Three The contact hole can be satisfactorily formed by switching to 1 and etching the gate insulating film.
[0068]
Then, a conductive metal film is formed by sputtering or vacuum vapor deposition, a resist mask pattern is formed, and source wirings 148 to 152 and drain wirings 153 to 157 are formed by etching. Here, the drain wiring 157 functions as a pixel electrode. Although not shown, in this embodiment, this electrode is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with the semiconductor film forming the source or drain region of the island-shaped semiconductor film, and then forming the Ti film. Overlaid on top, aluminum (Al) is formed to a thickness of 300 to 400 nm to form wiring.
[0069]
When the hydrogenation treatment is performed in this state, a favorable result can be obtained for improving the characteristics of the TFT. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Further, by such heat treatment, hydrogen present in the protective insulating film 146 and the base film 102 can be diffused into the island-shaped semiconductor films 104 to 108 to be hydrogenated. In any case, the defect density in the island-like semiconductor films 104 to 108 is 10 ¹⁶ /cm ^Three It is desirable that the hydrogen content be as follows, and hydrogen may be added in an amount of about 0.01 to 0.1 atomic% (FIG. 5C).
[0070]
In this way, a substrate having the TFT of the driving circuit and the pixel TFT of the pixel portion can be completed on the same substrate. A first p-channel TFT 200, a first n-channel TFT 201, a second p-channel TFT 202, and a second n-channel TFT 203 are formed in the driver circuit, and a pixel TFT 204 and a storage capacitor 205 are formed in the pixel portion. Yes. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0071]
The first p-channel TFT 200 of the driving circuit has a single drain structure having a channel formation region 206, source regions 207a and 207b made of high-concentration p-type impurity regions, and drain regions 208a and 208b in the island-like semiconductor film 104. have. The first n-channel TFT 201 includes a channel formation region 209, an LDD region 210 that overlaps with the gate electrode 119, a source region 212, and a drain region 211 on the island-shaped semiconductor film 105. In this LDD region, when the LDD region overlapping with the gate electrode 119 is Lov, the length in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 2.0 μm. By making the length of the LDD region in the n-channel TFT in this way, a high electric field generated in the vicinity of the drain region can be relaxed, hot carrier generation can be prevented, and deterioration of the TFT can be prevented. Similarly, the second p-channel TFT 202 of the driver circuit is a single drain having a channel formation region 213, source regions 214a and 214b composed of high-concentration p-type impurity regions, and drain regions 215a and 215b on the island-like semiconductor film 106. It has a structure. In the second n-channel TFT 203, a channel formation region 216, LDD regions 217 and 218 that partially overlap with the gate electrode 121, a source region 220, and a drain region 219 are formed on the island-shaped semiconductor film 107. The length of Lov overlapping the gate electrode of this TFT was also 0.5 to 3.0 μm, preferably 1.0 to 2.0 μm. The LDD region that does not overlap the gate electrode is Loff, and the length in the channel length direction is 0.5 to 4.0 μm, preferably 1.0 to 2.0 μm. The pixel TFT 204 includes channel formation regions 221 and 222, LDD regions 223 to 225, and source or drain regions 226 to 228 in the island-shaped semiconductor film 108. The length of the LDD region (Loff) in the channel length direction is 0.5 to 4.0 μm, preferably 1.5 to 2.5 μm. Further, a storage capacitor 205 is formed from the capacitor wiring 123, an insulating film made of the same material as the gate insulating film, and a semiconductor film 229 connected to the drain region 228 of the pixel TFT 204. Although the pixel TFT 204 has a double gate structure in FIG. 5C, it may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.
[0072]
FIG. 15 is a top view showing almost one pixel in the pixel portion. A cross section AA ′ shown in the drawing corresponds to the cross sectional view of the pixel portion shown in FIG. The gate electrode 122 of the pixel TFT 204 intersects the island-like semiconductor film 108 thereunder via a gate insulating film (not shown). The gate electrode 122 is in contact with the gate wiring 900 made of a low-resistance conductive material formed using a material such as Al or Cu without contact holes on the outside of the island-shaped semiconductor film 108. Although not shown, the island-shaped semiconductor film 108 is formed with a source region, a drain region, and an LDD region. Reference numeral 256 denotes a contact portion between the source wiring 152 and the source region 226, and 257 denotes a contact portion between the drain wiring 157 and the drain region 228. The storage capacitor 205 is formed in a region where the capacitor wiring 123 overlaps with the semiconductor film 229 extending from the drain region 228 of the pixel TFT 204 and the gate insulating film. In this structure, an impurity element for the purpose of valence electron control is not added to the semiconductor film 229.
[0073]
The configuration as described above makes it possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the drive circuit, and to improve the operation performance and reliability of the semiconductor device. Furthermore, activation of the LDD region, the source region, and the drain region is facilitated by forming the gate electrode from a heat-resistant conductive material. In order to fabricate an active matrix substrate provided with such TFTs, field effect transfer is achieved by fabricating TFTs using a crystalline silicon film having a high <110> orientation using the crystallization method of the present invention. The electrical characteristics such as the degree can be improved. Further, variation in characteristics of individual TFTs can be reduced. A liquid crystal display device or an EL display device can be manufactured using such an active matrix substrate.
[0074]
[Example 2]
In Example 1, an example in which a heat-resistant conductive material such as W or Ta is used as the material of the gate electrode of the TFT is shown. The reason for using such a material is that the impurity element added to the semiconductor film for the purpose of valence electron control after gate electrode formation is activated by thermal annealing at 400 to 700 ° C., prevention of electromigration, and improvement of corrosion resistance. This is due to multiple factors. However, such a heat-resistant conductive material has a sheet resistance of about 10Ω, and is not suitable for a liquid crystal display device or an EL display device having a screen size of 4 inches class or more. This is because if the gate wiring connected to the gate electrode is formed of the same material, the routing length on the substrate surface inevitably increases, and the delay time due to the influence of the wiring resistance cannot be ignored.
[0075]
For example, when the pixel density is VGA, 480 gate wirings and 640 source wirings are formed, and in the case of XGA, 768 gate wirings and 1024 source wirings are formed. The screen size of the display area is 340 mm for the 13-inch class and 460 mm for the 18-inch class. In this embodiment, as a means for realizing such a liquid crystal display device, a method of forming a gate wiring with a low-resistance conductive material such as Al or copper (Cu) will be described with reference to FIG.
[0076]
First, the steps shown in FIGS. 3A to 4D are performed in the same manner as in the first embodiment. Then, processing for activating the impurity element added to each island-shaped semiconductor film is performed for the purpose of valence electron control. This activation treatment is most preferably performed by the heat treatment method using laser light shown in the seventh embodiment. Further, heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a process of hydrogenating the island-shaped semiconductor film. This step is a step of terminating dangling bonds in the semiconductor film with thermally excited hydrogen. As another means for hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed (FIG. 6A).
[0077]
After the activation and hydrogenation processes are completed, a gate wiring is formed using a low resistance conductive material. This low resistance conductive layer is formed of a conductive film mainly composed of Al or Cu. For example, an Al film containing 0.1 to 2% by weight of Ti is formed as a conductive film on the entire surface (not shown). The conductive film may be 200 to 400 nm (preferably 250 to 350 nm). Then, a predetermined resist pattern is formed using a photomask, and etching is performed to form gate wirings 163 and 164 and a capacitor wiring 165. In the etching process, the conductive film is removed by wet etching with a phosphoric acid-based etching solution, whereby the gate wiring can be formed while maintaining selective processability with the base. Then, a protective insulating film 146 is formed (FIG. 6B).
[0078]
Thereafter, an interlayer insulating film 147 made of an organic insulating material, source wirings 148 to 151 and 167, and drain wirings 153 to 156 and 168 can be formed in the same manner as in Example 1 to complete the active matrix substrate. FIGS. 7A and 7B are top views of this state, and the BB ′ cross section of FIG. 7A and the CC ′ cross section of FIG. It corresponds to A ′ and CC ′. 7A and 7B, the gate insulating film, the protective insulating film, and the interlayer insulating film are omitted, but the source and drain regions of the island-shaped semiconductor films 104, 105, and 108 are not illustrated. The wirings 148, 149, and 167 and the drain wirings 153, 154, and 168 are connected through contact holes. Moreover, the DD 'cross section of FIG. 7 (A) and the EE' cross section of FIG. 7 (B) are shown to FIG. 8 (A) and (B), respectively. The gate wiring 163 is formed so as to overlap with the gate electrodes 118 and 119, and the gate wiring 164 is formed so as to overlap the gate electrode 122 and the outside of the island-shaped semiconductor films 104, 105, and 108. Conducted. By forming the gate wiring with a low-resistance conductive material in this way, the wiring resistance can be sufficiently reduced. Therefore, the present invention can be applied to a liquid crystal display device or EL display device having a pixel portion (screen size) of 4 inches class or more.
[0079]
[Example 3]
The active matrix substrate manufactured in Embodiment 1 can be applied to a reflective liquid crystal display device as it is. On the other hand, in the case of a transmissive liquid crystal display device, a pixel electrode provided in each pixel of the pixel portion may be formed using a transparent electrode. In this embodiment, a method for manufacturing an active matrix substrate corresponding to a transmissive liquid crystal display device will be described with reference to FIGS.
[0080]
The active matrix substrate is manufactured in the same manner as in Example 1. In FIG. 10A, a conductive metal film is formed for the source wiring and the drain wiring by a sputtering method or a vacuum evaporation method. In this method, a Ti film is formed to a thickness of 50 to 150 nm, a contact is formed with a semiconductor film that forms a source or drain region of the island-shaped semiconductor film, and aluminum (Al) 300 to 300 is stacked on the Ti film. The film was formed to a thickness of 400 nm, and a Ti film or a titanium nitride (TiN) film was formed to a thickness of 100 to 200 nm to form a three-layer structure. Thereafter, a transparent conductive film is formed over the entire surface, and a pixel electrode 171 is formed by patterning processing and etching processing using a photomask. The pixel electrode 171 is formed on the interlayer insulating film 147, and a portion overlapping the drain wiring 169 of the pixel TFT is provided to form a connection structure.
[0081]
In FIG. 10B, first, a transparent conductive film is formed over the interlayer insulating film 147, and after patterning treatment and etching treatment are performed to form the pixel electrode 193, a drain wiring 169 is provided so as to overlap with the pixel electrode 193. This is an example of formation. In the drain wiring 169, a Ti film is formed to a thickness of 50 to 150 nm, a contact is formed with a semiconductor film that forms a source or drain region of the island-shaped semiconductor film, and aluminum (Al) 300 is overlaid on the Ti film. It is formed with a thickness of ˜400 nm. With this configuration, the pixel electrode 171 is in contact with only the Ti film forming the drain wiring 169. As a result, the reaction between the transparent conductive film material and Al can be prevented.
[0082]
The material of the transparent conductive film is indium oxide (In ₂ O _Three ) Or indium tin oxide alloy (In ₂ O _Three -SnO ₂ ; ITO) or the like can be formed using a sputtering method, a vacuum deposition method, or the like. Etching treatment of such a material is performed with a hydrochloric acid based solution. However, in particular, etching of ITO is likely to generate a residue, so in order to improve etching processability, an indium oxide-zinc oxide alloy (In ₂ O _Three —ZnO) may also be used. Since the indium oxide-zinc oxide alloy has excellent surface smoothness and thermal stability with respect to ITO, it can prevent a corrosion reaction with Al coming into contact with the end face of the drain wiring 169. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.
[0083]
In this manner, an active matrix substrate corresponding to a transmissive liquid crystal display device can be completed. Although this embodiment has been described as a process similar to that of Embodiment 1, such a configuration can be applied to the active matrix substrate shown in Embodiment 2 or Embodiment 3.
[0084]
[Example 4]
As described in Embodiment Mode 1 or Embodiment Mode 3, a method for obtaining a crystalline semiconductor film using a catalytic element that promotes crystallization of an amorphous semiconductor film is used for the purpose of manufacturing a TFT having high field effect mobility. It is valid. However, in this case, a very small amount (1 × 10 10) is present in the crystalline semiconductor film. ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three Degree) catalyst element remains. Of course, the TFT can be completed even in such a state, but it is more preferable to remove at least the remaining catalyst element from the channel formation region in order to reduce the off-current. As one of means for removing the catalyst element, there is means for utilizing the gettering action by phosphorus (P) as shown in the second embodiment.
[0085]
The gettering process using phosphorus (P) can be performed simultaneously in the activation step described with reference to FIG. This will be described with reference to FIG. The concentration of phosphorus (P) necessary for gettering may be approximately the same as the impurity concentration of the high-concentration n-type impurity region, and the catalyst from the channel formation region of the n-channel TFT and the p-channel TFT is formed by thermal annealing in the activation process. The element can be segregated to the impurity region containing phosphorus (P) at that concentration (in the direction of the arrow shown in FIG. 9). As a result, the impurity region is 1 × 10 ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three About a catalytic element segregated. The TFT manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0086]
[Example 5]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described. First, as shown in FIG. 11A, a spacer made of a columnar spacer is formed on the active matrix substrate in the state of FIG. The spacer may be provided by dispersing particles of several μm, but here, a method of forming a resin film on the entire surface of the substrate and then patterning it is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Co. is used, and after applying with a spinner, a predetermined pattern is formed by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The spacers produced in this manner can have different shapes depending on the conditions of exposure and development processing. Preferably, the columnar spacers 173 have a columnar shape and a flat top, so that the opposite side has a flat shape. When the substrates are combined, the mechanical strength of the liquid crystal display panel can be ensured. The shape is not particularly limited, such as a conical shape or a pyramid shape. For example, when the shape is conical, specifically, the height is 1.2 to 5 μm, the average radius is 5 to 7 μm, the average radius and the bottom portion are The ratio with the radius is about 1: 1.5. At this time, the taper angle seen from the cross section is preferably ± 15 ° or less.
[0087]
The arrangement of the columnar spacers may be arbitrarily determined. Preferably, as shown in FIG. 11A, the pixel portion is overlapped with the contact portion 235 of the drain wiring 161 (pixel electrode) so as to cover the portion. A columnar spacer 168 may be formed. Since the flatness of the contact portion 235 is lost and the liquid crystal is not aligned well in this portion, the columnar spacer 168 is formed in such a manner that the spacer 168 is filled in the contact portion 235 so that disclination or the like is performed. Can be prevented.
[0088]
Thereafter, an alignment film 174 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After the alignment film was formed, rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The region that is not rubbed in the rubbing direction from the end of the columnar spacer 173 provided in the pixel portion is set to 2 μm or less. Also, the occurrence of static electricity is often a problem in the rubbing process. However, if the spacer 172 is also formed on the TFT of the drive circuit, the original role as the spacer and the effect of protecting the TFT from static electricity can be obtained. it can.
[0089]
A light shielding film 176, a transparent conductive film 177, and an alignment film 178 are formed on the counter substrate 175 on the counter side. The light shielding film 176 is made of Ti, Cr, Al or the like with a thickness of 150 to 300 nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are bonded together with a sealant 179. A filler 180 is mixed in the sealant 179, and two substrates are bonded to each other with a uniform interval by the filler 180 and the spacers 172 and 173. Thereafter, a liquid crystal material 606 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. In this manner, the active matrix liquid crystal display device illustrated in FIG. 11B is completed.
[0090]
Although FIG. 11 shows an example in which the spacer 172 is formed on the entire surface of the TFT of the drive circuit, this spacer may be divided into a plurality of spacers 172a to 172e as shown in FIG. The spacer provided in the portion where the drive circuit is formed may be formed so as to cover at least the source wiring and the drain wiring of the drive circuit. With such a structure, each TFT of the driving circuit is completely covered and protected by the protective insulating film 146, the interlayer insulating film 147, and the spacer 172 or the spacers 172a to 172e.
[0091]
FIG. 13 is a top view of an active matrix substrate on which spacers and a sealing agent are formed, and is a top view showing the positional relationship between the pixel portion and the drive circuit portion and the spacers and the sealing agent. Around the pixel portion 188, a scanning signal driving circuit 185 and an image signal driving circuit 186 are provided as driving circuits. Further, a signal processing circuit 187 such as a CPU or a memory may be added. These drive circuits are connected to the external input / output terminal 182 by connection wiring 183. In the pixel portion 188, a gate wiring group 189 extending from the scanning signal driving circuit 185 and a source wiring group 190 extending from the image signal driving circuit 186 intersect to form a pixel, and each pixel has a pixel TFT 204. And a storage capacitor 205 are provided.
[0092]
The columnar spacers 173 provided in the pixel portion may be provided for all the pixels, but may be provided every several to several tens of pixels arranged in a matrix. That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion is preferably 20 to 100%. Further, the spacers 172, 172 ′, 172 ″ provided in the driving circuit portion may be provided so as to cover the entire surface, or a plurality of spacers 172, 172 ′, 172 ″ may be provided according to the positions of the source and drain wirings of each TFT as shown in FIG. You may divide and provide. The sealant 179 is formed outside the pixel portion 188 and the scanning signal control circuit 185, the image signal control circuit 186, and other signal processing circuits 187 on the substrate 101 and inside the external input / output terminal 182.
[0093]
The structure of such an active matrix liquid crystal display device will be described with reference to the perspective view of FIG. In FIG. 14, the active matrix substrate includes a pixel portion 188, a scanning signal driving circuit 185, an image signal driving circuit 186, and other signal processing circuits 187 formed on the glass substrate 101. The pixel portion 188 is provided with a pixel TFT 204 and a storage capacitor 205, and a driver circuit provided around the pixel portion is configured based on a CMOS circuit. The scanning signal driving circuit 185 and the image signal driving circuit 186 are connected to the pixel TFT 204 by a gate wiring 122 and a source wiring 152, respectively. A flexible printed circuit (FPC) 191 is connected to an external input terminal 182 and used for inputting an image signal or the like. The connection wiring 183 is connected to each drive circuit. The counter substrate 175 is provided with a light shielding film and a transparent electrode (not shown).
[0094]
The liquid crystal display device having such a structure can be formed using the active matrix substrate shown in Embodiments 1 to 4. A reflective liquid crystal display device can be obtained by using the active matrix substrate shown in Embodiments 1 to 3, and a transmissive liquid crystal display device can be obtained by using the active matrix substrate shown in Embodiment 4.
[0095]
[Example 6]
In this embodiment, an example in which a self-luminous display panel (hereinafter referred to as an EL display device) using an electroluminescence (EL) material is manufactured using the active matrix substrate described in Embodiment 1 will be described. To do. FIG. 16A is a top view of an EL display panel using the present invention. In FIG. 16A, reference numeral 10 denotes a substrate, 11 denotes a pixel portion, 12 denotes a source side driver circuit, 13 denotes a gate side driver circuit, and each driver circuit reaches the FPC 17 via wirings 14 to 16 to an external device. Connected.
[0096]
FIG. 16B is a diagram illustrating a cross section taken along line AA ′ of FIG. 16A. At this time, a counter plate 80 is provided at least on the pixel portion, preferably on the driver circuit and the pixel portion. The counter plate 80 is bonded to an active matrix substrate on which a self-luminous layer using a TFT and an EL material is formed with a sealing material 19. A filler (not shown) is mixed in the sealing agent 19, and the two substrates are bonded to each other with a substantially uniform interval. Further, the outside of the sealing material 19 and the upper surface and the periphery of the FPC 17 are sealed with a sealant 81. The sealant 81 is made of a material such as silicone resin, epoxy resin, phenol resin, or butyl rubber.
[0097]
Thus, when the active matrix substrate 10 and the counter substrate 80 are bonded together by the sealant 19, a space is formed between them. The space is filled with a filler 83. This filler 83 also has the effect of bonding the opposing plate 80. As the filler 83, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), EVA (ethylene vinyl acetate), or the like can be used. In addition, since the self-luminous layer is weak and easily deteriorated due to moisture including moisture, it is desirable to mix a desiccant such as barium oxide in the filler 83 because the moisture absorption effect can be maintained. In addition, a passivation film 82 formed of a silicon nitride film, a silicon oxynitride film, or the like is formed over the self-light-emitting layer so that corrosion due to an alkali element or the like contained in the filler 83 is prevented.
[0098]
The counter plate 80 includes a glass plate, an aluminum plate, a stainless steel plate, a FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a Mylar film (trade name of DuPont), a polyester film, an acrylic film, an acrylic plate, etc. Can be used. Moreover, moisture resistance can also be improved using the sheet | seat of the structure which pinched | interposed several tens micrometer aluminum foil with the PVF film or the mylar film. In this way, the EL element is hermetically sealed from the outside air.
[0099]
In FIG. 16B, a driver circuit TFT (however, here, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined is illustrated) 22 and a pixel on the substrate 10 and the base film 21. The part TFT 23 (however, only the TFT for controlling the current to the EL element is shown here) is formed. Among these TFTs, especially n-channel TFTs are provided with an LDD region having the structure shown in this embodiment in order to prevent a decrease in on-current due to the hot carrier effect and a decrease in characteristics due to Vth shift and bias stress.
[0100]
For example, as the driver circuit TFT 22, p-channel TFTs 200 and 202 and n-channel TFTs 201 and 203 shown in FIG. As the pixel portion TFT 23, a pixel TFT 204 shown in FIG. 5B or a p-channel TFT having a similar structure may be used.
[0101]
In order to manufacture an EL display device from the active matrix substrate in the state of FIG. 5C or FIG. 6C, an interlayer insulating film (planarization film) 26 made of a resin material is formed over the source wiring and the drain wiring. A pixel electrode 27 made of a transparent conductive film electrically connected to the drain of the pixel portion TFT 23 is formed thereon. A compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used for the transparent conductive film. Then, after the pixel electrode 27 is formed, an insulating film 28 is formed, and an opening is formed on the pixel electrode 27.
[0102]
Next, the self-luminous layer 29 is formed. The self-light emitting layer 29 may have a laminated structure or a single layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, a vapor deposition method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.
[0103]
The self-luminous layer is formed by a vapor deposition method, an inkjet method, a dispenser method, or the like using a shadow mask. In any case, color display is possible by forming light emitting layers (red light emitting layer, green light emitting layer, and blue light emitting layer) capable of emitting light having different wavelengths for each pixel. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but either method may be used. Needless to say, an EL display device emitting monochromatic light can also be used.
[0104]
When the self-luminous layer 29 is formed, the cathode 30 is formed thereon. It is desirable to remove moisture and oxygen present at the interface between the cathode 30 and the self-luminous layer 29 as much as possible. Therefore, it is necessary to devise such that the self-luminous layer 29 and the cathode 30 are continuously formed in a vacuum, or the self-luminous layer 29 is formed in an inert atmosphere and the cathode 30 is formed in a vacuum without being released to the atmosphere. . In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0105]
In this embodiment, a laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 30. Specifically, a LiF (lithium fluoride) film having a thickness of 1 nm is formed on the self-light-emitting layer 29 by vapor deposition, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, you may use the MgAg electrode which is a well-known cathode material. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 through an anisotropic conductive paste material 32. A resin layer 80 is further formed on the FPC 17 to increase the adhesive strength of this portion.
[0106]
In order to electrically connect the cathode 30 and the wiring 16 in the region indicated by 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed when the interlayer insulating film 26 is etched (when the pixel electrode contact hole is formed) or when the insulating film 28 is etched (when the opening before the self-light emitting layer is formed). Further, when the insulating film 28 is etched, the interlayer insulating film 26 may be etched all at once. In this case, if the interlayer insulating film 26 and the insulating film 28 are the same resin material, the shape of the contact hole can be improved. In addition, the wiring 16 is electrically connected to the FPC 17 through a gap (but sealed with a sealing agent 81) between the sealil 19 and the substrate 10. Although the wiring 16 has been described here, the other wirings 14 and 15 are similarly electrically connected to the FPC 17 through the sealing material 18.
[0107]
Here, FIG. 17 shows a more detailed cross-sectional structure of the pixel portion, FIG. 18A shows a top structure, and FIG. 18B shows a circuit diagram. In FIG. 17A, a switching TFT 2402 provided over a substrate 2401 is formed with the same structure as the pixel TFT 204 of FIG. The double gate structure has a structure in which two TFTs are substantially connected in series, and there is an advantage that the off-current value can be reduced. In this embodiment, a double gate structure is used, but a triple gate structure or a multi-gate structure having more gates may be used.
[0108]
The current control TFT 2403 is formed using the n-channel TFT 201 shown in FIG. At this time, the drain line 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current control TFT by the wiring 36. A wiring indicated by 38 is a gate line for electrically connecting the gate electrodes 39a and 39b of the switching TFT 2402.
[0109]
At this time, it is very important that the current control TFT 2403 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and it is also an element with a high risk of deterioration due to heat or hot carriers. Therefore, by providing an LDD region that partially overlaps the gate electrode in the current control TFT, it is possible to prevent the TFT from being deteriorated and to improve the operation stability. In addition, by using a highly oriented crystalline semiconductor film manufactured according to the present invention, field effect mobility, on-current, and the like, which are characteristics of a TFT, can be increased.
[0110]
In this embodiment, the current control TFT 2403 is illustrated with a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.
[0111]
As shown in FIG. 18A, the wiring to be the gate electrode 37 of the current control TFT 2403 overlaps the drain line 40 of the current control TFT 2403 with an insulating film in the region indicated by 2404. At this time, a capacitor is formed in a region indicated by 2404. This capacitor 2404 functions as a capacitor for holding the voltage applied to the gate of the current control TFT 2403. The drain line 40 is connected to a current supply line (power supply line) 2501, and a constant voltage is always applied.
[0112]
A first passivation film 41 is provided on the switching TFT 2402 and the current control TFT 2403, and a planarizing film 42 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 42. Since the self-light-emitting layer formed later is very thin, a light emission failure may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the self-luminous layer can be formed as flat as possible.
[0113]
Reference numeral 43 denotes a pixel electrode (EL element cathode) made of a highly reflective conductive film, which is electrically connected to the drain of the current control TFT 2403. As the pixel electrode 43, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used. Further, the light emitting layer 44 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene. There are various types of PPV organic EL materials such as “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,“ Polymers for Light Emitting ”. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and JP-A-10-92576 may be used.
[0114]
As a specific light emitting layer, cyanopolyphenylene vinylene may be used for a light emitting layer that emits red light, polyphenylene vinylene may be used for a light emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm). However, the above example is an example of an organic EL material that can be used as a light emitting layer, and is not necessarily limited to this. A self-luminous layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0115]
In this embodiment, a self-luminous layer having a laminated structure in which a hole injection layer 46 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light-emitting layer 45 is used. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. What can form into a film at low temperature as much as possible is preferable.
[0116]
When the anode 47 is formed, the self-luminous element 2405 is completed. Note that the EL element 2405 here refers to a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. As shown in FIG. 18A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.
[0117]
By the way, in the present embodiment, a second passivation film 48 is further provided on the anode 47. The second passivation film 48 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to cut off the EL element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic EL material and the meaning of suppressing degassing from the organic EL material. This increases the reliability of the EL display device.
[0118]
As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 18, and includes a switching TFT having a sufficiently low off-current value and a current control TFT resistant to hot carrier injection. Have. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.
[0119]
FIG. 17B shows an example in which the structure of the self-luminous layer is inverted. The current control TFT 2601 is formed using the p-channel TFT 200 of FIG. For the manufacturing process, Example 1 may be referred to. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Of course, a conductive film made of a compound of indium oxide and tin oxide may be used.
[0120]
Then, after banks 51a and 51b made of insulating films are formed, a light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, the EL element 2602 is formed. In the case of the present embodiment, the light generated in the light emitting layer 53 is emitted toward the substrate on which the TFT is formed as indicated by an arrow. In the case of the structure as in this embodiment, the current control TFT 2601 is preferably a p-channel TFT.
[0121]
The configuration of this example as described above is carried out by producing a highly oriented crystalline semiconductor film by the method of the present invention shown in Embodiments 1 to 3, and freely combining the configurations of the TFTs of Examples 1 and 2. Is possible. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 8.
[0122]
[Example 7]
In this embodiment, an example of a pixel having a structure different from the circuit diagram shown in FIG. 18B is shown in FIG. In this embodiment, 2701 is a source wiring of the switching TFT 2702, 2703 is a gate wiring of the switching TFT 2702, 2704 is a current control TFT, 2705 is a capacitor, 2706 and 2708 are current supply lines, and 2707 is an EL element. .
[0123]
FIG. 19A shows an example in which the current supply line 2706 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 2706. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0124]
FIG. 19B illustrates an example in which the current supply line 2708 is provided in parallel with the gate wiring 2703. In FIG. 19B, the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, since the exclusive area can be shared by the power supply line 2708 and the gate wiring 2703, the pixel portion can be further refined.
[0125]
In FIG. 19C, a current supply line 2708 is provided in parallel with the gate wiring 2703 as in the structure of FIG. 19B, and two pixels are symmetrical with respect to the current supply line 2708. It is characterized in that it is formed. It is also effective to provide the current supply line 2708 so as to overlap any one of the gate wirings 2703. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined. In FIGS. 19A and 19B, a capacitor 2404 is provided to hold a voltage applied to the gate of the current control TFT 2403. However, the capacitor 2404 can be omitted.
[0126]
Since the n-channel TFT of the present invention as shown in FIG. 17A is used as the current control TFT 2403, it has an LDD region provided so as to overlap with the gate electrode through the gate insulating film. In this overlapping region, a parasitic capacitance generally called a gate capacitance is formed, but this embodiment is characterized in that this parasitic capacitance is actively used in place of the capacitor 2404. The capacitance of this parasitic capacitance 19 is determined by the length of the LDD region included in the overlapped region because the gate electrode and the LDD region change in the overlapped area, and the structure shown in FIGS. Similarly, the capacitor 2705 can be omitted.
[0127]
The configuration of this example as described above is carried out by producing a highly oriented crystalline semiconductor film by the method of the present invention shown in Embodiments 1 to 3, and freely combining the configurations of the TFTs of Examples 1 and 2. Is possible. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 8.
[0128]
[Example 8]
In this embodiment, a semiconductor device incorporating an active matrix liquid crystal display device using a TFT circuit of the present invention will be described with reference to FIGS.
[0129]
Examples of such a semiconductor device include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer, a television, and the like. Examples of these are shown in FIGS.
[0130]
FIG. 20A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display device 9004, operation switches 9005, and an antenna 9006. The present invention can be applied to a display device 9004 including an active matrix substrate.
[0131]
FIG. 20B illustrates a video camera which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be applied to a display device 9102 including an active matrix substrate, a TFT constituting an image sensor reading circuit provided as an image receiving portion 9106, and the like.
[0132]
FIG. 20C illustrates a mobile computer or a portable information terminal, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205. The present invention can be applied to a display device 9205 including a TFT and an active matrix substrate which constitute a reading circuit of an image sensor provided as the image receiving portion 9203.
[0133]
FIG. 20D illustrates a head mounted display which includes a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can also be used for TFTs for forming other signal control circuits.
[0134]
FIG. 20E illustrates a television set including a main body 9401, speakers 9402, a display device 9403, a receiving device 9404, an amplifying device 9405, and the like. The liquid crystal display device shown in Embodiment 5 and the EL display device shown in Embodiment 6 or 7 can be applied to the display device 9403.
[0135]
FIG. 20F illustrates a portable book which includes a main body 9501, display devices 9502 and 9503, a storage medium 9504, operation switches 9505, and an antenna 9506, and data stored in a minidisc (MD) or DVD, The data received by the antenna is displayed. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to them.
[0136]
FIG. 21A illustrates a personal computer which includes a main body 9601, an image input portion 9602, a display device 9603, and a keyboard 9604. The liquid crystal display device shown in Embodiment 5 and the EL display device shown in Embodiment 6 or 7 can be applied to the display device 9603.
[0137]
FIG. 21B shows a player that uses a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 9701, a display device 9702, a speaker portion 9703, a recording medium 9704, and operation switches 9705. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The liquid crystal display device shown in Embodiment 5 and the EL display device shown in Embodiment 6 or 7 can be applied to the display device 9702.
[0138]
FIG. 21C illustrates a digital camera, which includes a main body 9801, a display device 9802, an eyepiece unit 9803, an operation switch 9804, and an image receiving unit (not illustrated). The liquid crystal display device shown in Embodiment 5 and the EL display device shown in Embodiment 6 or 7 can be applied to the display device 9802.
[0139]
FIG. 22A illustrates a front type projector, which includes a projection device 3601 and a screen 3602. The present invention can be applied to the projection device 3601 and other signal control circuits.
[0140]
FIG. 22B illustrates a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, and a screen 3704. The present invention can be applied to the projection device 3702 and other signal control circuits.
[0141]
Note that FIG. 22C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 22A and 22B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0142]
FIG. 22D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 22D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0143]
【The invention's effect】
By using the present invention, the orientation of a crystalline semiconductor film manufactured using a thermal crystallization method or a laser crystallization method for an amorphous semiconductor film can be improved. Further, by using such a crystalline semiconductor film, characteristics of the TFT can be improved and variation in characteristics can be reduced.
[Brief description of the drawings]
FIG. 1 shows steps of a crystallization method of the present invention.
FIG. 2 is a diagram showing a process of a crystallization method of the present invention.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a driver circuit TFT;
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 7 is a top view illustrating a structure of a TFT and a pixel TFT of a driver circuit.
FIG. 8 is a cross-sectional view illustrating structures of a TFT and a pixel TFT of a driver circuit.
FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a driver circuit TFT;
FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 11 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 12 is a cross-sectional view illustrating a structure of an active matrix liquid crystal display device.
FIG. 13 is a top view illustrating the arrangement of input terminals, wiring, circuit arrangement, spacers, and sealant of a liquid crystal display device.
FIG. 14 is a perspective view illustrating a structure of a liquid crystal display device.
FIG. 15 is a top view illustrating a pixel in a pixel portion.
FIGS. 16A and 16B are a top view and a cross-sectional view illustrating a structure of an EL display device. FIGS.
FIG. 17 is a cross-sectional view of a pixel portion of an EL display device.
18A and 18B are a top view and a circuit diagram of a pixel portion of an EL display device.
FIG. 19 is an example of a circuit diagram of a pixel portion of an EL display device.
FIG 20 illustrates an example of a semiconductor device.
FIG. 21 illustrates an example of a semiconductor device.
FIG. 22 is a diagram showing a configuration of a projection type liquid crystal display device.

Claims (8)

Forming an insulating film containing silicon on the substrate;
To terminate dangling bonds on the surface of the insulating film including silicon by fluorine is exposed to an atmosphere of fluorine or fluorine radicals the surface of the insulating film including silicon,
Forming an amorphous semiconductor film on the insulating film containing silicon terminated with dangling bonds on the surface ;
Adding a catalyst element for promoting crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
A method for manufacturing a semiconductor device, wherein a heat treatment is performed on the amorphous semiconductor film to form a crystalline semiconductor film. Forming an insulating film containing silicon on the substrate;
To terminate dangling bonds on the surface of the insulating film including silicon by fluorine is exposed to an atmosphere of fluorine or fluorine radicals the surface of the insulating film including silicon,
Forming an amorphous semiconductor film on the insulating film containing silicon terminated with dangling bonds on the surface ;
Adding a catalyst element for promoting crystallization of the amorphous semiconductor film to the amorphous semiconductor film;
A heat treatment is performed on the amorphous semiconductor film to form a crystalline semiconductor film,
A method for manufacturing a semiconductor device, wherein the crystalline semiconductor film is crystallized by irradiating a laser beam. In claim 2 ,
The method for manufacturing a semiconductor device, wherein the laser light is excimer laser light having a wavelength of 400 nm or less. In claim 2 ,
The laser beam is one laser beam selected from a YAG laser, a YVO ₄ laser, a YAlO ₃ laser, and a YLF laser. The second harmonic (532 nm), the third harmonic (355 nm), and the fourth harmonic ( 266 nm). A method for manufacturing a semiconductor device, wherein In any one of Claims 1 thru | or 4 ,
The catalyst elements are nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold A method for manufacturing a semiconductor device, wherein the method is (Au). In any one of Claims 1 thru | or 5 ,
Semiconductor, characterized in that to terminate the dangling bonds of the surface of the insulating film including silicon and exposed in plasma atmosphere to the surface of the silicon tetrafluoride or nitrogen trifluoride insulating film including silicon Device fabrication method. In any one of Claims 1 thru | or 6 ,
The method for manufacturing a semiconductor device is characterized in that the insulating film containing silicon is a single layer or a stacked layer made of a material selected from silicon oxide, silicon nitride, and silicon oxynitride.   In any one of Claims 1 thru | or 7,
  Termination of dangling bonds on the surface of the insulating film containing silicon and formation of the amorphous semiconductor film are continuously performed using a plasma CVD apparatus without being exposed to an air atmosphere. Manufacturing method.

Images