JP4683710B2 - Liquid crystal display device, EL display device and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) on a substrate having an insulating surface, and a manufacturing method thereof. For example, the present invention relates to an electro-optical device typified by a liquid crystal display device, an electric appliance (also referred to as an electronic device) on which the electro-optical device is mounted, and a manufacturing method thereof. Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electric appliance in which the electro-optical device is mounted.
[0002]
[Prior art]
In recent years, attention has been paid to an active matrix liquid crystal display device in which a circuit is constituted by TFTs using a polysilicon film (hereinafter referred to as crystalline TFTs). This realizes a high-definition image display device by controlling the electric field applied to the liquid crystal in a matrix by a plurality of pixels arranged in a matrix.
[0003]
In many cases, an n-channel TFT is formed in a pixel portion of an active matrix liquid crystal display device (hereinafter, a TFT formed in the pixel portion is referred to as a pixel TFT). Since a gate voltage having an amplitude of about 15 to 20 V is applied to the pixel TFT, it is necessary to satisfy the characteristics of both the on region and the off region. On the other hand, the peripheral circuit provided for driving the pixel portion is configured based on a CMOS circuit, and the characteristics of the on region are mainly important. However, the crystalline TFT has a problem that the off-current tends to increase. When the crystalline TFT is driven for a long period of time, deterioration phenomena such as a decrease in mobility, an on-current, and an increase in off-current are often observed. One of the causes is considered to be a hot carrier injection phenomenon that occurs due to a high electric field near the drain.
[0004]
In the LSI technical field, a lightly doped drain (LDD) structure is known as a method for reducing the off-current of a MOS transistor and further mitigating a high electric field in the vicinity of the drain. In this structure, a low concentration impurity region is provided between a drain region and a channel formation region, and this low concentration impurity region is called an LDD region.
[0005]
Similarly, it has been known that a crystalline TFT forms an LDD structure. In the conventional technique, a low-concentration impurity region that becomes an LDD region is formed by adding a first impurity element using a gate electrode as a mask, and then an anisotropic etching technique is used on both sides of the gate electrode. In this method, sidewalls are formed, and a high concentration impurity region to be a source region and a drain region is formed by adding a second impurity element using the gate electrode and the sidewall as a mask.
[0006]
[Problems to be solved by the invention]
However, the LDD structure has a drawback in that, even if the off-current can be reduced, the series resistance component increases structurally, and as a result, the on-current of the TFT also decreases. It was. Moreover, the deterioration of the on-current could not be prevented completely.
[0007]
The present invention provides a technique for overcoming such a problem, and an object thereof is to provide a TFT having a structure in which a gate electrode and an LDD region are overlapped. In order to achieve the object, an object is to provide a technique for manufacturing a TFT having a structure in which a gate electrode overlaps an LDD region by a simple method. Another object of the present invention is to provide a semiconductor device in which a circuit is formed using highly reliable TFTs.
[0008]
[Means for Solving the Problems]
The structure of the invention disclosed in this specification includes a TFT having a gate wiring on a gate insulating film, and having a metal film having the same film thickness on a side surface and an upper surface of the gate wiring. Device.
[0009]
According to another aspect of the invention, there is provided a TFT having a gate wiring on a gate insulating film, and having a metal film deposited by an electrolytic plating method on a side surface and an upper surface of the gate wiring. It is a semiconductor device.
[0010]
According to another aspect of the invention, there is provided a semiconductor device having a CMOS circuit formed of an n-channel TFT and a p-channel TFT, wherein the n-channel TFT and the p-channel TFT are arranged on a gate insulating film on a gate wiring. And the gate wiring has a metal film on a side surface and an upper surface.
[0011]
According to another aspect of the invention, in a semiconductor device including a CMOS circuit formed of an n-channel TFT and a p-channel TFT, gate insulation is provided on each active layer of the n-channel TFT and the p-channel TFT. A gate wiring on the gate insulating film, and a metal film covering a side surface and an upper surface of the gate wiring, and an active layer of the n-channel TFT is in contact with the channel forming region and the channel forming region. A first impurity region; a second impurity region in contact with the first impurity region; a third impurity region in contact with the second impurity region; and the gate wiring overlapping the channel formation region. The width of the first impurity region is determined by the thickness of the metal film formed on the side surface of the gate wiring.
[0012]
According to another aspect of the invention, there is provided a semiconductor device including a CMOS circuit formed of an n-channel TFT and a p-channel TFT, wherein a gate insulating film is formed on an active layer, and a gate wiring is formed on the gate insulating film. A metal film covering the side surface and the upper surface of the gate wiring,
An active layer of the n-channel TFT includes a channel formation region, a first impurity region in contact with the channel formation region, a second impurity region in contact with the first impurity region, and a third impurity in contact with the second impurity region. And the length of the channel formation region, the width of the gate wiring, the length of the first impurity region, and the film thickness of the metal film coincide with each other through the gate insulating film,
In the third impurity region, the catalyst element used for crystallization of the active layer is 1 × 10 6. ¹⁷ ~ 1x10 ²⁰ atoms / cm ^Three It is a semiconductor device characterized by existing at a concentration of
[0013]
According to another aspect of the invention, there is provided a step of crystallizing a semiconductor layer formed on a substrate having an insulating surface to form an active layer, a step of forming a gate insulating film on the active layer, and the gate insulation. A step of forming a gate wiring on the film; a step of forming a first impurity region by adding an impurity using the gate wiring as a mask; and a step of forming a metal film on a side surface and an upper portion of the gate wiring by an electrolytic plating method Adding a impurity by using the metal film as a mask to form a fourth impurity region in the p-channel type thin film transistor; adding a impurity by using the metal film as a mask to form a second impurity region; And a step of forming a third impurity region by adding an impurity to a selected portion of the active layer.
[0014]
According to another aspect of the invention, there is provided a step of adding a catalytic element to a semiconductor layer formed on a substrate having an insulating surface, a step of crystallizing the semiconductor layer by heat treatment, and a step of forming the active layer. Forming a gate insulating film on the layer; forming a gate wiring on the gate insulating film; adding a impurity using the gate wiring as a mask to form a first impurity region;
Forming a metal film on a side surface and an upper portion of the gate wiring by an electrolytic plating method, adding an impurity using the metal film as a mask to form a fourth impurity region in a p-channel thin film transistor, and A semiconductor device comprising: a step of forming a second impurity region by adding an impurity using a mask; and a step of forming a third impurity region by adding an impurity to a selected portion of the active layer. This is a manufacturing method.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
[Example 1]
In this embodiment, a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.
[0016]
First, as the substrate 301, for example, a glass substrate represented by a 1737 glass substrate manufactured by Corning was used. Then, a base film 302 made of a silicon oxide film was formed to a thickness of 200 nm on the surface of the substrate 301 on the side where the TFT is formed. The base film 302 may be a silicon nitride film deposited or only a silicon oxynitride film. As a method for forming the base film, a plasma CVD method, a thermal CVD method, or a sputtering method may be used.
[0017]
Next, an amorphous silicon film was formed to a thickness of 30 nm on the base film 302 by plasma CVD. The method for forming the amorphous silicon film may be a thermal CVD method or a sputtering method. After the amorphous silicon film was dehydrogenated, a crystallization process was performed to form a polycrystalline silicon film.
[0018]
In this crystallization step, a known laser crystallization technique or thermal crystallization technique may be used. In this embodiment, a pulsed transmission type KrF excimer laser beam is condensed into a linear shape and irradiated to the amorphous silicon film to form a crystalline silicon film.
[0019]
In this embodiment, the initial film is used as an amorphous silicon film, but a microcrystalline silicon film may be used as the initial film, or a crystalline silicon film may be formed directly.
[0020]
The crystalline silicon film thus formed was patterned to form active layers 303 and 304 made of island-like silicon layers.
[0021]
Note that after the crystalline silicon film is formed, excimer laser light may be irradiated to increase crystallinity. Further, it may be performed after the active layers 303 and 304 are formed.
[0022]
Next, a gate insulating film 305 made of a silicon oxide film was formed to a thickness of 100 nm so as to cover the active layers 303 and 304. Subsequently, gate wirings 306 and 307 having a laminated structure of tantalum and tantalum nitride were formed on the gate insulating film 305. Although another metal can be used for the gate wiring 306, a material having a high etching selectivity with respect to silicon is preferable in consideration of a later process. (Fig. 2 (A))
[0023]
A resist mask 308 was formed over the gate insulating film 305 so as to cover the entire region to be a later p-channel thin film transistor (hereinafter referred to as PTFT).
[0024]
In this state, the first step of adding phosphorus was performed. Here, since the impurity is added through the gate insulating film, the acceleration voltage is set to 80 KeV. The first impurity region 309 thus formed has a phosphorus concentration of 1 × 10 5. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three (Preferably 3 × 10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three ) To adjust the dose. The phosphorus concentration at this time is expressed as (n ^- ). The first impurity region was formed in a self-aligned manner using the gate wiring 306 as a mask. The first impurity region 309 functions as an LDD region. (Fig. 2 (B))
[0025]
Next, in this example, CuSO _Four ・ 5H ₂ Copper (Cu) was deposited to 0.1 to 1 μm (preferably 0.2 to 0.5 μm) on the side and top surfaces of the conductive layer by a known electrolytic plating method using an O electrolyte. (Fig. 2 (C))
[0026]
As shown in FIG. 1, the electrolytic plating method is performed by immersing two electrodes in an electrolyte solution 103 and causing an electrochemical change on both electrode surfaces when electric current is passed from the outside. Therefore, the cathode electrode 101 (the electrode on the metal deposition side) from which + ions in the liquid are discharged is used as the gate wiring, and the anode electrode 102 in which − ions are discharged or the metal is dissolved to form metal ions is formed as Cu. If the electrode is formed and an electric current flows through the contact pad, a metal film made of Cu can be deposited on the side wall and upper part of the gate wiring.
[0027]
The electrolytic plating method is a phenomenon in which metal ions are reduced and deposited at the cathode electrode, and the amount of electrode reaction is proportional to the amount of current applied, so the thickness of the deposited metal film can be easily adjusted, and the gate electrode It is easy to equalize the film thickness of the metal film deposited on the side surface and the upper surface of the metal film.
[0028]
After forming the metal films 311, 312, a resist mask 313 was formed so as to cover the entire NTFT.
[0029]
In this state, a step of adding boron was performed. Here, the acceleration voltage is 10 KeV, and the fourth impurity region 314 is formed. Boron is 3 × 10 ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (Preferably 5 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three The dose was adjusted so as to be contained at a concentration of The boron concentration at this time is expressed as (p ⁺⁺ ). In addition, a channel formation region 315 of the PTFT is defined. (Fig. 2 (D))
[0030]
Next, a resist mask 316 was formed so as to cover the entire PTFT.
[0031]
In this state, a second step of adding phosphorus was performed. Also in this case, the applied voltage was set to 80 KeV. In the second impurity addition (phosphorus doping) step, the second impurity region 317 is formed in a self-aligning manner using the metal layer 311 as a doping mask, and phosphorus is 2 × 10 6. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three (Preferably 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three The dose was adjusted so that it was included at the concentration of The phosphorus concentration at this time is represented by (n). The second impurity region 317 functions as an LDD region. (Figure 2 (E))
[0032]
Next, a resist mask 318 covering a part of a region to be a later n-channel TFT (hereinafter referred to as NTFT) and a resist mask 319 covering the entire PTFT were formed.
[0033]
In this state, the third step of adding phosphorus was performed to form the third impurity region 320. Here, the acceleration voltage is 10 KeV, and phosphorus is 1 × 10 3 in the third impurity region. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Preferably 2 × 10 ²⁰ ~ 5x10 ^{twenty one} atoms / cm ^Three The dose was adjusted so that it was included at the concentration of The phosphorus concentration at this time is expressed as (n ⁺ ). The third impurity region 320 functions as a source region or a drain region. (Fig. 3 (A))
[0034]
The resist masks 318 and 319 were removed, and a protective film 321 was formed to cover the entire region to be the later NTFT and the entire region to be the later PTFT. At this time, the silicon nitride film provided as a protective film prevents the gate wirings (tantalum films) 306 and 307 and the metal films (copper films) 311 and 312 from being oxidized. As the protective film, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used, and the film thickness range is 1 to 30 nm, preferably 5 to 20 nm. (Fig. 3 (B))
[0035]
Since the PTFT is originally highly reliable, it may be advantageous to provide an on-current without providing an LDD region or the like without any problem. In this embodiment, both the LDD region and the offset region are formed with respect to the PTFT. Not done.
[0036]
Thus, finally, a channel formation region, a first impurity region, a second impurity region, and a third impurity region are formed in the active layer of the NTFT. _ov = 0.5-3.0 μm (1.0-1.5 μm), L _off = 0.5 to 3.0 μm (1.0 to 2.0 μm). Only the channel formation region and the fourth impurity region were formed in the active layer of the PTFT.
[0037]
An LDD region could be formed in a self-aligned manner by forming a metal film on the side and top surfaces of the gate wiring by electrolytic plating and adding impurities using the metal film as a mask. Further, if the thickness of the metal film is changed, the length (width) of the LDD region can be changed.
[0038]
[Example 2]
The TFT manufactured in Example 1 (FIG. 3B) is used as a driver circuit, and the NTFT manufactured in the pixel TFT of the active matrix substrate by the method shown in Example 1 (however, has a multi-gate structure). The structure of the storage capacitor connected to the TFT in the pixel portion of the active matrix liquid crystal display device employing the above will be described with reference to FIG.
[0039]
A first interlayer insulating film 322 was formed to a thickness of 1 μm. In this embodiment, an acrylic resin film is used. After forming the first interlayer insulating film 322, source wirings 323, 324, and 325 and drain wirings 326 and 327 made of a metal material were formed. In this embodiment, a three-layer wiring having a structure in which an aluminum film containing titanium is sandwiched between titanium is used.
[0040]
After the source wiring and the drain wiring were formed in this way, a 50 nm thick silicon nitride film 328 was formed as the first interlayer insulating film. A second interlayer insulating film 329 was formed thereon. The second interlayer insulating film 329 employs a structure in which an organic resin film is stacked on a 50 nm thick silicon oxide film. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. An organic resin film other than those described above can also be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate.
[0041]
Next, a light shielding layer 330 was formed in a part of the pixel region on the second interlayer insulating film 329. The light shielding layer 330 may be formed using a metal material such as aluminum, titanium, or tantalum, a film containing these metals as a main component, or an organic resin film. Here, titanium was formed by a sputtering method.
[0042]
When the light shielding film is formed, a third interlayer insulating film 331 is formed. The third interlayer insulating film 331 is preferably formed using an organic resin film, like the second interlayer insulating film 329. Then, a contact hole reaching the drain electrode 327 was formed in the second interlayer insulating film 329 and the third interlayer insulating film 331, and the pixel electrode 332 was formed. The pixel electrode 332 may be a transparent conductive film in the case of a transmissive liquid crystal display device, and a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method, and a pixel electrode 332 was formed.
[0043]
When the state of FIG. 4A is formed, an alignment film 333 is formed. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A transparent conductive film (pixel electrode) 335 and an alignment film 334 were formed on the opposite substrate 336. After the alignment film was formed, it was rubbed so that the liquid crystal molecules were aligned in parallel with a certain pretilt angle.
[0044]
Through the above steps, the pixel matrix circuit, the substrate on which the CMOS circuit is formed, and the counter substrate are bonded together by a known cell assembling process via a sealant or a spacer (both not shown). Thereafter, a liquid crystal material 337 was injected between both substrates and completely sealed with a sealing material (not shown). Thus, the active matrix liquid crystal display device shown in FIG. 4B is completed.
[0045]
According to this embodiment, a metal film is formed on the side surface and the upper surface of the gate wiring, and the completed CMOS circuit has excellent reliability, so that the reliability of the entire circuit is greatly improved. Further, it was found that when the structure as in this example is used, the characteristic balance between NTFT and PTFT is improved, so that it is difficult for malfunctions to occur.
[0046]
[Example 3]
In the manufacturing method of Example 1, after the step illustrated in FIG. 2A is completed, resist masks 403 and 404 that cover the entire PTFT and the entire pixel portion are formed, and the first phosphorus is added. It was.
As a result, in the NTFT of the driver circuit portion, the first impurity region 309 and the channel formation region 310 were formed in a self-aligning manner using the gate wiring 306 as a mask. (Fig. 5 (A))
[0047]
Next, metal films 311, 312, 406 and 407 were formed on the side surfaces and upper portions of the gate wirings 311, 312, 401 and 402 by electrolytic plating. (Fig. 5 (B))
[0048]
Subsequent steps were performed according to Example 2, and an active matrix liquid crystal display device as shown in FIG. 7B was completed.
[0049]
[Example 4]
In the first embodiment, a stack of tantalum and tantalum nitride is used as the gate wirings 306 and 307, and copper is used as the metal films 311, 312. However, in this embodiment, a low-resistance metal such as Al, W, Mo, or the like is used as the material for the gate wiring. , Cu, Au, Nb, and the like. Further, as the metal film, a high melting point metal material, for example, a metal, such as Ta, Mo, and W, is used.
If the refractory metal is formed on the side surface and the upper portion of the gate wiring as in this embodiment, the refractory metal protects the gate wiring, and therefore has an advantage that thermal activation can be performed at a high temperature. This embodiment can be used in combination with the first to third embodiments.
[0050]
[Example 5]
In the first embodiment, tantalum and tantalum nitride are laminated as the gate wirings 306 and 307, and copper is used as the metal films 311 and 312. However, in this embodiment, a refractory metal such as Ta, It was formed using a material mainly composed of W, Mo, Cr, Ni, Zn or the like.
Since both the gate wiring and the metal film are refractory metals, they can be thermally activated at a high temperature, and by making the two metals the same, it is possible to make the metals difficult to peel off. This embodiment can be used in combination with the first to third embodiments.
[0051]
[Example 6]
In this embodiment, an example in which a crystalline semiconductor film used as a semiconductor layer in Embodiment 1 is formed by a thermal crystallization method using a catalytic element is shown. In the case of using a catalyst element, it is desirable to use the techniques disclosed in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329.
[0052]
Here, FIG. 8 shows an example in which the technique disclosed in Japanese Patent Laid-Open No. 7-130652 is applied to the present invention. First, a silicon oxide film 602 was provided on a substrate 601, and an amorphous silicon film 603 was formed thereon. Furthermore, a nickel acetate layer solution containing 10 ppm of nickel in terms of weight was applied to form a nickel-containing layer 604. (Fig. 8 (A))
[0053]
Next, after a dehydrogenation step at 500 ° C. for 1 hour, a heat treatment was performed at 500 to 650 ° C. for 4 to 12 hours (550 ° C. for 14 hours in this embodiment) to form a crystalline silicon film 605. The crystalline silicon film 605 thus obtained had very excellent crystallinity. (Fig. 8 (B))
[0054]
Further, the technique disclosed in Japanese Patent Laid-Open No. 8-78329 enables selective crystallization of an amorphous semiconductor film by selectively adding a catalytic element. The case where this technique is applied to the present invention will be described with reference to FIG.
[0055]
First, a silicon oxide film 702 was provided over a glass substrate 701, and an amorphous silicon film 703 and a silicon oxide film 704 were continuously formed thereon.
[0056]
Next, the silicon oxide film 704 was patterned to selectively form opening portions 705, and then a nickel acetate salt solution containing 10 ppm of nickel in terms of weight was applied. As a result, a nickel-containing layer 706 was formed, and the nickel-containing layer 706 was in contact with only the amorphous silicon film 702 exposed from the opening 705. (Fig. 9 (A))
[0057]
Next, a heat treatment was performed at 500 to 650 ° C. for 4 to 24 hours (580 ° C. for 14 hours in this embodiment) to form a crystalline silicon film 707. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and the crystallization proceeds laterally therefrom. The crystalline silicon film 707 formed in this way is formed by a collection of rod-like or needle-like crystals, and each crystal grows macroscopically in a specific direction, so that the crystallinity is uniform. There are advantages.
[0058]
The catalyst elements that can be used in the above two techniques are not only nickel (Ni) but also germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt ( Elements such as Co), platinum (Pt), copper (Cu), and gold (Au) may be used.
[0059]
If a crystalline semiconductor film (including a crystalline silicon film or a crystalline silicon germanium film) is formed using the above technique and patterned, a semiconductor layer of a TFT can be formed. Although a TFT manufactured from a crystalline semiconductor film can provide excellent characteristics, high reliability is required. However, by adopting the TFT structure of the present invention, it has become possible to produce a TFT that makes the most of the technique of this embodiment. This embodiment can be used in combination with any one of Embodiments 1 to 5.
[0060]
[Example 7]
In this example, as a method of forming the semiconductor layer used in Example 1, after forming a crystalline semiconductor film using the above catalytic element using an amorphous semiconductor film as an initial film as in Example 6, An example in which the step of removing the catalyst element from the crystalline semiconductor film is performed will be described. In the present embodiment, the technique described in Japanese Patent Application Laid-Open No. 10-135468 or Japanese Patent Application Laid-Open No. 10-135469 is used as the method.
[0061]
The technique described in the publication is a technique for removing a catalytic element used for crystallization of an amorphous semiconductor film by using a gettering action of phosphorus after crystallization. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 10. ¹⁷ atoms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atoms / cm ^Three It can be reduced to.
[0062]
The configuration of this example will be described with reference to FIG. Here, an alkali-free glass substrate typified by Corning's 1737 substrate was used. FIG. 20A shows a state in which the base film 802 and the crystalline silicon film 803 are formed by using the crystallization technique shown in Embodiment 6. A silicon oxide film 804 for masking is formed to a thickness of 150 nm on the surface of the crystalline silicon film 803, an opening is provided by patterning, and a region where the crystalline silicon film is exposed is provided. Then, a step of adding phosphorus was performed to provide a region 805 in which phosphorus was added to the crystalline silicon film.
[0063]
In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours (in this embodiment, 600 ° C. and 12 hours), a region 805 in which phosphorus is added to the crystalline silicon film becomes a gettering site. The catalytic element remaining in the crystalline silicon film 803 could be moved to the region 805 to which phosphorus was added.
[0064]
Then, the silicon oxide film 804 for mask and the region 805 to which phosphorus is added are removed by etching, so that the concentration of the catalytic element used in the crystallization step is 1 × 10. ¹⁷ atoms / cm ^Three A crystalline silicon film reduced to the following could be obtained. This crystalline silicon film could be used as the active layer of the TFT of the present invention shown in Example 1 as it was. This example can be used in combination with any of Examples 1-5.
[0065]
[Example 8]
In this embodiment, another embodiment in which a semiconductor layer and a gate insulating film are formed in the process of manufacturing the TFT of the present invention shown in Embodiment 1 will be described.
[0066]
Here, a substrate having a heat resistance of at least about 700 to 1100 ° C. is necessary, and a quartz substrate 901 is used. A crystalline semiconductor film was formed by using the techniques shown in Examples 6 and 7, and active layers 902 and 903 were formed by patterning into island shapes. Then, the gate insulating film 904 was formed using a film containing silicon oxide as a main component so as to cover the active layers 902 and 903. In this embodiment, a silicon nitride oxide film with a thickness of 70 nm is formed by plasma CVD. (FIG. 21 (A))
[0067]
Then, heat treatment was performed in an atmosphere containing halogen (typically chlorine) and oxygen. In this example, the temperature was 950 ° C. for 30 minutes. The treatment temperature may be selected in the range of 700 to 1100 ° C., and the treatment time may be selected between 10 minutes and 8 hours. (Fig. 21 (B))
[0068]
As a result, under the conditions of this example, a thermal oxide film was formed at the interface between the active layers 902 and 903 and the gate insulating film 904, and a gate insulating film 907 was formed.
[0069]
The gate insulating film 907 manufactured through the above steps had a high withstand voltage, and the interface between the active layers 905 and 906 and the gate insulating film 907 was very good. In order to obtain the structure of the TFT of the present invention, the subsequent steps may be performed according to the first embodiment.
[0070]
Of course, the combination of the sixth embodiment and the seventh embodiment with this embodiment may be appropriately determined by the practitioner.
[0071]
[Example 9]
In addition to the nematic liquid crystal, various liquid crystals can be used for the above-described liquid crystal display device of the present invention. For example, 1998, SID, "Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability" by H. Furue et al., 1997, SID DIGEST, 841, "A Full -Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time "by T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 671-673," Thresholdless antiferroelectricity in liquid crystals and its application to The liquid crystal disclosed in "displays" by S. Inui et al. or US Pat. No. 5,945,569 can be used.
[0072]
Using a ferroelectric liquid crystal (FLC) exhibiting an isotropic phase-cholesteric phase-chiral smectic C phase transition series, a cholesteric phase-chiral smectic C phase transition is applied while applying a DC voltage, and the cone edge is substantially in the rubbing direction. The electro-optical characteristics of the matched monostable FLC are shown in FIG. The display mode using the ferroelectric liquid crystal as shown in FIG. 10 is called “Half-V-shaped switching mode”. The vertical axis of the graph shown in FIG. 10 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. Regarding "Half-V-shaped switching mode", Terada et al., "Half-V-shaped switching mode FLCD", Proceedings of the 46th Joint Physics Related Conference, March 1999, p. 1316, and Yoshihara et al. "Time-division full-color LCD with ferroelectric liquid crystal", Liquid Crystal Vol. 3, No. 3, page 190.
[0073]
As shown in FIG. 10, it can be seen that when such a ferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible. In the liquid crystal display device of the present invention, a ferroelectric liquid crystal exhibiting such electro-optical characteristics can also be used.
[0074]
A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optic response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) is also found. Has been.
[0075]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.
[0076]
In addition, since such a thresholdless antiferroelectric mixed liquid crystal is used for the liquid crystal display device of the present invention, low voltage driving is realized, so that low power consumption is realized.
[0077]
Example 10
The CMOS circuit and the pixel portion formed by implementing the present invention can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EL display). That is, the present invention can be implemented in all electric appliances in which these electro-optical devices are incorporated in the display unit.
[0078]
Such electric appliances include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned. Examples of these are shown in FIGS. 11, 12 and 13.
[0079]
FIG. 11A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.
[0080]
FIG. 11B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The present invention can be applied to the display portion 2102 and other signal control circuits.
[0081]
FIG. 11C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.
[0082]
FIG. 11D shows a goggle type display, which includes a main body 2301, a display portion 2302, an arm portion 2303, and the like. The present invention can be applied to the display portion 2302 and other signal control circuits.
[0083]
FIG. 11E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.
[0084]
FIG. 11F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.
[0085]
FIG. 12A illustrates a front projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 constituting a part of the projection device 2601 and other signal control circuits.
[0086]
FIG. 12B illustrates a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like. The present invention can be applied to the liquid crystal display device 2808 constituting a part of the projection device 2702 and other signal control circuits.
[0087]
FIG. 12C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 12A and 12B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0088]
FIG. 12D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 12D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0089]
However, the projector shown in FIG. 12 shows a case where a transmissive electro-optical device is used, and an application example in a reflective electro-optical device and an EL display device is not shown.
[0090]
FIG. 13A shows a mobile phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, and the like. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal control circuits.
[0091]
FIG. 13B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003 and other signal circuits.
[0092]
FIG. 13C shows a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0093]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-8.
[0094]
Example 11
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described.
[0095]
FIG. 14A is a top view of an EL display device using the present invention. In FIG. 14A, reference numeral 4010 denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, 4013 denotes a gate side driver circuit, and each driver circuit reaches an FPC 4017 through wirings 4014 to 4016 to an external device. Connected.
[0096]
At this time, a cover material 6000, a sealing material (also referred to as a housing material) 7000, and a sealing material (second sealing material) 7001 are provided so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion.
[0097]
FIG. 14B shows a cross-sectional structure of the EL display device of this embodiment. A driver circuit TFT (here, an n-channel TFT and a p-channel TFT are combined on a substrate 4010 and a base film 4021). And the pixel portion TFT 4023 (however, only the TFT for controlling the current to the EL element is shown here). These TFTs may be TFTs manufactured according to the present invention.
[0098]
The present invention can be used for the driver circuit TFT 4022 and the pixel portion TFT 4023.
[0099]
When the driving circuit TFT 4022 and the pixel portion TFT 4023 are completed using the present invention, a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on the interlayer insulating film (planarization film) 4026 made of a resin material. A pixel electrode 4027 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (referred to as ITO) or a compound of indium oxide and zinc oxide can be used. Then, after the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.
[0100]
Next, an EL layer 4029 is formed. The EL layer 4029 may have a stacked structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, a vapor deposition method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.
[0101]
In this embodiment, the EL layer is formed by vapor deposition using a shadow mask. Color display is possible by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but either method may be used. Needless to say, an EL display device emitting monochromatic light can also be used.
[0102]
After the EL layer 4029 is formed, a cathode 4030 is formed thereon. It is desirable to remove moisture and oxygen present at the interface between the cathode 4030 and the EL layer 4029 as much as possible. Therefore, it is necessary to devise such that the EL layer 4029 and the cathode 4030 are continuously formed in a vacuum, or the EL layer 4029 is formed in an inert atmosphere and the cathode 4030 is formed without being released to the atmosphere. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0103]
In this embodiment, a stacked structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 4030. Specifically, a 1 nm-thick LiF (lithium fluoride) film is formed on the EL layer 4029 by evaporation, and a 300 nm-thick aluminum film is formed thereon. Of course, you may use the MgAg electrode which is a well-known cathode material. The cathode 4030 is connected to the wiring 4016 in the region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and is connected to the FPC 4017 through a conductive paste material 4032.
[0104]
In order to electrically connect the cathode 4030 and the wiring 4016 in the region indicated by 4031, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These may be formed when the interlayer insulating film 4026 is etched (when the pixel electrode contact hole is formed) or when the insulating film 4028 is etched (when the opening before the EL layer is formed). In addition, when the insulating film 4028 is etched, the interlayer insulating film 4026 may be etched all at once. In this case, if the interlayer insulating film 4026 and the insulating film 4028 are the same resin material, the shape of the contact hole can be improved.
[0105]
A passivation film 6003, a filler 6004, and a cover material 6000 are formed so as to cover the surface of the EL element thus formed.
[0106]
Further, a sealing material is provided inside the cover material 6000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.
[0107]
At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0108]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0109]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0110]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0111]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0112]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 7000 and the sealing material 7001 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are electrically connected to the FPC 4017 through the sealing material 7000 and the sealing material 7001 in the same manner.
[0113]
[Example 12]
In this embodiment, an example of manufacturing an EL display device having a different form from that of Embodiment 11 by using the present invention will be described with reference to FIGS. 15A and 15B. Components having the same numbers as those in FIGS. 14 (A) and 14 (B) indicate the same parts, and thus description thereof is omitted.
[0114]
FIG. 15A is a top view of the EL display device of this embodiment, and FIG. 15B is a cross-sectional view taken along line AA ′ of FIG.
[0115]
According to the tenth embodiment, the passivation film 6003 is formed so as to cover the surface of the EL element.
[0116]
Further, a filler 6004 is provided so as to cover the EL element. The filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0117]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0118]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0119]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0120]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0121]
Next, after the cover material 6000 is bonded using the filler 6004, the frame material 6001 is attached so as to cover the side surface (exposed surface) of the filler 6004. The frame material 6001 is bonded by a sealing material (functioning as an adhesive) 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used if the heat resistance of the EL layer permits. Note that the sealing material 6002 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, a desiccant may be added inside the sealing material 6002.
[0122]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 6002 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.
[0123]
[Example 13]
Here, FIG. 16 shows a more detailed cross-sectional structure of the pixel portion in the EL display panel, FIG. 17A shows a top structure, and FIG. 17B shows a circuit diagram. In FIG. 16, FIG. 17 (A), and FIG.
[0124]
In FIG. 16, a switching TFT 3502 provided on a substrate 3501 is formed using the NTFT of the present invention (see Examples 1 to 7). In this embodiment, a double gate structure is used. However, there is no significant difference in structure and manufacturing process, and thus description thereof is omitted. However, the double gate structure substantially has a structure in which two TFTs are connected in series, and there is an advantage that the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure may be used, and a triple gate structure or a multi-gate structure having more gates may be used.
[0125]
The current control TFT 3503 is formed using the NTFT of the present invention. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current control TFT by the wiring 36. A wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.
[0126]
At this time, it is very important that the current control TFT 3503 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and it is also an element with a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided in the current control TFT so as to overlap the gate electrode through the gate insulating film is very effective.
[0127]
In this embodiment, the current control TFT 3503 is illustrated as a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.
[0128]
Further, as shown in FIG. 17A, the wiring that becomes the gate electrode 37 of the current control TFT 3503 overlaps the drain wiring 40 of the current control TFT 3503 with an insulating film in the region indicated by 3504. At this time, a capacitor is formed in a region indicated by 3504. This capacitor 3504 functions as a capacitor for holding the voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is always applied.
[0129]
A first passivation film 41 is provided on the switching TFT 3502 and the current control TFT 3503, and a planarizing film 42 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0130]
Reference numeral 43 denotes a pixel electrode (EL element cathode) made of a highly reflective conductive film, which is electrically connected to the drain of the current control TFT 3503. As the pixel electrode 43, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used.
[0131]
A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.
[0132]
There are various types of PPV organic EL materials. For example, “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,” Polymers for Light Emitting. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and Japanese Patent Application Laid-Open No. 10-92576 may be used.
[0133]
As a specific light emitting layer, cyanopolyphenylene vinylene may be used for a light emitting layer that emits red light, polyphenylene vinylene may be used for a light emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm).
[0134]
However, the above example is an example of an organic EL material that can be used as a light emitting layer, and is not necessarily limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer.
[0135]
For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0136]
In this embodiment, the EL layer has a laminated structure in which a hole injection layer 46 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light emitting layer 45. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. What can form into a film at low temperature as much as possible is preferable.
[0137]
When the anode 47 is formed, the EL element 3505 is completed. Note that the EL element 3505 here refers to a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. As shown in FIG. 17A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.
[0138]
By the way, in the present embodiment, a second passivation film 48 is further provided on the anode 47. The second passivation film 48 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to cut off the EL element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic EL material and the meaning of suppressing degassing from the organic EL material. This increases the reliability of the EL display device.
[0139]
As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 16, and includes a switching TFT having a sufficiently low off-current value and a current control TFT resistant to hot carrier injection. Have. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.
[0140]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-9. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 10.
[0141]
Example 14
In this embodiment, a structure in which the structure of the EL element 3505 is inverted in the pixel portion described in Embodiment 13 will be described. FIG. 18 is used for the description. Note that the only difference from the structure of FIG. 16 is the EL element portion and the current control TFT, and other descriptions are omitted.
[0142]
In FIG. 18, a current control TFT 3503 is formed using a PTFT.
[0143]
In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Of course, a conductive film made of a compound of indium oxide and tin oxide may be used.
[0144]
Then, after banks 51a and 51b made of insulating films are formed, a light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.
[0145]
In the case of the present embodiment, the light generated in the light emitting layer 52 is emitted toward the substrate on which the TFT is formed, as indicated by the arrows.
[0146]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-9. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 10.
[0147]
Example 14
In this embodiment, FIGS. 19A to 19C show an example of a pixel having a structure different from the circuit diagram shown in FIG. In this embodiment, 3801 is a source wiring of the switching TFT 3802, 3803 is a gate wiring of the switching TFT 3802, 3804 is a current control TFT, 3805 is a capacitor, 3806 and 3808 are current supply lines, and 3807 is an EL element. .
[0148]
FIG. 19A shows an example in which the current supply line 3806 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 3806. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0149]
FIG. 19B illustrates an example in which the current supply line 3808 is provided in parallel with the gate wiring 3803. In FIG. 19B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, since the exclusive area can be shared by the power supply line 3808 and the gate wiring 3803, the pixel portion can be further refined.
[0150]
In FIG. 19C, a current supply line 3808 is provided in parallel with the gate wiring 3803 as in the structure of FIG. 19B, and two pixels are symmetrical with respect to the current supply line 3808. It is characterized in that it is formed. It is also effective to provide the current supply line 3808 so as to overlap with any one of the gate wirings 3803. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0151]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Example 1-9, 11 or 12. In addition, it is effective to use the EL display panel having the pixel structure of this embodiment as the display portion of the electronic apparatus of Embodiment 10.
[0152]
[Example 16]
In FIGS. 17A and 17B shown in Embodiment 13, the capacitor 3504 is provided to hold the voltage applied to the gate of the current control TFT 3503. However, the capacitor 3504 can be omitted. is there. In the case of Example 12, since the NTFT of the present invention as shown in Examples 1 to 8 is used as the current control TFT 3503, it has an LDD region provided so as to overlap the gate electrode through the gate insulating film. ing. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region, but this embodiment is characterized in that this parasitic capacitance is positively used in place of the capacitor 3504.
[0153]
Since the capacitance of the parasitic capacitance varies depending on the area where the gate electrode and the LDD region overlap, the capacitance of the parasitic capacitance is determined by the length of the LDD region included in the overlapping region.
[0154]
Similarly, in the structure of FIGS. 19A to 19C shown in the fourteenth embodiment, the capacitor 3805 can be omitted.
[0155]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-9, 11-15. In addition, it is effective to use the EL display panel having the pixel structure of this embodiment as the display portion of the electronic apparatus of Embodiment 10.
[0156]
【The invention's effect】
According to the present invention, the metal film can be easily deposited on the side surface and the upper portion of the gate wiring by setting the deposition conditions by electrolytic plating. Further, an impurity element can be added to the island-like semiconductor layer using this metal film as a mask, so that the LDD regions can be formed with a uniform width on both sides of the gate wiring.
As a result, a semiconductor device having a GOLD structure can be obtained, so that a high breakdown voltage and high reliability TFT can be manufactured. Further, even if a gate voltage of 15 to 20 V is applied to the pixel TFT in the pixel portion and driven, stable operation can be obtained. As a result, the reliability of a semiconductor device including a CMOS circuit manufactured using a crystalline TFT, and more specifically, a driving circuit provided around a liquid crystal display device or an EL display device can be improved and can be used for a long time. A liquid crystal display device or an EL display device can be obtained.
[Brief description of the drawings]
FIG. 1 is a simplified diagram of an electrolytic plating method.
FIG. 2 is a cross-sectional view showing a manufacturing process of a TFT according to the present invention.
FIG. 3 is a cross-sectional view showing a manufacturing process of a TFT according to the present invention.
FIG. 4 is a cross-sectional view showing a manufacturing process of an active matrix substrate according to the present invention.
FIG. 5 is a cross-sectional view showing a manufacturing process of an active matrix substrate according to the present invention.
FIG. 6 is a cross-sectional view showing a manufacturing process of an active matrix substrate according to the present invention.
FIG. 7 is a cross-sectional view showing a manufacturing process of an active matrix substrate according to the present invention.
FIG. 8 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 9 is a cross-sectional view showing a manufacturing process of a TFT.
FIG. 10 is a diagram showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.
FIG. 11 illustrates an example of an electric appliance.
FIG. 12 is a diagram showing an example of an electric appliance.
FIG. 13 shows an example of an electric appliance.
FIG 14 illustrates a structure of an EL display device.
FIG. 15 illustrates a structure of an EL display device.
FIG 16 illustrates a structure of an EL display device.
FIG 17 illustrates a structure of an EL display device.
FIG 18 illustrates a structure of an EL display device.
FIG 19 illustrates a structure of an EL display device.
20 is a cross-sectional view showing a manufacturing process of a TFT. FIG.
FIG. 21 is a cross-sectional view showing a manufacturing process of a TFT.

Claims (6)

a pixel portion in which a plurality of pixels each having an n-channel type pixel TFT are disposed;
a liquid crystal display device having a driving circuit having an n-channel driving circuit TFT and a p-channel driving circuit TFT,
The n-channel pixel TFT and the n-channel driver TFT are as follows:
A first active layer on an insulating surface;
A first gate insulating film on the first active layer;
A first gate wiring on the first gate insulating film;
A first metal film formed on a side surface and an upper surface of the first gate wiring,
The first active layer includes a first channel formation region, an n-type first impurity region sandwiching the first channel formation region, the first channel formation region, and the first impurity region. An n-type second impurity region sandwiched, and an n-type third impurity region sandwiching the first channel formation region, the first impurity region, and the second impurity region,
The impurity added to the first impurity region has a lower concentration than the impurity added to the second impurity region, and the impurity added to the second impurity region is added to the third impurity region. Lower concentration than the impurities produced,
The first channel formation region overlaps with the first gate wiring through the first gate insulating film,
The first impurity region overlaps with a first metal film formed on a side surface of the first gate wiring via the first gate insulating film,
The second impurity region does not overlap with the first metal film formed on the side surface of the first gate wiring via the first gate insulating film,
The p-channel type driving circuit TFT is:
A second active layer on the insulating surface;
A second gate insulating film on the second active layer;
A second gate wiring on the second gate insulating film;
A second metal film formed on a side surface and an upper surface of the second gate wiring,
The second active layer has a second channel formation region and a p-type fourth impurity region sandwiching the second channel formation region,
The second channel formation region overlaps with the second gate wiring and the second metal film formed on the side surface of the second gate wiring through the second gate insulating film,
The first gate wiring and the second gate wiring are made of a material mainly composed of Cu,
The liquid crystal display device, wherein the first metal film and the second metal film are made of a refractory metal material. 2. The liquid crystal display device according to claim 1, wherein the refractory metal material is Ta, W, Mo, Cr, Ni, or Zn. a pixel portion in which a plurality of pixels each having an n-channel type switching TFT and an n-channel type current control TFT are disposed;
An EL display device having an n-channel type driving circuit TFT and a p-channel type driving circuit TFT,
The n-channel switching TFT, the n-channel current control TFT, and the n-channel driver circuit TFT are:
A first active layer on an insulating surface;
A first gate insulating film on the first active layer;
A first gate wiring on the first gate insulating film;
A first metal film formed on a side surface and an upper surface of the first gate wiring,
The first active layer includes a first channel formation region, an n-type first impurity region sandwiching the first channel formation region, the first channel formation region, and the first impurity region. An n-type second impurity region sandwiched, and an n-type third impurity region sandwiching the first channel formation region, the first impurity region, and the second impurity region,
The impurity added to the first impurity region has a lower concentration than the impurity added to the second impurity region, and the impurity added to the second impurity region is added to the third impurity region. Lower concentration than the impurities produced,
The first channel formation region overlaps with the first gate wiring through the first gate insulating film,
The first impurity region overlaps with a first metal film formed on a side surface of the first gate wiring via the first gate insulating film,
The second impurity region does not overlap with the first metal film formed on the side surface of the first gate wiring via the first gate insulating film,
The p-channel type driving circuit TFT is:
A second active layer on the insulating surface;
A second gate insulating film on the second active layer;
A second gate wiring on the second gate insulating film;
A second metal film formed on a side surface and an upper surface of the second gate wiring,
The second active layer has a second channel formation region and a p-type fourth impurity region sandwiching the second channel formation region,
The second channel formation region overlaps with the second gate wiring and the second metal film formed on the side surface of the second gate wiring through the second gate insulating film,
The first gate wiring and the second gate wiring are made of a material mainly composed of Cu,
The EL display device, wherein the first metal film and the second metal film are made of a refractory metal material. 4. The EL display device according to claim 3, wherein the refractory metal material is Ta, W, Mo, Cr, Ni, or Zn. 5. The EL display device according to claim 3, wherein the n-channel type current control TFT has a multi-gate structure. An electronic apparatus comprising the liquid crystal display device according to claim 1 or 2 or the EL display device according to any one of claims 2 to 5 as a display unit.

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