JP2002025907A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for obtaining a crystalline semiconductor film of large grain diameter by controlling a position by a simple method. SOLUTION: The manufacturing method of a semiconductor device comprises a process for forming an amorphous semiconductor film 103 on an insulator 102, a process of forming a mask formed of an insulation film 104 on the amorphous semiconductor film 103, and adding an element, which promotes crystallization, to a region of an amorphous semiconductor film exposed from an opening part of the mask, a process of forming a polycrystalline semiconductor region 103b selectively by carrying out heating treatment after the addition process, and a process of forming a crystalline semiconductor film by irradiating laser beam whose wavelength is in the range of 390 to 600 nm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor (hereinafter referred to as a TFT) using a semiconductor film which is crystallized by irradiating a laser beam. In particular, the present invention provides a semiconductor device which functions by utilizing semiconductor characteristics manufactured by including a step of crystallizing an amorphous semiconductor film by laser light in a manufacturing process, a pixel portion, and a driving circuit provided around the pixel portion. The present invention relates to a liquid crystal display device provided on the same substrate, an electro-optical device (also referred to as an electronic device) represented by an EL (electroluminescence) display device, or an electric appliance manufacturing method equipped with the electro-optical device.

[Prior art]

[0002] A method of irradiating a semiconductor film with a laser beam to obtain a crystalline semiconductor film having a large grain size has been actively studied. As a result of observing the result of crystallization of the semiconductor film using an excimer laser, it is known that a single crystal having a grain size of about several hundreds of nanometers is formed innumerably. Many lattice defects are present at an interface (hereinafter, referred to as a crystal grain boundary), and these are the causes of significantly impairing the characteristics of the semiconductor device.

Therefore, a method of increasing the crystal grain size to reduce the crystal grain boundaries and reduce the density of many lattice defects existing in the crystal grain boundaries has been considered. For example, during (and after) laser light irradiation, leaving a solid phase only in a certain region,
For other regions, there is a method of completely melting.

When a semiconductor film is solidified after irradiation with a pulse laser represented by an excimer laser, a solid phase nucleus that can serve as a crystal growth nucleus is generated in completely melted silicon, and the crystal grows at a stretch from the solid phase nucleus. However, it takes some time before solid phase nuclei are generated. When solid phase nuclei, which are solid phase nuclei, are left only at certain positions and the surrounding area is completely melted, crystal growth starts immediately from the solid phase silicon after laser beam irradiation, and the crystal grains that have grown collide with each other. Then, the crystal growth stops.

Further, in a region where the semiconductor film is completely melted by irradiating the laser beam, until a uniform nucleus (or a non-uniform nucleus) is generated, the horizontal direction with respect to the film surface (hereinafter referred to as a lateral direction). By moving the solid-liquid interface in step (1), crystal grains grow over a length of several tens of times the film thickness. Hereinafter, this phenomenon is referred to as super lateral growth. It is known that this super lateral growth usually grows in the lateral direction over 1 μm or more in the case of the Si / base SiO ₂ / substrate structure. This super lateral growth is countless uniform (non-uniform)
It is believed that the nucleation will end.

[0006] Even if it is not the above structure, there is a laser beam irradiation energy region for realizing super lateral growth. However, in practice, the energy region of laser light capable of realizing super lateral growth is very narrow, and it has not been possible to obtain a crystal having a large grain size by controlling the position.

[0007] In order to solve the above-mentioned problem, "R.
Ishihara and A. Burtsev: AM-LCD '98., P153-p156, 19
98 ", a structure of Si / SiO ₂ / metal / substrate is formed, and laser light is irradiated from above and below the substrate using an excimer laser. The laser light from below is absorbed by the metal film and turned into heat, heating the metal film to a high temperature. That is, since the metal film works as a heat accumulation layer, the cooling rate of the silicon film is low. By this method, a crystalline semiconductor film having a crystal grain size of several μm in diameter can be obtained at any place.

[0010] James S. Im of Columbia University et al. Has shown a Sequential Lateral Solidification method (hereinafter, referred to as an SLS method) that can realize super lateral growth at an arbitrary location. The SLS method is a method of growing a crystal by shifting a slit-shaped mask by one pulse by a distance (up to 0.75 μm) for super lateral growth for each shot.

[0009]

In the method of R. Ishihara et al., If a high melting point metal is used as a metal between a substrate and an insulating film (SiO ₂ ) to form a gate electrode, it is effective for a bottom gate type thin film transistor. This structure can be applied to However, when this structure is used for a top-gate thin film transistor, parasitic capacitance occurs, power consumption increases, and it is difficult to realize high-speed operation of the thin film transistor. Further, peeling may occur at the time of laser light irradiation depending on a material.

In the SLS method, a relative positioning technique between the mask and the substrate requires a precision on the order of microns, which makes the apparatus more complicated than an ordinary laser apparatus. In addition, there is a problem in throughput when the TFT is used for manufacturing a TFT applied to a liquid crystal display having a large area.

An object of the present invention is to provide a method for obtaining a crystalline semiconductor film having a large crystal grain size by controlling the position by a simpler method than the conventional method.

[0012]

In order to solve the above problems, the present invention provides a step of forming an amorphous semiconductor film on an insulator, and forming a mask made of an insulating film on the amorphous semiconductor film. A step of adding an element that promotes crystallization to the region of the amorphous semiconductor film exposed from the opening of the mask, and after the addition step, a step of performing a heat treatment to selectively form a polycrystalline semiconductor region, A method for manufacturing a semiconductor device, including a step of forming a crystalline semiconductor film by irradiating laser light having a wavelength in a range of 390 to 600 nm.

In the above invention, the laser beam is a second harmonic (wavelength: 532 nm) of a Nd: YAG laser.
It is characterized by being light.

In the above invention, the elements promoting the crystallization are nickel (Ni), germanium (G
e), iron (Fe), palladium (Pd), tin (S
n), lead (Pb), cobalt (Co), platinum (Pt),
It is characterized by being copper (Cu) or gold (Au).

Further, in the above invention, the opening of the mask is 1 μm or more and 10 μm or less.

According to another aspect of the present invention, there is provided a method of forming an amorphous semiconductor film on an insulator, and irradiating a selected region of the amorphous semiconductor film with a first laser beam to selectively form the amorphous semiconductor film. A method for manufacturing a semiconductor device, including a step of forming a crystalline semiconductor region and a step of irradiating a second laser beam to form a crystalline semiconductor film.

Further, in the above invention, the first laser light is light of an excimer laser, and the second laser light is a second harmonic (wavelength of 532 nm) of a Nd: YAG laser.
It is characterized by being light.

In the above invention, the first laser light and the second laser light are light of a second harmonic (wavelength: 532 nm) of a Nd: YAG laser.

Further, in the above invention, the first laser light and the second laser light are irradiated from the front surface, the back surface, or both surfaces of the substrate.

Another aspect of the invention is a process for forming a polycrystalline semiconductor film on an insulator, forming a mask made of an insulating film on the polycrystalline semiconductor film, and forming a mask on a region exposed from an opening of the mask. Silicon (Si), germanium (Ge),
A step of selectively forming an amorphous semiconductor region by adding any element selected from argon (Ar), oxygen (O), and hydrogen (H); and irradiating a laser beam to the crystalline semiconductor film. Forming a semiconductor device.

Further, in the above invention, the laser beam is a beam of a second harmonic (wavelength: 532 nm) of a Nd: YAG laser.

[0022]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIG. Substrate 10 on substrate 101
A base film 102 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed in order to prevent diffusion of an impurity element from the beginning. In this embodiment, the silicon oxynitride film 102a formed from SiH ₄ , NH ₃ , and N ₂ O by a plasma CVD method has a thickness of 10 to 200 nm (preferably 50 to 200 nm).
100 nm), and a silicon oxynitride hydride film 102 b similarly made of SiH ₄ and N ₂ O is formed to a thickness of 50 to 200 nm.
(Preferably 100 to 150 nm).

Next, 25 to 80 n is formed on the underlying insulating film 102.
An amorphous semiconductor film 103 having a thickness of m (preferably 30 to 60 nm) is formed by a known method such as a plasma CVD method or a sputtering method.

After the formation of the amorphous semiconductor film 103, an SiO ₂ film 104 is formed thereon. Further, a mask SiO ₂ 104 having an opening through which the surface of the amorphous semiconductor film 103 is selectively exposed is formed by patterning. In this specification, the surface of the amorphous semiconductor film in contact with the base insulating film is referred to as the back surface of the amorphous semiconductor film, and the surface of the amorphous semiconductor film in contact with the gate insulating film is referred to as the surface of the amorphous semiconductor film. Mask Si
O ₂ 104 has a thickness of 50 nm or more, and a width of an opening where the surface of the amorphous semiconductor film 103 is exposed is 1 μm or more and 10 μm or more.
μm or less.

Next, a mask Si for the amorphous semiconductor film 103 is used.
The region exposed from the opening of O ₂ 104 is crystallized.

A solution containing nickel (Ni) as a catalyst element for promoting crystallization of the amorphous semiconductor film was applied by spin coating to form a Ni-containing layer 105. In addition, as a catalyst element, in addition to nickel, cobalt (C
o), iron (Fe), palladium (Pd), platinum (P
t), copper (Cu), gold (Au), germanium (Ge)
Can be used (FIG. 1B).

In this embodiment, the mask SiO ₂ 1
In order to control so that there is not much difference between the width of the opening 04 and the width of the polycrystalline semiconductor region, an aqueous solution containing a catalyst element at a concentration of 100 ppm is applied by a spin coating method, and the solution is applied at 550 ° C. for 2 hours. A heat treatment is performed. The addition of the catalyst element may be performed by a sputtering method other than the spin coating method.

By this heat treatment, the amorphous semiconductor film 10
3 shows an amorphous semiconductor region 103a and a polycrystalline semiconductor region 10
3b can be selectively formed adjacent to each other. The polycrystalline semiconductor region 1 is formed in the opening of the mask SiO ₂ 104b.
03b is formed. Note that the width of the polycrystalline semiconductor region is
Depending on the method of controlling crystal growth, the width may be slightly larger than the width of the mask opening. Then, the mask SiO ₂ 10
4 is removed, and the second harmonic (wavelength: 532 nm) of the Nd: YAG laser is irradiated from the surface side of the amorphous semiconductor film.
Irradiation with laser light may be performed from the back surface side or both surfaces of the amorphous semiconductor film (FIG. 1C).

In this embodiment, the mask SiO ₂ 104
Was removed, but irradiation with laser light may be performed without removing it.

Here, the region where the amorphous silicon region and the polycrystalline silicon region are formed adjacent to each other has a wavelength of 390-6.
The effectiveness of crystallization by irradiating a laser beam of 00 nm will be described.

As shown in FIG.
In the light of the region (the region including the second harmonic light of the Nd: YAG laser), the absorption coefficient of amorphous silicon is more than twice as large as that of polycrystalline silicon.

Second harmonic wavelength 5 of Nd: YAG laser
At 32 nm, the absorption coefficient of amorphous silicon is 9.53
× 10 ⁴ / cm, and the absorption coefficient of polycrystalline silicon is 2.7.
It is 5 × 10 ⁴ / cm. The absorption coefficient of amorphous silicon is 3.5 times that of polycrystalline silicon. In this case, the heat generation amount distribution in the silicon film depth direction is as shown in FIG. It can be seen that the calorific value of amorphous silicon is larger than that of polycrystalline silicon.

Next, an example of a temperature history simulation result will be shown. The simulation is a model in which the second harmonic (wavelength: 532 nm) of a Nd: YAG laser is irradiated to a silicon film thickness of 55 nm on a quartz glass substrate. FIG. 23 shows the temperature history of the interface between the silicon layer and the quartz glass substrate obtained from the simulation. When the silicon layer is amorphous silicon, the highest temperature is 2583K.
On the other hand, the maximum temperature when the silicon layer is made of polycrystalline silicon is 1292K. That is, amorphous silicon is completely melted, but polycrystalline silicon is in a solid phase.

As described above, the second Nd: YAG laser
When light of a harmonic (wavelength: 532 nm) is applied to the semiconductor film in which the polycrystalline semiconductor region formed in FIG. 1B is formed (the amorphous semiconductor region and the polycrystalline semiconductor region are adjacent to each other),
The amorphous semiconductor region 103a is in a completely molten state, and the polycrystalline semiconductor region 103b is in an incompletely molten state in which a solid phase partially exists (at least a state in which the solid phase exists at the interface with the base).

Then, it is considered that the solid phase remaining in the polycrystalline semiconductor region 103b becomes a nucleus, the solid-liquid interface moves toward the completely melted region 103a, and crystal growth proceeds.

By performing the laser light irradiation once,
Super laterally grown crystal grains 106 of about 0.5 to 3 μm are formed between amorphous semiconductor region 103a and polycrystalline semiconductor region 103b. By producing the super lateral growth grains in the channel region of the TFT, a TFT having good current transport characteristics can be obtained. In particular, it is desirable to design and manufacture the TFT so that the direction of crystal growth is the length direction of the channel.

[Embodiment 2] An amorphous semiconductor region 103a and a polycrystalline semiconductor region 103b are selectively formed adjacent to an amorphous semiconductor film 103 by a method different from the method shown in the embodiment 1. The method will be described with reference to FIG.

After the amorphous semiconductor film 103 is formed, the amorphous semiconductor film 103 is irradiated with laser light through the mask 201 to selectively form the amorphous semiconductor region 103a and the polycrystalline semiconductor region 103b. Form. The laser used here may be an excimer laser or an Nd: YAG laser. Irradiation with laser light may be performed from the front surface, the back surface, or both the front and back surfaces of the amorphous semiconductor film.

The slit 201a has a thickness of 1 μm or more and 10 μm or less. The mask 201 is made of W (tungsten),
Mo (molybdenum), Ta (tantalum), TaN (tantalum nitride), Cr (chromium), Nb (niobium), TiN
A single-layer film or a laminated film made of (titanium nitride) or Si (silicon) may be formed in a predetermined pattern on a glass or quartz substrate. Any mask may be used as long as the slit is within the above range.

The amorphous semiconductor region 103a and the polycrystalline semiconductor region 103b are selectively irradiated with laser light.
Is formed. The semiconductor (silicon) film 103 in which the amorphous semiconductor region and the polycrystalline semiconductor region are adjacent to each other has N
When the second harmonic of the d: YAG laser is irradiated, the amorphous semiconductor region 103a is in a completely molten state, and the polycrystalline semiconductor region 103b is in an incompletely molten state in which a solid phase partially remains. Thereafter, the solid phase of the polycrystalline semiconductor region serves as a nucleus for crystal growth, from which crystal growth proceeds toward the amorphous semiconductor region 103a, and a super lateral growth region 202 can be realized.

[Embodiment 3] A state in which an amorphous semiconductor region and a polycrystalline semiconductor region are adjacent to each other by controlling the position on an amorphous semiconductor (silicon) film by a method different from that of the embodiment 1 or 2. The method for forming the semiconductor device will be described with reference to FIG.

A polycrystalline semiconductor film 301 is formed by irradiating the entire surface of the amorphous semiconductor film 103 with a laser beam. Then, S
An iO ₂ film 302 is formed, and a polycrystalline semiconductor film 301 corresponding to an opening of the SiO ₂ mask 302 is doped with a doping species. 303 is formed. The doping species are argon (Ar), germanium (G
e), oxygen (O), hydrogen (H), and silicon (Si), and any element may be used. Among them, silicon (Si) is preferably used as a doping species.

The method for forming the polycrystalline semiconductor film is as follows.
A crystallization method using a laser, a crystallization method using a catalytic element, or a crystallization method using heat may be used. However, when the polycrystalline semiconductor film is formed by a crystallization method using a catalytic element, it is preferable to use silicon (Si) as a doping species for destroying a crystal structure.

Nd: YAG is selectively applied to a semiconductor film in which a polycrystalline semiconductor region and an amorphous semiconductor region are formed adjacent to each other.
Irradiate the second harmonic of the laser. By irradiating the second harmonic light of the Nd: YAG laser, the amorphous semiconductor region is brought into a completely molten state, and the polycrystalline semiconductor region is brought into an incompletely molten state in which a solid phase partially remains. The solid phase remaining in the polycrystalline semiconductor region serves as a nucleus for crystal growth, from which crystal growth proceeds toward the amorphous semiconductor region, and a super lateral growth region 304 is obtained.

By using the method of this embodiment, it is possible to control the position where crystal grains are grown by the shape of the mask used in the step of doping the impurity element.

As described above, a TFT may be manufactured using the crystallized semiconductor film by using any one of the crystal growth methods described in the first to third embodiments.

[0047]

[Embodiment 1] This embodiment will be described with reference to FIGS. Here, the n-channel TFT in the pixel section
(Hereinafter referred to as a pixel TFT), a storage capacitor, and an n-channel TFT and a p of a driving circuit provided around the pixel portion.
A process for manufacturing a channel type TFT at the same time will be described.

In FIG. 5A, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass can be used as the substrate 501. Furthermore, depending on the processing temperature, polyethylene terephthalate (PET), polyethylene terephthalate (PE)
N), a plastic substrate having no optical anisotropy such as polyethersulfone (PES) can also be used.

A base film 502 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 501 where a TFT is to be formed, in order to prevent diffusion of an impurity element from the substrate 501. In this embodiment, the plasma CV
The silicon oxynitride film 502a formed from SiH ₄ , NH ₃ , and N ₂ O by Method D is formed to a thickness of 10 to 200 nm (preferably
0 to 100 nm), as well 50~200n SiH _4, N ₂ O, hydrogenated silicon oxynitride film 502b made from
m (preferably 100 to 150 nm).

The silicon oxynitride film may be formed by using a conventional parallel plate type plasma CVD method. As for the silicon oxynitride 502a, SiH ₄ is 10 (SCCM) and NH ₃ is 1
00 (SCCM), N ₂ O was introduced into the reaction chamber at 20 (SCCM), the substrate temperature was 325 ° C., the reaction pressure was 40 Pa, the discharge power density was 0.41 W / cm ² , and the discharge frequency was 60 MHz. On the other hand, hydrogenated silicon nitride oxide 502b is the SiH ₄ 5
(SCCM), N ₂ O 120 (SCCM), H ₂ 125 (SCC)
M), and introduced into the reaction chamber at a substrate temperature of 400 ° C., a reaction pressure of 20 Pa, a discharge power density of 0.41 W / cm ² , and a discharge frequency of 60 MHz. These films can be continuously formed only by changing the substrate temperature and switching the reaction gas.

The silicon oxynitride film 502a is formed so that its internal stress becomes a tensile stress, considering the substrate as a center. The silicon oxynitride film 502b also has an internal stress in the same direction, but has a smaller stress in absolute value than the silicon oxynitride film 502a.

Next, 25 to 80 nm (preferably 30 to 80 nm)
An amorphous semiconductor film (a silicon germanium film is used as a semiconductor film in this embodiment) 50 with a thickness of 60 nm) 50
3 is formed by a known method such as a plasma CVD method or a sputtering method. For example, an amorphous semiconductor film is formed to a thickness of 55 nm by a plasma CVD method. At this time, the base film 502
The amorphous semiconductor film 503 and the amorphous semiconductor film 503 can be formed continuously. For example, as described above, after a silicon oxynitride film 502a and a silicon oxynitride hydride film 502b are continuously formed by a plasma CVD method,
By switching from H ₄ , N ₂ O, and H ₂ to only SiH ₄ and H ₂ or SiH ₄ , continuous formation can be performed without once exposing to air. As a result, the hydrogenated silicon oxynitride film 5
02b can be prevented from being contaminated, and variations in TFT characteristics and fluctuations in threshold voltage can be reduced.

Next, in this example, as shown in FIG. 24A, after forming a semiconductor film according to the first embodiment, a mask is formed. After that, heat treatment is performed by adding a catalyst element, so that a polycrystalline semiconductor region is formed in part of the semiconductor film. Next, as shown in FIG. 25, N is perpendicular to a plurality of polycrystalline semiconductor regions formed over the entire semiconductor film.
d: Irradiation of light of the second harmonic (532 nm) of a YAG laser is performed to grow a crystal using the polycrystalline semiconductor region as a crystal growth nucleus. In this example, the semiconductor film is crystallized using Embodiment 1, but the method of crystallizing the semiconductor film is as follows.
The method described in Embodiment Mode 2 or 3 may be used.

After the crystallization step, the island-like semiconductor layers 504-5
06 is formed. In this embodiment, as shown in FIG. 24C, the semiconductor film is formed in an island shape so that the crystal growth proceeds in the direction of the arrow. The island-shaped semiconductor layer is rectangular and has a side of 50μ.
m or less, but the shape of the island-shaped semiconductor layer may be any shape, and is preferably such that the minimum distance from the center to the end is 50 μm or less. Any polygonal or circular shape may be used, but it is preferable to form the island-shaped semiconductor layer so that the crystal growth direction is along the channel length direction.

Next, a gate insulating film 507 covering the island-shaped semiconductor layers 504 to 506 is formed. Gate insulating film 507
Uses a plasma CVD method or a sputtering method and has a thickness of 4
The insulating film containing silicon is formed to have a thickness of 0 to 150 nm. In this embodiment, a silicon oxynitride film with a thickness of 120 nm is formed. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethylorthosilicate) and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, and the substrate temperature is 300 to 4.
00 ° C., high frequency (13.56 MHz) power density 0.5
It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film thus manufactured is
Good characteristics as a gate insulating film can be obtained by the heat treatment at 0 to 500 ° C.

Then, a first conductive film 508 and a second conductive film 509 for forming a gate electrode are formed over the gate insulating film 507. In the present embodiment, the first conductive film 50
8 is formed from Ta (tantalum) to a thickness of 50 to 100 nm, and the second conductive film 509 is formed from W (tungsten) to 100 nm.
It is formed to a thickness of about 300 nm.

The Ta film is formed by a sputtering method, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for the gate electrode. α phase T
If a film of tantalum nitride having a crystal structure close to that of the α phase of Ta is formed on a base of Ta with a thickness of about 10 to 50 nm to form the a film, a Ta film of the α phase can be easily obtained. .

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set the resistance to Ωcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, the crystallization is inhibited and the resistance is increased. From this, when using the sputtering method,
By using a W target having a purity of 99.9 to 99.9999% and forming a W film with sufficient care so as not to mix impurity elements from the gas phase during the film formation, the resistivity is 9 to 20 μΩcm. Can be realized.

In this embodiment, the first conductive film 508 is used.
Is Ta, and the second conductive film 509 is W. However, the present invention is not particularly limited thereto, and any of them is an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material containing the above element as a main component or It may be formed of a compound material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Another example of the combination other than this embodiment is a combination in which the first conductive film 508 is formed of tantalum nitride (TaN), the second conductive film 509 is formed of W, and the first conductive film 508 is formed of tantalum nitride (TaN). Ta
N), and the second conductive film is made of Al.
Forming a first conductive film of tantalum nitride (TaN);
It is preferable to form the conductive film 509 by using a combination of Cu.

Next, resist masks 510 to 51 are used.
3 and a first etching process for forming electrodes and wirings is performed. In this embodiment, the ICP (Inductively
Coupled Plasma: Inductively coupled plasma) etching method, CF ₄ and Cl ₂ are mixed in the etching gas and 1 Pa
500W RF (13.56M)
Hz) Power is applied to generate plasma. 100W RF (13.56MHz) on substrate side (sample stage)
Power is applied and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, both the W film and the Ta film are etched to the same extent.

Under the above-mentioned etching conditions, by making the shape of the resist mask suitable, the edges of the first conductive layer and the second conductive layer become tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 514 to 517 (the first conductive layers 514 a to 514 a) each including the first conductive layer and the second conductive layer are formed by the first etching process.
17a and second conductive layers 514b to 517b). The first shape conductive layers 514 to 514 of the gate insulating film 507
The region which is not covered with 517 is etched by about 20 to 50 nm to form a thinned region.

Next, a second etching process is performed as shown in FIG. Similarly, using the ICP etching method,
Mix CF ₄ , Cl ₂ and O ₂ in the etching gas
RF power (13.56 MH)
z) is supplied to generate plasma. Apply 50W RF (13.56MHz) power to the substrate side (sample stage)
A self-bias voltage lower than that in the first etching process is applied. Under these conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a lower etching rate to form the second shape conductive layers 518 to 521 (first Of conductive layers 518a to 521a and second conductive layers 518b to 521b). Regions of the gate insulating film 507 that are not covered by the second shape conductive layers 518 to 521 are further etched by about 20 to 50 nm to form thinned areas.

The etching reaction of the W film or the Ta film by the mixed gas of CF ₄ and Cl ₂ can be inferred from the generated radical or ion species and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

After the first etching process and the second etching process are completed, a first doping process is performed to
An impurity element for imparting a mold is added (FIG. 5D). The doping may be performed by an ion doping method or an ion implantation method. An impurity element imparting n-type is added to the island-shaped semiconductor layer using the second shape conductive layers 518 to 520 as a mask. Acceleration is performed so that n-type impurity regions (b) 522 to 526 having a concentration range of 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ (preferably 3 × 10 ^{17 to} 3 × 10 ¹⁸ / cm ³ ) are formed. The doping process is performed at a voltage of 70 to 120 keV. An element belonging to Group XV, typically phosphorus (P) or arsenic (As) is used as the n-type impurity element. Here, phosphorus (P) is used.

The island-shaped semiconductor layer in a region where a part of the second conductive layers 518b to 520b is etched is an impurity element which passes through the first conductive layers 518a to 520a and the gate insulating film 507 and gives n-type conductivity. Was added and 2 × 1
0 ¹⁶ to 1 × 10 ¹⁷ / cm ³ (preferably 6 × 10 ^{16 to} 6 ×
N-type impurity region (c) 527 in a concentration range of 10 ¹⁷ / cm ³ )
To 530 are formed.

When the first doping process is completed,
The resist masks 510b to 513b are removed (FIG.
(A)).

Next, a second doping process is performed as shown in FIG. First, a resist mask 531 is formed so as to cover a channel formation region of the island-shaped semiconductor 506. Next, the acceleration voltage was set to 80 to 200 keV,
× 10 ^{17 to} 5 × 10 ¹⁹ / cm ³ (preferably 1 × 10 ¹⁸ to
N-type impurity region (b ′) in a concentration range of 1 × 10 ¹⁹ / cm ³ )
In order to form 538, an impurity element imparting n-type is doped. At this time, the impurity element is
5, first conductive layer 514a and gate insulating film 507
And is added.

Next, the impurity concentration range is from 1 × 10 ²⁰ to 1
× 10 ²¹ / cm ³ (preferably 2 × 10 ^{20 to} 5 × 10 ²⁰ / c
In order to form the n-type impurity regions (a) 533 to 536 as m ³ ), an impurity element imparting n-type is added (FIG. 6B).

Then, as shown in FIG. 6C, a p-type impurity region is formed in the island-shaped semiconductor layer 504 forming the p-channel TFT. First, a resist mask 543 for covering a region other than a region to which a p-type impurity element is added is formed. Then, using the first conductive layer 514a as a mask for the impurity element, a p-type impurity region (a) 544 and a p-type impurity region (b) 545 are formed. p-type impurity region 54
The 4,545 are doped with phosphorus in different concentrations, respectively, but, B ₂ H ₆ was formed by ion doping using, 2 × 10 ²⁰ ~2 × the impurity concentration in that any region
It should be 10 ²¹ / cm ³ .

Through the above steps, impurity regions are formed in the respective island-like semiconductor layers. Second overlapping with the island-shaped semiconductor layer
Of the conductive layers 518 to 520 function as gate electrodes.
Further, 521 functions as a capacitance wiring.

For the purpose of controlling the conductivity type, a step of activating the impurity element added to each island-like semiconductor layer is performed. In this step, a heat treatment (furnace annealing method) using a furnace is performed. In addition, a laser annealing method can be applied. Heat treatment has an oxygen concentration of 1 ppm
Or less, preferably in a nitrogen atmosphere of 0.1 ppm or less.
The heat treatment is performed at 00 to 700 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours. However, when the wiring material used for 518 to 521 is weak to heat, activation is preferably performed after forming an interlayer insulating film (mainly containing silicon) to protect the wiring and the like.

At this time, nickel used for crystallization of the amorphous silicon film is applied to the region to which the n-type impurity element is added, that is, the region including the n-type impurity element in the n-type impurity region or the p-type impurity region. It moves toward the region to which the n-type impurity element is added, and is gettered. That is, T
The nickel concentration in the FT channel formation regions 560 to 562 is significantly reduced to at least 1 × 10 ¹⁶ / cm ³ or less.

Further, a heat treatment is carried out at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation,
Plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, a first interlayer insulating film 546 is formed from a silicon oxynitride film to a thickness of 100 to 200 nm. A second interlayer insulating film 547 made of an organic insulating material is formed thereon. Next, an etching step for forming a contact hole is performed.

Then, in the drive circuit 405, the source wiring 5 forming a contact with the source region of the island-shaped semiconductor layer
48, 549, and 550, and drain wirings 551 and 552 that form contacts with the drain region are formed.
(A)). The drain wiring 552 is also used as a pixel electrode. In this embodiment, the wires 548 to 552
i film is 100 nm, aluminum film containing Ti is 300 n
A laminated film having a three-layer structure was formed by continuously forming an m and Ti film of 150 nm by a sputtering method.

As described above, the p-channel type TFT 4
A driver circuit 405 having a 01 and n-channel TFT 402 and a pixel portion 406 having a pixel TFT 403 and a storage capacitor 404 can be formed over the same substrate.
In this specification, such a substrate is referred to as an active matrix substrate for convenience.

As shown in FIG. 21, the drain electrode (pixel electrode) 552 is replaced with a drain electrode 601 formed of the same material as the wirings 548 to 551 and a pixel electrode 602 formed of an oxide conductive film. By forming, a transmissive liquid crystal display device can be manufactured.

The p-channel TFT 40 of the driving circuit 405
Reference numeral 1 denotes a p-type impurity region (b) 5 overlapping a channel formation region 560 and a first conductive layer 518a forming a gate electrode.
45, p functioning as a source or drain region
It has a type impurity region (a) 544. In the n-channel TFT 402, a channel formation region 561, an n-type impurity region (b) 538 overlapping with the first conductive layer 519a for forming a gate electrode (Lov region: ov is overlapped), and a source region. Alternatively, an n-type impurity region (a) 534 functioning as a drain region is provided.

The pixel TFT 403 in the pixel portion 406 has an n-type impurity region (c) 539 (Lov) overlapping the channel forming region 562 and the first conductive layer 520a forming the gate electrode.
Region), an n-type impurity region (b) 540 formed outside the gate electrode (Loff region, where off means offset), and an n-type impurity region (a) functioning as a source region or a drain region. 535. In addition, a region 536 having the same concentration as the n-type impurity region (a) is formed in the semiconductor layer functioning as one electrode of the storage capacitor 404, and the semiconductor layer in the region where the first capacitor wiring 521a remains has n A region 541 having the same concentration as the type impurity region (c) is formed. A storage capacitor is formed by the capacitor wiring 521 and an insulating layer (the same layer as the gate insulating film) therebetween.

Next, a process for manufacturing a reflection type active matrix type liquid crystal display device from an active matrix substrate will be described. An alignment film 701 is formed over the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. A light-shielding film 703, a transparent conductive film 704, and an alignment film 705 were formed on the opposite substrate 702 on the opposite side. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. And
The pixel portion, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are attached to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. Thereafter, a liquid crystal material 706 was injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix liquid crystal display device shown in FIG. 7B was completed.

According to the steps described in this embodiment, a semiconductor film having good characteristics can be manufactured, and further, it is possible to contribute to reduction of manufacturing cost and improvement of yield.

Embodiment 2 According to Embodiment 1, a base insulating film is provided on a substrate, a semiconductor film is formed thereon, and crystallization is performed. In this embodiment, a silicon film is used as a semiconductor film. The crystallization step of the semiconductor film in this example is performed by any of the methods described in the first to third embodiments.

Next, in this example, as shown in FIG. 24A, after forming a semiconductor film according to the first embodiment, a mask is formed. After that, heat treatment is performed by adding a catalyst element, so that a polycrystalline region is formed in part of the semiconductor film. Next, as shown in FIG. 25, Nd: Y is perpendicular to a plurality of polycrystalline semiconductor regions formed over the entire semiconductor film.
Irradiation with the second harmonic (532 nm) of an AG laser is performed to grow a crystal using the polycrystalline semiconductor region as a crystal growth nucleus.
In this example, the semiconductor film is crystallized using the first embodiment, but the method for crystallizing the semiconductor film is described in the second embodiment.
Alternatively, the method shown in 3 may be used.

After the crystallization step, the island-like semiconductor layers 1102 to 1102
1106 is formed. In this embodiment, as shown in FIG. 24C, the semiconductor film is formed in an island shape so that the crystal growth proceeds in the direction of the arrow. The island-shaped semiconductor layer has a rectangular shape and each side is 5
Although it is formed so as to be 0 μm or less, the shape of the island-shaped semiconductor layer can be arbitrarily set, and it is preferable that the minimum distance from the center to the end is 50 μm or less. Any polygonal or circular shape may be used, but it is preferable to form the island-shaped semiconductor layer so that the crystal growth direction is along the channel length direction.

Next, a gate insulating film 1107 is formed so as to cover the island-shaped semiconductor layer. Further, the gate insulating film 1
First conductive film 1 for forming a gate electrode on 107
In this embodiment, a TaN film and a W film are formed as in the first embodiment as the second conductive film 108 and the second conductive film 1109 (FIG. 6A). The material of the first conductive film 1108 and the material of the second conductive film are not particularly limited, and any of Ta, W, T
It may be formed of an element selected from i, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component.

Next, a resist mask 1101-1 is used.
116 for forming electrodes and wirings.
Is performed. In this embodiment, the ICP (Indu
Using a ctively Coupled Plasma (Inductively Coupled Plasma) etching method, CF ₄ and Cl ₂ are mixed as an etching gas, and a 500 W RF (1) is applied to a coil-type electrode at a pressure of 1 Pa.
(3.56 MHz) power is supplied to purify the plasma. The substrate side (sample stage) also has a 100 W RF (1
(3.56 MHz), and apply a substantially negative self-bias voltage. When CF ₄ and Cl ₂ are mixed, both the W film and the TaN film are etched to the same extent.

Under the above-mentioned etching conditions, the shape of the resist mask is made appropriate, so that the edges of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 1118 to 1124 (the first conductive layer 111) including the first conductive layer and the second conductive layer are formed by the first etching process.
8a to 1124a and second conductive layers 1118b to 1124
b) is formed. Reference numeral 1117 denotes a gate insulating film.
The region which is not covered with the conductive layers 1118 to 1124 having the above-mentioned shape is etched by about 20 to 50 nm to form a thinned region.

Then, a first doping process is performed to add an impurity element imparting n-type (FIG. 8B). The doping may be performed by an ion doping method or an ion implantation method. Impurity concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ / c
The impurity element was added so as to obtain m ³ (preferably 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ ).

As the impurity element imparting the n-type, an element belonging to Group XV, typically, phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 1118 to 1122 serve as a mask for the impurity element imparting n-type, and
Type impurity regions (a) 1125 to 1129 are formed.

Next, a second etching process is performed as shown in FIG. Similarly, ICP etching is performed, and CF ₄ , Cl _2, and O ₂ are mixed as an etching gas, and 1 Pa
RF power of 500 W (13.
(56 MHz) to generate plasma. 50 W RF (13.56 MH) on the substrate side (sample stage)
z) Power is applied to apply a lower self-bias voltage than in the first etching process. Under such conditions, W
The film is anisotropically etched, and TaN, which is the first conductive layer, is anisotropically etched at a lower etching rate to form second-shaped conductive layers 1131 to 1137 (first conductive layers 1131a to 1137a). And second conductive layer 1131b
To 1137b). Reference numeral 1130 denotes a gate insulating film, and a region which is not covered with the second shape conductive layers 1131 to 1137 is further etched by about 20 to 50 nm to form a thinned region.

The etching reaction of the W film or the TaN film by the mixed gas of CF ₄ and Cl ₂ can be inferred from the generated radical or ion species and the vapor pressure of the reaction product. Comparing the vapor pressures of the fluorides of W and TaN with the chlorides, the fluoride of W, WF _6, is extremely high, and the other WCl ₅ , TaF ₅ , and TaCl ₅ are comparable. Therefore, with the mixed gas of CF ₄ and Cl ₂ , both the W film and the TaN film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in TaN, the increase in the etching rate is relatively small even if the F increases. Further, since TaN is more easily oxidized than W, the surface of TaN is slightly oxidized by adding O ₂ . Since the oxide of TaN does not react with fluorine or chlorine, it is possible to further make a difference in the etching rate of the TaN film.
It can be made larger than the membrane.

Then, a second doping process is performed as shown in FIG. n-type impurity region (b) 1138-
Form 1142. n in the n-type impurity region (b)
The impurity element is added so that the concentration of the type impurity becomes 5 × 10 ^{17 to} 5 × 10 ¹⁹ / cm ³ (preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ ). In addition, the first conductive film 1 of the second shape
131 to 1137 and the gate insulating film 1130, the impurity element passes through and the impurity concentration is 1 × 10 ^{17 to} 5 × 10 ¹⁸ / c.
Area n of m ³ (preferably 3 × 10 ^{17 to} 3 × 10 ¹⁸ / cm ³ )
Type impurity regions (c) 1143 to 1147 are also formed at the same time.

Next, as shown in FIG. 9B, a p-type impurity region 1151 is added to the island-shaped semiconductor layer 1103 forming the p-channel TFT by adding an impurity element of a conductivity type opposite to that of one conductivity type. To 1156 are formed. Second conductive layer 1132
By using b as a mask for the impurity element, an impurity region is formed in a self-aligned manner. At this time, the n-channel type TF
Island-shaped semiconductor layers 1102, 1104, 110 forming T
Reference numeral 5 covers the entire surface with resist masks 1148 to 1150. Phosphorus is added to the impurity regions 1151 to 1156 at different concentrations, respectively.
₂ H ₆ ) and an impurity concentration of 2 × 10 ²⁰ to 2 × 10 ²¹ / c in any of the regions.
made to be m ^3.

By the steps described above, impurity regions are formed in the respective island-like semiconductor layers. Second overlapping with the island-shaped semiconductor layer
Of the conductive layers 1131 to 1134 function as gate electrodes. 1136 functions as an island-shaped source wiring, 1137 functions as a gate wiring, and 1135 functions as a capacitor wiring.

FIG. 9 shows an example of controlling the conductivity type.
As shown in (c), a step of activating the impurity element added to each island-like semiconductor layer is performed. In this step, a heat treatment (furnace annealing method) using a furnace is performed. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the heat treatment, the oxygen concentration is 1 ppm or less, preferably 0.1 pp.
m or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this embodiment, 50
A heat treatment is performed at 0 ° C. for 4 hours. However, 1131-1
When the wiring material used for 137 is weak to heat, it is preferable to activate after forming an interlayer insulating film (mainly composed of silicon) in order to protect the wiring and the like.

At this time, nickel used for crystallization of the amorphous semiconductor film is added to the region to which the n-type impurity element is added, that is, the region containing the n-type impurity element in the n-type impurity region or the p-type impurity region. It moves to the region to which the n-type impurity element is added and is gettered. That is, the nickel concentration in the channel formation regions 1168 to 1171 of the TFT is greatly reduced to at least 1 × 10 ¹⁶ / cm ³ or less.

Further, a heat treatment is performed in an atmosphere containing 3 to 100% of hydrogen at 300 to 450 ° C. for 1 to 12 hours to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation,
Plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, the first interlayer insulating film 1157 is formed with a thickness of 100 to 200 nm from a silicon oxynitride film. A second interlayer insulating film 1158 made of an organic insulating material is formed thereon. Then, an etching step for forming a contact hole is performed.

In drive circuit 1405, source wiring 1159 forming a contact with the source region of the island-shaped semiconductor layer
To 1161, and drain wirings 1162 to 1164 forming a contact with the drain region are formed. In the pixel portion 1406, the pixel electrode 1167, the gate wiring 1
166, a connection electrode 1165 is formed (FIG. 10). With the connection electrode 1165, the source wiring 1137 is electrically connected to the pixel TFT 1404. Further, the gate wiring 1166 is electrically connected to the first electrode.

In this embodiment, a transmission type liquid crystal display device can be manufactured by forming the pixel electrode 1167 with an oxide conductive film (typically, an ITO film).

As described above, the n-channel TFT 1
401, p-channel TFT 1402, n-channel TFT
Driving circuit 1405 having FT1403 and pixel TFT
A pixel portion 1406 having a 1404 and a storage capacitor 1405
Can be formed on the same substrate.

[Embodiment 3] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described. FIG. 11 (A) shows the E of the present invention.
FIG. 11B is a top view of the L display device, and FIG. 11B is a cross-sectional view thereof.

In FIG. 11A, reference numeral 4001 denotes a substrate;
4002 is a pixel portion, 4003 is a source side driver circuit, 40
Reference numeral 04 denotes a gate-side drive circuit. Each drive circuit reaches an FPC (flexible print circuit) 4006 via a wiring 4005 and is connected to an external device.

At this time, a first sealant 4101, a cover 4102, a filler 4103, and a second sealant 4104 are provided so as to surround the pixel portion 4002, the source side drive circuit 4003, and the gate side drive circuit 4004.

FIG. 11 (B) shows FIG.
A driving TFT (n-channel TFT and p-channel TFT) 4201 included in the source-side driving circuit 4003 and a current controlling TFT (including TFT) included in the pixel portion 4002 correspond to a cross-sectional view cut along A ′. A TFT (TFT) 4202 for controlling current to the EL element is formed.

In this embodiment, a TFT having the same structure as the p-channel TFT or the n-channel TFT shown in FIG.
The TFT 2 has the same structure as the p-channel TFT of FIG. 7 or FIG. The pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the current control TFT 4202.

Driving TFT 4201 and Pixel TFT 420
An interlayer insulating film (flattening film) 43 made of a resin material is formed on
01 is formed thereon, and a pixel electrode (anode) 4302 electrically connected to the drain of the pixel TFT 4202 is formed thereon. As the pixel electrode 4302, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used.

An insulating film 4303 is formed on the pixel electrode 4302, and the insulating film 4303 is formed on the pixel electrode 430.
2, an opening is formed. In this opening, an EL (electroluminescence) layer 4304 is formed on the pixel electrode 4302. For the EL layer 4304, a known organic EL material or inorganic EL material can be used. As the organic EL material, there are a low-molecular (monomer) material and a high-molecular (polymer) material, and either may be used.

As a method for forming the EL layer 4304, a known vapor deposition technique or coating technique may be used. The EL layer may have a stacked structure or a single-layer structure by freely combining a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer.

On the EL layer 4304, a cathode 4305 made of a light-shielding conductive film (typically, a conductive film containing aluminum, copper, or silver as a main component or a laminated film of these and another conductive film) is provided. It is formed. In addition, the cathode 4305
It is desirable that moisture and oxygen existing at the interface between the EL layer and the EL layer 4304 be eliminated as much as possible. Therefore, the two layers are continuously formed in a vacuum or the EL layer 4304 is formed in a nitrogen or rare gas atmosphere, and the cathode 430 is not exposed to oxygen or moisture.
5 is required. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

The cathode 4305 is electrically connected to the wiring 4005 in a region indicated by 4306. A wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305, and an FPC through an anisotropic conductive film 4307.
4006.

As described above, the pixel electrode (anode) 43
02, an EL element including the EL layer 4304 and the cathode 4305 is formed. This EL element has a first sealing material 410
Are surrounded by a cover material 4102 bonded to the substrate 4001 by the first and first seal materials 4101,
3 enclosed.

As the cover material 4102, a glass material, a metal material (typically, a stainless steel material), a ceramic material, and a plastic material (including a plastic film) can be used. As a plastic material, FRP (Fi
Berglass-Reinforced Plast
ics) plate, PVF (polyvinyl fluoride) film, mylar film, polyester film or acrylic resin film. Further, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

However, when the light is emitted from the EL element in the direction of the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

As the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicon resin, PVB (polyvinyl butyral) can be used.
Alternatively, EVA (ethylene vinyl acetate) can be used. By providing a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen inside the filler 4103, deterioration of the EL element can be suppressed.

Further, a spacer may be contained in the filler 4103. At this time, if the spacer is made of barium oxide, the spacer itself can have hygroscopicity. In the case where a spacer is provided, it is also effective to provide a resin film on the cathode 4305 as a buffer layer for relaxing pressure from the spacer.

The wiring 4005 is electrically connected to the FPC 4006 via the anisotropic conductive film 4307. The wiring 4005 transmits a signal transmitted to the pixel portion 4002, the source driver circuit 4003, and the gate driver circuit 4004 to the FPC 4006, and is electrically connected to an external device by the FPC 4006.

In this embodiment, the first sealing material 4101 is used.
A second sealing material 4104 is provided so as to cover the exposed part of the FPC 4006 and a part of the FPC 4006, and the EL element is completely shut off from the outside air. Thus, an EL display device having the cross-sectional structure of FIG.

FIG. 12 shows a more detailed sectional structure of the pixel portion, FIG. 13A shows a top view structure, and FIG.
It is shown in (B). FIGS. 12, 13A and 13B
Then, since a common code is used, they may be referred to each other.

In FIG. 12, a switching TFT 4402 provided on a substrate 4401 is formed using the n-channel TFT 403 of FIG. Therefore, for the description of the structure, the description of the n-channel TFT 403 may be referred to. A wiring denoted by 4403 is a gate wiring for electrically connecting the gate electrodes 4404a and 4404b of the switching TFT 4402.

Although the present embodiment has a double gate structure in which two channel forming regions are formed, a single gate structure in which one channel forming region is formed or a triple gate structure in which three channel forming regions are formed. good.

The drain wiring 4405 of the switching TFT 4402 is electrically connected to the gate electrode 4407 of the current control TFT 4406. The current control TFT 4406 is the p-channel TFT 4 shown in FIG.
01 is formed. Therefore, for the description of the structure, the description of the p-channel TFT 401 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The first passivation film 4 is formed on the switching TFT 4402 and the current control TFT 4406.
408 are provided, and a planarizing film 44 made of resin is provided thereon.
09 is formed. It is very important to flatten the step due to the TFT using the flattening film 4409. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 4418 denotes a pixel electrode (anode of an EL element) made of a transparent conductive film.
06 is electrically connected to the drain wiring 4414. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide,
Tin oxide or indium oxide can be used.
Further, a material obtained by adding gallium to the transparent conductive film may be used.

On the pixel electrode 4418, an EL layer 4411 is provided.
Is formed. Although only one pixel is shown in FIG. 12, in this embodiment, EL layers corresponding to R (red), G (green), and B (blue) are separately formed. In this embodiment, a low-molecular organic EL material is formed by an evaporation method. Specifically, a laminated structure in which a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a tris-8-quinolinolato aluminum complex (Alq ₃ ) film having a thickness of 70 nm is provided thereon as a light emitting layer. And Al
quinacridone q _3, it is possible to control the luminescent color by adding a fluorescent dye such as perylene or DCM1.

However, the above example is an example of the organic EL material that can be used for the EL layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, a low molecular organic EL material is
Although an example in which the layer is used as a layer has been described, a polymer organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

Next, a cathode 4412 made of a conductive film is provided on the EL layer 4411. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film.
Of course, a known MgAg film (an alloy film of magnesium and silver) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

At the time when the cathode 4412 is formed, E
The L element 4413 is completed. Note that the EL element 4413 here includes a pixel electrode (anode) 4418 and an EL layer 441.
1 and the cathode 4412.

Next, the top structure of the pixel in this embodiment will be described with reference to FIG. Switching TFT
The source of 4402 is connected to the source wiring 4415, and the drain is connected to the drain wiring 4405. Further, the drain wiring 4405 is electrically connected to the gate electrode 4407 of the current controlling TFT 4406. The source of the current control TFT 4406 is electrically connected to the current supply line 4416, and the drain is electrically connected to the drain wiring 4417. Further, the drain wiring 4417 is electrically connected to a pixel electrode (anode) 4418 shown by a dotted line.

At this time, a storage capacitor is formed in a region indicated by 4419. The storage capacitor 4419 is formed between the semiconductor film 4420 electrically connected to the current supply line 4416, an insulating film (not shown) in the same layer as the gate insulating film, and the gate electrode 4407. In addition, the gate electrode 440
7. A capacitor formed by the same layer (not shown) as the first interlayer insulating film and the current supply line 4416 can also be used as a storage capacitor.

[Embodiment 4] In this embodiment, an EL display device having a pixel structure different from that of Embodiment 3 will be described. FIG. 14 is used for the description. The description of the third embodiment may be referred to for the portions denoted by the same reference numerals as in FIG.

In FIG. 14, a TF having the same structure as the n-channel TFT 403 of FIG.
Use T. Needless to say, the gate wiring 4502 of the current control TFT 4501 is electrically connected to the drain wiring 4405 of the switching TFT 4402. The drain wiring 4503 of the current controlling TFT 4501 is electrically connected to the pixel electrode 4504.

In this embodiment, the pixel electrode 4 made of a conductive film is used.
504 functions as a cathode of the EL element. In particular,
Although an alloy film of aluminum and lithium is used, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

On the pixel electrode 4504, an EL layer 4505 is provided.
Is formed. Although only one pixel is shown in FIG. 14, in this embodiment, an EL layer corresponding to G (green) is formed by a vapor deposition method and a coating method (preferably a spin coating method). Specifically, 20n is used as the electron injection layer.
It has a laminated structure in which a m-thick lithium fluoride (LiF) film is provided, and a 70-nm-thick PPV (polyparaphenylene vinylene) film is provided thereon as a light emitting layer.

Next, an anode 4506 made of a transparent conductive film is provided on the EL layer 4505. In the case of this embodiment,
As the transparent conductive film, a conductive film including a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide is used.

At the time when the anode 4506 is formed, E
The L element 4507 is completed. Note that the EL element 4507 used here includes a pixel electrode (cathode) 4504 and an EL layer 450.
5 and the anode 4506.

When the voltage applied to the EL element is as high as 10 V or more, deterioration of the current control TFT 4501 due to the hot carrier effect becomes apparent. In such a case, it is effective to use an n-channel TFT having the structure of the present invention as the current control TFT 4501.

Further, the current controlling TFT 450 of the present embodiment is used.
1 forms a parasitic capacitance called a gate capacitance between the gate electrode 4502 and the LDD region 4509. By adjusting the gate capacitance, a function equivalent to that of the storage capacitor 4419 shown in FIGS. 13A and 13B can be provided. In particular, when the EL display device is operated by the digital driving method, the capacitance of the storage capacitor can be smaller than when the EL display device is operated by the analog driving method.
The gate capacitance can substitute for the storage capacitance.

When the voltage applied to the EL element is 10 V or less, preferably 5 V or less, the deterioration due to the hot carrier effect does not become a problem.
In FIG. 14, n has a structure in which the LDD region 4509 is omitted.
A channel type TFT may be used.

[Embodiment 5] In this embodiment, FIGS. 15A to 15C show an example of a pixel structure which can be used in the pixel portion of the EL display device shown in Embodiment 3 or 4. . In this embodiment, reference numeral 4601 denotes a source wiring of the switching TFT 4602, 4603 denotes a gate wiring of the switching TFT 4602, 4604 denotes a current control TFT, 4605 denotes a capacitor, 4606, and 4608.
Is a current supply line, and 4607 is an EL element.

FIG. 15A shows an example in which the current supply line 4606 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 4606. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 15B shows a current supply line 460.
8 is provided in parallel with the gate wiring 4603. Note that FIG. 15B illustrates a structure in which the current supply line 4608 and the gate wiring 4603 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 4608 and the gate wiring 4603 can share an occupied area, the pixel portion can have higher definition.

In FIG. 15C, a current supply line 4608 is provided in parallel with the gate wiring 4603, and two pixels are connected to the current supply line 4608, as in the structure of FIG.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 4608 so as to overlap with one of the gate wirings 4603. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

[Embodiment 6] In this embodiment, an example of a pixel structure of an EL display device embodying the present invention will be described with reference to FIG.
It is shown in (B). Note that in this embodiment, 4701 is a source wiring of the switching TFT 4702, 4703 is a gate wiring of the switching TFT 4702, and 4704.
Is a current control TFT, 4705 is a capacitor (may be omitted), 4706 is a current supply line, 4707 is a power control TFT, 4708 is a power control gate wiring, 47
09 is an EL element. For the operation of the power supply control TFT 4707, refer to Japanese Patent Application No. 11-341272.

In this embodiment, the power supply control TFT 47 is used.
07 is provided between the current controlling TFT 4704 and the EL element 4708, but the power controlling TFT 4707 and the EL
A current control TFT 4704 may be provided between the element 4708 and the element 4708. Also, the power supply control TFT 47
07 has the same structure as the current control TFT 4704,
It is preferable to form them in series with the same active layer.

FIG. 16A shows an example in which a current supply line 4706 is shared between two pixels. That is,
It is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 4706. In this case, the number of current supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 16B shows a gate wiring 470.
A current supply line 4710 is provided in parallel with
This is an example in the case where a power supply control gate wiring 4711 is provided in parallel with the line 01. In FIG. 16B, the current supply line 47
Although the structure is such that 10 and the gate wiring 4703 are provided so as not to overlap with each other, the wiring may be provided so as to overlap via an insulating film as long as both are formed in different layers. In this case, the current supply line 4710 and the gate wiring 47
03 can share the occupied area, so that the pixel portion can be further refined.

[Embodiment 7] In this embodiment, an example of a pixel structure of an EL display device embodying the present invention will be described with reference to FIG.
It is shown in (B). In this embodiment, reference numeral 4801 denotes a source wiring of the switching TFT 4802, 4803 denotes a gate wiring of the switching TFT 4802, and 4804.
Is a current control TFT, 4805 is a capacitor (can be omitted), 4806 is a current supply line, 4807 is an erasing TFT, 4808 is an erasing gate wiring, and 4809 is E
L element. For the operation of the erasing TFT 4807, refer to Japanese Patent Application No. 11-338786.

The drain of the erasing TFT 4807 is connected to the gate of the current controlling TFT 4804,
The gate voltage of the FT4804 can be forcibly changed. The erasing TFT 4807
May be an n-channel TFT or a p-channel TFT, but preferably has the same structure as the switching TFT 4802 so that off-state current can be reduced.

FIG. 17A shows an example in which a current supply line 4806 is shared between two pixels. That is,
The feature is that two pixels are formed so as to be line-symmetric with respect to the current supply line 4806. In this case, the number of current supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 17B shows a case where a gate wiring 480 is formed.
3, a current supply line 4810 is provided in parallel with the source line 48.
This is an example in which an erasing gate wiring 4811 is provided in parallel with the line 01. Note that in FIG. 17B, the current supply line 4810
Although the gate wiring 4803 and the gate wiring 4803 are provided so as not to overlap with each other, they may be provided so as to overlap with each other via an insulating film as long as they are formed in different layers. In this case, the current supply line 4810 and the gate wiring 480
3 can share an occupied area, so that the pixel portion can be further refined.

Embodiment 8 The EL display device of the present invention may have a structure in which any number of TFTs are provided in a pixel. For example, four to six or more TFTs may be provided. The present invention can be implemented without being limited to the pixel structure of the EL display device.

[Embodiment 9] A CMOS circuit and a pixel portion formed by implementing the present invention can be used for various electro-optical devices (active matrix type liquid crystal display, active matrix type EL display). That is,
The present invention can be applied to all electric appliances in which these electro-optical devices are incorporated in a display unit.

Such electric appliances include a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), car navigation, car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS. 18, 19 and 20.

FIG. 18A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like.

FIG. 18B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on.

FIG. 18C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like.

FIG. 18D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on.

FIG. 18E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet.

FIG. 18F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like.

FIG. 19A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like.

FIG. 19B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like.

FIG. 19C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 19A and 19B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in an optical path indicated by an arrow in FIG. Good.

FIG. 19D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 19C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 19D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 19, a case where a transmissive electro-optical device is used is shown, and examples of application to a reflective electro-optical device and an EL display device are not shown.

FIG. 20A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on.

FIG. 20B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on.

FIG. 20C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electric appliances in various fields. Further, the electric appliance of this embodiment can be realized by a liquid crystal display device configured by combining Embodiments 1 to 3 and Embodiments 1 and 2.

[0170]

According to the present invention, 390-600 nm
Utilizing the difference in the number of absorption systems between the amorphous silicon film and the polycrystalline silicon film with respect to light in the wavelength range, a crystalline semiconductor film having a larger crystal grain size than conventional ones can be obtained by a simple method. . Further, by manufacturing a semiconductor device using the crystalline semiconductor film having a large crystal grain size, performance of the semiconductor device can be significantly improved.

For example, a silicon film having an amorphous silicon region and a polycrystalline silicon region adjacent to each other has a thickness of 390-6 nm.
Light at a wavelength in the range of 00 nm (typically Nd: Y
By irradiating the second harmonic light of the AG laser, the amorphous silicon region is completely melted, and the polycrystalline silicon region is incompletely melted. Starts, and a semiconductor film having a large grain size whose position is controlled can be formed.

Compared with a method requiring precise position control such as the SLS method, the present method can obtain a crystalline semiconductor film having a large grain size by performing position control by a simple method. Furthermore, a favorable TFT can be obtained by applying the semiconductor film obtained by the present invention to a TFT.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing a laser energy region and laser absorption coefficients of amorphous silicon and polycrystalline silicon.

FIG. 5 is a view showing a step of manufacturing a TFT using the present invention.

FIG. 6 is a view showing a step of manufacturing a TFT using the present invention.

FIG. 7 is a view showing a step of manufacturing a TFT using the present invention.

FIG. 8 is a view showing a step of manufacturing a TFT by utilizing the present invention.

FIG. 9 is a view showing a step of manufacturing a TFT using the present invention.

FIG. 10 is a view showing a step of manufacturing a TFT using the present invention.

FIG. 11 illustrates a structure of an EL display device.

FIG. 12 illustrates a structure of an EL display device.

FIG. 13 illustrates a structure of an EL display device.

FIG. 14 illustrates a structure of an EL display device.

FIG. 15 illustrates a circuit of an EL display device.

FIG. 16 illustrates a circuit of an EL display device.

FIG. 17 illustrates a circuit of an EL display device.

FIG. 18 illustrates a specific example of an electric appliance.

FIG. 19 illustrates a specific example of an electric appliance.

FIG. 20 illustrates a specific example of an electric appliance.

FIG. 21 is a diagram showing a cross section of a TFT manufactured by using the present invention.

FIG. 22 is a graph showing heat values of amorphous silicon and polycrystalline silicon in the thickness direction.

FIG. 23 is a diagram showing a temperature history at an interface between a silicon layer and a quartz glass substrate.

FIG. 24 is a diagram showing an embodiment of the present invention.

FIG. 25 is a diagram showing an embodiment of the present invention.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 H01L 29/78 627G 5F110 H01S 3/00 F-term (Reference) 2H092 GA59 JA25 JA46 JB58 KA04 MA30 NA27 5C094 AA07 AA22 AA25 AA43 BA03 BA27 BA43 CA19 DA09 DA13 DB01 DB04 EA04 EA05 EA10 EB02 FA01 FA02 FB02 FB12 FB14 FB15 GB10 JA11 5F048 AB10 AC04 BA16 BB09 BC06 BG07 5F052 AA02 AA02 DB03 FA03 AB02 JJ12 YY06 5F110 AA30 BB02 BB04 CC02 DD01 DD02 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE23 EE28 EE44 EE45 FF02 FF04 FF28 FF30 FF36 NN01 NN02 NN13 NN03 NN PP03 PP04 PP05 PP07 PP23 PP33 PP34 QQ04 QQ09 QQ11 QQ24 QQ25 QQ28

Claims (10)

[Claims] A step of forming an amorphous semiconductor film on the insulator; forming a mask made of the insulating film on the amorphous semiconductor film; and exposing the amorphous semiconductor film from an opening of the mask. A step of adding an element that promotes crystallization to the region, a step of performing a heat treatment after the addition step to selectively form a polycrystalline semiconductor region, and irradiating a laser beam having a wavelength in the range of 390 to 600 nm. Forming a crystalline semiconductor film by performing the method. 2. The method according to claim 1, wherein the laser light is N
d: A method for manufacturing a semiconductor device, which is light of a second harmonic (wavelength: 532 nm) of a YAG laser. 3. The element according to claim 1, wherein the elements that promote crystallization are nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), and lead (P).
b) Cobalt (Co), platinum (Pt), copper (Cu) or gold (Au). 4. The method according to claim 1, wherein the opening of the mask is 1 μm or more and 10 μm or less. 5. A step of forming an amorphous semiconductor film on an insulator, and irradiating a selected region of the amorphous semiconductor film with a first laser beam to selectively form a polycrystalline semiconductor region. And a step of irradiating a second laser beam to form a crystalline semiconductor film. 6. The method according to claim 5, wherein the first laser light is light of an excimer laser, and the second laser light is light of a second harmonic (wavelength: 532 nm) of an Nd: YAG laser. A method for manufacturing a semiconductor device, comprising: 7. The method according to claim 5, wherein the first laser light and the second laser light are the second laser light of a Nd: YAG laser.
A method for manufacturing a semiconductor device, comprising light of a harmonic (wavelength: 532 nm). 8. The method for manufacturing a semiconductor device according to claim 5, wherein the first laser light and the second laser light are irradiated from a front surface, a back surface, or both surfaces of the substrate. 9. A step of forming a polycrystalline semiconductor film on an insulator, forming a mask made of an insulating film on the polycrystalline semiconductor film, and forming silicon (Si) in a region exposed from an opening of the mask. Germanium (Ge), argon (Ar),
A step of selectively forming an amorphous semiconductor region by adding any element selected from oxygen (O) or hydrogen (H), and a step of forming a crystalline semiconductor film by irradiating a laser beam. A method for manufacturing a semiconductor device, comprising: 10. The method according to claim 9, wherein the laser light is N
d: A method for manufacturing a semiconductor device, which is light of a second harmonic (wavelength: 532 nm) of a YAG laser.