JP2001196599A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a crystalline semiconductor film, where the position and size of crystal grain are controlled, and to realize a first TFT by using the crystalline semiconductor film as a TFT channel formation region. SOLUTION: A strip-like first insulating layer 1002 is formed on a glass substrate 1001, over which a second insulating layer 1003 is formed, and then an island-like semiconductor layer 1004 id formed over it. The both surfaces of glass substrate are irradiated with laser beam, to cause the island-like semiconductor layer to crystallize.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor film having a crystal structure formed on a substrate having an insulating surface, and a method for manufacturing a semiconductor device using the semiconductor film as an active layer. In particular, the present invention relates to a method for manufacturing a thin film transistor in which an active layer is formed using a crystalline semiconductor. Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics, and includes an electro-optical device represented by an active matrix driving liquid crystal display device formed using a thin film transistor; Also, an electronic device including such an electro-optical device as a component is included in the category.

[0002]

2. Description of the Related Art An amorphous semiconductor film is formed on a light-transmitting substrate having an insulating surface, and is subjected to a heat treatment using a laser annealing method or a furnace annealing furnace (hereinafter referred to as a thermal annealing method).
The crystalline semiconductor film crystallized by
Techniques for use in the active layer of in Film Transistor (hereinafter referred to as TFT) have been developed. As a light-transmitting substrate having an insulating surface, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass is often used. Such a glass substrate is inferior in heat resistance to a quartz substrate, but is commercially available at a low price, and has the advantage that a large-area substrate can be easily manufactured.

[0003] The laser annealing method is known as a crystallization technique capable of imparting high energy only to an amorphous semiconductor film for crystallization without increasing the temperature of a glass substrate so much. In particular, an excimer laser that oscillates short-wavelength light having a wavelength of 400 nm or less is a typical laser that has been used since the beginning of development of this laser annealing method. In recent years, a technique using a solid-state laser, such as a YAG laser, has also been developed. In these laser annealing methods, a laser beam is processed by an optical system so as to form a spot or a line on the surface to be irradiated, and the surface to be irradiated on a substrate is scanned with the processed laser light (the laser light Move the irradiation position relatively to the irradiated surface)
Performed by For example, in the excimer laser annealing method using linear laser light, it is possible to perform laser annealing on the entire irradiated surface by scanning only in a direction perpendicular to the longitudinal direction, and since liquid crystal using TFTs is excellent in productivity, It is becoming mainstream as a display device manufacturing technique. The technology uses a TFT (pixel TFT) for forming a pixel portion on a single glass substrate and a TFT for a driving circuit provided around the pixel portion.
This enables a monolithic liquid crystal display device having an FT formed thereon.

[0004] However, a crystalline semiconductor film produced by laser annealing an amorphous semiconductor film is a collection of a plurality of crystal grains, and the position and size of the crystal grains are random. TFT fabricated on a glass substrate,
For element isolation, the crystalline semiconductor layer is formed in an island pattern. In that case, it was not possible to form the crystal grains by designating the position and size of the crystal grains. At the interface of crystal grains (grain boundaries), the current transport characteristics of carriers are degraded by the influence of recombination centers, trapping centers, and potential levels at the crystal grain boundaries caused by the amorphous structure and crystal defects. It is known that there is. However, it has been almost impossible to form a channel forming region in which the properties of the crystal have a significant effect on the characteristics of the TFT with a single crystal grain excluding the influence of the crystal grain boundary. For this reason, a TFT using a crystalline silicon film as an active layer has not been obtained to date that has the same characteristics as those of a MOS transistor manufactured on a single crystal silicon substrate.

[0005] In order to solve such problems, attempts have been made to increase the size of crystal grains. For example, "" High-Mobility Poly-Si Thin-Film Transistors
Fabricatedby a Novel Excimer Laser Crystallizatio
n Method ", K.Shimizu, O.Sugiura and M.Matumura, IE
EE Transactions on Electron Devices vol.40, No.1,
pp. 112-117, 1993 ”describes that Si / SiO ₂ / Si
There is a report on a laser annealing method in which a film having a three-layer structure is formed and excimer laser light is irradiated from both the film side and the substrate side. According to this method, it is disclosed that crystal grains can be made large by irradiating a laser beam with a certain energy intensity.

[0006]

According to the method of Ishihara et al., The thermal characteristics of the underlying material of the amorphous silicon film are locally changed to control the flow of heat to the substrate to provide a temperature gradient. It is characterized by: However, for this purpose, a three-layer structure of a refractory metal layer / a silicon oxide layer / a semiconductor film is formed on a glass substrate. Although it is structurally possible to form a top gate type TFT using this semiconductor film as an active layer, parasitic capacitance is generated by a silicon oxide film provided between the semiconductor film and the high melting point metal layer. ,
Power consumption increases, and it becomes difficult to realize high-speed operation of the TFT.

On the other hand, it is considered that by using a high melting point metal layer as a gate electrode, it can be effectively applied to a bottom gate type or inverted stagger type TFT. However, in the three-layer structure, even if the thickness of the semiconductor film is excluded, the thicknesses of the refractory metal layer and the silicon oxide layer are suitable for the crystallization step and for the characteristics as the TFT element. Since the film thickness does not always coincide with each other, it is impossible to satisfy both the optimum design in the crystallization step and the optimum design of the element structure at the same time.

Further, if a high melting point metal layer having no translucency is formed on the entire surface of a glass substrate, it is impossible to manufacture a transmission type liquid crystal display device. The high melting point metal layer is useful in that it has a high thermal conductivity, but the chromium (Cr) film and titanium (Ti) film used as the high melting point metal material have high internal stress, so that the adhesion to the glass substrate is high. Is likely to cause problems. Further, the influence of the internal stress extends to the semiconductor film formed thereon, and there is a great possibility that the internal stress acts as a force for giving a strain to the formed crystalline semiconductor film.

On the other hand, in order to control a threshold voltage (hereinafter, referred to as Vth), which is an important characteristic parameter in a TFT, within a predetermined range, in addition to controlling valence electrons in a channel forming region, the active layer needs to be controlled. It is necessary to reduce the charge defect density of a base film and a gate insulating film which are closely formed by an insulating film and to consider a balance of internal stresses. In response to such demands, materials containing silicon as a constituent element, such as a silicon oxide film and a silicon oxynitride film, have been suitable.
Therefore, there is a concern that providing a high-melting-point metal layer to have a temperature gradient will break the balance.

The present invention is a technique for solving such a problem, in which a crystalline semiconductor film in which the positions and the sizes of crystal grains are controlled is manufactured, and the crystalline semiconductor film is formed by T
A TFT capable of high-speed operation is realized by using the TFT in a channel formation region of an FT. Further, another object of the present invention is to provide a technique in which such a TFT can be applied to various semiconductor devices such as a transmission type liquid crystal display device and a display device having an electroluminescent material.

[0011]

A laser annealing method is used for forming a crystalline semiconductor layer from an amorphous semiconductor layer formed on a substrate such as glass. The laser annealing method of the present invention uses a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or an argon laser as a light source, and applies a linear or rectangular laser light to an island-like semiconductor layer by an optical system. On the other hand, the front side of the substrate on which the island-shaped semiconductor layer is formed (defined as the surface on which the island-shaped semiconductor layer is formed in this specification) and the back side (in this specification, the island-shaped semiconductor layer is formed) Surface is defined as the opposite side)
Irradiate from both.

FIG. 2A is a diagram showing a configuration of a laser annealing apparatus according to the present invention. The laser annealing apparatus has a laser oscillator 1201, an optical system 1100, and a stage 1202 for fixing a substrate, and a heater 1203 and a heater controller 1204 are added to the stage 1202 so that the substrate can be heated to 100 to 450 ° C. . A reflection plate 1205 is provided on the stage 1202, and a substrate 1206 is set thereon. In the structure of the laser annealing apparatus having the structure in FIG. 2A, a method for holding the substrate 1206 will be described with reference to FIG. The substrate 1206 held on the stage 1202 is
213, and is irradiated with laser light. The reaction chamber can be heated to 100 to 450 ° C. without contaminating the semiconductor film by reducing the pressure or using an inert gas atmosphere by an exhaust system or a gas system (not shown). Stage 1202 is guide rail 1
216 can be moved in the reaction chamber, and the entire surface of the substrate can be irradiated with linear racer light. The laser light enters from a quartz window (not shown) provided on the upper surface of the substrate 1206. In FIG. 2B, a transfer chamber 1210, an intermediate chamber 1211 and a load / unload chamber 1212 are connected to the reaction chamber 1213, and are separated by gate valves 1217 and 1218. A cassette 1214 capable of holding a plurality of substrates is installed in the load / unload chamber 1212, and the transfer chamber 1
The substrate is transported by a transport mechanism 1215 provided in 210. The substrate 1206 'represents the substrate being transported. With such a configuration, laser annealing can be continuously performed under reduced pressure or in an inert gas atmosphere.

FIG. 3 is a view for explaining the basic configuration of the optical system 1100 of the laser annealing apparatus shown in FIG. As the laser oscillator 1101, an excimer laser, a YAG laser, an argon laser, or the like is used. FIG. 3A is a diagram of the optical system 1100 viewed from the side, and a laser beam emitted from a laser oscillator 1101 is split in a vertical direction by a cylindrical lens array 1102. The split laser light is once condensed by the cylindrical lens 1104, spreads, is reflected by the mirror 1107, and then is reflected by the cylindrical lens 1104.
By 108, a linear laser beam is formed on the irradiation surface 1109. Thereby, the energy distribution in the width direction of the linear laser light can be made uniform. FIG.
FIG. 11B is a diagram of the optical system 1100 as viewed from above, and the laser light emitted from the laser oscillator 1101 is divided in a horizontal direction by a cylindrical lens array 1103. After that, the laser light is combined into one at the irradiation surface 1109 by the cylindrical lens 1105. This allows
The energy distribution in the longitudinal direction of the linear laser light can be made uniform.

FIG. 1 is a view for explaining the concept of the laser annealing method of the present invention. A first insulating layer 1002 in a stripe shape or a strip shape is formed over a substrate 1001 such as glass, and a second insulating layer 1003 is formed thereover. Further, an island-shaped semiconductor layer 1004 is formed thereon. For the first insulating layer 1002 and the second insulating layer 1003, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an insulating film containing aluminum as a component, or the like is used. Used.

Then, the laser light passing through the cylindrical lens 1006 having the same function as the cylindrical lens 1108 by the optical system 1100 described with reference to FIGS. Is irradiated. A first laser beam component 1007 that passes through the cylindrical lens 1006 and directly irradiates the island-shaped semiconductor layer 1004 is provided on the island-shaped semiconductor layer 1004.
Transmits through the first insulating layer 1002, the second insulating layer 1003, and the substrate 1001, is reflected by the reflector 1005, and transmits through the substrate 1001, the first insulating layer 1002, and the second insulating layer 1003 again. Then, there is a second laser beam component 1008 irradiated to the island-shaped semiconductor layer 1004. In any case, the laser light that has passed through the cylindrical lens 1006 is 45 to 90 ° with respect to the substrate surface during the focusing process.
, The laser beam reflected by the reflector 1005 is also reflected in the direction inside the island-shaped semiconductor layer 1004. The reflective plate 1005 forms a reflective surface with aluminum (Al), titanium (Ti), titanium nitride (TiN), chromium (Cr), tungsten (W), tungsten nitride (WN), or the like. As described above, by appropriately selecting the material for forming the reflective surface, the reflectance can be increased to 20 to 90.
%, And the intensity of laser light incident from the back side of the substrate 1001 can be changed. In addition, if this reflecting surface is mirror-finished,
A regular reflectance of about 90% is obtained in the wavelength range of 320 nm.
Also, the material is aluminum, and several hundreds of
If a fine irregular shape of nm is formed, a diffuse reflectance (integral reflectance-specular reflectance) of 50 to 70% can be obtained.

In this way, the laser beam is applied to the substrate 100
Irradiation is performed from the front and back surfaces of the substrate 1 and the island-shaped semiconductor layer 1004 formed on the substrate 1001 is laser-annealed from both surfaces. In the laser annealing method, the semiconductor film is instantaneously heated and melted by optimizing the conditions of laser light to be irradiated, and the generation density of crystal nuclei and the crystal growth from the crystal nuclei are controlled. Since the oscillation pulse width of a pulsed excimer laser or YAG laser is several nanoseconds to several tens of nanoseconds, for example, 30 nanoseconds, when irradiation is performed with a pulse oscillation frequency of 30 Hz, the semiconductor layer in the region irradiated with the laser light is pulsed laser light. Is heated instantaneously, and is cooled for a much longer time than the heating time.

When the island-like semiconductor layer formed on the substrate is irradiated with laser light from only one surface, only one side is heated, so that the cycle of heating and melting and cooling and solidification becomes steep, and Even if the generation density of GaN can be controlled, sufficient crystal growth cannot be expected. However, when laser light is irradiated from both surfaces of the semiconductor layer, the cycle of heating and melting and cooling and solidification becomes gentle, and the time allowed for crystal growth in the process of cooling and solidification becomes relatively long, which is sufficient. Crystal growth can be obtained.

In the transient phenomenon, the island-shaped semiconductor layer is provided with a temperature distribution, a region having a gentle temperature change is provided, and the nucleation rate and the nucleation density are controlled to increase the crystal grain size. Specifically, as shown in FIG. 1, a first insulating layer 1002 in a stripe shape is provided over a substrate 1001, and a second insulating layer 1003 is formed thereover. The island-shaped semiconductor layer 1004 is formed over the second insulating layer 1003, but is provided so as to intersect with the first insulating layer 1002.
That is, the second insulating layer 10 is formed under the island-shaped semiconductor layer 1004.
03 is formed, and a region where the insulating films of the first insulating layer 1002 and the second insulating layer 1003 are formed is provided. Since the latter region increases in volume and heat capacity, the maximum temperature reached by laser light irradiation is lower than in the former region. As a result, generation of crystal nuclei occurs preferentially in the latter region, and crystal growth starts from this portion.
At this time, it is also an important factor that the semiconductor layer is sufficiently heated by irradiating laser light from both surfaces of the semiconductor layer. By making the cycle of temperature change due to the irradiation of the pulsed laser beam to the island-shaped semiconductor layer gentle, the crystal grains are made large.

A method of irradiating a laser beam from the front side and the back side of a substrate having an island-shaped semiconductor layer formed on one side is as follows.
The configuration shown in FIG. 4 may be used. Excimer laser and Y
Light emitted from a laser oscillator 401 such as an AG laser is split by a cylindrical lens array 402 (or 403). The split laser light is once condensed by the cylindrical lens 404 (or 405), then spread and reflected by the mirror 408. A beam splitter 406 is placed in the middle of this optical path to split the optical path into two. One of the laser beams is reflected by mirrors 407 and 413, is converted into a linear laser beam by a cylindrical lens 414, and is emitted to the front side of the substrate 418. This laser light is used as the first laser light. A base film 419 and an island-shaped semiconductor layer 420 are formed on the front side of the substrate 418. The other laser light is reflected by mirrors 408, 409, and 411, converted into a linear laser light by a cylindrical lens 412, and emitted to the back side of the substrate 418. This laser light is used as a second laser light. An attenuator 410 is provided in the middle of the optical path to adjust the intensity of the laser light. With such a configuration, even when laser light is irradiated from the front side and the back side of the substrate, the crystal grains of the semiconductor layer can be made large in the same manner as described above.

In this specification, the laser annealing method having the structure shown in FIGS. 1 and 4 is called a dual beam laser annealing method, and the crystal grains of the island-shaped semiconductor layer are made larger by applying this method. A TFT having a structure corresponding to the function of each circuit by using the island-shaped semiconductor layer as an active layer of the TFT.
The performance of the semiconductor device is improved by manufacturing a semiconductor device having the above.

According to the structure of the present invention using the dual beam laser annealing method, the stripe-shaped first insulating layer is formed on one surface of the light-transmitting substrate, and the second insulating layer is formed on the striped first insulating layer. Is provided. The island-shaped semiconductor layers provided over these insulating layers are formed to intersect with the stripe-shaped first insulating layers. As a preferred embodiment of the present invention, a plurality of striped first insulating layers are formed, and an island-shaped semiconductor layer is formed so as to intersect with the plurality of striped first insulating layers. A channel forming region of a TFT is formed between the single striped first insulating layer and the striped first insulating layer adjacent thereto.

As described above, according to the structure of the present invention, the island-shaped semiconductor layer and the strip-shaped first insulating layer provided below the island-shaped semiconductor layer are formed on one surface of the light-transmitting substrate. And the strip-shaped first insulating layer is provided so as to intersect with the island-shaped semiconductor layer. The first insulating layers may be formed as a pair, and the pair of strip-shaped first insulating layers is provided so as to intersect with the island-shaped semiconductor layers.

The above structure can be suitably applied to a TFT, and a channel forming region of the thin film transistor formed in the island-shaped semiconductor layer is formed adjacent to the strip-shaped first insulating layer. A channel formation region of a TFT is formed between a pair of strip-shaped first insulating layers.

Further, a method for manufacturing a semiconductor device according to the present invention
Forming a strip-shaped first insulating layer on one surface of the light-transmitting substrate; and forming an island on the strip-shaped first insulating layer so as to intersect with the strip-shaped first insulating layer. Forming a semiconductor layer, and irradiating the island-shaped semiconductor layer with laser light from one surface side of the light-transmitting substrate and the other surface side to crystallize the island-shaped semiconductor layer. And a process.

In another aspect of the invention, a step of forming a pair of strip-shaped first insulating layers on one surface of a light-transmitting substrate, and a step of forming a pair of strip-shaped first insulating layers on the pair of strip-shaped first insulating layers. Forming an island-shaped semiconductor layer so as to intersect with the pair of strip-shaped first insulating layers; and forming the island-shaped semiconductor layer from one surface side of the light-transmitting substrate and the other surface side. Irradiating the layer with laser light to crystallize the island-shaped semiconductor layer.

[0026]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. In FIG. 5A, an alkali-free glass substrate such as barium borosilicate glass or aluminoborosilicate glass is used for a substrate 501. For example, # 7059 glass or # 1737 glass based on Corning Inc. can be suitably used.

On a surface of the substrate 501 where a TFT is to be formed, a first insulating layer 502 having a light-transmitting and insulating property is provided.
503 is formed. This first insulating layer may be formed of a material having excellent thermal conductivity. In that case, the thermal conductivity is 10Wm
^-1 K ^-1 or more is desirable. As such a material, an oxide of aluminum (aluminum oxide (Al ₂
O ₃ ) is transparent to visible light and has a thermal conductivity of 20 W
m ^-1 K ^-1 is suitable. Further, aluminum oxide is not limited to the stoichiometric ratio, and other elements may be added to control characteristics such as thermal conductivity characteristics and internal stress. For example, letting aluminum oxide contain nitrogen,
Aluminum oxynitride (AlN _x O _1-x : 0.02 ≦ x ≦
0.5) may be used, or aluminum nitride (A
1N _x ) can also be used. Alternatively, a compound containing silicon (Si), oxygen (O), nitrogen (N), and M (M is at least one selected from aluminum (Al) or a rare earth element) can be used. For example, A
lSiON and LaSiON can be suitably used. In addition, boron nitride or the like can be used.

The above oxides, nitrides, and compounds can all be formed by sputtering or plasma CVD. In the case of the sputtering method, it can be formed by sputtering using a target having a desired composition and using an inert gas such as argon (Ar) or nitrogen. In addition, a thin diamond layer having a thermal conductivity of 1000 Wm ^-1 K ^-1 or D
An LC (Diamond Like Carbon) layer may be provided. In any case, the first insulating layers 502, 5
By forming 03 with a thickness of 50 to 500 nm, preferably 200 nm, a rise in temperature due to laser light irradiation can be suppressed. Further, a film to be laminated on the first insulating layers 502 and 503 is etched in a tapered shape so that an angle of a side wall at an end surface of the first insulating layers 502 and 503 is not less than 5 ° and less than 40 ° with respect to the main surface of the glass substrate 501. Ensure step coverage.

A second insulating layer 504 is formed thereover from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. The silicon oxynitride film is made of Si by a plasma CVD method.
H ₄ and N ₂ O are used as source gases. O ₂ may be added to this source gas. Although the manufacturing conditions are not limited, the thickness of the silicon oxynitride film as the second insulating layer is 5
0 to 500 nm, oxygen content is 55 atomic% or more 7
Less than 0 atomic% and the nitrogen concentration is 1 atomic%
At least 20 atomic%. With such a composition, the internal stress of the silicon oxynitride film is reduced and the fixed charge density is reduced. The second insulating layer is not necessarily required, but is preferably provided for the purpose of preventing alkali metal from diffusing from the substrate 501.

The island-shaped semiconductor layer 505 shown in FIG.
It is formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm). In this method, a semiconductor film having an amorphous structure is formed by a known method such as a plasma CVD method or a sputtering method, and then unnecessary portions are removed by etching. FIG. 5C is a top view thereof, in which the first insulating layer is formed in a striped, rectangular, or strip-shaped pattern, intersects with an island-shaped semiconductor layer 505 formed thereabove, and has a short side. The edge portions are arranged so as not to overlap with the island-shaped semiconductor layer. Examples of the semiconductor film having an amorphous structure for forming the island-shaped semiconductor layer include an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film. May be applied.

FIG. 6 is a view for explaining a crystallization step by the dual beam laser annealing method of the present invention. The crystallization uses a laser annealing method. Alternatively, a rapid thermal annealing method (RTA method) can be applied. In the RTA method, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. Also in this case, light from a light source is irradiated from the surface of the island-shaped semiconductor layer on the substrate side and the surface on the opposite side. In the crystallization step, first, it is desirable to release hydrogen contained in the amorphous semiconductor film.
Heat treatment at about 1 hour for about 1 hour to reduce hydrogen content to 5 atom
It is good to keep it below ic%.

When crystallization is performed by laser annealing, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or argon laser is used as the light source. The configuration of the laser annealing method is as shown in FIGS.

In FIG. 6A, the first laser light 510
And the second laser beam 520 being irradiated to the island-shaped semiconductor layer. Reference numeral 506 denotes a region A in which the island-shaped semiconductor layer is sandwiched between the first insulating layers 502 and 503, and reference numeral 507 denotes a region B outside the region. In any case, the island-shaped semiconductor layer is heated by the irradiation of the laser beam, and temporarily becomes a molten state. It is presumed that crystal nuclei are formed during the cooling process of transition from the molten state to the solid state. The tendency to increase the nucleation density has been obtained as empirical knowledge.

In the structure of FIG. 6A, the portion where the first insulating layers 502 and 503 are formed increases in volume and heat capacity, so that the temperature rise due to laser light irradiation is suppressed. In the dual-beam laser annealing method, laser light is irradiated from the surface of the island-shaped semiconductor layer 505 on the substrate side and the surface on the opposite side, and heating is performed from both surfaces. It is relatively slow in comparison. As a result, the crystal nucleus becomes the first insulating layer 5.
It occurs preferentially from the portion of the island-shaped semiconductor layer overlapping with 02 and 503, and crystal growth starts from that portion toward the periphery.

As a result, large-grain crystals grow around the first insulating layers 502 and 503, and large-grain crystals are formed in a region A 508 surrounded by the first insulating layers 502 and 503. In the region B indicated by 509, relatively small crystal grains are formed. FIG. 6C is a top view showing this state. The distance between the first insulating layers 502 and 503 in the region A is preferably about 2 to 6 μm. Further, such an effect becomes remarkable when the number of repetition pulses of the pulsed laser light to be applied is increased.

Thereafter, the island-shaped semiconductor layer is subjected to a heat treatment at 300 to 450 ° C. in an atmosphere containing 3 to 100% of hydrogen, or a heat treatment at 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. , The residual defects can be neutralized. By manufacturing an active layer of a TFT using the region A of the island-shaped semiconductor layer 505 manufactured as described above as a channel formation region, characteristics of the TFT can be improved.

[Embodiment 2] The method of manufacturing an island-shaped semiconductor layer having a crystal structure to be used as an active layer of a TFT is not only manufactured by a laser annealing method, but also by a laser annealing method and a thermal annealing method according to the present invention. May be used together. In particular, crystallization by thermal annealing is disclosed in
When applied to the crystallization method using a catalyst element disclosed in Japanese Patent No. 30652, crystallization can be realized at a temperature of 600 ° C. or less, and the crystalline semiconductor layer thus manufactured is subjected to a laser annealing method according to the present invention. , A high-quality crystalline semiconductor layer can be obtained. Such an embodiment will be described with reference to FIG.

In FIG. 26A, the glass substrate described in Embodiment Mode 1 can be suitably used for the substrate 550. In addition, the first insulating layers 551 and 552, the second insulating layer 553, and the amorphous semiconductor layer 554 are manufactured in a manner similar to that in Embodiment 1. Then, an aqueous solution containing 5 to 100 ppm by weight of a catalytic element is applied by a spin coating method to form a layer 555 containing the catalytic element. Alternatively, the layer 555 containing a catalyst element may be formed by a sputtering method, an evaporation method, or the like. In that case, the thickness of the layer 555 containing the catalyst element is 0.5 to 2 nm. Nickel (N
i), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (C
o), platinum (Pt), copper (Cu), gold (Au) and the like.

Thereafter, a heat treatment is first performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous semiconductor layer to 5 at.
om% or less. Then, using a furnace annealing furnace, thermal annealing is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours, preferably at 550 ° C. for 4 hours.
Through the above steps, a crystalline semiconductor layer 556 including a crystalline silicon film can be obtained (FIG. 26B). When the crystalline semiconductor layer produced by this thermal annealing is macroscopically observed with an optical microscope, it may be observed that an amorphous region locally remains in such a case. In Raman spectroscopy, an amorphous component having a broad peak at 480 cm ^-1 is observed. But,
Such an amorphous region can be easily removed by the dual beam laser annealing method of the present invention,
A high-quality crystalline semiconductor layer can be obtained.

As shown in FIG. 26C, an island-shaped semiconductor layer is formed from the crystalline semiconductor layer 556. The substrate in this state is subjected to dual-beam laser annealing as in the first embodiment, as shown in FIG. As a result, the first laser light 557 and the second laser light 5
With 58, an island-shaped semiconductor layer 560 having a new crystal structure is once formed through a molten state. In the island-shaped semiconductor layer 560 manufactured in this manner, crystal grains having a grain shape equal to or larger than that of the island-shaped semiconductor layer 508 described with reference to FIG. . However,
In the island-shaped semiconductor layer 560, a catalyst element is 1 × 10 ¹⁷ to 1 ×.
It is contained at a concentration of about 10 ¹⁹ atoms / cm ³ .

[Embodiment 3] In the crystallization method of the semiconductor layer by the dual beam laser annealing method of the present invention, a large crystal is grown in the region A as described with reference to FIGS. There is a feature. In this embodiment, another method for forming a similar crystalline semiconductor layer will be described.

As shown in FIG. 27A, the glass substrate described in Embodiment Mode 1 can be suitably used for the substrate 561. In addition, the first insulating layers 562 and 563, the second insulating layer 564, and the amorphous semiconductor layer 565 are manufactured in the same manner as in Embodiment 1. Then, as shown in FIG. 27B, an island-shaped semiconductor layer 566 is formed from the amorphous semiconductor layer 565. Then, an aqueous solution containing 5 to 100 ppm by weight of a catalytic element is applied by spin coating to form a layer 567 containing the catalytic element.

Thereafter, as shown in FIG. 27C, dual beam laser annealing is performed in the same manner as in the first embodiment. As a result, an island-shaped semiconductor layer 571 having a new crystal structure is formed through the first laser light 568 and the second laser light 569 once in a molten state. In the island-shaped semiconductor layer 571 manufactured in this manner, large crystal grains can be manufactured around the region A. Also in this case, the catalyst element is contained in the island-like semiconductor layer 571 in a range of 1 × 10 ¹⁷ to 1 ×.
It is contained at a concentration of about 10 ¹⁹ atoms / cm ³ .

[0044]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, the n-channel type TF of the pixel portion
A method for simultaneously manufacturing T (hereinafter, referred to as a pixel TFT), a storage capacitor, and an n-channel TFT and a p-channel TFT of a driver circuit provided around a pixel portion will be described in accordance with steps.

In FIG. 7A, a barium borosilicate glass substrate or an aluminoborosilicate glass substrate is used as a substrate 201. In this embodiment, an aluminoborosilicate glass substrate was used. First insulating layers 202 to 206 are formed on a surface of the substrate 201 on which a TFT is to be formed. The first insulating layer is formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like.

When a silicon oxide film is used, tetraethyl orthosilicate (Tetraethyl
Ortho Silicate (TEOS) and O ₂ are mixed, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (1
(3.56 MHz) can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . When a silicon oxynitride film is used, SiH ₄ , N ₂ O, NH ₃
A silicon oxynitride film made from SiH ₄ ,
N ₂ O may be formed by a silicon oxynitride film made from. The production conditions in this case are a reaction pressure of 20 to 200 Pa,
The substrate can be formed at a substrate temperature of 300 to 400 ° C. and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² .
Alternatively, a hydrogenated silicon oxynitride film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method.

As the first insulating layer, an insulating film typified by the above is formed on the entire surface of the substrate 201 to a thickness of 20 to 200 nm (preferably 30 to 60 nm), and then the photolithography technique is used. A resist mask is formed, and unnecessary portions are removed by etching to form a predetermined pattern. For the insulating film, a dry etching method using a fluorine-based gas may be used, or a wet etching method using a fluorine-based aqueous solution may be used. When the latter method is selected, for example, a mixed solution containing 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and 15.4% of ammonium fluoride (NH ₄ F) (manufactured by Stella Chemifa, It is good to etch with LAL500 (trade name).

The pattern size of the first insulating layer is appropriately determined by a practitioner, but may actually be determined in consideration of the size (channel length, channel width) of the TFT to be manufactured. For example, 0.5 to 2 μm (preferably 1 μm) in the channel length direction of the TFT forming the first insulating layers 202a and 202b, and 0.2 to 1 μm in the channel width direction.
It is formed in a stripe shape, a rectangular shape or a strip shape of 0 μm (preferably 4 to 8 μm). The distance between the first insulating layers 202a and 202b is 1 to 10 μm (preferably 3 to 6 μm). The other first insulating layers illustrated in FIG. 7A have the same structure.

Next, the second insulating layer 2 is formed on the first insulating layer.
07 is formed. This layer is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like to a thickness of 50 to 300 nm (preferably 100 to 200 nm), like the first insulating layer.

Next, 25 to 80 nm (preferably 30 to 80 nm)
Semiconductor layer 208 having a thickness of 60 nm and having an amorphous structure.
Is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. Also,
Since the second insulating layer 207 and the amorphous silicon layer 208 can be formed by a plasma CVD method, both may be formed continuously in a reduced-pressure atmosphere. Second insulating layer 2
After the formation of the TFT 07, it is possible to prevent the surface from being contaminated by not once exposing it to the air atmosphere.
And variations in threshold voltage can be reduced.

Then, as shown in FIG. 7B, unnecessary portions of the amorphous semiconductor layer 208 are removed by etching to form island-like semiconductor layers 209 to 212. The shape and size of the island-shaped semiconductor layer may be appropriately determined by a practitioner. For example, when combined with the above-described first insulating layers 202a and 202b, the shape and size are 0.2 to 20 μm (preferably 4 to 20 μm) in the channel length direction. ~
10 μm), 0.5 to 50 μm in the channel width direction
(Preferably 4 to 20 μm).

The crystallization of the island-like semiconductor layers 209 to 212 is performed by a dual beam laser annealing method. For this, any of the methods described in the first to third embodiments may be applied. For example, a XeCl excimer laser (wavelength 308n)
m) was used as a laser light generator, and the laser annealing apparatus shown in FIGS. 2 to 4 was used to form a linear beam with an optical system.
Irradiation is performed with a linear beam overlap ratio of 80 to 98% at 500 mJ / cm ² . Thus, the island-shaped semiconductor layers 209 to 212 are crystallized.

Thereafter, plasma CVD or low pressure CVD
A mask layer 213 of a silicon oxide film having a thickness of 50 to 100 nm is formed by a sputtering method or a sputtering method. For example, using a mixed gas of SiH ₄ and O ₂ by a low pressure CVD method,
The silicon oxide film is formed by heating at 266 Pa to 400 ° C. (FIG. 7C).

In the channel doping step, a photoresist mask 214 is provided, and 1 × 10 ^{16 to} 5 × 10
^At a concentration of about ¹⁷ atoms / cm ³ , boron (B) is added as an impurity element imparting p-type. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. The channel doping is performed for the purpose of controlling the threshold voltage, and is not an essential step for manufacturing a TFT. (See FIG. 7).
(D)).

Then, in order to form the LDD region of the n-channel TFT of the driving circuit, an impurity element imparting n-type is selectively added to the island-shaped semiconductor layers 210b and 211b. Photoresist masks 215 to 218 are formed in advance. In this step, an ion doping method using phosphine (PH ₃ ) is applied to add phosphorus (P). The phosphorus (P) concentration of the impurity regions (n ⁻ ) 219 and 220 to be formed is 1 × 10 ^{17 to} 5 × 10 ¹⁹ atoms / cm ³ (FIG. 8A). The impurity region 221 is a semiconductor layer for forming a storage capacitor in a pixel portion, and it is preferable that phosphorus (P) be added to this region at the same concentration to improve conductivity.

Next, a step of removing the mask layer 213 with hydrofluoric acid or the like to activate the impurity element added in FIGS. 7D and 8A is performed. Activation can be performed by thermal annealing at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or by laser annealing.
Further, both may be performed in combination. In this embodiment, a linear beam is formed using a KrF excimer laser beam (wavelength: 248 nm) using a laser activation method, and has an oscillation frequency of 5 to 50 Hz and an energy density of 100 to 500.
Scanning is performed with the overlap ratio of the linear beam set to 80 to 98% at mJ / cm ² to process the entire surface of the substrate on which the island-shaped semiconductor layer is formed. The irradiation conditions of the laser beam are not particularly limited, and may be appropriately determined by the practitioner.

Then, the gate insulating film 222 is formed by plasma C
The insulating film containing silicon is formed with a thickness of 40 to 150 nm by a VD method or a sputtering method. For example, SiH
₄ , a silicon oxynitride film formed by a plasma CVD method using N ₂ O and O ₂ as raw materials (FIG. 8B).

Next, a first conductive layer for forming a gate electrode is formed. This conductive layer may be formed as a single layer, but may have a laminated structure such as two layers or three layers as necessary. In this embodiment, a structure is used in which a conductive layer (A) 223 made of a conductive metal nitride film and a conductive layer (B) 224 made of a metal film are stacked. Conductive layer (B)
Reference numeral 224 denotes an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the above elements as a main component, or an alloy film combining the above elements (typically, Mo-W alloy film, Mo-Ta
The conductive layer (A) 223 may be formed using tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), molybdenum nitride (MoN), or the like. The conductive layer (A) 223 may be formed using tungsten silicide, titanium silicide, or molybdenum silicide. The conductive layer (B) 224 preferably has a low impurity concentration in order to reduce the resistance, and particularly preferably has an oxygen concentration of 30 ppm or less. For example, tungsten (W) can realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.

The conductive layer (A) 223 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 224 has a thickness of 200 to 400 nm (preferably 250 to 350 nm).
It is good. In this embodiment, the conductive layer (A) 223
A TaN film having a thickness of 0 nm is formed on the conductive layer (B) 224 by 3
All are formed by a sputtering method using a 50 nm Ta film. The TaN film is formed using Ta as a target and a mixed gas of Ar and nitrogen as a sputtering gas. Ta uses Ar as a sputtering gas. When an appropriate amount of Xe or Kr is added to these sputter gases, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. α
The phase Ta film has a resistivity of about 20 μΩcm and can be used as a gate electrode, but the β phase Ta film has a resistivity of 1 μm.
It is about 80 μΩcm, which is not suitable for a gate electrode. Since the TaN film has a crystal structure close to the α-phase, an α-phase Ta film can be easily obtained by forming a Ta film thereon.
Although not shown, 2 to 20 layers are formed below the conductive layer (A) 223.
It is effective to form a silicon film doped with phosphorus (P) with a thickness of about nm. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 222. Can be prevented. In any case, the conductive layer (B) preferably has a resistivity in the range of 10 to 500 μΩcm (FIG. 8C).

Next, photoresist masks 225 to 22
9 and a conductive layer (A) 223 and a conductive layer (B) 224
Are collectively etched to form gate electrodes 230-233. For example, it can be performed at a reaction pressure of 1 to 20 Pa using a mixed gas of CF ₄ and O ₂ or Cl ₂ by a dry etching method. Gate electrodes 230 to 233
Is formed integrally with the conductive layers (A) 230a to 233a and the conductive layers (B) 230b to 233b. At this time, the gate electrodes 231 and 232 provided in the n-channel TFT are formed so as to overlap with part of the impurity regions 219 and 220 (FIG. 8D). Further, the gate electrode can be formed using only the conductive layer (B).
234 is formed as a storage capacitor line (FIG. 8).
(D)).

Next, in order to form a source region and a drain region of the p-channel TFT of the driving circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 230 as a mask. A region where the n-channel TFT is to be formed is covered with a photoresist mask 235. Then, an impurity region (p ⁺ ) 236 is formed at a concentration of 1 × 10 ²¹ atoms / cm ³ by an ion doping method using diborane (B ₂ H ₆ ) (FIG. 9A).

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region is formed. Resist masks 237 to 239 are formed, and an impurity element for imparting n-type
41 to 244 are formed. This is a phosphine (PH
₃ ) The impurity region (n ⁺ )
The (P) concentration of 241 to 244 is set to 5 × 10 ²⁰ atoms / cm ³ (FIG. 9B). The impurity region 240 already contains boron (B) added in the previous step, but only phosphorus (P) is added at a concentration of ２〜 to し て of that in the impurity region 240. It is not necessary to consider the effect of the phosphorus (P) that has been applied, and the characteristics of the TFT are not affected at all.

The L of the n-channel TFT in the pixel portion is
In order to form a DD region, a step of adding an impurity for imparting n-type is performed. Here, an impurity element imparting n-type is added in a self-aligned manner by an ion doping method using the gate electrode 233 as a mask. The concentration of phosphorus (P) to be added is 5 × 10
And ¹⁶ atoms / cm ^3, as FIG. 8 (A) and FIG. 9 (A) 9
By adding at a concentration lower than the concentration of the impurity element added in (B), the impurity regions (n ⁻ ) 245,
Only 46 are formed (FIG. 9C).

Thereafter, a heat treatment step is performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation step is performed by furnace annealing. The heat treatment has an oxygen concentration of 1 ppm or less, preferably 0.1 ppm.
The heat treatment is performed at 400 to 700 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere of 1 ppm or less. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours.

In this thermal annealing, the gate electrode 23
0 to 233 and a Ta film 230b to form the capacitor wiring 234
234b has conductive layers (C) 230c to 234c made of TaN with a thickness of 5 to 80 nm from the surface. In addition, when the conductive layers (B) 230b to 234b are tungsten (W), tungsten nitride (WN) is formed, and when the conductive layers (B) 230b to 234b are titanium (Ti), titanium nitride (Ti) is formed.
N) can be formed. Alternatively, the gate electrodes 230 to 234 can be formed similarly by exposing the gate electrodes 230 to 234 to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, in an atmosphere containing 3 to 100% hydrogen,
Thermal annealing is performed at 00 to 450 ° C. for 1 to 12 hours to hydrogenate the island-shaped semiconductor layer. This step in the island-like semiconductor layers by thermally excited hydrogen 10 ^16-10
This is a step of terminating dangling bonds of ¹⁸ / cm ³ . As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

In the case of using a catalytic element for promoting crystallization of silicon in the crystallization step and not performing the gettering step described in the third embodiment thereafter, a very small amount (1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ ) of the catalytic element remains. Of course, the TFT can be completed in such a state, but it is more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing a gettering action by phosphorus (P).
The concentration of phosphorus (P) required for gettering may be the same as that of the impurity region (n ⁺ ) formed in FIG. 9B, and the n-channel type The catalyst element can be segregated into the impurity regions 240 to 244 from the channel formation region of the TFT and the p-channel TFT. As a result, impurity regions 240 to 244
The catalyst elements of about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ are segregated (FIG. 9D).

FIGS. 12A and 13A show FIG.
FIG. 10D is a top view of the TFT in FIG. 9D, in which AA ′ section and CC ′ section are AA ′ and CC ′ in FIG. 9D.
It corresponds to. In addition, the BB ′ cross section and the DD ′ cross section correspond to the cross-sectional views of FIGS. 14A and 15A. Although the gate insulating film is omitted in the top views of FIGS. 12 and 13, the gate insulating film is formed on the island-shaped semiconductor layers 209, 210, and 212 formed on the first and second insulating layers in the steps so far. Electrodes 230, 231, 233 and capacitance wiring 234
Are formed as shown in the figure.

When the activation and hydrogenation steps are completed,
A second conductive layer for forming a gate line is formed. This second
Is formed of a conductive layer (D) mainly composed of a low-resistance material such as aluminum (Al) or copper (Cu). In any case, the resistivity of the second conductive layer is 0.1 to 10 μΩ.
cm. Furthermore, titanium (Ti) and tantalum (T
a), a conductive layer (E) made of tungsten (W) and molybdenum (Mo) is preferably formed by lamination. In this embodiment,
A conductive layer (D) 247 is formed of an aluminum (Al) film containing 0.1 to 2% by weight of titanium (Ti), and titanium (T) is formed.
i) The film was formed as the conductive layer (E) 248. The conductive layer (D) 247 has a thickness of 200 to 400 nm (preferably 250 nm).
３５０350 nm), and the conductive layer (E) 248
The thickness may be from 0 to 200 (preferably 100 to 150 nm) (FIG. 10A).

Then, the conductive layer (E) 248 and the conductive layer (D) 24 are formed to form a gate line connected to the gate electrode.
7 is etched to form gate wirings 249, 250
And a capacitor wiring 251 are formed. The etching treatment is first performed from the surface of the conductive layer (E) to the conductive layer (D) by a dry etching method using a mixed gas of SiCl ₄ , Cl ₂ and BCl _3.
Then, the conductive layer (D) is removed by wet etching using a phosphoric acid-based etching solution, whereby the gate wiring can be formed while maintaining the selectivity with the base (FIG. 10B )).

FIGS. 12 (B) and 13 (B) show top views in this state, and the AA 'section and CC' section are taken along AA 'and CC' in FIG. 10 (B). It corresponds to. The BB 'section and the DD' section correspond to BB 'and DD' in FIGS. 14B and 15B, respectively. In FIGS. 12B and 13B, part of the gate wirings 249 and 250 are
1 and 233, and overlaps and is in electrical contact. This state is shown in FIG. 14 corresponding to the BB ′ section and the DD ′ section.
15B and FIG. 15B, the conductive layer (C) forming the first conductive layer and the conductive layer (D) forming the second conductive layer are electrically connected to each other. In contact.

The first interlayer insulating film 252 has a thickness of 500 to 150
It is formed using a silicon oxide film or a silicon oxynitride film with a thickness of 0 nm. In this embodiment, 27 SCCM of SiH ₄ and N ₂
O is 900 SCCM, reaction pressure 160 Pa, substrate temperature 3
It was formed at 25 ° C. with a discharge power density of 0.15 W / cm ² . After that, a contact hole reaching the source region or the drain region formed in each island-shaped semiconductor layer is formed,
Source wirings 253 to 256 and drain wirings 257 to 2
Form 60. Although not shown, in this embodiment, this electrode is a laminated film having a three-layer structure in which a 100 nm thick Ti film, a 300 nm thick aluminum film containing Ti, and a 150 nm thick Ti film are continuously formed by a sputtering method.

Next, as a passivation film 261,
Silicon nitride, silicon oxide, or silicon oxynitride
50-500 nm (typically 100-300 nm)
(nm). Hydrogenation is performed in this state
In addition, favorable results can be obtained for improving the characteristics of the TFT.
For example, in an atmosphere containing 3 to 100% hydrogen, 300
It is good to perform heat treatment at ~ 450 ° C for 1 to 12 hours.
The same effect can be obtained by using the plasma hydrogenation method.
You. Further, the first interlayer insulating film 2 is formed by such heat treatment.
The hydrogen existing in the region 52 is spread to the island-shaped semiconductor layers 209 to 212.
Hydrogenation can also be carried out. In any case, the island
Defect density of the semiconductor layers 209 to 212 is 10 ¹⁶/cm^ThreeLess than
It is desirable that the hydrogen for 0.01 ~
What is necessary is just to give about 0.1 atomic% (FIG.10 (C)).
Note that the pixel electrode and the drain wiring are connected later.
At the position where the contact hole for
An opening may be formed in the activation film 261.

FIGS. 12 (C) and 13 (C) show top views in this state. AA ′ section and CC ′ section are taken along AA ′ and CC in FIG. 10 (C). 'Is supported.
The BB 'section and the DD' section correspond to BB 'and DD' in FIGS. 14C and 15C, respectively. Although the first interlayer insulating film is omitted in FIGS. 12C and 13C, the island-shaped semiconductor layers 209, 210, and 21 are omitted.
Source lines 253, 254, 256 and drain lines 257, 25
8 and 260 are connected via a contact hole formed in the first interlayer insulating film.

Thereafter, as shown in FIG. 11, a second interlayer insulating film 262 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, a polyimide that is thermally polymerized after being applied to the substrate is used.
It is formed by firing at 00 ° C. Then, a contact hole reaching the drain wiring 260 is formed in the second interlayer insulating film 262, and pixel electrodes 263 and 264 are formed. As the pixel electrode, a transparent conductive film may be used for a transmission type liquid crystal display device, and a metal film may be used for a reflection type liquid crystal display device. In this embodiment, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film,
A transparent conductive film selected from a zinc oxide (ZnO) film, an indium oxide / tin / zinc oxide film, or the like is formed to a thickness of 100 nm by a sputtering method.

As described above, the TFT of the driving circuit is formed on the same substrate.
And a substrate having the pixel TFT of the pixel portion. The driving circuit includes a p-channel TFT 301, a first n-channel TFT 302, and a second n-channel TFT
FT303, pixel TFT 304 in the pixel portion, storage capacitor 3
05 is formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the p-channel TFT 301 of the driving circuit, the channel forming region 306, the source regions 307a and 307b, the drain region 308a,
308b. First n-channel TFT 30
2 includes a channel formation region 30 in the island-shaped semiconductor layer 210.
9. LDD region (Lov) 31 overlapping gate electrode 231
0, a source region 311, and a drain region 312. The length of the Lov region in the channel length direction is 0.5 to
3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 303 has an island-shaped semiconductor layer 21.
Reference numeral 1 denotes a channel forming region 313, an Lov region and an Loff region (an LDD region which does not overlap with the gate electrode.
The Loff region has a length in the channel length direction of 0.3 to 2.0 μm, preferably 0.5 to 2.0 μm.
１．５1.5 μm. In the pixel TFT 304, channel formation regions 318, 319, Loff
Regions 320 to 323, source or drain region 324
To 326. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm.
μm. Further, the capacitor wirings 234 and 251, an insulating film made of the same material as the gate insulating film,
4 and a semiconductor layer 327 to which an impurity element imparting n-type is added.
5 are formed. In FIG. 12, the pixel TFT 304 has a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

With the above-described configuration, it is possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the driving circuit, and to improve the operation performance and reliability of the semiconductor device. . Further, the activation of the LDD region, the source region, and the drain region is facilitated by forming the gate electrode with a conductive material having heat resistance,
By forming the gate wiring from a low-resistance material, the wiring resistance can be sufficiently reduced. Therefore, the pixel portion (screen size) is 4
The invention can be applied to a display device of an inch class or more.
Then, the first insulating layers 203 to 206 forming an underlayer are formed.
By using the crystalline silicon film having a single crystal structure selectively formed above, n
In the channel type TFT, the S value is 0.10 V / dec or more.
30 V / dec or less, Vth 0.5 V or more and 2.5 V or less,
Field effect mobility of 300 cm ² / V · sec or more can be realized. In a p-channel type TFT, the S value is set to 0.1.
10V / dec or more and 0.30V / dec or less, Vth is -0.5V
-2.5 V or less, field-effect mobility is 200 cm ² / V · se
c or more can be achieved.

[Embodiment 2] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described. As shown in FIG. 16, an alignment film 601 is formed on the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. A light-shielding film 603, a counter electrode 604, and an alignment film 605 are formed on the counter substrate 602. After forming the alignment film, a rubbing treatment is performed so that the liquid crystal molecules are aligned with a certain pretilt angle. Then, the active matrix substrate on which the pixel portion and the CMOS circuit are formed and the opposing substrate are bonded to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. Thereafter, a liquid crystal material 606 is injected between the two substrates, and a sealing agent (not shown) is used.
Complete sealing. A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 16 is completed.

Next, the configuration of this active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 17 and the top view of FIG. Note that FIGS. 17 and 18 correspond to FIGS.
In order to correspond to the cross-sectional structural views of FIG. 1 and FIG. 16, common reference numerals are used. The cross-sectional structure along EE ′ shown in FIG. 18 corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG.

In FIG. 17, an active matrix substrate includes a pixel portion 406 formed on a glass substrate 201,
It is composed of a scanning signal driving circuit 404 and an image signal driving circuit 405. A pixel TFT 304 is provided in the pixel portion,
The driving circuit provided on the periphery is configured based on a CMOS circuit. The scanning signal driving circuit 404 and the image signal driving circuit 405 are connected to the pixel TFT 304 by a gate wiring 250 and a source wiring 256, respectively. Also, F
A PC (Flexible Print Circuit) 731 is connected to the external input terminal 734, and is connected to each drive circuit via input wirings 402 and 403.

FIG. 18 is a top view showing almost one pixel of the pixel portion 406. FIG. The gate wiring 250 crosses the semiconductor layer 212 thereunder via a gate insulating film (not shown). Although not shown, an Loff region including a source region, a drain region, and an n ⁻ region is formed in the semiconductor layer. Reference numeral 265 denotes a contact portion between the source wiring 256 and the source region 324, and 266 denotes a drain wiring 26.
A contact portion 267 between the zero and the drain region 326 is a contact portion between the drain wiring 260 and the pixel electrode 263. The storage capacitor 305 is formed in a region where the capacitor wirings 234 and 251 overlap with the semiconductor layer 327 extending from the drain region 326 of the pixel TFT 304 via a gate insulating film.

Although the active matrix type liquid crystal display device of the present embodiment has been described with reference to the structure described in the first embodiment, the present invention is not limited to the configuration of the first embodiment. An active matrix substrate completed by applying the configuration shown in to the first embodiment may be used.

[Embodiment 3] FIG. 19 is a diagram showing an example of an arrangement of input / output terminals, a pixel portion, and a driving circuit of a liquid crystal display device.
In the pixel portion 406, m gate wirings and n source wirings intersect in a matrix. For example, if the pixel density is V
In the case of GA, 480 gate lines and 640 source lines are formed, and in the case of XGA, 768 gate lines and 1024 source lines are formed. The screen size of the pixel unit is 3 inches for a 13-inch class.
40mm, 460m for 18 inch class
m. In order to realize such a liquid crystal display device, it is necessary to form the gate wiring with a low-resistance material as described in the first embodiment. When the time constant (resistance × capacitance) of the gate wiring increases, the response speed of the scanning signal decreases, and the liquid crystal cannot be driven at high speed. For example, when the specific resistance of the material forming the gate wiring is 100 μΩcm, the screen size of the 6-inch class is almost the limit.

A scanning signal driving circuit 404 and an image signal driving circuit 405 are provided around the pixel portion 406. Since the length of the gate wiring of these driving circuits is inevitably increased with the increase in the screen size of the pixel portion, the aluminum (A
1) It is preferable to form the gate wiring with a low-resistance material such as copper (Cu). In addition, according to the present invention, the input wirings 402 and 403 connecting the input terminal 401 to each drive circuit can be formed of the same material as the gate wiring, which can contribute to a reduction in wiring resistance.

On the other hand, when the screen size of the pixel portion is in the class of 0.9 inch, the length of the diagonal line is about 24 mm. Fits within ² . In such a case, it is not always necessary to form the gate wiring with a low-resistance material as described in Embodiment 3, and the gate wiring is formed with the same material as the gate electrode such as Ta or W. It is also possible.

The liquid crystal display device having such a configuration can be completed using an active matrix substrate completed by applying the crystallization method described in Embodiments 1 to 3 to Example 1. In any case, an active matrix type liquid crystal display device can be manufactured by freely combining active matrix substrates that are completed by the crystallization techniques described in Embodiments 1 to 3.

[Embodiment 4] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured using the active matrix substrate of the present invention will be described. FIG.
0 (A) is a top view of an EL display device using the present invention. In FIG. 20A, 10 is a substrate, 11 is a pixel portion, 12 is a source side drive circuit, 13 is a gate side drive circuit, and each drive circuit has
The PC 17 is connected to an external device.

At this time, the opposing plate 18 is provided so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion. The opposing plate 18 is adhered to the active matrix substrate on which the TFT and the EL layer are formed by a sealant 81. The space formed between the active matrix substrate and the opposing plate is filled with a resin material 20, such as silicone, phenol, epoxy, or acrylic. Since the EL element is susceptible to moisture and moisture and easily deteriorates, mixing a desiccant such as barium oxide into the resin material 20 is effective in increasing moisture resistance. The opposite plate 18 may be a glass plate, a plastic plate, a metal plate, or the like. Thus, the EL element is completely sealed in the closed space, and is completely shut off from the outside air.

FIG. 20B shows a cross-sectional structure of the EL display device of this embodiment, in which a TFT for a driving circuit (here, an n-channel TFT and a p-channel TFT) is formed on a substrate 10 and a base film 21. A CMOS circuit combining TFTs is shown) 22 and a TFT 23 for a pixel portion (however, only a TFT for controlling current to an EL element is shown here). As the driving circuit TFT 22, the n-channel TFT 302 or the p-channel TFT 302 shown in FIG.
A channel type TFT 301 may be used. The n-channel TFT 3 shown in FIG.
04 or p-channel type TF having a structure similar thereto
T may be used.

When the TFT 22 for the drive circuit and the TFT 23 for the pixel portion are completed by using the present invention, a transparent electrically connected to the drain of the TFT 23 for the pixel portion is formed on the interlayer insulating film (flattening film) 26 made of a resin material. Pixel electrode 27 made of conductive film
To form As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used. After the pixel electrode 27 is formed, an insulating film 28 is formed, and an opening is formed on the pixel electrode 27.

Next, an EL layer 29 is formed. EL layer 29
Are known EL materials (a hole injection layer, a hole transport layer, a light emitting layer,
An electron transport layer or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. EL materials include low molecular weight materials and high molecular weight (polymer) materials.
When a low molecular material is used, an evaporation method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.

In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After the EL layer 29 is formed, the cathode 3
0 is formed. It is desirable to remove moisture and oxygen existing at the interface between the cathode 30 and the EL layer 29 as much as possible. Therefore, the EL layer 29 and the cathode 30 are continuously formed in a vacuum,
It is necessary to devise that the EL layer 29 is formed in an inert atmosphere and the cathode 30 is formed without opening to the atmosphere. In this embodiment, a multi-chamber method (cluster tool method)
By using the film forming apparatus described above, the film forming as described above can be performed.

In this embodiment, the cathode 30 is made of Li
A laminated structure of an F (lithium fluoride) film and an Al (aluminum) film is used. Specifically, one layer is formed on the EL layer 29 by vapor deposition.
A LiF (lithium fluoride) film having a thickness of 300 nm is formed, and an aluminum film having a thickness of 300 nm is formed thereon. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 30 is connected to the wiring 16 in a region indicated by 31. The wiring 16 is a power supply line for applying a predetermined voltage to the cathode 30, and is connected to the FPC 17 via a conductive paste material 32. A resin layer 80 is further formed on the FPC 17 to increase the adhesive strength at this portion.

In order to electrically connect the cathode 30 and the wiring 16 in the region 31, it is necessary to form contact holes in the interlayer insulating film 26 and the insulating film 28. These may be formed at the time of etching the interlayer insulating film 26 (at the time of forming a contact hole for a pixel electrode) or at the time of etching the insulating film 28 (at the time of forming an opening before forming an EL layer). Further, when the insulating film 28 is etched, the etching may be performed all at once up to the interlayer insulating film 26. In this case, if the interlayer insulating film 26 and the insulating film 28 are made of the same resin material, the shape of the contact hole can be made good.

The wiring 16 has a gap between the sealing material 81 and the substrate 10 (however, the wiring 16 is closed with the adhesive 19).
And is electrically connected to the FPC 17. Although the wiring 16 has been described here, the other wirings 14, 15
In the same manner, pass under the sealing material 18 and pass through the FPC 17
Is electrically connected to

The present invention can be used in the EL display device having the above configuration. FIG. 21 shows a more detailed sectional structure of the pixel portion, and FIG.
FIG. 22A shows a circuit diagram. FIG. 21, FIG.
2 (A) and FIG. 22 (B) use the same reference numerals, so they may be referred to each other.

In FIG. 21, the switching TFT 2402 provided on the substrate 2401 is the same as that of the present invention (for example,
N-channel type TF of the TFT shown in FIG.
It is formed using T303. In this embodiment, a double gate structure is used. However, since there is no significant difference in the structure and the manufacturing process, the description is omitted. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure may be used, or a triple gate structure or a multi-gate structure having more gates may be used. Alternatively, the p-channel TFT of the present invention
May be used.

The current controlling TFT 2403 is the same as that shown in FIG.
1 is formed using an n-channel TFT 302.
At this time, the drain wiring 35 of the switching TFT 2402 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. The wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 2402.

At this time, it is very important that the current control TFT 2403 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current control TFT so as to overlap with the gate electrode (strictly, a sidewall functioning as a gate electrode) via the gate insulating film is extremely effective.

In this embodiment, the current controlling TFT 2403 is shown in a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

As shown in FIG. 22A, the current control T
A wiring serving as the gate electrode 37 of the FT 2403 is a region indicated by reference numeral 2404 and overlaps with the drain wiring 40 of the current controlling TFT 2403 via an insulating film. At this time, 2404
A capacitor is formed in the region indicated by. The capacitor 2404 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 2403. The drain wiring 40 is connected to the current supply line (power supply line) 2
501, a constant voltage is always applied.

The first passivation film 4 is formed on the switching TFT 2402 and the current control TFT 2403.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the steps due to the TFT using the flattening film 42. Since an EL layer formed later is very thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
403 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

The light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by the banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green), B
Light emitting layers corresponding to each color of (blue) may be separately formed. As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

There are various types of PPV-based organic EL materials, for example, H. Shenk, Becker, O. Gel
sen, E. Kluge, W. Kreuder and H. Spreitzer, “Polymers
for Light Emitting Diodes ”, Euro Display, Proceedi
ngs, 1999, p.33-37 "and JP-A-10-92576.

As specific light emitting layers, cyanopolyphenylenevinylene is used for a red light emitting layer, polyphenylenevinylene is used for a green light emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example is shown in which a polymer material is used for the light emitting layer, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
The EL layer has a laminated structure in which a hole injection layer 46 made of (polythiophene) or PAni (polyaniline) is provided. An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 2
405 is completed. Note that the EL element 2405 referred to here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, and the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display device of the present invention has the structure shown in FIG.
A switching TFT having a sufficiently low off-current value and a current controlling TFT resistant to hot carrier injection are provided. Therefore, an EL display device having high reliability and capable of displaying an excellent image can be obtained.

The configuration of this embodiment is similar to that of the first to third embodiments.
The present invention can be freely combined with the configuration of the first embodiment. In addition, it is effective to use the EL display device according to the present embodiment as the display unit of the electronic device according to the eighth embodiment.

[Embodiment 5] In this embodiment, a structure in which the EL element 2405 is inverted in the pixel portion shown in Embodiment 4 will be described. FIG. 23 is used for the description. Note that only the structure of FIG. 22A is different from that of the EL element and the current controlling TFT, and therefore, the other description is omitted.

In FIG. 23, the current controlling TFT 260
1 is formed using the p-channel TFT of the present invention.
Embodiment 1 can be referred to for the manufacturing process. In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50.
Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, the banks 51a and 51b made of an insulating film are used.
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 2602 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed as shown by the arrow. In the case of the structure as in this embodiment, it is preferable that the current control TFT 2601 be formed of a p-channel TFT.

The configuration of the present embodiment is similar to the first to third embodiments.
The present invention can be freely combined with the configuration of the first embodiment. In addition, it is effective to use the EL display of this embodiment as the display unit of the electronic device of the eighth embodiment.

[Embodiment 6] In this embodiment, FIG. 24 shows an example in which a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, 2701
270 is the source wiring of the switching TFT 2702, 270
3 is a gate wiring of the switching TFT 2702, 27
04 is a current control TFT, 2705 is a capacitor, 27
Reference numerals 06 and 2708 denote current supply lines, and 2707 denotes an EL element.

FIG. 24A shows an example in which a current supply line 2706 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 2706. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 24B shows the current supply line 270.
8 is provided in parallel with the gate wiring 2703. Note that although FIG. 24B illustrates a structure in which the current supply line 2708 and the gate wiring 2703 are provided so as not to overlap with each other, if the wiring is formed in a different layer,
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 2708 and the gate wiring 2703 can share an occupied area, the pixel portion can have higher definition.

In FIG. 24C, a current supply line 2708 is provided in parallel with the gate wiring 2703 in the same manner as in the structure of FIG. 24B, and two pixels are connected to the current supply line 2708.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 2708 so as to overlap with one of the gate wirings 2703. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

In FIGS. 24A and 24B, the capacitor 2705 is provided to hold the voltage applied to the gate of the current controlling TFT 2704. However, the capacitor 2705 can be omitted.

Since the n-channel TFT of the present invention as shown in FIG. 21 is used as the current controlling TFT 2704, it has an LDD region provided so as to overlap with the gate electrode (via the gate insulating film). In this overlapped region, a parasitic capacitance generally called a gate capacitance is formed, but in this embodiment, this parasitic capacitance is
It is characterized in that it is actively used in place of 05.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

In the structure shown in FIGS. 24A, 24B and 24C, the capacitor 2705 can be omitted in the same manner.

The configuration of this embodiment is similar to that of the first to third embodiments.
The present invention can be freely combined with the configuration of the first embodiment. In addition, it is effective to use the EL display device having the pixel structure of the present embodiment as the display unit of the electronic device of the eighth embodiment.

[Embodiment 7] Various liquid crystals other than the nematic liquid crystal can be used in the liquid crystal display device shown in the embodiment 2. For example, 1998, SID, "Characteristics
and Driving Scheme of Polymer-Stabilized Monostabl
e FLCD Exhibiting Fast Response Time and High Cont
rast Ratio with Gray-Scale Capability "by H. Furue
et al., 1997, SID DIGEST, 841, "A Full-Color Th
resholdless Antiferroelectric LCD Exhibiting Wide
Viewing Angle with Fast Response Time "by T. Yoshi
daet al., 1996, J. Mater. Chem. 6 (4), 671-673, "
Thresholdless antiferroelectricity in liquid cryst
als and its application to displays "by S. Inui et
al. and US Pat. No. 5,594,569.

Using a ferroelectric liquid crystal (FLC) exhibiting an isotropic phase-cholesteric phase-chiral smectic phase transition series, a cholesteric phase-chiral smectic phase transition is performed while applying a DC voltage, and the cone edge is almost rubbed in the rubbing direction. FIG. 25 shows the electro-optical characteristics of the monostable FLC according to FIG. The display mode using the ferroelectric liquid crystal as shown in FIG. 25 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 25 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Half-
For the "V-shaped switching mode", see "Ha
lf-V switching mode FLCD ", Proceedings of the 46th Joint Lecture on Applied Physics, March 1999,
Pp. 1316, and "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal" by Yoshihara et al., Liquid Crystal, Vol.

As shown in FIG. 25, when such a ferroelectric mixed liquid crystal is used, it can be seen that low voltage driving and gradation display can be performed. A ferroelectric liquid crystal having such electro-optical characteristics can be used in the liquid crystal display device of the present invention.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

Since low-voltage driving is realized by using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low power consumption is realized.

[Embodiment 8] In this embodiment, the TFT of the present invention is used.
A semiconductor device incorporating an active matrix type liquid crystal display device using circuits will be described with reference to FIGS.

Such a semiconductor device includes a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer,
TV and the like. FIGS. 28 and 29 show examples of these.
Shown in

FIG. 28A shows a portable telephone, and a main body 90.
01, audio output unit 9002, audio input unit 9003, display device 9004, operation switch 9005, antenna 900
6. The present invention provides an audio output unit 9002,
The present invention can be applied to the voice input portion 9003 and the display device 9004 including the active matrix substrate.

FIG. 28B shows a video camera, which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
06. The present invention relates to a display device 910 including a voice input unit 9103 and an active matrix substrate.
2. It can be applied to the image receiving unit 9106.

FIG. 28C shows a mobile computer, which includes a main body 9201, a camera section 9202, and an image receiving section 920.
3, an operation switch 9204, and a display device 9205. The invention can be applied to the display device 9205 including the image receiving portion 9203 and the active matrix substrate.

FIG. 28D shows a head-mounted display, which comprises a main body 9301, a display device 9302, and an arm portion 9303. The invention can be applied to the display device 9302. Although not shown, it can be used for other signal control circuits.

FIG. 28E shows a rear type projector, which includes a main body 9401, a light source 9402, a display device 9403,
Polarizing beam splitter 9404, reflector 940
5, 9406 and a screen 9407. The invention can be applied to the display device 9403.

FIG. 28F shows a portable book, and a main body 95.
01, display devices 9502 and 9503, storage medium 950
4, comprising an operation switch 9505 and an antenna 9506 for displaying data stored on a mini disk (MD) or a DVD or data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 29A shows a personal computer, which includes a main body 9601, an image input section 9602, and a display device 9.
603 and a keyboard 9604.

FIG. 29B shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 9701, a display device 9702, and a speaker unit 97.
03, a recording medium 9704, and operation switches 9705. This device uses a DVD (Digi
(tal Versatile Disc), CDs, etc., to enjoy music, movies, games and the Internet.

FIG. 29C shows a digital camera, which comprises a main body 9801, a display device 9802, an eyepiece 9803, operation switches 9804, and an image receiving unit (not shown).

FIG. 30A shows a front type projector, which comprises a display device 3601 and a screen 3602. The present invention can be applied to a display device and other signal control circuits.

FIG. 30B shows a rear type projector, which includes a main body 3701, a display device 3702, and a mirror 370.
3. It is composed of a screen 3704. The present invention can be applied to a display device and other signal control circuits.

FIG. 30C is a diagram showing an example of the structure of the display devices 3601 and 3702 in FIGS. 30A and 30B. Display devices 3601, 37
02 denotes a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal display device 3808, retardation plate 380
9. It is composed of a projection optical system 3810. Projection optical system 38
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 30D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 30C. In this embodiment, the light source optical system 3801 includes the reflector 38.
11, light source 3812, lens arrays 3813, 381
4. It is composed of a polarization conversion element 3815 and a condenser lens 3816. Note that the light source optical system shown in FIG. 30D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

The present invention also includes an image sensor and an E
It is also possible to apply to an L-type display element. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

[Embodiment 9] A combination in which the width of a first insulating layer and an island-shaped semiconductor layer intersecting with the width of the first insulating layer can be changed to increase the size of crystal grains was examined.
As shown in FIG. 31, the width of the first insulating layer formed in the shape of a strip is W2, the interval is Δ, the width of the island-shaped semiconductor layer is W1, and as shown in Table 1, W1 is 4 to 50 μm and W2 is 1
５5 μm and Δ were changed in the range of 2 to 10 μm. Also,
The thickness of the first insulating layer was 30 nm, the thickness of the second insulating layer formed over the first insulating layer was 160 nm, and the thickness of the island-shaped semiconductor layer was 55 nm. The crystallization was performed by irradiating energy of 460 mJ / cm 2 using a dual beam laser annealing method.

[0152]

[Table 1]

The state of the crystallized semiconductor layer was observed with a scanning electron microscope (SEM: Scanning Electron microscopy). FIG. 32A shows W1 = 8 μm, W2 = 1 μm, Δ
2 shows an SEM image of a sample having a thickness of 2 μm. The surface of the sample was etched with a Seco solution (main component (volume ratio) HF: H ₂ O = 67: 33, additive K ₂ Cr ₂ O ₇ ) to make the crystal grains visible. As can be seen from FIG. 31, the crystals grow from the step formed by the first insulating layer and from the end of the island-shaped semiconductor layer toward the inside.

FIG. 32B shows an observation of an end portion of the island-shaped semiconductor layer in which the first insulating layer is not formed periodically in the same sample. In that case, a region where small crystal grains are aggregated inside the island-shaped semiconductor layer is observed. Such a phenomenon supports the crystallization mechanism described in the present invention, and indicates that crystal grains grow from a region of the island-shaped semiconductor layer overlapping with the first insulating layer. Therefore, there is an optimum range for the magnitudes of W1 and Δ. As a result of preparing samples of various shapes and performing the same evaluation, a region surrounded by a thick line in Table 1 (W1 is about 4 to 10 μm, Δ Is 2-5
(about μm), it was possible to realize a large grain size of the crystal grains. On the other hand, W2 is preferably about 1 μm, and when it is further increased, another mode of crystal growth was observed on the first insulating layer.

The above experimental results show that the gap between the first insulating layers formed in a strip shape and the width of the island-shaped semiconductor layer are formed in a suitable combination, so that the large grain size can be adjusted according to the channel forming region of the TFT. It has been demonstrated that a crystalline semiconductor layer can be formed.

[0156]

By using the dual beam laser annealing technique of the present invention, it is possible to manufacture a crystalline semiconductor film in which the position and size of crystal grains are controlled. The position of crystal grains of such a crystalline semiconductor film is determined by TFT
Is formed in accordance with the channel formation region of
The static characteristics and dynamic characteristics of the FT can be dramatically improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a dual beam laser annealing method of the present invention.

FIG. 2 is a diagram illustrating a configuration of a laser annealing apparatus.

FIG. 3 is a diagram illustrating a configuration of an optical system of a laser annealing apparatus.

FIG. 4 is a diagram illustrating a configuration of an optical system of a laser annealing apparatus.

FIG. 5 is a diagram illustrating a crystallization step of the present invention.

FIG. 6 is a diagram illustrating a crystallization step of the present invention.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 12 is a top view illustrating a manufacturing process of a TFT of a driver circuit.

FIG. 13 is a top view illustrating a manufacturing process of a pixel TFT.

FIG. 14 is a cross-sectional view illustrating a manufacturing process of a TFT of a driver circuit.

FIG. 15 is a cross-sectional view illustrating a manufacturing process of a pixel TFT.

FIG. 16 is a cross-sectional view of an active matrix liquid crystal display device.

FIG. 17 is a perspective view illustrating a structure of a liquid crystal display device.

FIG. 18 is a top view illustrating a pixel structure of a pixel portion.

FIG. 19 is a top view illustrating input / output terminals, wiring, circuit arrangement, spacers, and sealants of a liquid crystal display device.

20A and 20B are a top view and a cross-sectional view illustrating a structure of an EL display device.

FIG. 21 is a cross-sectional view of a pixel portion of an EL display device.

FIG. 22 is a top view and a circuit diagram of a pixel portion of an EL display device.

FIG. 23 is a cross-sectional view of a pixel portion of an EL display device.

FIG. 24 is an example of a circuit diagram of a pixel portion of an EL display device.

FIG. 25 is a diagram showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.

FIG. 26 is a diagram illustrating a crystallization step of the present invention.

FIG. 27 is a diagram illustrating a crystallization step of the present invention.

FIG 28 illustrates an example of a semiconductor device.

FIG 29 illustrates an example of a semiconductor device.

FIG. 30 illustrates a configuration of a projection type liquid crystal display device.

FIG. 31 illustrates a dimensional relationship when a first insulating layer and an island-shaped semiconductor layer are overlapped with each other.

FIG. 32 is an SEM image of a crystalline semiconductor film manufactured according to the present invention.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference)

Claims (16)

[Claims] And a first insulating layer provided below the island-shaped semiconductor layer on one surface of the light-transmitting substrate. A semiconductor device, wherein the first insulating layer is provided so as to intersect with the island-shaped semiconductor layer. 2. An island-shaped semiconductor layer and a pair of strip-shaped first insulating layers provided below the island-shaped semiconductor layer on one surface of the light-transmitting substrate. A semiconductor device in which a strip-shaped first insulating layer is provided so as to intersect with the island-shaped semiconductor layer. 3. The semiconductor device according to claim 1, wherein a second insulating layer is formed between the island-shaped semiconductor layer and the strip-shaped first insulating layer. . 4. A semiconductor device in which a thin film transistor is provided on a light-transmitting substrate, wherein one surface of the light-transmitting substrate is
An island-shaped semiconductor layer; and a strip-shaped first insulating layer provided below the island-shaped semiconductor layer. The strip-shaped first insulating layer intersects with the island-shaped semiconductor layer. A semiconductor device provided, wherein a channel formation region of the thin film transistor formed in the island-shaped semiconductor layer is formed adjacent to the strip-shaped first insulating layer. 5. A semiconductor device comprising a thin film transistor provided on a light-transmitting substrate, wherein one surface of the light-transmitting substrate is
An island-shaped semiconductor layer, and a pair of strip-shaped first insulating layers provided below the island-shaped semiconductor layer, wherein the pair of strip-shaped first insulating layers are A semiconductor device provided so as to intersect with each other, wherein a channel formation region of the thin film transistor formed in the island-shaped semiconductor layer is formed between the pair of strip-shaped first insulating layers. 6. A semiconductor device comprising a thin film transistor provided on a light-transmitting substrate, wherein one surface of the light-transmitting substrate is
An island-shaped semiconductor layer, and a strip-shaped first insulating layer provided below the island-shaped semiconductor layer; the island-shaped semiconductor layer forms a channel formation region of the thin film transistor; The first insulating layer is provided so as to intersect with a channel length direction of the island-shaped semiconductor layer, and a channel formation region of the thin film transistor formed in the island-shaped semiconductor layer is formed on the strip-shaped first insulating layer. A semiconductor device formed adjacent to a semiconductor device. 7. A semiconductor device having a thin film transistor provided on a light-transmitting substrate, wherein one surface of the light-transmitting substrate is
An island-shaped semiconductor layer, and a pair of strip-shaped first insulating layers provided below the island-shaped semiconductor layer; the island-shaped semiconductor layer forms a channel formation region of the thin film transistor;
The pair of strip-shaped first insulating layers are provided so as to intersect with a channel length direction of the island-shaped semiconductor layer, and a channel formation region of the thin film transistor formed in the island-shaped semiconductor layer includes the pair of strip-shaped first insulating layers. A semiconductor device formed between the first insulating layers. 8. The semiconductor device according to claim 4, wherein a second insulating layer is formed between the island-shaped semiconductor layer and the strip-shaped first insulating layer. Characteristic semiconductor device. 9. A step of forming a strip-shaped first insulating layer on one surface of a light-transmitting substrate; and forming the strip-shaped first insulating layer on the strip-shaped first insulating layer. Forming an island-like semiconductor layer so as to intersect, irradiating the island-like semiconductor layer with laser light from one surface side and the other surface side of the light-transmitting substrate, And a step of crystallizing the layer. 10. A step of forming a pair of strip-shaped first insulating layers on one surface of a light-transmitting substrate, and forming the pair of strip-shaped first insulating layers on the pair of strip-shaped first insulating layers. Forming an island-shaped semiconductor layer so as to intersect with the first insulating layer; and irradiating the island-shaped semiconductor layer with laser light from one surface side and the other surface side of the light-transmitting substrate. Crystallizing the island-shaped semiconductor layer. 11. A method for manufacturing a semiconductor device in which a thin film transistor is provided over a light-transmitting substrate, wherein: a step of forming a strip-shaped first insulating layer on one surface of the light-transmitting substrate; Forming an island-shaped semiconductor layer on the first insulating layer so as to intersect the strip-shaped first insulating layer; and forming the island-shaped semiconductor layer on one surface side and the other surface side of the light-transmitting substrate. Irradiating the island-shaped semiconductor layer with a laser beam to crystallize the island-shaped semiconductor layer. 12. A method for manufacturing a semiconductor device in which a thin film transistor is provided over a light-transmitting substrate, comprising: forming a pair of strip-shaped first insulating layers on one surface of the light-transmitting substrate; Forming an island-shaped semiconductor layer over the strip-shaped first insulating layer so as to intersect with the pair of strip-shaped first insulating layers; one surface side of the light-transmitting substrate; Irradiating the island-shaped semiconductor layer with laser light from the surface side of the semiconductor device to crystallize the island-shaped semiconductor layer. 13. A method for manufacturing a semiconductor device in which a thin film transistor is provided over a light-transmitting substrate, wherein: a step of forming a strip-shaped first insulating layer on one surface of the light-transmitting substrate; Forming an island-shaped semiconductor layer on the first insulating layer so that the strip-shaped first insulating layer intersects the channel length direction; one surface side of the light-transmitting substrate and the other surface side; Irradiating the island-shaped semiconductor layer with laser light from the side to crystallize the island-shaped semiconductor layer. 14. A method for manufacturing a semiconductor device in which a thin film transistor is provided over a light-transmitting substrate, wherein: a step of forming a pair of strip-shaped first insulating layers on one surface of the light-transmitting substrate; Forming an island-shaped semiconductor layer on the strip-shaped first insulating layer so that the pair of strip-shaped first insulating layers intersect with the channel length direction; and one surface of the light-transmitting substrate. A step of irradiating the island-shaped semiconductor layer with laser light from the side and the other surface side to crystallize the island-shaped semiconductor layer. 15. The method according to claim 9, wherein a second insulating layer is provided between the step of forming the first insulating layer and the step of forming the island-shaped semiconductor layer. Forming a semiconductor device. 16. The laser beam applied to the island-shaped semiconductor layer from the other surface side according to any one of claims 9 to 14, wherein the laser beam is transmitted through the light-transmitting substrate. A method for manufacturing a semiconductor device, comprising: