JP3460650B2 - Electro-optical device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electro-optical device, and in particular, electrostatic breakdown used in a drive circuit-integrated electro-optical device in which an image display area and a drive circuit are formed on the same substrate. It belongs to the technical field of prevention circuits.

[0002]

2. Description of the Related Art Generally, a thin film transistor (hereinafter referred to as TF
T. In the case of an active matrix type liquid crystal device having a switching element as a switching element, an electro-optical material such as a liquid crystal layer is sandwiched between a TFT array substrate and a counter substrate.

An image display area and a drive circuit for controlling the display of the image display area are arranged on the TFT array substrate. An external circuit connection terminal portion that is electrically connected to the drive circuit is arranged on the TFT array substrate, and a control system signal such as a clock signal and a display signal are externally input to the external circuit connection terminal portion. . And T
On the FT array substrate, for example, in order to prevent electrostatic breakdown of the drive circuit due to static electricity generated when assembling the liquid crystal device,
A single-gate thin film transistor is arranged as an electrostatic breakdown prevention circuit in the middle of the wiring connecting the external circuit connection terminal portion and the drive circuit.

[0004]

However, the electrostatic breakdown prevention circuit described above has insufficient pressure resistance, and for example,
The static electricity destruction circuit itself may be destroyed due to the generation of static electricity of high voltage such as 000V. If the electrostatic breakdown circuit is destroyed, static electricity may destroy the switching elements arranged in the image display area and the drive circuit, resulting in a significant deterioration in the display characteristics of the electro-optical device.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to provide a structure of an electro-optical device having a sufficient electrostatic breakdown preventing effect.

[0006]

In order to solve the above-mentioned problems, an electro-optical device according to the present invention is an electro-optical device having a switching element region in which a switching element is arranged on a substrate. A connection wiring for electrically connecting the switching element and the terminal arranged in the element region, two channel regions, and a source region and a drain region arranged so as to sandwich the two channel regions with the connection wiring. A thin film transistor electrically connected between ground wirings, wherein two gate electrodes corresponding to two channel regions of the thin film transistor are electrically connected to the connection wiring or the ground wiring. To do.

According to such a configuration of the present invention, when a high current is input from the terminal due to the generation of static electricity or the like, the dual gate type thin film transistor is turned on and the high current is released to the ground through the dual gate type thin film transistor. Therefore, it has an effect of preventing electrostatic breakdown of the switching element. By using the dual gate type thin film transistor as the electrostatic breakdown prevention circuit, the withstand voltage of the electrostatic breakdown prevention circuit can be improved as compared with the case of using the single gate type thin film transistor. This makes it possible to reduce the occurrence rate of electrostatic breakdown of the switching element and obtain an electro-optical device having excellent display characteristics. Further, compared with the case where the thin film transistor having the LDD structure is used as the electrostatic breakdown prevention circuit, the responsiveness is good, so that even if static electricity occurs, the thin film transistor as the electrostatic breakdown prevention circuit is quickly turned on.

Further, the switching element region includes a plurality of data lines and a plurality of scanning lines formed in a matrix, and a pixel electrode and a pixel transistor arranged corresponding to intersections of the data lines and the scanning lines. And an image display area including a drive circuit area including a drive circuit for supplying a signal to at least one of the data line and the scanning line. With such a configuration, even in the electro-optical device integrated with the drive circuit in which the image display region and the drive circuit region are formed on the same substrate, it is possible to prevent switching element destruction due to static electricity, and display characteristics It is possible to obtain an excellent electro-optical device.

The switching element has a first semiconductor layer and a first gate electrode, and the thin film transistor has a second semiconductor layer made of the same layer as the first semiconductor layer and the first gate electrode. And a second gate electrode formed of the same layer. With such a configuration, the switching element in the switching element region and the dual-gate thin film transistor can be formed in the same step, so that the dual-gate thin film transistor can be manufactured without increasing the number of manufacturing steps.

[0010]

Further, the thin film transistor electrically connected to the connection wiring connected to the terminal to which a control system signal or a display signal is input is arranged with two channel regions sandwiching the two channel regions. A semiconductor layer having a source region and a drain region, and two gate electrodes arranged corresponding to the channel region. The source region is electrically connected to the ground wiring, and the connection wiring is provided. The gate electrode and the drain region are electrically connected to each other. The dual-gate thin film transistor with such a configuration is always on during normal operation of the electro-optical device, and prevents electrostatic breakdown when a control system signal such as a clock signal or a display signal is regularly input. It can be used as a circuit.

Further, the thin film transistor electrically connected to the connection wiring connected to the terminal to which a power system signal is input has two channel regions and a source region arranged with the two channel regions sandwiched therebetween. A semiconductor layer having a drain region and two gate electrodes arranged corresponding to the channel region, the drain region is electrically connected to the connection wiring, and the gate electrode and the source are provided. The region is characterized in that the ground wiring is electrically connected. With such a configuration, the dual-gate thin film transistor has the gate electrode grounded and is in the off state during the normal operation of the electro-optical device, and thus electrostatic potential is generated when a potential is constantly applied like a power system signal. It can be used as a destruction prevention circuit.

According to the present invention, a plurality of scanning lines and a plurality of data lines arranged on a substrate, a ground wiring arranged on a substrate, and a pixel arranged corresponding to an intersection of the scanning line and the data line. A peripheral drive circuit including an image display area including electrodes and pixel switching elements, at least one of a scan line drive circuit for supplying a signal to the scan line and a data line drive circuit for supplying a signal to the data line. And a signal from a terminal portion is supplied to the peripheral drive circuit via a signal wiring, and the peripheral drive circuit includes two channel regions and a source region and a drain region arranged with the two channel regions sandwiched therebetween. A thin film transistor electrically connected between the signal line and the ground line is provided, and two gate electrodes corresponding to two channel regions of the thin film transistor and the signal line are provided. Or wherein the ground wiring are electrically connected to each other.

According to such a configuration of the present invention, when a high current is input from the terminal portion due to the generation of static electricity or the like, the dual gate type thin film transistor is turned on and the high current is released to the ground through the dual gate type thin film transistor. The effect of preventing electrostatic breakdown of the switching element is obtained. And by using a dual gate type thin film transistor as an electrostatic breakdown prevention circuit,
The withstand voltage of the electrostatic breakdown prevention circuit can be improved as compared with the case of using a single-gate thin film transistor. This makes it possible to reduce the occurrence rate of electrostatic breakdown of the switching element and obtain an electro-optical device having excellent display characteristics. Further, compared with the case where the thin film transistor having the LDD structure is used as the electrostatic breakdown prevention circuit, the responsiveness is good, so that even if static electricity occurs, the thin film transistor as the electrostatic breakdown prevention circuit is quickly turned on.

Further, in the electro-optical device according to the present invention, the thin film transistor is composed of two thin film transistors connected in series.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) The first embodiment of the present invention will be described below with reference to the drawings, taking as an example the case where the present invention is applied to a liquid crystal device as an electro-optical device.

The structure of the liquid crystal device according to the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing an equivalent circuit of various elements, wirings, etc. in a plurality of pixels formed in a matrix forming an image display area of a liquid crystal device and an equivalent circuit of an electrostatic breakdown prevention circuit. FIG. 2 is a plan view of a plurality of pixel groups in a pixel image display area of a TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed. FIG. 3 is a partially enlarged view of the TFT array substrate for explaining the electrostatic breakdown prevention circuit. FIG. 4 shows AA ′ and B of FIG.
FIG. 4B is a vertical cross-sectional view of each of −B ′ and CC ′. In each drawing, in order to make each layer and each member recognizable in the drawing, the scale is different for each layer and each member.

The liquid crystal device has a liquid crystal cell in which a liquid crystal layer is sandwiched between a TFT array substrate and a counter substrate, and a drive circuit for inputting various signals to an external circuit connection terminal portion arranged on the TFT array substrate. The external control circuit board is attached and connected. The counter electrode is arranged on the counter substrate, and the pixel electrode is arranged on the TFT array substrate, and the liquid crystal device is displayed by changing the optical characteristics of the liquid crystal due to the potential difference between the counter electrode and the pixel electrode.

As shown in FIG. 1, the TFT array substrate 10
Is composed of a switching element region in which the switching element is arranged and a terminal portion region in which the external circuit connecting terminal portion is arranged beyond the switching element region.

The switching element area comprises an image display area and a peripheral drive circuit area arranged adjacent to the image display area. In the image display area, the capacitance lines 3b and the scanning lines 3 arranged in parallel, the data lines 6 arranged so as to intersect the scanning lines 3, and the intersections of the scanning lines 3 and the data lines 6 are provided. Pixel electrodes 9a arranged in a matrix,
A thin film transistor (hereinafter referred to as a TFT) 30 as a switching element for controlling the pixel electrode 9a is arranged. TF is provided on the data line 6 to which the image signal is supplied.
The source of T30 is electrically connected, and the gate of the TFT 30 is electrically connected to the scanning line 3 to which the scanning signal is supplied. The scanning line drive circuit 104 is provided in the peripheral drive circuit area.
The data line driving circuit 101 is arranged, the scanning line driving circuit 104 supplies the scanning line signal to the scanning line 3, and the data line driving circuit 101 supplies the image signal to the data line 6.

On the other hand, the scanning line drive circuit 1 is provided in the terminal area.
04 and the data line drive circuit 101, respectively, wiring 127
External circuit connection terminal portion 121 to be electrically connected by
126 and a ground terminal 120 are arranged. A control system circuit 1 arranged on an external control circuit board (not shown) externally attached to each of the external circuit connection terminal portions 121 to 126.
Various signals are input from 50, the power supply circuit 151, and the display signal circuit 152. External circuit connection terminal portions 121 to 126
A dual-gate type TFT, that is, TFTs 141 and 142 in which two transistors are connected in series are electrically connected to each other as an electrostatic breakdown prevention circuit. The drain regions of the semiconductor layers of the dual gate TFTs 141 and 142 are electrically connected to the ground terminal 120 via the ground wiring 128, and the ground terminal is grounded. The dual-gate TFTs 141 and 142 have different structures depending on the type of signal input to the external circuit connection terminal portion that is electrically connected. Although a specific structure will be described later, external circuit connection terminal portions 121, 122, 12 to which a control system signal or an image signal to which a potential is periodically applied are input.
Dual gate type TFT connected to 5 and 126 respectively
141 and the dual gate type TFT 142 respectively connected to the external circuit connection terminal portions 123 and 124 to which the power supply system signal to which a potential is always applied are input, and the gate electrode connection structure is different.

The scanning line driving circuit 104 of the peripheral driving circuit is
Based on the power supplied from the power supply circuit which is an external control circuit, the reference clock supplied from the control system circuit which is an external control circuit, its inverted clock, and the like, the scanning signal is pulsed to the scanning line 3 at predetermined timing. Apply in sequence.

The data line drive circuit 1 of the peripheral drive circuit
Reference numeral 01 includes a sampling circuit and a precharge circuit. In the data line drive circuit 101, the power supplied from the power supply circuit and the reference clock CL supplied from the control system circuit
A sampling circuit drive signal is supplied to the sampling circuit for each data line 6 at a predetermined timing in synchronization with the timing at which the scanning line drive circuit 104 applies a scanning signal based on X and its inverted clock. The precharge circuit is supplied with a precharge circuit drive signal from the external control circuit so that the precharge circuit writes the precharge signal at a timing preceding the supply of the image signal for each data line 6.
When the image signal supplied from the image signal circuit 152 is input, the sampling circuit samples these. That is, when the sampling circuit drive signal is input,
Image signals are sequentially applied to the data lines 6.

Next, the structure of the wirings and pixel electrodes in the image display area of the TFT array substrate will be described with reference to FIG.

As shown in FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on the TFT array substrate of the liquid crystal device.
a is provided, and the data line 6, the scanning line 3 (dotted line), and the capacitance line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a.
(Dotted line) is provided. The data line 6 is formed in a shape extending in the vertical direction, and the data line 6 is formed in the contact hole 5.
The data line 6 is electrically connected to a later-described source region of the semiconductor layer 1 (hatched portion) made of the polysilicon film via a, and the data line 6 has a wide width in the vicinity of the region connected to the source region. Is formed. The conductive layer 6b formed in the same layer as the data line 6 has a contact hole 5
It is electrically connected to a drain region of the semiconductor layer 1 which will be described later through b, and the conductive layer 6b is electrically connected to the pixel electrode 9a through a contact hole 8. Further, the scanning line 3 is arranged so as to face the channel region of the semiconductor layer 1, and the scanning line 3 functions as a gate electrode. In the present embodiment, there are two overlapping portions of the semiconductor layer 1 and the scanning line 3. There are two places and it has a double gate structure. In the drawing, a portion where the scanning line 3 and the semiconductor layer 1 overlap in a plane, that is, a semiconductor layer at a position corresponding to the gate electrode is hidden by the scanning line and is not shown. The capacitance line 3b extends in a substantially linear shape along the scanning line 3 and has a protruding portion protruding along the data line 6 from a position intersecting with the data line 6, and the semiconductor layer substantially corresponds to the protruding portion. Some are located. The capacitance line 3b planarly overlaps with a part of the pixel electrode 9a, forms a capacitance in this region, and further forms a capacitance with the pixel electrode 9a. The semiconductor layer 1 is extended below the data lines 6 and the scanning lines 3,
Similarly, the capacitance line 3 extending along the data line 6 and the scanning line 3
The capacitor is formed by being opposed to the portion b via the insulating film 2.

Although not shown, a complementary structure TFT as a switching element is arranged in the peripheral drive circuit, and the complementary structure TFT is a p-channel type T.
It is composed of an FT and an n-channel TFT, and is formed in the same process as the TFT in the display area.

Next, the structure of the terminal area will be described with reference to FIGS. FIG. 3 shows the ground terminal 120 of FIG.
And a partially enlarged plan view in the vicinity of the terminal area in which the external circuit connection terminal sections 121 to 126 are arranged, and FIG. 4 is a line A- in FIG.
It is a longitudinal cross-sectional view when cut | disconnecting by A ', BB', and CC '.

As shown in FIG. 3, each of the external circuit connection terminal portions 121 to 126 is electrically connected to the scanning line driving circuit or the data line driving circuit via the wiring 127. Further, each wiring 127 includes a dual gate type TFT 141,
142 electrically connected to the dual gate type TFT 14
1, 142 are connected to the ground terminal 120 via the ground wiring 128, and the ground terminal 120 is grounded.

Each wiring 127 has a branch portion 127a,
Further, the external circuit connection terminal portions 121, 122, 125, 12
The wiring connected to 6 has a re-branching portion 127b branched further from the branching portion. Each branch 127a corresponds to the semiconductor layer 13 of the corresponding dual gate type TFT 141 or 142.
5, 136 are electrically connected to the drain regions 135b, 136b through the contact holes 130, 132. The source regions 135c and 136c of the semiconductor layers 135 and 136 of the dual type TFTs 141 and 142 are
It is electrically connected to the ground wiring 128 through the contact holes 130 and 132.

Of the external circuit connection terminal portion, the external circuit connection terminal portion 121 to which the control system signal or the display signal is input,
The dual gate type thin film transistor 141 connected to 122, 125 and 126 is arranged on the glass substrate 60 on which the base film 12 is formed, as shown in FIG. 4 (longitudinal sectional view of AA ′ and BB ′). And a semiconductor layer having two channel regions 135a and a source region 135b and a drain region 135c arranged so as to sandwich the two channel regions 135a, and the channel region 135a on the semiconductor layer with the gate insulating film 2 interposed therebetween. And two gate electrodes 131 arranged in parallel. Further, as shown in the figure, the interlayer insulating film 4 is arranged so as to cover the gate electrode 131, and the branch portion 127 of the wiring 127 electrically connected to the drain region 135b of the semiconductor layer 135 is disposed on the interlayer insulating film 4.
a and a ground wiring 128 electrically connected to the source region 135c are arranged. The gate electrode 131 is
It is electrically connected to the re-branching portion 127b through the contact hole 133. Then, the interlayer insulating film 7 is arranged so as to cover the TFT 141.

Of the external circuit connection terminal portions, the dual gate type thin film transistor 142 connected to the external circuit connection terminal portions 123 and 124 to which the power supply system signal is input is
As shown in FIG. 4 (longitudinal sectional view of CC ′), the base film 12
And a drain region 136b and a source region 1 which are arranged on the glass substrate 60 in which the two are formed and sandwich the two channel regions 136a.
Semiconductor layer 136 having 36c, and this semiconductor layer 136
The gate insulating film 2 is composed of two gate electrodes 134 arranged corresponding to the channel region 136a.
Further, as shown in the drawing, the interlayer insulating film 4 is arranged so as to cover the gate electrode 134, and the semiconductor layer 13 is formed on the interlayer insulating film 4.
6 has a wiring branch portion 127a electrically connected to the drain region 136b and a ground wiring branch portion 128a electrically connected to the source region 136c.
The gate electrode 134 is electrically connected to the ground wiring 128. Then, the interlayer insulating film 7 is arranged so as to cover the TFT 141.

Next, a method of manufacturing the TFT array substrate will be described with reference to FIGS. 5 to 13, a vertical sectional view of a switching element region having a peripheral circuit region and an image display region and a vertical sectional view of a terminal portion region are shown. The vertical sectional view in the image display area is line E- in FIG.
FIG. 4 is a vertical sectional view taken along the line E ′, and the vertical sectional view in the terminal area corresponds to FIG. 4.

First, as shown in FIG. 5A, a SiO ₂ film of 200 to 200 is formed as a base film 12 on a glass substrate 60 by PE (Plasma Enhanced) CVD method or ECR (electron cyclotron resonance) CVD method. Fifty
It is formed with a thickness of about 0 nm. This base film has a function of preventing the surface of the glass substrate 60 from being contaminated and impurities contained in the glass substrate from deteriorating the characteristics of the TFT 30.

Next, as shown in FIG. 5B, PECV
An a-Si film 401a is laminated on the base film with a thickness of about 30 to 100 nm by the D method or the LP (low pressure) CVD method.

Next, as shown in FIG. 5C, a-Si
Excimer laser light such as KrF or XeCl is applied to the film 3 times.
By irradiating with 0 to 600 mJ / cm ^2, aS
The i film is crystallized to obtain a p-Si film 401b. The irradiation intensity and irradiation time of the excimer laser light are appropriately adjusted depending on the film thickness and film quality of the a-Si film. In this embodiment, since the polysilicon layer can be obtained at a low temperature by laser annealing, a glass substrate that is cheaper than a silicon substrate can be used as the substrate.

Next, as shown in FIG. 5D, a shape corresponding to the semiconductor layer of each TFT in the image display area and the peripheral drive circuit area, and a semiconductor of a dual gate type TFT arranged in the terminal area. A photoresist film 402 is formed in a shape corresponding to the layer.

Next, as shown in FIG. 6A, the photoresist film 402 is used as a mask and the p-Si film 401b is subjected to RIE (reactive ion etc.) using chlorine-based gas.
Then, the p-Si layer 1 and the semiconductor layers 135 and 136 of the dual gate type TFT are formed by etching. still,
In addition to dry etching such as RIE, wet etching using a chemical solution such as etching using hydrofluoric nitric acid can also be used.

Next, as shown in FIG. 6 (b), after removing the photoresist film 402, as shown in FIG. 6 (c), PE is removed.
Using a mixed gas of TEOS (tetraethyl orthosilicate) and oxygen gas as a source gas by the CVD method,
The gate insulating film 2 having a film thickness of 120 nm is formed. Here, SiH ₄ and oxygen gas may be used as the source gas.

Next, as shown in FIG. 6D, a photoresist film 403 having a shape in which a portion of the semiconductor layer 1 in the image display region corresponding to the region functioning as a capacitor is removed is formed. Then, using the photoresist film 403 as a mask, phosphorus ions as impurities are implanted into the semiconductor layer 1 at a dose amount of 5 × 10 ¹⁴ to 10 ¹⁶ ions / cm ² by an ion implantation method to form a capacitor electrode 1f. . After the implantation, the photoresist film 403 is peeled off.

Next, as shown in FIG. 7A, PVD (physical vapor deposition) is formed on the gate insulating film 2.
Film thickness of 200 to 600 nm, here 400
A two-layer film 405 including an aluminum film and a titanium nitride film having a thickness of 0.25 nm is formed.

Next, as shown in FIG. 7B, a control system signal, an electrical system signal, and a control system signal in the terminal area having a shape corresponding to the scanning line, the gate electrode, and the capacitance line in the switching element area. A photoresist film 404 having a shape corresponding to a gate electrode of a dual gate type TFT connected to an external circuit connection terminal portion to which an image signal is input is formed. Using this as a mask, as shown in FIG. 7C, a two-layer film 405 of an aluminum film and a titanium nitride film is etched by RIE using a fluorine-based gas or a chlorine-based gas. After etching, the photoresist film 404 is peeled off, and as shown in FIG. 8A, a scanning line and a gate electrode in a switching element region having a multilayer structure including a lower layer made of aluminum and an upper layer made of titanium nitride. Gate electrodes 131 and 134 of the dual gate type TFT connected to the external circuit connection terminal portions to which the control system signals in the terminal region, the electric system signals and the image signals are input.

Next, as shown in FIG. 8B, the peripheral circuit
Semiconductor layer 1 to be a P-channel TFT 140b in the region
The photoresist with the shape where the resist at the position corresponding to
A dist film 405 is formed. After this, the photoresist film
405 and a gate electrode 1 corresponding to a P-channel type TFT
03 as a mask, 5 × 10¹⁴-10 ¹⁶
Pieces / cm²Boron ions are implanted by the ion implantation method
The channel region self-aligned with the gate electrode 103.
Half having region 1a, source region 1g, drain region 1h
The conductor layer 1 is obtained.

Next, after removing the photoresist film 405 as shown in FIG. 8C, the semiconductor layer 1 to be the P-channel TFT 140b in the peripheral circuit region as shown in FIG. 8D.
A photoresist film 406 having a shape corresponding to is formed. This photoresist film 406 and the gate electrode 3
a, a gate electrode 103 corresponding to an N-channel TFT,
The semiconductor layers 1, 135, 136 are masked with the gate electrodes 131 and 134 corresponding to the dual gate type TFTs connected to the external circuit connection terminal portion into which the capacitance line 3b, the control system signal, the electric system signal and the image signal are input. 5 × 10 ¹²
˜2 × 10 ¹⁴ / cm 2 of phosphorus ions are implanted by the ion implantation method. As a result, in the peripheral circuit region, the channel region 1a self-aligned with the gate electrode 103, the high-concentration source region formed later, the low-concentration source region 1b having a lower impurity concentration than the high-concentration drain region, and the low-concentration drain region are formed. The semiconductor layer 1 corresponding to the N-channel TFT having 1c is obtained. In the image display area, 2
A channel region 1a at one place (only one is shown), a high concentration source region formed so as to sandwich these two channel regions, a low concentration source region 1b having a lower impurity concentration than the high concentration drain region, and a low concentration Drain region 1c
A semiconductor 1 having is obtained. Further, the semiconductor layer 135 corresponding to the dual gate type TFT connected to the external circuit connection terminal portion to which the control system signal and the image signal are input is arranged with the two channel regions 135a sandwiching the two channel regions 135a. It has source regions 135b and 135c, and has a self-aligned structure. The semiconductor layer 136 corresponding to the dual gate type TFT connected to the external circuit connection terminal portion to which the power supply system signal is input has two channel regions 136a and source regions 136b and 136c arranged so as to sandwich the two channel regions. And has a self-aligned structure.

Next, as shown in FIG. 9A, the gate electrode 103 of the N-channel TFT 140a and the gate electrode 3a of the TFT in the image display area have a pattern shape that covers the semiconductor layer of the P-channel TFT 140b. A photoresist film 407 having a shape corresponding to a portion to be a channel region of the semiconductor layer of the dual gate type TFT having a shape covering the peripheral portion is formed. Using this as a mask, 5 × 10 ¹⁴ to 10 ¹⁶ pieces / c are formed in the semiconductor layers 1, 135 and 136.
Phosphorus ions of m ² are implanted by the ion implantation method. After that, the photoresist film 407 is stripped by a stripping solution.
As a result, as shown in FIG. 9B, a semiconductor layer having an LDD structure having a low-concentration source region 1b, a high-concentration source region 1d having a higher impurity concentration than the low-concentration drain region 1c, and a high-concentration drain region 1e. Can be obtained. Therefore, the TFT in the pixel image display area and the N-channel TFT in the peripheral drive circuit area have a semiconductor layer having an LDD structure.

Next, as shown in FIG. 9C, the PECVD method is used to cover the gate electrodes 103, 3a, 131, and 134 and the capacitance line 3b by using TEOS and ozone gas as source gases, and the thickness is 1500 nm. An interlayer insulating film 4 made of SiO _{2 having a} thickness is formed on the entire surface of the substrate. After that, in order to activate the impurity ions, activation heat treatment (activation annealing treatment) is performed under a temperature condition of 400 ° C.

Next, as shown in FIG. 9D, a source / drain region of each TFT in the peripheral circuit region and a data line to be formed later, a contact hole for connecting a conductive layer, and an image display region. A contact hole for connecting the source region of the TFT with a data line to be formed later,
A contact hole for connecting the drain region of the TFT in the image display region and a conductive layer to be formed later, a contact hole for connecting the source region 135b of the dual gate type TFT and a branch portion 127a to be formed later,
Ground wiring 1 to be formed later with the drain region 135c
28, a contact hole for connecting the gate electrode 131 and a re-branching part 127b formed later, a contact hole for connecting the source region 136b and a branching part 127a formed later. Then, a photoresist film 409 patterned into a shape corresponding to a contact hole for connecting the drain region 136c and the branch portion 128a of the ground wiring to be formed later is formed.

As shown in FIG. 10A, the interlayer insulating film 4 is etched by using the photoresist film 409 as a mask, and the contact holes 5, 5a, 5b, 130, 13 are formed.
2 and 133 are formed. Then, the photoresist film 40
9 is peeled off to obtain the structure shown in FIG.

Next, as shown in FIG. 10C, an aluminum / titanium multilayer film 410 having a film thickness of 300 to 1000 nm is formed on the interlayer insulating film 4 by the PVD method. Further, as shown in FIG.
On the titanium multilayer film 410, the data line in the switching element region, the conductive layer, the wiring in the terminal portion region, the ground wiring,
A photoresist film 411 having a shape in which a portion corresponding to the external circuit connection terminal portion is removed is formed.

Next, as shown in FIG. 11A, the aluminum / titanium film 410 is etched by RIE using a chlorine-based gas with the photoresist film 411 as a mask, and then the photoresist film 411 is removed.

As a result, as shown in FIG. 11 (b),
In the peripheral circuit region, the data line 1 electrically connected to the source regions 1d and 1g and the drain regions 1e and 1h of the semiconductor layers of the N-channel TFT and the P-channel TFT, respectively.
06a, 107a and conductive layers 106b, 107b are obtained.
In the image display region, the source region 1d of the semiconductor layer,
The data line 6 and the conductive layer 6b electrically connected to the drain region 1e are obtained. In the terminal area, the drain area 135c of the semiconductor layer of the dual gate type TFT
The branch portion 12 of the ground wiring 128 electrically connected to the source region 135b and the wiring 127 electrically connected to the source region 135b.
7a, the wiring 12 electrically connected to the gate electrode 131
7 re-branching portion 127b, a branch portion 128a of the ground wiring 128 electrically connected to the drain region 136c, a branch portion 127a of the wiring 127 electrically connected to the source region 136b, and an external circuit connection terminal portion external circuit connection. Obtain a terminal portion (not shown).

Next, as shown in FIG. 11C, the conductive layer 6
An interlayer insulating film 7 is formed by PECVD using a mixed gas of TEOS and oxygen gas as a source gas so as to cover b, the data line 6, the wiring 127, and the ground wiring 128. Here, as a method for forming the interlayer insulating film 7, an atmospheric pressure CVD method may be used, and as a raw material gas, a mixed gas of TEOS and ozone gas or a mixed gas of SiH ₄ and oxygen gas may be used. Good. Further, not only an inorganic film but also an organic film such as an acrylic film can be used. In this case, a film having a larger film thickness than that of an inorganic film can be easily obtained, and thus it can be used as a flattening film.

Next, as shown in FIG. 12A, a photoresist film is formed on the inter-layer insulating film 7 by removing the resist at the portions corresponding to the contact holes connecting the conductive layer 6b and the pixel electrode to be formed later. 413 is formed. Thereafter, as shown in FIG. 12B, the interlayer insulating film 7 is etched by the RIE method or the wet etching method using the photoresist film 413 as a mask, and the photoresist film 4
13 is peeled off to obtain an interlayer insulating film 7 having a contact hole 8 as shown in FIG.

Next, as shown in FIG. 13A, an ITO film 414 having a thickness of about 50 to 200 nm is formed on the interlayer insulating film 7 by the sputtering method. After that, FIG.
As shown in (b), a photoresist film 415 corresponding to the pixel electrode shape is formed on the ITO film 414, and the ITO film 414 is wet-etched with aqua regia or HBr using this as a mask, or CH ₄ Alternatively, as shown in FIG. 13C, the pixel electrode 9a is formed by dry etching by RIE using a gas such as HI.
To get

The TFT array substrate manufactured as described above and a separately formed counter substrate are arranged so as to face each other, and liquid crystal is injected between both substrates to form a liquid crystal cell. Then, the external circuit connection terminal portion of the liquid crystal cell and the external control circuit are connected to obtain a liquid crystal device. In the present invention, in the liquid crystal cell forming process and the external control circuit mounting process, even if static electricity is generated, the dual gate type TFT is turned on, and the current is released through the drain of the semiconductor layer. It is possible to prevent electrostatic breakdown of the switching element arranged in the region. Furthermore, by adopting a dual gate structure as the electrostatic breakdown prevention circuit, the withstand voltage can be improved as compared with the single gate type TFT, and the breakdown of the electrostatic breakdown prevention circuit itself can be prevented.

The liquid crystal device obtained as described above has excellent display characteristics because there is no electrostatic breakdown of the switching element.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS. 14 and 15. This embodiment has the same configuration as that of the first embodiment, and only different points will be described in detail.

In the first embodiment, the dual gate type TF is used.
The drain region of the semiconductor layer of T is 1 through the ground wiring.
One ground terminal portion is collectively connected, and this ground terminal portion is grounded. On the other hand, in the second embodiment, the semiconductor pattern 137 is arranged in the terminal area, and the drain areas of the semiconductor layers of the dual gate TFTs 141 and 142 are electrically connected to the semiconductor pattern 137 via the ground wiring 139. The semiconductor pattern 137 has a different structure in that it is grounded. Note that FIG. 15 is shown in FIG.
4 is a vertical cross-sectional view taken along line DD ′ of FIG. 4, showing a connection structure between a semiconductor pattern 137 and a ground wiring 139. FIG. The detailed structure will be described below, but description of the same structure and manufacturing method as in the first embodiment will be omitted.

As shown in FIG. 14, in this embodiment, the mounting terminals 121 to 126 and the dual gate structure T are used.
A semiconductor pattern 137 surrounding the FT 141, 142
Are placed. The semiconductor pattern 137 is formed in the same layer as the semiconductor layer of each of the dual gate structure TFTs 141 and 142, and the semiconductor pattern 137 is formed by the steps shown in FIGS. 8D and 9A of the first embodiment described above. Ion implantation is performed at the same time as the ion implantation process that is performed. The drain region of the semiconductor layer of each dual-gate TFT 141, 142 is electrically connected to the semiconductor pattern 137 via the ground wiring 139. As shown in FIG. 15, the connection structure between the semiconductor pattern 137 and the ground wiring 139 is such that the semiconductor pattern 137 is arranged on the glass substrate 60 having the base film 12, and the gate insulating film 2 and the interlayer insulation film are formed on the semiconductor pattern 137. The film 4 is arranged, and the semiconductor pattern 137 and the ground wiring 13 are formed by the contact holes 138 formed in the gate insulating film 2 and the interlayer insulating film 4.
9 and 9 are electrically connected. The ground wiring 139 is formed in the same layer as the data line in the image display area.

In the present embodiment, since the formation region of the semiconductor pattern can be made large, the ground area is widened, and even if a high current is generated, the current can be efficiently flowed to the semiconductor pattern, and the electrostatic charge is more electrostatic. It is possible to obtain an electrostatic breakdown prevention circuit having a high destruction effect.

The dual gate type TFT of the present invention is
It is not limited to the structures described in the above embodiments. Although the above-mentioned dual gate type TFT is located between the external circuit connecting terminal portion and the peripheral circuit, for example, as shown in FIG. 16, the dual gate type TFT receives signals from the control system circuit and the image signal circuit. Type TFT has an external circuit connection terminal 1
A structure directly connected to 21 may be used. In FIG. 16, the dual-gate TFT is composed of a semiconductor layer 142, a gate insulating film (not shown) formed so as to cover the semiconductor layer 142, and two gate electrodes 141 arranged on the gate insulating film. . In the source region of the semiconductor layer 142, the mounting terminal 1
The branch part 140 branched from 21 is electrically connected,
Further, the branch portion 140 is electrically connected to the gate electrode 141. Further, the ground wiring 143 is electrically connected to the drain region of the semiconductor layer 142. Even in such a structure, it is possible to obtain the same effect of preventing electrostatic breakdown as in the above-described embodiment.

Although the present embodiment has been described by using the liquid crystal device as the electro-optical device, the present invention is not limited to this, and can be applied to various electro-optical devices such as electroluminescence or a plasma display.

[Brief description of drawings]

FIG. 1 is a diagram showing a TF provided in a plurality of pixels in a matrix forming an image display area in the liquid crystal device of the first embodiment.
It is an equivalent circuit diagram of an equivalent circuit of a T element, wiring, etc. and an electrostatic breakdown prevention circuit.

FIG. 2 is an enlarged plan view of TFT elements, wirings and the like in an image display area of the TFT array substrate in the liquid crystal device of the first embodiment.

FIG. 3 is a partially enlarged plan view of an electrostatic breakdown prevention circuit of the TFT array substrate in the liquid crystal device of the first embodiment.

FIG. 4 is a vertical cross-sectional view taken along the lines AA ′, BB ′, and CC ′ of FIG.

FIG. 5 is a process chart (1) showing the manufacturing process of the TFT array substrate in the liquid crystal device of the first embodiment step by step.
Is.

FIG. 6 is a process diagram (No. 2) sequentially showing the manufacturing process of the TFT array substrate in the liquid crystal device of the first embodiment.
Is.

7A and 7B are process diagrams (No. 3) sequentially showing the manufacturing process of the TFT array substrate in the liquid crystal device of the first embodiment.
Is.

FIG. 8 is a process chart (No. 4) sequentially showing the manufacturing process of the TFT array substrate in the liquid crystal device of the first embodiment.
Is.

FIG. 9 is a process chart (No. 5) sequentially showing the manufacturing process of the TFT array substrate in the liquid crystal device of the first embodiment.
Is.

FIG. 10 is a process diagram (sixth) sequentially showing the manufacturing process of the TFT array substrate in the liquid crystal device of the first embodiment.

FIG. 11 is a process diagram (No. 7) sequentially showing the manufacturing process of the TFT array substrate in the liquid crystal device of the first embodiment.

FIG. 12 is a process chart (No. 8) that sequentially shows the manufacturing process of the TFT array substrate in the liquid crystal device of the first embodiment.

FIG. 13 is a process diagram (9) showing the manufacturing process of the TFT array substrate in the liquid crystal device of the first embodiment step by step.

FIG. 14 is a partially enlarged plan view of an electrostatic breakdown prevention circuit for a TFT array substrate in the liquid crystal device of the second embodiment.

15 is a vertical cross-sectional view taken along the line DD ′ of FIG.

FIG. 16 is a partially enlarged plan view showing the structure of another electrostatic breakdown prevention circuit.

[Explanation of symbols]

1, 135, 136, 142 ... Semiconductor layer 2 ... Gate insulating films 3a, 103, 131, 134 ... Gate electrodes 30, 140a, 140b ... TFT 60 ... Substrate 120 ... Ground terminals 121, 122, 123, 124, 125, 126 External circuit connection terminal portion 127 ... Wiring 128 ... Ground wirings 135a, 136a ... Channel regions 135b, 136b ... Source regions 135c, 136b ... Drain region 137 ... Semiconductor pattern 141 ... Prevention of electrostatic breakdown for control system signals or display signals Dual gate type TFT 142 as a circuit ... Dual gate type TFT 150 as an electrostatic breakdown preventing circuit for power source system signals ... Control system circuit 151 ... Power source circuit 152 ... Display signal circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 623A (56) References JP-A-9-74204 (JP, A) JP-A-10-93143 (JP, A) JP-A-3-177061 (JP, A) JP-A-9-15647 (JP, A) JP-A-9-80471 (JP, A) JP-A-11-174970 (JP, A) JP-A-59-126663 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/133 550 G02F 1/1368 G09F 9/30 338 H01L 29/786

Claims (7)

(57) [Claims] 1. An electro-optical device having a switching element region in which a switching element is arranged on a substrate, for electrically connecting a switching element arranged in the switching element region and a terminal on the substrate. A thin film transistor in which a connection wiring, two channel regions, and a source region and a drain region arranged with the two channel regions sandwiched therebetween are electrically connected between the connection wiring and the ground wiring; 2 corresponding to two channel regions
An electro-optical device, wherein one gate electrode is electrically connected to the connection wiring or the ground wiring. 2. The switching element region includes a plurality of data lines and a plurality of scanning lines formed in a matrix, and a pixel electrode and a pixel transistor arranged corresponding to intersections of the data lines and the scanning lines. 2. The electro-optical device according to claim 1, wherein the electro-optical device includes an image display area including a drive circuit and a drive circuit area including a drive circuit for supplying a signal to at least one of the data line and the scanning line. . 3. The switching element has a first semiconductor layer and a first gate electrode, and the thin film transistor has a second semiconductor layer formed of the same layer as the first semiconductor layer, and the first gate electrode. And a second gate electrode formed of the same layer.
Alternatively, the electro-optical device according to claim 2. 4. The thin film transistor electrically connected to the connection wiring connected to the terminal to which a control system signal or a display signal is input is arranged with two channel regions sandwiching the two channel regions. A semiconductor layer having a source region and a drain region, and two gate electrodes arranged corresponding to the channel region, the source region being electrically connected to the ground line, the connection line The gate electrode and the drain region are electrically connected to each other.
Alternatively, the electro-optical device according to claim 2. 5. The thin film transistor electrically connected to the connection wiring connected to the terminal to which a power supply system signal is input is provided with two channel regions and a source region arranged so as to sandwich the two channel regions. A semiconductor layer having a drain region and two gate electrodes arranged corresponding to the channel region, the drain region is electrically connected to the connection wiring, the gate electrode and the source The electro-optical device according to claim 1, wherein the ground wiring is electrically connected to the region. 6. A plurality of scanning lines and a plurality of data lines arranged on a substrate, a ground wiring arranged on a substrate, a pixel electrode arranged corresponding to an intersection of the scanning line and the data line, An image display area including a pixel switching element, and a peripheral drive circuit including at least one of a scan line drive circuit for supplying a signal to the scan line and a data line drive circuit for supplying a signal to the data line. A signal from a terminal portion is supplied to the peripheral driving circuit through a signal wiring, and the two signals are provided with two channel regions and a source region and a drain region which are arranged so as to sandwich the two channel regions. A thin film transistor electrically connected between the wiring and the ground wiring, corresponding to two channel regions of the thin film transistor;
An electro-optical device, wherein one gate electrode is electrically connected to the signal wiring or the ground wiring. 7. The electro-optical device according to claim 1, wherein the thin film transistor includes two thin film transistors connected in series.