JP2001135640A - Electrode substrate, photoelectric device, method for manufacturing electrode substrate, and manufacturing method of photoelectric device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an electrode substrate without any wiring defect and an photoelectric device without any display defect and with improved display characteristics in the method for manufacturing the electrode substrate with wiring having aluminum as a material and the photoelectric device. SOLUTION: A semiconductor layer 1 is formed on a substrate 60, a gate insulation film 2 with an etching rate of 4 nm/sec or less by BHF is formed so that the semiconductor layer 1 can be covered, a titanium film 34, a film 35 containing aluminum, and a titanium nitride film 36 are successively formed on the gate insulation film 2. After that, a lamination film of the titanium film 34, the film 35 containing aluminum, and the titanium nitride film 36 is subjected to patterning to obtain wiring 33. In this manner, by limiting the film quality of the gate insulation film, the crystal orientation state of the titanium film is controlled, the flat aluminum film 35 with improved crystallizability being preferentially orientated on a crystal orientation (111) face can be formed, and wiring were the generation of hillock has been suppressed can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode substrate and an electro-optical device, and more particularly to an electrode substrate and an electro-optical device in which hillocks are suppressed when a wiring having a laminated structure of titanium and aluminum is provided. Belongs to the device.

[0002]

2. Description of the Related Art Generally, a thin film transistor (hereinafter referred to as TF) is used.
It is called T. In the case of an active matrix type liquid crystal device having ()) as a switching element, an electro-optical material such as a liquid crystal layer is sandwiched between a TFT array substrate and a counter substrate.

[0003] Such a TFT array substrate has a plurality of scanning lines and a plurality of data lines arranged crossing each other on the substrate, and a plurality of scanning lines and data lines arranged at intersections of the scanning lines and the data lines. The thin film transistor includes an electrically connected thin film transistor and a pixel electrode electrically connected to the thin film transistor. The thin film transistor is configured by arranging a gate electrode in the same layer as the scanning line and electrically connected to the semiconductor layer via a gate insulating film. And
A source electrode and a drain electrode formed in the same layer as the data line are formed thereon via an insulating film, and the data line and the source electrode are electrically connected.

[0004] When a liquid crystal device is used in a device such as a portable information terminal, there has recently been a strong demand for reducing its power consumption as much as possible. In order to reduce the power consumption of the TFT array substrate constituting the liquid crystal device, it is effective to reduce the resistance of the scanning line which is a wiring. Therefore, attention has been paid to using low-resistance aluminum in place of conventionally used materials such as chromium and tantalum. Since it is necessary to pay attention to heat resistance and chemical resistance of aluminum due to its characteristics, a wiring having a laminated structure in which a titanium layer is disposed below aluminum and a titanium nitride layer is disposed above aluminum has been used.

[0005] A TFT array substrate having a wiring having a laminated structure of titanium, aluminum, and titanium nitride as described above is formed through the following forming steps.

First, a semiconductor layer serving as a channel region made of polysilicon is formed on a glass substrate, and a gate insulating film made of a SiO ₂ film (silicon oxide film) is formed. Next, a titanium film, an aluminum film, and a titanium nitride film are sequentially stacked on the entire surface of the gate insulating film to form a stacked film.
By patterning this laminated film into a predetermined shape, a scanning line having a gate electrode at a position facing the channel region is formed. After that, an insulating film is formed on the gate insulating film so as to cover the scanning line and the gate electrode, and on this insulating film,
A source electrode, a drain electrode, and a data line are formed.

[0007]

However, the TFT array substrate formed by the above-described method has a problem that a projection called a hillock is formed even if a titanium nitride layer is laminated on an aluminum layer. When this hillock occurs, the hillock breaks through the insulating film covering the scanning line, and the data line and the scanning line formed on the insulating film may be short-circuited. When a short circuit occurs, the pixel electrode electrically connected to the shorted scan line and data line cannot perform any display, and a line defect occurs in each of the scan line and the data line, thereby deteriorating the display quality of the liquid crystal device. There has been a problem of remarkable reduction.

Japanese Patent Laid-Open No.
No. 0-135462 describes the following technology. In other words, paying attention to the fact that hillocks increase due to the desorption of water absorbed by the insulating film disposed below the wiring, a film for inhibiting the desorption of water is provided between the wiring and the insulating film. This is the technique of intervening. However, this technique can prevent the increase of hillocks, but cannot solve the fundamental problem itself of the generation of hillocks.

The present invention has been made in view of the above-mentioned problems, and when a wiring having a titanium layer and a layer containing aluminum is used, the generation of hillocks is suppressed, and a high-quality electrode substrate free from short-circuit failure is provided. An object is to provide an electro-optical device.

[0010]

According to the present invention, a silicon oxide film having a limited etching rate with respect to a buffered hydrofluoric acid solution (BHF) is used as a lower layer of a wiring in which a layer containing aluminum is laminated on a titanium layer. It has been found by the inventor that a wiring that suppresses generation of hillocks with good flatness can be formed.

That is, the electrode substrate of the present invention comprises:
A buffered hydrofluoric acid solution (BHF 50
% Hydrofluoric acid: 40% ammonium fluoride = 1: 6 room temperature. Hereinafter, unless otherwise specified, the buffered hydrofluoric acid solution is used under these conditions. A) a silicon oxide film having an etching rate of 4 nm / sec or less, and a wiring which is disposed on the silicon oxide film and in which a layer containing aluminum is laminated on a titanium layer.

According to such a configuration, by using a silicon oxide film having a specific film quality, the crystal orientation (11
1) It is possible to obtain a layer containing aluminum preferentially oriented on the surface, which has an effect of obtaining a flat and high-quality wiring in which hillock generation is suppressed. This is because, when a titanium layer is formed on the basis of a silicon oxide film having a wet etching rate of 4 nm / sec or less, more preferably 3 nm / sec or less with respect to a buffered hydrofluoric acid solution, the crystal structure of the titanium layer becomes crystal orientation (002). This is because it is easy to be formed with preferential orientation on the surface. When the layer containing aluminum has a crystal structure that is preferentially oriented in a single crystal orientation (111) plane, hillocks are less generated. Since the crystal orientation (111) plane of the aluminum-containing layer has good alignment with the crystal orientation (002) plane of the titanium layer, the layer containing aluminum is preferentially oriented on the titanium orientation (002) plane. Forming the crystal orientation (111)
A layer containing aluminum with a single preferential orientation in the plane can be obtained. The layer containing aluminum includes aluminum alone, for example, an aluminum alloy such as an alloy of aluminum and copper.

Further, the wiring is characterized in that a layer containing titanium is laminated on the layer containing aluminum. According to such a configuration, there is an effect that the layer containing aluminum can be protected by the layer containing titanium and the generation of hillocks can be further suppressed. In the case of using titanium nitride, it is preferable to use a cubic crystal system in order to obtain a hillock suppressing effect.

Further, a first wiring made of the wiring and a second wiring insulated from and intersecting with the first wiring are arranged on the substrate. According to such a configuration, since the occurrence of hillocks in the first wiring is suppressed, there is an effect that a short circuit between the first wiring and the second wiring due to the hillock is prevented, and an electrode substrate having no short-circuit defect is obtained.

Further, a semiconductor layer serving as a channel region is formed on the substrate, and the silicon oxide film is formed so as to cover the semiconductor layer. A gate made of the same layer as the wiring is provided at a position facing the semiconductor layer. The method is characterized by including a step of forming an electrode. According to such a configuration, even when the gate electrode of the switching element having the semiconductor layer is formed, similarly to the above-described wiring, a gate electrode in which hillocks are suppressed can be obtained, and the switching element having good switching characteristics can be obtained. And an effect that an electrode substrate having a wiring with good film quality is obtained.

Further, the electrode substrate of the present invention has an etching rate of 4 nm / sec for a substrate, a semiconductor layer serving as a channel region disposed on the substrate, and a buffered hydrofluoric acid solution disposed over the semiconductor layer. And preferably 3 nm /
A silicon oxide film having a thickness of not more than seconds and a gate electrode which is disposed on the silicon oxide film so as to face the semiconductor layer and has a layer containing aluminum stacked on a titanium layer. According to such a configuration, when forming the gate electrode of the switching element having the semiconductor layer, it is possible to obtain a flat gate electrode in which the occurrence of hillocks is suppressed, so that an electrode substrate having the switching element with good switching characteristics is obtained. It has the effect of.

Further, the gate electrode is characterized in that a layer containing titanium is laminated on the layer containing aluminum. According to such a configuration, there is an effect that generation of hillocks can be further suppressed.

Further, in the above-mentioned electrode substrate, the titanium layer has a thickness of 40 nm or more. According to such a structure, a flat titanium layer having good crystallinity can be obtained as a base layer of the layer containing aluminum by setting the thickness to 40 nm or more. This has the effect that a flat surface can be obtained, and a wiring or gate electrode having a uniform film quality within the substrate surface can be obtained. Here, the thickness of the titanium layer is desirably 100 nm or less in consideration of its resistivity.

An electro-optical device according to the present invention includes the above-described electrode substrate and a counter electrode disposed to face the electrode substrate. According to such a configuration, there is an effect of obtaining an electro-optical device having reduced display power and having good display characteristics without variation in display and capable of realizing a large screen and high definition.

The method of manufacturing an electrode substrate according to the present invention comprises the steps of: forming a silicon oxide film having an etching rate on a buffered hydrofluoric acid solution of 4 nm / sec or less, preferably 3 nm / sec or less, on the substrate; A step of forming a titanium film thereon, and a step of forming a film containing aluminum on the titanium film to form a stacked film.

According to such a configuration, by using a silicon oxide film having a specific film quality, the crystal orientation (11
1) A film containing aluminum with a single preferential orientation on the surface can be obtained, and a film containing aluminum which is flat and has good film quality and in which hillock generation is suppressed can be obtained. And
By patterning a film having a laminated film of such a titanium film and a film containing aluminum into a predetermined shape, there is an effect that a high-quality wiring or a gate electrode of a switching element is obtained. This is because when a titanium film is formed on the basis of a silicon oxide film having an etching rate with respect to a buffered hydrofluoric acid solution of 4 nm / sec or less, and more preferably 3 nm / sec or less, the crystal structure of the titanium film has a crystal orientation (002) plane. This is considered to be due to the fact that it is easy to be formed with preferential orientation. When the film containing aluminum has a crystal structure in which the film has a single preferential orientation in the crystal orientation (111) plane, hillocks are less generated, and the crystal orientation (111) plane of the aluminum-containing film has a crystal orientation ( Since the alignment between the (002) plane and the plane interval is good, a film containing aluminum is formed on a titanium film preferentially oriented in the (002) plane to obtain the (111) plane.
A film containing aluminum with a single preferential orientation on the surface can be obtained. The film containing aluminum includes aluminum alone, for example, an aluminum alloy such as an alloy of aluminum and copper.

The method further comprises the step of forming a film containing titanium on the film containing aluminum to form a laminated film. According to such a configuration, there is an effect that a layer containing aluminum can be protected and generation of hillocks can be further suppressed.

The method further comprises the steps of patterning the laminated film into a predetermined shape to form a first wiring, and forming a second wiring insulated from the first wiring and crossing the first wiring. And According to such a configuration, since the occurrence of hillocks in the first wiring is suppressed, there is an effect that a short circuit between the first wiring and the second wiring due to the hillock is prevented, and an electrode substrate having no short-circuit defect is obtained.

Further, a semiconductor layer serving as a channel region is formed on the substrate, and the silicon oxide film is formed so as to cover the semiconductor layer. The stacked film is patterned to form a gate electrode at a position facing the semiconductor layer. Is formed. According to such a configuration, when forming the gate electrode of the switching element having the semiconductor layer, it is possible to obtain a flat gate electrode in which generation of hillocks is suppressed and to obtain a switching element having good switching characteristics.

Further, the titanium film has a thickness of 40 nm or more. According to such a configuration,
With a thickness of 40 nm or more, a flat titanium film with good crystallinity can be obtained as a base film of a true film containing aluminum. Therefore, a flat surface can be obtained even when a film containing aluminum is stacked. Thus, there is an effect that a wiring or a gate electrode having a uniform film quality in a substrate surface is obtained. Here, the thickness of the titanium film is desirably 100 nm or less in consideration of its resistivity.

A method of manufacturing an electro-optical device according to the present invention is a method of manufacturing an electro-optical device having an electrode substrate and a counter electrode disposed to face the electrode substrate, wherein the electrode substrate is formed by the above-described manufacturing method. It is characterized by being manufactured by. According to such a configuration, the power consumption is reduced, the screen is enlarged,
This has the effect of obtaining an electro-optical device with good display characteristics and high display definition without display variations.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Method of Manufacturing Electrode Substrate) In the embodiment of the present invention, a semiconductor substrate having a semiconductor layer is taken as an example of an electrode substrate. In particular, wirings formed on the semiconductor substrate are shown in FIGS. This will be described with reference to FIG. FIG. 1 is a partial schematic view of a semiconductor substrate, and FIG. 2 is a view for explaining a manufacturing method thereof.

As shown in FIG. 1, a semiconductor substrate is formed by disposing a polysilicon layer 1 on a substrate 60 made of, for example, glass, and a gate insulating film 2 made of a silicon oxide film so as to cover the polysilicon layer. I have. Further, a wiring 33 is arranged at a position corresponding to a part of the polysilicon layer 1.
The wiring 33 has a three-layer structure, and includes a titanium layer, an aluminum / copper alloy layer, and a titanium nitride layer from below. When the thickness of the titanium layer is 40 nm or more, the crystallinity and flatness are good, and the orientation of the aluminum / copper alloy layer to be formed thereon can be improved. The thickness of the aluminum / copper alloy layer is 100 to 1000
nm, and here 400 nm. The thickness of the titanium nitride layer is set to 50 to 150 nm, and by setting the thickness to 50 nm or more, hillock generation can be suppressed.
m. In each of the drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

Next, a method for manufacturing a semiconductor substrate will be described with reference to FIG.

As shown in FIG. 2A, an a-Si film is formed with a thickness of about 30 to 100 nm by PECVD or LP (low pressure) CVD, and the crystal is irradiated with an excimer laser beam. After the formation, the polysilicon layer 1 is obtained by patterning into a predetermined shape.

Next, as shown in FIG.
Method D (plasma enhanced chemical vapor depositio
According to n), a gate insulating film 2 made of a silicon oxide film having a thickness of 50 to 120 nm, here, 75 nm is formed on the entire surface of the substrate by using TEOS (tetraethyl orthosilicate) as a source gas. This gate insulating film 2 had an etching rate of 3.5 nm / sec with respect to a buffered hydrofluoric acid solution. After the gate insulating film 2 was formed, the substrate was cleaned using a cleaning solution such as an alkaline cleaning solution that hardly erodes the silicon oxide film. Here, it is preferable to use an alkaline or sulfuric acid-based cleaning liquid without using a silicon oxide film eroding liquid such as dilute hydrogen fluoride as the cleaning liquid. Next, FIG.
As shown in FIG.
An aluminum / copper alloy film 35 and a titanium nitride film 36 are sequentially laminated and formed. Specifically, first, the substrate on which the semiconductor layer and the gate insulating film are formed is carried into a reaction chamber,
An m-thick titanium film 34 is formed. After forming the titanium film,
The substrate on which the titanium film 34 has been formed is carried into another reaction chamber, and an aluminum / copper alloy film 35 having a thickness of 400 nm is formed on the titanium film 34. After the formation of the aluminum / copper alloy film, the substrate is transported from the reaction chamber to another reaction chamber. A mixed gas of argon and nitrogen is introduced into the reaction chamber, and a titanium nitride film 36 having a thickness of 100 nm is formed using titanium target. Next, as shown in FIG.
The titanium film 34 and the aluminum film are formed so as to have a predetermined shape.
The wiring 33 is obtained by simultaneously patterning the copper alloy film 35 and the titanium nitride film 36.

FIG. 15A shows an evaluation of the crystal orientation of the titanium film at this time. In the sample of FIG. 15A, a single titanium film is formed and evaluated in order to exclude other signal components of the laminated film. The etching rate of the silicon oxide film, which was the base film of titanium, with respect to the buffered hydrofluoric acid solution was about 3.
5 nm / sec. On the other hand, FIG. 15 shows that a titanium single film was similarly formed on a silicon oxide film having an etching rate of about 9 nm / sec with a buffered hydrofluoric acid solution, and the crystal orientation was evaluated.
(B). As is clear from the comparison between the two, FIG.
The signal intensity of the sample shown in FIG. 15A is twice or more that of FIG. 15B. That is, when a titanium film is formed on a silicon oxide film having a low etching rate with respect to a buffered hydrofluoric acid solution, the crystallinity of titanium is improved.

Further, an aluminum / copper alloy film was formed on the titanium film and the crystal orientation was evaluated.
(A) and (b). FIG. 16 shows the etching rate of the underlying silicon oxide film with respect to the buffered hydrofluoric acid solution.
(A) is about 3.5 nm / sec, and FIG.
nm / sec. As is clear from comparison between the two, FIG.
The signal intensity of the sample of FIG. 5 (a) is about 1.5 in FIG. 15b (b).
The value is doubled. That is, when a titanium film and an aluminum / copper alloy film are formed by lamination on a silicon oxide film having a small etching rate with respect to a buffered hydrofluoric acid solution, the crystallinity of not only titanium but also an aluminum / copper alloy film is improved. I have.

The aluminum / copper alloy film 3 after film formation
In the crystal structure No. 5, the (111) plane was preferentially oriented, and the (200) plane was not detected. Here, the crystallinity is measured by an X-ray diffraction analyzer (device name RINIT-1).
400).

The wiring 33 formed through such a manufacturing process is a film in which the crystal structure of aluminum is preferentially oriented in the crystal orientation (111) plane and has excellent crystallinity as described above. At this time, good flatness can be obtained, and a short circuit between the wiring 33 and a wiring (not shown) formed on the wiring 33 via an insulating film (not shown) can be prevented. Thus, a highly reliable semiconductor substrate could be manufactured.

FIG. 17 shows a sample obtained by laminating an aluminum / copper alloy film on a titanium film to evaluate the average surface roughness by AFM. The etching rate of the silicon oxide film used as the base film with respect to the buffered hydrofluoric acid solution is about 3.5 nm / sec in FIG. 17A and about 9 nm / sec in FIG. 16B. This means that a film with good flatness can be formed by forming a titanium film and an aluminum / copper alloy film on a silicon oxide film having a small etching rate with respect to a buffered hydrofluoric acid solution.

In the semiconductor substrate formed through such a manufacturing process, generation of hillocks in the wiring could be suppressed even after a high-temperature processing step of, for example, 400 ° C. or more in a subsequent process.

FIG. 18 shows a sample obtained by laminating a titanium film, an aluminum-copper alloy film, and a titanium nitride film on a silicon oxide film having an etching rate of about 3.5 nm / sec in a buffered hydrofluoric acid solution, and heat-treated at 450 ° C. for 3 hours. It is a photograph showing a state. It can be seen that good flatness is maintained even after the heat treatment.

FIG. 19 shows a surface state of a laminated film in which a silicon oxide film, a titanium film, an aluminum / copper alloy film, and a titanium nitride film having an etching rate of 3.5 nm / sec by BHF are sequentially laminated on a glass substrate. . In FIG. 19A, the thickness of the titanium film is 400 nm, and in FIG. 19B, the thickness of the titanium film is 200 nm. As shown in the figure, it is found that the surface roughness of the laminated film is reduced by increasing the thickness of the titanium film which is the lower layer of the aluminum alloy film.

In the above embodiment and experimental results, the aluminum-copper alloy was used as the film containing aluminum.
Aluminum alone or an aluminum alloy composed of an alloy with a metal other than copper may be used.

(Method of Manufacturing Electro-Optical Device) In the present embodiment, a liquid crystal device is taken as an example of an electro-optical device using a switching element, a thin film transistor is used as a switching element, and a gate electrode of the thin film transistor and scanning as a wiring are used. Line and the same layer as this,
The titanium film of the embodiment of the electrode substrate described above, aluminum
A film formed by patterning a laminated film of a copper alloy film and a titanium nitride film is used.

In the present embodiment, FIGS.
This will be described with reference to FIG.

FIG. 3 is an equivalent circuit of various elements, wiring, etc. in a plurality of pixels formed in a matrix forming an image forming area of the liquid crystal device. FIG. 4 is a plan view of a plurality of pixel groups in a display area of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG. 5 is a longitudinal sectional view of a display region and a peripheral driving circuit region of the liquid crystal device. The longitudinal sectional view of the pixel region is a sectional view taken along line AA ′ of FIG. In each of the drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

In FIG. 3, the liquid crystal device comprises a display area and a peripheral drive circuit area for controlling the display area.

The display area includes the capacitor lines 3b arranged in parallel.
A scanning line 3, a data line 6 intersecting the scanning line 3, a pixel electrode 9a arranged in a matrix at each intersection of the scanning line 3 and the data line 6, and a pixel electrode 9a.
And a thin film transistor (hereinafter, referred to as a TFT) 30 for controlling the operation. The source of the TFT 30 is electrically connected to the data line 6 to which the image signal is supplied, and the gate of the TFT 30 is electrically connected to the scanning line 3 to which the scanning signal is supplied. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30, which is a switching element, for a predetermined period, the image signals S1 and S1 supplied from the data line 6.
2, ..., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are held for a certain period between the counter electrodes (described later) formed on the counter substrate (described later). .

On the other hand, the peripheral drive circuit area includes a scan line drive circuit 104, a data line drive circuit 101, a sampling circuit 301, and a precharge circuit 201. The scanning line driving circuit 104 supplies the scanning signals G1, G2,..., G to the scanning line 3 at a predetermined timing based on the power supplied from the external control circuit, the reference clock CLY and its inverted clock, and the like.
m is applied in a pulsed manner in a line-sequential manner. Data line drive circuit 1
01 is the data line 6 based on the power supplied from the external control circuit, the reference clock CLX and its inverted clock, etc., in accordance with the timing at which the scanning line driving circuit 104 applies the scanning signals G1, G2,. Transfer signal X from the shift register as a sampling circuit drive signal every time
, Xn are supplied to the sampling circuit 301 at a predetermined timing via the sampling circuit drive signal line 306. The precharge circuit 201 includes, for example, a TFT 202 as a switching element for each data line 6, a precharge signal line 204 is connected to the drain or source electrode of the TFT 202, and a precharge circuit drive signal line 206 is connected to the TFT 202. Is connected to the gate electrode of In operation, a precharge signal N is supplied from an external power supply via a precharge signal line 204.
Power is supplied at a predetermined voltage required for writing the RS, and the precharge signal is supplied via the precharge circuit drive signal line 206 at the timing preceding the supply of the image signals S1, S2,. A precharge circuit drive signal NRG is supplied from an external control circuit so as to write NRS. The precharge circuit 201 preferably includes image signals S1, S2,.
Precharge signal NRS (image auxiliary signal) corresponding to n
Supply. The sampling circuit 301 includes a TFT 302
Is provided for each data line 6, and the image signal line 304
The sampling circuit driving signal line 306 is connected to the source electrode of the FT 302 and the gate electrode of the TFT 302. Then, via the image signal line 304,
When the image signals S1, S2,..., Sn are input, they are sampled. That is, transfer signals X1, X2,..., X as sampling circuit drive signals from the data line drive circuit 101 via the sampling circuit drive signal line 306.
When n is input, the image signals S1, S2,..., Sn from the respective image signal lines 304 are sequentially applied to the data lines 6a.

In this embodiment, since polysilicon is used as the semiconductor layer of the TFT 30 in the display area, the TFT used in the peripheral drive circuit and the TFT 30 in the display area are formed in the same step on the same substrate. However, it is also possible to form a part of the peripheral drive circuit on another substrate and externally attach it.

In FIG. 4, a plurality of transparent pixel electrodes 9a are provided in a matrix on a TFT array substrate of a liquid crystal device, and data lines 6 and scanning lines are respectively provided along vertical and horizontal boundaries of the pixel electrodes 9a. 3 (dotted line) and a capacitance line 3b (dotted line). The data line 6 is formed in a shape extending in the vertical direction, and a source 6a, which is a part of the data line 6, is formed through a contact hole 5a in the semiconductor layer 1 made of a polysilicon film (hatched portion falling to the left) which will be described later. The data line 6 is electrically connected to the source region and is connected to the source 6a.
In the vicinity, it is formed so that its width becomes wide. A drain 6b formed in the same layer as the data line 6 is electrically connected to a later-described drain region of the semiconductor layer 1 through a contact hole 5b. 9a is electrically connected. Further, the scanning line 3 is arranged so as to face the channel region in the semiconductor layer 1, and the scanning line 3 functions as a gate electrode. In the present embodiment, the semiconductor layer 1 and the scanning line 3 overlap at two places. It has a double gate structure. In the drawing, a portion where the scanning line 3 and the semiconductor layer 1 overlap in a plane, that is, a semiconductor layer at a position corresponding to the gate electrode is hidden by the scanning line and is not shown. The capacitance line 3 b extends substantially linearly along the scanning line 3, and has a protruding portion protruding along the data line 6 from a portion intersecting with the data line 6. Some are located. The capacitance line 3b overlaps a part of the pixel electrode 9a in a plane, forms a capacitance in this region, and further forms a capacitance with the pixel electrode 9a. The semiconductor layer 1 extends below the data line 6 and the scanning line 3,
Similarly, the capacitance line 3 extending along the data line 6 and the scanning line 3
The capacitor is opposed to the portion b via the insulating film 2 to form a capacitor.

Next, as shown in the cross-sectional view of FIG. 5, the liquid crystal device 100 includes a liquid crystal layer 50 between the TFT array substrate 10 and an opposing substrate 80 disposed to oppose the TFT array substrate.

In the TFT array substrate 10, in a display area, a base film 12 made of silicon oxide and a semiconductor layer 1 made of polysilicon are arranged on a glass substrate 60. On the semiconductor layer 1, a gate insulating film 2 made of a silicon oxide film having an etching rate of 4 nm / sec or less by BHF is arranged. On the gate insulating film 2, a scanning line 3 (not shown) having a layer structure in which a titanium layer, an aluminum / copper alloy layer, and a titanium nitride layer are stacked from below, a gate electrode 3a which is a part of the scanning line, The capacitance line 3b is arranged. Then, the scanning line 3, the gate electrode 3a and the capacitance line 3
The insulating film 4 is disposed so as to cover “b”. On the insulating film 4, a data line 6 formed in the same layer and a source 6a and a drain 6b which are a part of the data line 6 are arranged. The source 6a is electrically connected to a source region of the semiconductor layer 1 described later by a contact hole 5a formed in the gate insulating film 2 and the insulating film 4, and a drain 6b is formed in the contact hole formed in the insulating film 4. 5b electrically connects to a drain region of the semiconductor layer 1 described later. Further, an interlayer insulating film 7 is arranged so as to cover the data line 6, the source 6a, and the drain 6b, and the drain 6b is formed on the interlayer insulating film 7 by an ITO (Indium) by a contact hole 8 formed in the interlayer insulating film 7. It is electrically connected to the pixel electrode 9a made of a Tin Oxide) film. Finally,
An alignment film 16 made of polyimide is arranged to cover the pixel electrode. Here, the semiconductor layer 1 of the TFT in the display area
Has an LDD (lightly doped drain) structure, and will be described later in detail.

In the peripheral drive circuit area of the TFT array substrate 10, a complementary transistor structure is employed. As shown in FIG. 5, the complementary transistor structure includes an N-channel TFT 130a and a P-channel TFT
An N-channel type semiconductor layer 1 and a P-channel type semiconductor layer 1 are provided on an underlayer 12 provided on a glass substrate 60, and a gate insulating film is formed so as to cover these. An insulating film 2 is provided. A gate electrode 103 is disposed on the gate insulating film 2 at a position corresponding to a channel region of the semiconductor layer. Further, the insulating film 4 is disposed so as to cover the gate electrode 103, and the source electrode 106a, 107a and the drain electrode 106b, 107b disposed on the insulating film 4 correspond to the corresponding semiconductor layer 1 respectively.
Is electrically connected to the source region or the drain region. Then, an interlayer insulating film 7 is disposed on the TFT having the complementary transistor structure. The semiconductor layer of the N-channel TFT has an LDD structure.

On the other hand, the opposing substrate 80 is composed of a light-shielding film 23 formed in a matrix on the glass substrate 20, an opposing electrode 21 made of an ITO film and formed over the same, and an alignment film 16 made of polyimide. Have been.

Next, a method of manufacturing a TFT array substrate will be described with reference to FIGS. 6 to 14 are cross sections in the display area and the peripheral circuit area, and the display area is a cross section taken along line AA ′ in FIG.

First, as shown in FIG. 6A, an SiO ₂ film as a base film 12 is formed on a glass substrate 60 by a plasma enhanced (PE) CVD method or an electron cyclotron resonance (ECR) CVD method to form a base film 12. 500
It is formed with a thickness of about nm. This base film is formed by removing impurities such as dirt on the surface of the glass substrate 60 and impurities contained in the glass substrate.
It has a function of preventing the characteristics of the FT 30 from deteriorating.

Next, as shown in FIG.
An a-Si film 401a is laminated on the underlying film to a thickness of about 30 to 100 nm by the D method or the LP (low pressure) CVD method.

Next, as shown in FIG. 6C, a-Si
Excimer laser light such as KrF or XeCl
Irradiation of 100 to 600 mJ / cm2 results in a-S
The i-film is crystallized to obtain a p-Si film 401b. The irradiation intensity, irradiation time, and the like of the excimer laser light are appropriately adjusted depending on the thickness, film quality, and the like of the a-Si film. In the present embodiment, since the polysilicon layer can be obtained at a low temperature by laser annealing, a glass substrate that is less expensive than a silicon substrate can be used as the substrate.

Next, as shown in FIG. 6D, a resist film 402 is formed in a shape corresponding to the semiconductor layer of each TFT in the display region and the peripheral drive circuit region.

Next, as shown in FIG. 7A, using the resist film 402 as a mask, the p-Si film 401b is subjected to RIE (reactive ion etching) using a chlorine-based gas.
The p-Si layer 1 is formed by etching. In addition to the dry etching such as RIE, wet etching using a chemical such as etching using hydrofluoric nitric acid can also be used.

Next, as shown in FIG. 7B, after the resist film 402 is peeled off, as shown in FIG.
TEOS (tetraethyl orthosilicate) by the method
A gate insulating film 2 made of a silicon oxide film having a thickness of 50 to 120 nm, here 75 nm,
Is formed on the entire surface of the substrate. This gate insulating film 2 had an etching rate for BHF of about 3.5 nm / sec.

Next, as shown in FIG. 7D, a resist film 403 having a shape in which a portion corresponding to a region functioning as a capacitor in the semiconductor layer 1 in the display region is removed is formed.
Then, using this resist film 403 as a mask, phosphorus ions are implanted as impurities into 5 × 10 ¹⁴ -1 by ion implantation.
Implanted into the semiconductor layer 1 at a dose of 0 ¹⁶ / cm ² ,
The capacitor electrode 1f is formed. After the implantation, the resist film 403 is peeled off.

The silicon oxide film was cleaned using a cleaning solution that is hardly eroded. Here, as the cleaning liquid, a silicon oxide film erodible liquid such as dilute hydrogen fluoride is not used, and it is preferable to use a low erodible alkali-based or sulfuric acid-based cleaning liquid. Orientation can be maintained.

Next, as shown in FIG. 8A, a titanium film 34, an aluminum / copper alloy film 35, and a titanium nitride film 36 are sequentially formed on the gate insulating film 2 by a sputtering method.

Next, as shown in FIG.
A resist film 404 having a shape corresponding to a gate electrode and a capacitance line
To form Using this as a mask, as shown in FIG. 8C, the titanium film 34, the aluminum / copper alloy film 35, and the titanium nitride film 36 are etched by RIE using a fluorine-based or chlorine-based gas. After etching, the resist film 404 is peeled off, and as shown in FIG. 9A, a three-layer structure in which a titanium nitride layer is laminated on a laminated structure composed of a titanium layer as a lower layer and an aluminum / copper alloy layer as an upper layer, A scanning line 3, gate electrodes 3a and 103, and a capacitance line 3b are obtained.

Next, as shown in FIG. 9B, a P-channel type TFT covering the entire display area and surrounding the display area is provided.
A resist film 405 from which the resist has been removed only at a position corresponding to the semiconductor layer to be formed. After that, the resist film 4
05 and a gate electrode 10 corresponding to a P-channel type TFT
3 is used as a mask, boron ions of 5 × 10 ¹⁴ to 10 ¹⁶ / cm ² are implanted into the semiconductor film 1 by an ion implantation method,
Channel region 1 self-aligned to gate electrode 103
a, a semiconductor layer 1 having source / drain regions 1g and 1h is obtained.

Next, as shown in FIG. 9 (c), the resist film 405 is peeled off by using (stripping liquid name).

Thereafter, as shown in FIG. 9D, a resist film 406 is formed at a position corresponding to the semiconductor layer to be a P-channel TFT in the peripheral circuit region. Next, using the resist film 406, the gate electrode 3a, the gate electrode 103 corresponding to the N-channel TFT, and the capacitor line 3b as a mask, 1 × 10 ¹³ to 2 × 10 ¹⁴ phosphorus ions / cm 2 are applied to the semiconductor layer 1. It is implanted by an ion implantation method. As a result, in the peripheral circuit region, the channel region 1a self-aligned with the gate electrode 103, the high-concentration source region 1b formed later, the low-concentration source region 1b having a lower impurity concentration than the high-concentration drain region, and the low-concentration drain region The semiconductor layer 1 corresponding to the N-channel TFT having 1c is obtained. In the display region, two channel regions 1a
(Only one is shown), having a low-concentration source region 1b and a low-concentration drain region 1c formed so as to sandwich the two channel regions and having a lower impurity concentration than the later-formed high-concentration source region and high-concentration drain region. Semiconductor 1 is obtained.

Next, the resist film 406 is stripped with a stripping solution. After that, as shown in FIG. 10A, a resist film 407 is formed. As shown in FIG.
Reference numeral 7 denotes a shape that covers the respective peripheral portions of the gate electrode 103 of the N-channel TFT in the peripheral drive circuit region and the gate electrode 3a in the display region and covers the semiconductor layer of the P-channel TFT. Next, using the resist film 407 as a mask, phosphorus ions are implanted into the semiconductor layer 1 at a dose of 5 × 10 ¹⁴ to 10 ¹⁶ / cm ² by an ion implantation method. After that, the resist film 407 is peeled off. As a result, as shown in FIG.
b, a semiconductor layer having a high concentration source region 1d and a high concentration drain region 1e having a higher impurity concentration than the low concentration drain region 1c can be obtained. Therefore, the TFT in the display region and the N-channel TFT in the peripheral driving circuit region become a semiconductor layer having an LDD structure.

Next, as shown in FIG. 10C, the PECV is formed so as to cover the gate electrodes 103, 3a and the capacitance line 3b.
According to Method D, using TEOS and ozone gas as source gases, an insulating film 4 made of SiO _{2 having} a thickness of 1500 nm
To form After that, activation heat treatment (activation annealing treatment) is performed at a temperature of 400 ° C. in order to activate the impurity ions.

Next, as shown in FIG. 10D, a contact hole for connecting the source / drain region of each TFT in the peripheral circuit region to a source / drain formed later, and a contact hole for the TFT in the display region. A resist film 409 patterned into a shape corresponding to a contact hole for connecting a source region and a source to be formed later, and a contact hole for connecting a drain region of a TFT in a display region and a drain to be formed later is formed. Form.

As shown in FIG. 11A, the resist film 4
Using the mask 09 as a mask, the insulating film 4 is etched to form contact holes 5, 5a, 5b. After that, the resist film 409 is peeled off to obtain the structure of FIG.

Next, as shown in FIG. 11C, an aluminum / titanium film 410 having a thickness of 300 to 1000 nm is formed on the insulating film 4 by a PVD method. Furthermore,
As shown in FIG. 11D, a resist film 411 is formed on the aluminum film / titanium film 410 in such a manner that portions corresponding to data lines, sources, and drains are removed.

Next, as shown in FIG. 12A, the aluminum / titanium film 410 is etched by RIE using a chlorine-based gas using the resist film 411 as a mask, and then the resist film 411 is peeled off. As a result, FIG.
As shown in (b), in the peripheral circuit region, source electrodes 106a and 107a and drain electrodes 106b and 107 electrically connected to the source and drain regions of the semiconductor layers of the N-channel TFT and the P-channel TFT, respectively.
Obtain b. In the display region, a data line 6 and a drain electrode 6b serving as a source electrode 6a electrically connected to a source region and a drain region of the semiconductor layer, respectively, are obtained.

Next, as shown in FIG. 12C, the interlayer insulating film 7 is covered with T to cover the source electrode, the drain electrode, and the data line.
PEC using mixed gas of EOS and oxygen gas as source gas
It is formed by the VD method. Here, a normal pressure CVD method may be used as a method for forming the interlayer insulating film 7, and a mixed gas of TEOS and ozone gas or a mixed gas of SiH ₄ and oxygen gas may be used as a source gas. Good. Also,
Not only an inorganic film but also an organic film such as an acrylic film can be used. In this case, a film having a larger thickness can be easily obtained as compared with the inorganic film, and thus can be used as a flattening film.

Next, as shown in FIG. 12D, a resist film 413 from which a resist corresponding to a contact hole connecting the drain 6b and a pixel electrode to be formed later is removed is formed on the interlayer insulating film 7. Form. Then, FIG.
As shown in (a), the resist film 413 is used as a mask to etch the interlayer insulating film 7 by RIE or wet etching, and the resist film 413 is peeled off.
As shown in FIG. 13B, an interlayer insulating film 7 having a contact hole 8 is obtained.

Next, as shown in FIG. 13C, an ITO film 414 having a thickness of about 50 to 200 nm is formed on the interlayer insulating film 7 by a sputtering method. Then, FIG.
(A), a resist film 415 corresponding to the pixel electrode shapes on the ITO film 414 is formed, an ITO film 414 as a mask, or wet etching in aqua regia or HBr, or CH ₄ or By performing dry etching by RIE using a gas such as HI, a pixel electrode 9a is obtained as shown in FIG.

As described above, in the present embodiment, when a wiring having a laminated structure of a titanium layer and an aluminum / copper alloy layer is formed, the film quality of the silicon oxide film located under the wiring is limited. By controlling the crystal structure of the titanium film, the crystal structure of the aluminum / copper alloy film having the titanium film as a base can be made to suppress the occurrence of hillocks. Accordingly, a thin film transistor having no defect can be obtained, and a liquid crystal device with no display defect and excellent display characteristics can be obtained in order to prevent a short circuit between a scanning line and a data line.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of an electrode substrate according to an embodiment.

FIG. 2 is a process chart sequentially showing a manufacturing process of the electrode substrate of the embodiment.

FIG. 3 is an equivalent circuit of various elements, wiring, and the like provided in a plurality of pixels in a matrix forming an image forming area in the liquid crystal device of the embodiment.

FIG. 4 is a plan view of a TFT array substrate on which data lines, scanning lines, and pixel electrodes are formed in a display area of the liquid crystal device according to the embodiment.

FIG. 5 is a vertical cross-sectional view of a peripheral circuit region and a display region of the liquid crystal device according to the embodiment, and the vertical cross-sectional view of the display region is a cross-sectional view taken along line AA ′ of FIG.

FIG. 6 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 7 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 8 is a process view (part 3) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 9 is a process diagram (part 4) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 10 is a process diagram (part 5) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 11 is a process diagram (part 6) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 12 is a process view (part 7) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 13 is a process view (part 8) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 14 is a process view (part 9) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 15 is a diagram showing a difference in crystal state of a titanium film due to a difference in film quality of a silicon oxide film.

FIG. 16 is a diagram showing a difference in crystal state between a titanium film and an aluminum / copper alloy laminated film due to a difference in film quality of a silicon oxide film.

FIG. 17 shows a titanium film due to a difference in film quality of a silicon oxide film,
It is a figure which shows the difference of the surface roughness of an aluminum-copper-alloy laminated film.

FIG. 18 is a view showing a state after heat treatment of a wiring film to which the present invention is applied.

FIG. 19 is a diagram showing a difference in the surface state of the laminated film due to a difference in the thickness of the titanium film.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor layer 2 ... Gate insulating film 3 ... Scanning line 3a ... Gate electrode 4 ... Insulating film 6 ... Data line 6a ... Source electrode 7 ... Interlayer insulating film 9a ... Pixel electrode 33 ... Wiring 34 ... Titanium film 35 ... Aluminum / copper Alloy film 36 ... Titanium nitride film 60 ... Substrate

Continued on the front page F term (reference) 2H092 JA25 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB57 JB63 JB69 KA04 KA07 KA16 KA18 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA28 MA35 MA37 MA41 NA15 A25 A25 A23 A06 A23 BA03 BA43 CA19 DA09 DA13 DA15 DB01 DB04 EA04 EA05 EA10 EB02 FA02 FB02 FB12 FB14 FB15 GB10 JA08 JA20 5F033 GG04 HH09 HH18 HH33 HH38 JJ01 JJ08 JJ18 JJ38 KK04 KK08 KK18 LL07 MM08 VQV XXV XXXV AA30 BB02 DD02 DD13 EE01 EE03 EE04 EE06 EE15 EE44 FF02 FF05 FF30 GG02 GG13 GG25 HJ01 HJ04 HJ13 HJ23 HL03 HL04 HL22 HL23 HL26 HM15 NN23 NN72 PP03 5G435 AA14 H12H13 BBH

Claims (16)

[Claims] 1. A substrate, a silicon oxide film disposed on the substrate, and having an etching rate with respect to a buffered hydrofluoric acid solution of 4 nm / sec or less; and a silicon oxide film disposed on the silicon oxide film;
An electrode substrate, comprising: a wiring in which a layer containing aluminum is stacked on a titanium layer. 2. The electrode substrate according to claim 1, wherein the wiring is formed by stacking cubic titanium nitride on the layer containing aluminum. 3. A first substrate comprising the wiring is provided on the substrate.
3. The wiring according to claim 1, wherein a wiring and a second wiring insulated from and intersect with the first wiring are arranged.
An electrode substrate according to claim 1. 4. A semiconductor layer serving as a channel region on the substrate, and the silicon oxide film is formed so as to cover the semiconductor layer, and a gate made of the same layer as the wiring is provided at a position facing the semiconductor layer. The electrode substrate according to any one of claims 1 to 3, further comprising a step of forming an electrode. 5. An etching rate for a substrate, a semiconductor layer serving as a channel region disposed on the substrate, and a buffered hydrofluoric acid solution disposed over the semiconductor layer, is 4 nm.
An electrode substrate, comprising: a silicon oxide film having a thickness of not more than 1 / sec; . 6. The electrode substrate according to claim 5, wherein the gate electrode is formed by stacking cubic titanium nitride on the layer containing aluminum. 7. The electrode substrate according to claim 1, wherein the titanium layer has a thickness of 40 nm or more. 8. The electrode substrate according to claim 1, wherein the silicon oxide film is formed by a CVD method using a tetraethylorthosilicate gas. 9. An electro-optical device comprising: the electrode substrate according to claim 1; and an opposing electrode disposed to face the electrode substrate. 10. A step of forming a silicon oxide film having an etching rate with respect to a buffered hydrofluoric acid solution of 4 nm / sec or less on a substrate; a step of forming a titanium film on the silicon oxide film; Forming a film containing aluminum on the substrate to form a laminated film. 11. The method for manufacturing an electrode substrate according to claim 10, further comprising a step of forming a film containing titanium on the film containing aluminum to form a laminated film. 12. The method according to claim 1, further comprising: forming a first wiring by patterning the laminated film into a predetermined shape; and forming a second wiring insulated from and intersecting with the first wiring. The method for manufacturing an electrode substrate according to claim 10 or 11, wherein 13. A semiconductor layer serving as a channel region on the substrate, wherein the silicon oxide film is formed so as to cover the semiconductor layer. A gate electrode is formed at a position facing the semiconductor layer by patterning the laminated film. The method for manufacturing an electrode substrate according to claim 10, further comprising: 14. The method for manufacturing an electrode substrate according to claim 10, wherein said titanium film has a thickness of 40 nm or more. 15. The manufacturing method of an electrode substrate according to claim 10, wherein the silicon oxide film is formed by a CVD method using a tetraethylorthosilicate gas. Method. 16. A method for manufacturing an electro-optical device having an electrode substrate and a counter electrode arranged to face the electrode substrate, wherein the electrode substrate is any one of claims 10 to 15. A method for manufacturing an electro-optical device, wherein the method is manufactured by the manufacturing method described above.