JP2002083812A - Wiring material and semiconductor device with the wiring material and its manufacturing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable electrooptical device and its manufacturing method using a material having sufficiently low electric resistivity and high heat resistance as the wiring or electrode of each circuit of the electrooptical device represented by an AM-LCD. SOLUTION: A target with a high degree of purity is used, a unitary argon gas (Ar) is used as a sputter gas, the temperature of a substrate is set to 300 deg.C or less, sputter power is set to 1 to 9 kW, and the pressure of the sputter gas is set to 1.0 to 3.0 Pa, thus setting the stress of a film to -1×1010 to 1×1010 dyn/cm2. Using a conductive film where sodium contained in the film is set to 0.03 ppm or less (preferably, 0.01 ppm or less) and at the same time an electric resistance rate is set to 40 μΩcm or less as the gate wiring material of TFT and other wiring materials, the operation performance and reliability of the semiconductor device with TFT can be improved greatly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring material for a semiconductor device. In particular, the present invention relates to a semiconductor device having a circuit including a thin film transistor (hereinafter, referred to as a TFT) and a manufacturing method thereof. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

Conventionally, as a wiring material of the TFT, an aluminum film having a low resistivity using a sputtering method is often used. However, when a TFT is manufactured using aluminum as a wiring material, heat treatment may cause protrusions such as hillocks and whiskers, and diffusion of aluminum atoms into a channel formation region, resulting in malfunction of the TFT and deterioration of TFT characteristics. I was

[0005]

As described above, aluminum is not a preferable wiring material in a TFT manufacturing process because of its low heat resistance.

For this reason, attempts have been made to use a material containing tantalum (Ta), titanium (Ti), or the like as a main component as a wiring material other than aluminum. Tantalum and titanium have higher heat resistance than aluminum, but have a problem of high electrical resistivity. Further, when heat treatment of tantalum is performed at about 500 ° C., the electric resistivity increases several times as compared with that before heat treatment, which has been a problem.

If the film formed on the substrate has a large stress, the substrate may be warped or the film itself may be peeled off. It is desired to form a film having a low stress. As one means to control film stress,
Argon (Ar), krypton (Kr), xenon (X
It has been proposed to use the mixed gas of e) as a sputtering gas. However, since krypton (Kr) and xenon (Xe) are expensive, using a mixed gas is not suitable for mass production.

The present invention has been made in view of the above problems, and has a sufficiently low electric resistivity and low heat resistance as wirings or electrodes of each circuit of an electro-optical device represented by AM-LCD. It is an object to provide an electro-optical device having high reliability using a sufficiently high material and a manufacturing method thereof.

[0009]

According to the invention disclosed in this specification, a wiring material containing tungsten or a tungsten compound as a main component contains 90% or more of argon as an inert element in the wiring material. In addition, the wiring material has a sodium content of 0.3 ppm or less.

In the above structure, the tungsten compound is one kind of element selected from Ta, Ti, Mo, Cr, Nb, and Si, or a compound of plural kinds of elements and tungsten.

In the above structure, the wiring material has an electrical resistivity of 40 μΩ · cm or less, preferably 20 μΩ · cm.
・ It is characterized by being less than cm.

[0012] Further, another invention has a configuration of W, Ta, T
a kind of element selected from i, Mo, Cr, Nb, and Si;
Alternatively, a metal film containing a plurality of types of elements, a metal compound film containing the above elements as a main component, an alloy film combining the above elements, or a stacked film obtained by stacking thin films selected from the above metal films, metal compound films, and alloy films Wherein the wiring contains 90% or more of argon as an inert element in the wiring, and the content of sodium in the wiring is 0.3 ppm or less. is there.

According to another aspect of the present invention, there is provided a semiconductor device including a wiring including a film containing tungsten or a tungsten compound as a main component, wherein the wiring contains 90% or more of argon as an inert element in the wiring. And the content of sodium in the wiring is 0.3 ppm or less.

According to another aspect of the invention, there is provided a semiconductor device including a wiring having a stacked structure including a film containing tungsten or a tungsten compound as a main component and a tungsten nitride film, wherein the wiring is A semiconductor device characterized by including 90% or more of argon as an inert element in a wiring and having a sodium content of 0.3 ppm or less in the wiring.

In another aspect of the invention, a laminated structure including a silicon film to which an impurity element imparting a conductivity type is added, a film containing tungsten or a tungsten compound as a main component, and a tungsten nitride film is provided. A semiconductor device provided with a wiring, wherein the wiring contains 90% or more of argon as an inert element in the wiring, and the content of sodium in the wiring is 0.3 ppm or less. Semiconductor device.

In each of the above structures, the wiring is formed by a sputtering method using argon as a sputtering gas.

In each of the above structures, the inert element (Xe or Kr) other than argon contained in the wiring is 1
It is characterized by being at most atoms%, preferably at most 0.1 atoms%.

In any one of the above structures,
The internal stress of the film containing tungsten or a tungsten compound as a main component is −2 × 10 ¹⁰ dyn / cm ² to 2 × 10 ¹⁰ dyn / cm 2.
^{× 10 1 0 dyn / cm 2} , preferably -1 × ¹⁰ 10 dy
It is characterized by n / cm ² to 1 × 10 ¹⁰ dyn / cm ² .

Further, in any one of the above configurations,
The line width of the wiring is 5 μm or less.

Further, in any one of the above structures,
The thickness of the wiring is 0.1 μm or more and 0.7 μm or less.

Further, in any one of the above structures,
It is characterized in that the wiring is used as a gate wiring of a TFT.

According to another aspect of the invention for realizing each of the above structures, in a method for manufacturing a semiconductor device including at least wiring on an insulating surface, the wiring is formed by a step of forming a tungsten film by a sputtering method; Forming a film by patterning a film.

In the above structure, the sputtering method is characterized in that a tungsten target having a purity of 4N or more is used.

In the above structure, the sputtering method is characterized by using a tungsten alloy target having a purity of 4N or more.

The above structure is characterized in that the sputtering method is a sputtering method using only argon as a sputtering gas.

In each of the above-mentioned structures, the stress of the film is adjusted to −2 × 10 ¹⁰ dyn / cm ² to 2 × 10 ¹⁰ dy by appropriately adjusting the substrate temperature, the gas pressure, and the sputtering power.
n / cm ² , preferably −1 × 10 ¹⁰ dyn / cm ² to 1
It is possible to obtain a desired value within the range of × 10 ¹⁰ dyn / cm ² .

Further, the substrate temperature in the sputtering method is set to 300 ° C. or less. The gas pressure in the sputtering method is 0.1 Pa to 3.0 P.
a, preferably 1.0 Pa to 2.0 Pa.

Further, the sputtering power in the sputtering method is used.
Power is 300W ~ 15KW, preferably 1KW ~ 9KW
(Target with a size of φ305 mm)
It is a sign. That is, it is converted to the sputtering power per unit area.
When calculated, 0.41 W / cm ^Two~ 20.53W / cm^Two,
Preferably 1.37 W / cm^Two~ 12.32W / cm^Twoso
is there.

As shown in FIG. 28, when the thin film 51 is about to contract with respect to the substrate 52, the substrate 52 is pulled in such a direction as to impede the contraction, as shown in FIG. , And this is called tensile stress, which is expressed as stress in the “+” direction. On the other hand, when the thin film 51 is about to be stretched, the substrate 52 is compressed and deformed with the thin film 51 facing outward. This is called a compressive stress and is expressed as a stress in the “−” direction.

[0030] In this specification, the term "electrode" refers to
It is a part of the “wiring” and refers to a portion where electrical connection with another wiring or a portion intersecting with a semiconductor layer is made. Therefore,
For convenience of explanation, we use "wiring" and "electrode" properly,
It is assumed that the term “electrode” always includes “wiring”.

[0031]

Embodiments of the present invention will be described below.

In order to solve the above-mentioned problems, the present invention provides:
A high-melting-point metal film obtained by a sputtering method using a high-purity high-melting-point metal target is provided as a wiring material. Typically, one of the features of the present invention is to use tungsten (W) as a high melting point metal.

As a target, 4N (9
9.99%) or more, preferably 6N (99.9999).
%) Or more, and a single gas of argon (Ar) is used as a sputtering gas.

Further, according to the present invention, the substrate temperature, the sputtering gas
Stress control by adjusting the pressure (gas pressure)
Is one of the features. Substrate temperature below 300 ° C
And the pressure of the sputtering gas is set to 1.0 Pa to 3.0 P
a, preferably 1.0 Pa to 2.0 Pa
The stress of the film is -5 × 10^Ten~ 5 × 10^Tendyn / cm
^Two, Preferably -2 × 10^Tendyn / cm^Two~ 2 × 10^Ten
dyn / cm^Two, More preferably -1 × 10^Tendyn
/ Cm^Two~ 1 × 10^Tendyn / cm^TwoAnd can
You.

Further, the present invention is characterized in that stress control is performed by adjusting a substrate temperature, a pressure of a sputtering gas (gas pressure), or a sputtering power.

Further, conventionally, when the sputtering power is increased, the film stress increases. However, by utilizing the present invention, an increase in film stress can be suppressed,
Larger sputtering power can be applied, and the sputtering rate can be improved.

The sodium (Na) concentration and potassium (K) concentration of the tungsten film of the present invention obtained by the sputtering method were analyzed by GDMS analysis. The analysis results are shown in Table 1 and FIG.

[0038]

[Table 1]

The GDMS analysis method in the present specification is defined as
Glow Discharge Mass Spectro
This is a solid-state mass spectrometry method in which a sample is sputtered and ionized by glow discharge and taken out. GD
The MS analysis method is an analysis method widely used as a trace analysis method because a stable ion source is obtained.

As shown in Table 1 and FIG. 25, the sodium (Na) concentration of the tungsten film was 0.3 ppm or less,
Preferably, it can be set to 0.1 ppm or less, and it can be suppressed to a range that does not affect the TFT characteristics even when used as a gate wiring. If a large amount of sodium (Na) is contained in the gate electrode, the TFT characteristics are adversely affected.

The wiring of the semiconductor device may have a laminated structure of a tungsten film and a nitrided tungsten film. For example, tungsten nitride (WNx
(However, 0 <x <1)) and then tungsten (W)
Are laminated. Further, a structure in which a silicon film having conductivity (for example, a phosphorus-doped silicon film, a boron-doped silicon film, or the like) is provided under tungsten nitride (WNx) to improve adhesion may be employed. The wiring can be formed with a line width of 5 μm or less and a film thickness of 0.1 to 0.7 μm.

FIG. 26 (a) shows the stress value of the tungsten film of the present invention, FIG. 26 (b) shows the stress value after heat treatment (500 ° C., 4 hours), and FIG. )
Later stress values are shown. The tungsten film was formed under the conditions of an argon gas flow rate of 100 sccm and a sputtering power of 6 kW. However, FIG. 26 (b) and FIG.
In (c), at the time of the heat treatment, the silicon oxynitride film SiOxNy (0 <x, y <1) is covered with 200 nm.

The tungsten film of the present invention, which initially had a tensile stress as the temperature of the heat treatment was raised, tends to further increase the tensile stress when the heat treatment is applied. Easy to control stress.

The stress of the tungsten film of the present invention can be controlled by the substrate temperature, the pressure and the sputtering power at the time of film formation.
The manner in which the stress of the tungsten film changes after annealing depends on whether or not a silicon oxynitride film is formed to cover the tungsten film. That is, when covered with the silicon oxynitride film, the stress changes in the tensile direction after annealing, and when not covered, changes in the compression direction. When forming the silicon oxynitride film over the tungsten film, adjust the film formation conditions of the tungsten film to have a weak compressive stress and a weak tensile stress when not forming the silicon oxynitride film. For example, it is possible to reduce the stress after annealing.

FIG. 30 is a graph showing the relationship between sputtering power and stress. FIG. 30 shows the stress before the heat treatment of the tungsten film (thickness: 400 nm) and the heat treatment (55
(0 ° C., 4 hours). Thus, the stress can be freely adjusted by adjusting the sputtering power. As shown in FIG. 31, when the sputtering power is changed, the resistivity also changes. FIG.
The resistivity of the tungsten film before heat treatment and the heat treatment (55
(0 ° C., 4 hours). However,
The sputtering power shown in FIGS. 30 and 31 is φ305 mm
This is data using a target of size. Therefore,
Needless to say, it can be converted into sputtering power per unit area.

As a comparative example of a general high melting point metal, FIG. 26A shows the stress value of a laminated film of tantalum and tantalum nitride, and FIG. 26B shows the stress after heat treatment (500 ° C., 4 hours). Value, heat treatment shown in FIG. 26 (c) (800 ° C., 4 hours)
Later stress values are shown. Similarly, FIG. 26 (b) and FIG.
In FIG. 6C, the silicon oxynitride film SiOxNy of 200 nm (where 0 <x, y <1) is covered when the heat treatment is performed.

As shown in FIGS. 26A to 26C, the laminated film of tantalum and tantalum nitride initially had a tensile stress as the heat treatment temperature was increased. When added, the film tends to shift to a film having a compressive stress, so that it is difficult to control the film stress.

FIG. 27 (a) shows the resistivity of the tungsten film of the present invention, FIG. 27 (b) shows the resistivity after heat treatment (500 ° C., 4 hours), and FIG. 4
H). Here, the resistivity is an electric resistivity.

As shown in FIGS. 27A to 27C, the tungsten film of the present invention has a low resistivity (12 to 16 μm).
Ω · cm), and there is almost no change in resistivity after the heat treatment. The resistivity of the tungsten film can be reduced to 12 μm by appropriately changing the sputtering conditions.
Ω · cm or less, preferably about 9 μΩ · cm.

On the other hand, general refractory metals have no resistance to oxidation and are easily oxidized by heat treatment in an atmosphere in which several ppm of residual oxygen exists. As a result, an increase in electrical resistivity and peeling of the film have occurred. In addition, at the time of ion doping, a small amount of an impurity element such as oxygen contained in the reaction gas is injected into the high melting point metal film, so that the electrical resistivity has increased.

For example, when heat treatment is performed on a laminated film of tantalum and tantalum nitride, a silicon oxynitride film SiO
Despite being covered with xNy (where 0 <x, y <1), the resistivity after heat treatment (about 50 to 80 μΩ · cm) is compared with the resistivity before heat treatment (about 25 μΩ · cm). )
Had increased several times.

In general, when forming a contact with another conductive film, an etching process for removing a thin oxide film and contaminants is performed before forming another conductive film.
Next, when the structure shown in FIG. 29 is formed on the substrate 60, the presence or absence of heat treatment (500 ° C., 1 hour) and the presence of the electrode 62 (Al-
Etching (1/1) before film formation of Si (2 wt%)
Table 2 shows the results of comparing the resistance values with and without the presence of 0-diluted HF).

[0053]

[Table 2]

The number of contacts was 50, and the total contact area was about 420 μm ^2. An electrode having a laminated structure of tantalum and tantalum nitride and an electrode having a laminated structure of a tungsten film and a tungsten nitride film were compared. Was done. In Table 2, resistance values per 1 μm square of contact area are shown. Here, the resistance value per 1 μm square of the contact area is called a contact resistance value.

Table 2 shows that the electrodes 61 and 62 (Al-Si (2 wt.
%)), The etching resistance (1/1)
The resistance value is lower in the presence of (0 dilution HF) than in the absence thereof. In addition, the contact resistance of the wiring having a laminated structure of tantalum and tantalum nitride is sharply increased when heat treatment is performed, and its value reaches 0.4 kΩ.

On the other hand, an electrode 61 and an electrode 62 (Al-S) having a laminated structure of a tungsten film and a tungsten nitride film
i (2 wt%)), no change is observed regardless of the presence or absence of heat treatment and etching treatment (1/10 diluted HF). The contact resistance value of the present application is 1.3Ω.
And a sufficiently low resistance value. If the contact resistance value is 40Ω or less, preferably 10Ω or less, more preferably 5Ω or less, it can be used as a wiring. Further, in Table 2, the heat treatment is not covered with the silicon oxynitride film as shown in FIG.

That is, the resistivity of the tungsten film of the present invention hardly changes even if it is not covered with a silicon oxynitride film or the like during the heat treatment. From these facts, it is understood that the tungsten film of the present invention has a very high heat resistance and is hardly oxidized. When the tungsten film of the present invention is used, this etching process can be omitted.

According to the present invention, sodium contained in the film is 0.03 ppm or less, the film has a low electric resistivity (40 μΩ · cm or less) even after the heat treatment, and the stress is −5 × 1.
0 ¹⁰ dyn / cm ^{2 to} 5 × 10 ¹⁰ dyn / cm ² , preferably −1 × 10 ¹⁰ dyn / cm ² to 1 × 10 ¹⁰ dyn /
By using a tungsten film controlled to a cm ² as a gate wiring material of a TFT and other wiring materials, T
The operating performance and reliability of the semiconductor device including the FT can be greatly improved.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0060]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. Here, the pixel TFT in the pixel section
A method for manufacturing TFTs of a driver circuit provided around a pixel portion over the same substrate will be described in detail according to steps. However, for the sake of simplicity, the control circuit shows a CMOS circuit as a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

In FIG. 1A, a low alkali glass substrate or a quartz substrate can be used as the substrate 101. In this embodiment, a low alkali glass substrate was used. in this case,
The heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. TFT of this substrate 101
In order to prevent impurity diffusion from the substrate 101, a base film 102 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is
It is formed with a thickness of nm. For example, S by plasma CVD
A silicon oxynitride film made of iH ₄ , NH ₃ , and N ₂ O is formed to a thickness of 100 nm, and a silicon oxynitride film made of SiH ₄ , N ₂ O is formed to a thickness of 200 nm.

Next, 20 to 150 nm (preferably 30 to
Semiconductor film 10 having an amorphous structure with a thickness of
3a is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. Examples of the semiconductor film having an amorphous structure include an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. Since the base film 102 and the amorphous silicon film 103a can be formed by the same film formation method, both may be formed continuously. After the formation of the base film, it is possible to prevent the surface from being contaminated by not once exposing it to the atmosphere, thereby reducing the variation in the characteristics of the TFT to be manufactured and the fluctuation of the threshold voltage. (Fig. 1 (A))

Then, a crystalline silicon film 103b is formed from the amorphous silicon film 103a using a known crystallization technique. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied.
According to the technique disclosed in Japanese Patent Publication No. 130652, the crystalline silicon film 103b was formed by a crystallization method using a catalytic element. Prior to the crystallization step, depending on the amount of hydrogen contained in the amorphous silicon film, heat treatment may be performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen to 5 atom% or less before crystallization. desirable. When the amorphous silicon film is crystallized, rearrangement of atoms occurs and the film becomes denser. Therefore, the thickness of the crystalline silicon film to be formed is larger than the initial thickness of the amorphous silicon film (55 nm in this embodiment). Also decreased by about 1 to 15%. (FIG. 1 (B))

Then, the crystalline silicon film 103b is divided into islands to form island-like semiconductor layers 104 to 107.
After that, the plasma CVD method or the sputtering method
Mask layer 1 of a silicon oxide film having a thickness of 100 nm
08 is formed. (Fig. 1 (C))

Then, a resist mask 109 is provided, and island-shaped semiconductor layers 105 to 107 for forming an n-channel TFT are formed.
1 × 10 ^{16 to} 5 for the purpose of controlling the threshold voltage
Boron (B) was added at a concentration of about × 10 ¹⁷ atoms / cm ³ as an impurity element imparting p-type. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Although the addition of boron (B) here is not always necessary, the semiconductor layers 110 to 112 to which boron (B) is added are preferably formed to keep the threshold voltage of the n-channel TFT within a predetermined range. It was good. (Figure 1
(D))

In order to form an LDD region of an n-channel TFT of a driving circuit, an impurity element imparting n-type is selectively added to the island-shaped semiconductor layers 110 and 111. Therefore, resist masks 113 to 116 were formed in advance. As an impurity element imparting n-type, phosphorus (P) or arsenic (As) may be used. Here, an ion doping method using phosphine (PH ₃ ) is applied to add phosphorus (P). Impurity regions 117, 118 formed
(P) concentration of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³
Should be within the range. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 117 to 119 formed here is expressed as (n ⁻ ). The impurity region 119 is a semiconductor layer for forming a storage capacitor in a pixel portion, and phosphorus (P) is added to this region at the same concentration. (Fig. 2 (A))

Next, a step of removing the mask layer 108 with hydrofluoric acid or the like and activating the impurity element added in FIGS. 1D and 2A is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or a laser activation method. Further, both may be performed in combination. In this embodiment, a KrF excimer laser beam (wavelength 248 n
m) to form a linear beam and generate an oscillation frequency of 5 to 5
Scanning was performed at 0 Hz, an energy density of 100 to 500 mJ / cm ^{2 and an} overlap ratio of the linear beam of 80 to 98%, and the entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed. There are no particular restrictions on the laser light irradiation conditions, and the conditions may be determined appropriately by the practitioner.

Then, the gate insulating film 120 is formed by plasma C
The insulating film containing silicon is formed with a thickness of 10 to 150 nm by a VD method or a sputtering method. For example, 120
A silicon oxynitride film is formed with a thickness of nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (FIG. 2 (B))

Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, or may be formed as a two-layer or three-layer structure as necessary. In this embodiment, a conductive layer (A) 121 made of a conductive nitride metal film and a conductive layer (B) 122 made of a metal film are stacked. The conductive layer (B) 122 is made of tantalum (Ta), titanium (Ti), molybdenum (M
o), an element selected from tungsten (W), or an alloy containing the above element as a main component, or an alloy film (typically, a Mo—W alloy film or a Mo—Ta alloy film) that combines the above elements. The conductive layer (A) 121 may be formed using tantalum nitride (TaN), tungsten nitride (WN), a titanium nitride (TiN) film, and molybdenum nitride (MoN). Alternatively, as the conductive layer (A) 121, tungsten silicide, titanium silicide, or molybdenum silicide may be used as an alternative material. The conductive layer (B) should preferably have a low impurity concentration in order to reduce the resistance. In particular, the sodium concentration should be 0.1 ppm or less, and the oxygen concentration should be 1 wt% or less. For example, tungsten (W) has an oxygen concentration of 0.2 wt% or less, and has a concentration of 40 μΩ · cm or less, preferably 20 μΩ.
-Resistivity of not more than cm could be realized.

The conductive layer (A) 121 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 122 has a thickness of 200 to 400 nm (preferably 250 to 350 nm).
It is good. In this embodiment, a 50-nm-thick tungsten nitride (WNx) film is used as the conductive layer (A) 121, and a 350-nm-thick tungsten (W) film is used as the conductive layer (B) 122. In this embodiment, the layers are continuously formed by a sputtering method without exposure to the air.

In this embodiment, 6N (99.9999%)
And a simple gas of argon (Ar) was used as a sputtering gas. Further, by setting the substrate temperature to 200 ° C., the pressure of the sputtering gas to 1.5 Pa, and the sputtering power to 6 kW, the stress of the film becomes −5 ×
10 ^{10 to} 5 × 10 ¹⁰ dyn / cm ² , preferably -2 ×
^{10 10 ~2 × 10 10 dyn /} cm 2, more preferably controlled within a range of ^{-1 × 10 10 ~1 × 10 1} 0 dyn / cm 2. Thus, the sodium (Na) concentration of the tungsten film of the present application can be made 0.3 ppm or less, preferably 0.1 ppm or less by GDMS analysis, so that it does not affect the TFT characteristics even when used as a gate wiring. I was able to. The resistivity of the tungsten film of the present invention hardly changes even after the heat treatment. If a low-resistance and highly reliable gate wiring is used, the TFT
The operation performance and reliability of have been greatly improved.

Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 121. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 120. Can be prevented. (Fig. 2 (C))

Next, resist masks 123 to 127 are formed, and the conductive layer (A) 121 and the conductive layer (B) 122 are collectively etched to form gate electrodes 128 to 131 and a capacitor wiring 132. The gate electrodes 128 to 131 and the capacitor wiring 132 are formed of conductive layers (A) 128 a to 132
a and 128b to 132b made of a conductive layer (B) are integrally formed. At this time, the gate electrodes 129 and 130 formed in the driver circuit are doped with the impurity regions 117 and 118.
Is formed so as to overlap with part of the gate insulating film 120 via the gate insulating film 120. (FIG. 2 (D))

Next, in order to form the source region and the drain region of the p-channel TFT of the driving circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity regions are formed in a self-aligned manner using the gate electrode 128 as a mask. At this time, a region where the n-channel TFT is to be formed is covered with a resist mask 133. Then, an impurity region 134 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 134 formed here is expressed as (p ⁺ ). (FIG. 3 (A))

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 135 to 137 are formed, and an impurity element imparting n-type
38 to 142 were formed. This is a phosphine (PH
₃ ), and the phosphorus (P) concentration in this region was set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . In this specification, the impurity region 13 formed here is used.
The concentration of the impurity element imparting n-type contained in 8-142 is represented as (n ⁺ ). (FIG. 3 (B))

The impurity regions 138 to 142 contain phosphorus (P) or boron (B) already added in the previous step, but phosphorus (P) is added at a sufficiently high concentration. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step. Since the concentration of phosphorus (P) added to the impurity region 138 is １ ／ to １ ／ of the concentration of boron (B) added in FIG.
The conductivity of the mold was ensured, and the characteristics of the TFT were not affected at all.

The L of the n-channel TFT in the pixel portion is
An n-type impurity-imparting process for forming a DD region was performed. Here, an impurity element imparting n-type in a self-aligned manner is added by an ion doping method using the gate electrode 131 as a mask. The concentration of phosphorus (P) to be added is 1 × 10
^{16 to} 5 × 10 ¹⁸ atoms / cm ^3, which is substantially lower than the concentration of the impurity element added in FIGS. 2A, 3A, and 3B. Is the impurity region 14
Only 3, 144 are formed. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 143 and 144 is expressed as (n ⁻ ). (FIG. 3 (C))

Thereafter, a heat treatment step is performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation step was performed by furnace annealing. The heat treatment is performed in a nitrogen atmosphere having an oxygen concentration of 8 ppm to 9% at 400 to 800 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. Also, substrate 1
In the case where a heat-resistant material such as a quartz substrate is used for the substrate 01, heat treatment may be performed at 800 ° C. for 1 hour to activate the impurity element and to form an impurity region to which the impurity element is added and a channel forming region. Was successfully formed.

In this heat treatment, the gate electrodes 128 to 128
131 and metal films 128b to 13 for forming the capacitance wiring 132
2b is a conductive layer (C) 1 having a thickness of 5 to 80 nm from the surface.
28c to 132c are formed. For example, the conductive layer (B)
In the case where 128b to 132b are tungsten (W), tungsten nitride (WN) is formed and tantalum (Ta) is formed.
In this case, tantalum nitride (TaN) can be formed. The conductive layers (C) 128c to 132c can be formed in the same manner even when the gate electrodes 128 to 131 are exposed to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-shaped semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When the island-like semiconductor layer was formed from the amorphous silicon film by a crystallization method using a catalytic element, a trace amount of the catalytic element remained in the island-like semiconductor layer. Of course, it is possible to complete the TFT in such a state,
It was more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing the gettering action of phosphorus (P). The concentration of phosphorus (P) necessary for gettering is almost the same as that of the impurity region (n ⁺ ) formed in FIG. 3B, and the heat treatment in the activation step performed here causes the n-channel TFT and the p-type. The catalyst element could be gettered from the channel forming region of the channel type TFT. (FIG. 3 (D))

FIGS. 6A and 7A are top views of the TFT in the steps up to here, and the AA 'section and the CC' section are taken along the lines AA 'and CC' in FIG. 3D. CC ′. The BB 'cross section and the DD' cross section correspond to the cross-sectional views of FIGS. 8A and 9A.
Although the gate insulating film is omitted in the top views of FIGS. 6 and 7, at least the island-shaped semiconductor layers 104 to
The gate electrodes 128 to 131 and the capacitance wiring 132
Are formed as shown in the figure.

When the activation and hydrogenation steps are completed,
A second conductive film serving as a gate wiring is formed. This second conductive film is made of a low-resistance material such as aluminum (Al), copper (Cu), silver (Ag), or an alloy (Ag-Pd-C).
u) as a main component, a conductive layer (D), titanium (Ti),
A conductive layer (E) made of tantalum (Ta), tungsten (W), or molybdenum (Mo) is preferably used. In this embodiment, titanium (Ti) is contained in an amount of 0.1 to 2% by weight.
The containing aluminum (Al) film was formed as the conductive layer (D) 145, and the titanium (Ti) film was formed as the conductive layer (E) 146. The conductive layer (D) 145 may have a thickness of 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (E) 146 may have a thickness of 50 to 200 (preferably 100 to 15 nm).
0 nm). (FIG. 4 (A))

Then, a gate wiring connected to the gate electrode
To form a conductive layer (E) 146 and a conductive layer (D) 1
45 to form gate wirings 147, 14
8 and the capacitor wiring 149 were formed. Etching first
To SiCl_FourAnd Cl_TwoAnd BCl _ThreeUsing a gas mixture with
Conductive layer from the surface of conductive layer (E) by light etching
(D) Removed partway, then phosphoric acid etching
The conductive layer (D) is removed by wet etching with a solution.
Gate wiring while maintaining selectivity with the base
Could be formed.

FIGS. 6B and 7B are top views in this state, and the AA ′ section and the CC ′ section are shown in FIG.
(B) corresponds to AA ′ and CC ′. Also,
The BB 'section and the DD' section are shown in FIGS.
(B) corresponds to BB ′ and DD ′. FIG.
7B and FIG. 7B, the gate wiring 147,
A part of the gate electrode 148 overlaps a part of the gate electrodes 128, 129, and 131 and is in electrical contact therewith. This situation is B-
8 (B) and 9 (B) corresponding to the B ′ section and the DD ′ section, the conductive layer (C) forming the first conductive layer and the second conductive layer. The conductive layer (D) forming the layer is in electrical contact.

The first interlayer insulating film 150 is 500 to 150
A contact hole is formed to a thickness of 0 nm with a silicon oxide film or a silicon oxynitride film, and then reaches a source region or a drain region formed in each of the island-shaped semiconductor layers. Wirings 155 to 158 are formed. Although not shown, in this embodiment, this electrode is formed by
Aluminum film containing i 300 nm, Ti film 150 nm
Was formed into a three-layer laminated film continuously formed by a sputtering method.

Next, as a passivation film 159,
A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is 50 to 500 nm (typically, 100 to 300 nm).
(nm). When hydrogenation was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics.
For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen or in a nitrogen atmosphere, or the same effect is obtained by using a plasma hydrogenation method. . Note that an opening may be formed in the passivation film 159 at a position where a contact hole for connecting a pixel electrode and a drain wiring is formed later. (FIG. 4 (C))

FIGS. 6C and 7C show top views in this state, and the AA 'section and CC' section are shown in FIG.
(C) corresponds to AA ′ and CC ′. Also,
The BB 'section and the DD' section are shown in FIGS.
(C) corresponds to BB ′ and DD ′. FIG.
In FIG. 7C and FIG. 7C, the first interlayer insulating film is omitted, but the source wiring 15 is formed in the not-shown source and drain regions of the island-shaped semiconductor layers 104, 105, and 107.
1, 152, 154 and drain wirings 155, 156, 1
Reference numeral 58 is connected through a contact hole formed in the first interlayer insulating film.

After that, a second interlayer insulating film 160 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used. Then, a contact hole reaching the drain wiring 158 is formed in the second interlayer insulating film 160, and pixel electrodes 161 and 162 are formed. For a pixel electrode, a transparent conductive film may be used for a transmission type liquid crystal display device, and a metal film may be used for a reflection type liquid crystal display device. In this embodiment, in order to obtain a transmission type liquid crystal display device,
An indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method. (Fig. 5)

Thus, the TFT of the driving circuit is formed on the same substrate.
And a substrate having pixel TFTs in the pixel portion. The driving circuit includes a p-channel TFT 201, a first n-channel TFT 202, and a second n-channel TFT
FT203, pixel TFT 204 in the pixel portion, storage capacitor 2
05 formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the p-channel TFT 201 of the driver circuit, the channel forming region 206, the source regions 207a and 207b, the drain regions 208a,
208b. First n-channel TFT 20
2 includes a channel formation region 20 in the island-shaped semiconductor layer 105.
9, an LDD region 210 overlapping the gate electrode 129 (hereinafter, such an LDD region is referred to as Lov), a source region 211, and a drain region 212. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. In the second n-channel TFT 203, the channel forming region 213, the LDD regions 214 and 215, the source region 2
16 and a drain region 217. The LDD region is formed with an Lov region and an LDD region that does not overlap with the gate electrode 130 (hereinafter, such an LDD region is referred to as Loff), and the length of the Loff region in the channel length direction is 0.3 to 2.0. 0 μm, preferably 0.5 to 1.5 μm. In the pixel TFT 204, channel formation regions 218 and 219 and Loff regions 220 to 2
23, a source or drain region 224 to 226. The length of the Loff region in the channel length direction is 0.5 to
It is 3.0 μm, preferably 1.5 to 2.5 μm. Further, a storage capacitor 205 is formed from the capacitor wirings 132 and 149, an insulating film made of the same material as the gate insulating film, and the semiconductor layer 227 connected to the drain region 226 of the pixel TFT 204 and doped with an n-type impurity element. Are formed. In FIG. 5, the pixel TFT 204 has a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

As described above, it is possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the driving circuit, and to improve the operation performance and reliability of the semiconductor device. it can. Further, the gate electrode is formed from a conductive material having heat resistance, thereby facilitating activation of the LDD region, the source region, and the drain region. By forming the gate wiring from a low-resistance material, the wiring resistance can be sufficiently reduced. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inch class or more.

[Embodiment 2] FIG. 16 is a diagram showing another example of the gate electrode and the gate wiring. The gate electrode and the gate wiring in FIG. 16 are formed in the same manner as in the steps described in Embodiment 1, and the island-shaped semiconductor layer 901 and the gate insulating film 902 are formed.
Is formed above.

In FIG. 16A, as a first conductive layer serving as a gate electrode, a conductive layer (A) 903 includes tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, and molybdenum nitride. (MoN).
The conductive layer (B) 904 is made of tantalum (Ta), titanium (T
i), an element selected from molybdenum (Mo), tungsten (W), an alloy containing the above elements as a main component, or an alloy film in which the above elements are combined, and formed on the surface in the same manner as in Example 1. A conductive layer (C) 905 is formed. The conductive layer (A) 903 has a thickness of 10 to 50 nm (preferably 20 to 3 nm).
0 nm), and the conductive layer (B) 904 has a thickness of 200 to 400 n.
m (preferably 250 to 350 nm). The second conductive layer serving as a gate wiring is a conductive layer (D) mainly composed of aluminum (Al) or copper (Cu), which is a low-resistance material, and titanium (Ti) or tantalum (Ta) thereon.
And a conductive layer (E) formed by lamination. Since aluminum (Al) and copper (Cu) are easily diffused by stress migration or electromigration, the silicon nitride film 90 is coated so as to cover the second conductive layer.
8 needs to be formed in a thickness of 50 to 150 nm.

FIG. 16B shows a gate electrode and a gate wiring manufactured in the same manner as in the first embodiment. A silicon film 909 doped with phosphorus (P) is formed under the gate electrode. The phosphorus (P) -doped silicon film 909 has an effect of preventing a trace amount of an alkali metal element contained in the gate electrode from diffusing into the gate insulating film, and is useful for securing the reliability of the TFT.

FIG. 16C shows a silicon film 910 doped with phosphorus (P) in a first conductive layer forming a gate electrode.
This is an example of forming with. The silicon film doped with phosphorus (P) has a higher resistance than other conductive metal materials, but the second conductive layer forming the gate wiring is formed of aluminum (Al), copper (Cu), silver ( By forming with Ag), it can be applied to a large-area liquid crystal display device.
Here, the gate wiring is made of a Ti film 911 of 100 nm,
300 n of aluminum (Al) film 912 containing Ti
By forming an aluminum (Al) film and a phosphorous (P) -doped silicon film directly out of contact with each other,
Heat resistance can be provided.

[Embodiment 3] FIG. 15 is a diagram for explaining the structure of a TFT according to the present invention. The channel formation region of the semiconductor layer, the LDD region, the gate insulating film on the semiconductor layer, and the gate insulating film In a TFT having an upper gate electrode,
The positional relationship between the gate electrode and the LDD region is described.

FIG. 15A shows a structure in which a semiconductor layer having a channel formation region 209, an LDD region 210, and a drain region 212, and a gate insulating film 120 and a gate electrode 129 thereon are provided. LDD region 2
Reference numeral 10 denotes Lov provided so as to overlap the gate electrode 129 with the gate insulating film 120 interposed therebetween. Lov has a function of alleviating a high electric field generated near the drain, can prevent deterioration due to hot carriers, and is suitable for use in an n-channel TFT such as a shift register circuit of a control circuit, a level shifter circuit, and a buffer circuit. I have.

FIG. 15B shows a structure in which a semiconductor layer having a channel formation region 213, LDD regions 215a and 215b, and a drain region 217, and a gate insulating film 120 and a gate electrode 130 are provided over the semiconductor layer. ing. The LDD region 215a is provided so as to overlap the gate electrode 130 via the gate insulating film 120. The LDD region 215b is Loff provided so as not to overlap with the gate electrode 130. Loff has an action of reducing the off-current value, and by providing Lov and Loff, the off-current value can be reduced while preventing deterioration due to hot carriers. It is suitable for use in a channel type TFT.

FIG. 15C shows that a channel formation region 219, an LDD region 223, and a drain region 226 are formed in a semiconductor layer.
Is provided. The LDD region 223 is the gate electrode 1
Loff is provided so as not to overlap with the pixel 31, and the off-current value can be effectively reduced.
Suitable for use in FT. The concentration of the impurity element imparting n-type in the LDD region 223 of the pixel TFT is １ ／ of the concentration of the LDD regions 210 and 215 of the driving circuit.
Is preferably reduced to 1/10.

[Embodiment 4] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 11, an alignment film 601 is formed on the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. A light-shielding film 603 and a transparent conductive film 6 are provided on the opposite substrate 602 on the opposite side.
04 and an alignment film 605 were formed. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the pixel portion, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. Thereafter, a liquid crystal material 606 was injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, FIG.
The active matrix type liquid crystal display device shown in FIG.

Next, the configuration of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 12 and the top view of FIG. 12 and 13 use the same reference numerals in order to correspond to the sectional structural views of FIGS. 1 to 5 and 11. The cross-sectional structure along EE ′ shown in FIG. 13 corresponds to the cross-sectional view of the pixel portion shown in FIG.

In FIG. 12, the active matrix substrate is a pixel portion 306 formed on the glass substrate 101.
, Scanning signal driving circuit 304 and image signal driving circuit 30
5 is comprised. A pixel TFT 204 is provided in the pixel portion, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The scanning signal driving circuit 304 and the image signal driving circuit 305 are connected to the pixel TFT 204 through a gate wiring 148 and a source wiring 154, respectively. Further, the FPC 731 is connected to the external input terminal 734, and is connected to each drive circuit through the input wirings 302 and 303.

FIG. 13 is a top view showing almost one pixel of the pixel section 306. FIG. The gate wiring 148 intersects the underlying semiconductor layer 107 via a gate insulating film (not shown). Although not shown, an Loff region including a source region, a drain region, and an n ⁻ region is formed in the semiconductor layer. 163 is a contact portion between the source wiring 154 and the source region 224, and 164 is a drain wiring 1
The contact portion 165 between the drain region 58 and the drain region 226 is a contact portion between the drain wiring 158 and the pixel electrode 161. The storage capacitor 205 is formed in a region where the capacitor wirings 132 and 149 overlap with the semiconductor layer 227 extending from the drain region 226 of the pixel TFT 204 via a gate insulating film.

Although the active matrix type liquid crystal display device of this embodiment has been described with reference to the structure described in the first embodiment, the active matrix type liquid crystal display device is manufactured by freely combining with the configuration of the second embodiment. can do.

[Embodiment 5] FIG. 10 is a diagram showing an example of an arrangement of input / output terminals, a pixel portion, and a driving circuit of a liquid crystal display device.
In the pixel portion 306, m gate wirings and n source wirings intersect in a matrix. For example, if the pixel density is V
In the case of GA, 480 gate lines and 640 source lines are formed, and in the case of XGA, 768 gate lines and 1024 source lines are formed. The screen size of the pixel part is 3 in the case of the 13-inch class.
40mm, 460m for 18 inch class
m. In order to realize such a liquid crystal display device, it is necessary to form the gate wiring with a low resistance material as shown in the first and second embodiments.

A scanning signal driving circuit 304 and an image signal driving circuit 305 are provided around the pixel portion 306. The length of the gate wiring of these driving circuits is inevitably increased with the increase in the screen size of the pixel portion. Therefore, in order to realize a large screen, a low-resistance material as described in the first and second embodiments is used. Preferably, it is formed.

Further, according to the present invention, the input wirings 302 and 303 connecting the input terminal 301 to each drive circuit can be formed of the same material as the gate wiring, which can contribute to lowering the wiring resistance.

[Embodiment 6] FIG. 14 is an example of the circuit configuration of the active matrix substrate shown in Embodiment 1 or 2, and is a diagram showing the circuit configuration of a direct-view display device. The active matrix substrate of this embodiment includes an image signal driving circuit 1001, a scanning signal driving circuit (A) 1007,
Scan signal drive circuit (B) 1011, precharge circuit 1
012 and a pixel portion 1006. Note that the driving circuit described in this specification is an image signal driving circuit 100.
1. General term including the scanning signal drive circuit (A) 1007.

The image signal driving circuit 1001 includes a shift register circuit 1002, a level shifter circuit 1003, a buffer circuit 1004, and a sampling circuit 1005. The scan signal driver circuit (A) 1007 includes a shift register circuit 1008, a level shifter circuit 1009, and a buffer circuit 1010. The scanning signal driving circuit (B) 1011 has a similar configuration.

The shift register circuits 1002 and 1008 have a driving voltage of 5 to 16 V (typically 10 V), and the n-channel TFT of the CMOS circuit forming this circuit has a structure shown by 202 in FIG. I have. Also, the level shifter circuits 1003 and 1009 and the buffer circuit 100
For 4,1010, the driving voltage is as high as 14 to 16 V,
Similarly to the shift register circuit, the n-channel type TF shown in FIG.
CMOS circuits including T202 are suitable. In these circuits, forming the gate in a multi-gate structure increases the withstand voltage, which is effective in improving the reliability of the circuit.

When the driving voltage is 1
The voltage is 4 to 16 V. However, since the polarity is alternately inverted and the off-state current value needs to be reduced, n in FIG.
A CMOS circuit including the channel type TFT 203 is suitable. In FIG. 5, only an n-channel TFT is shown, but in an actual sampling circuit, a p-channel TFT is also formed. At this time, the structure shown in FIG. 201 is sufficient for the p-channel TFT.

Further, the pixel TFT 204 has a drive voltage of 14
To 16 V, which is required to further reduce the off-current value compared to the sampling circuit from the viewpoint of low power consumption, and an LDD (Loff) region provided so as not to overlap the gate electrode as in the pixel TFT 204. It is desirable to have a structure having

The structure of this embodiment can be easily realized by manufacturing a TFT according to the steps shown in the first embodiment. In the present embodiment, only the configuration of the pixel portion and the drive circuit is shown. Further, a signal processing circuit such as a memory circuit or an arithmetic processing circuit, or a logic circuit can be formed over the same substrate. in this way,
The present invention can realize a semiconductor device including a pixel portion and a driver circuit over the same substrate, for example, a semiconductor device including a signal driver circuit and a pixel portion.

[Embodiment 7] FIG. 17 shows an example of various wiring structures formed on an insulating surface by using the present invention. FIG. 17A shows a film (or substrate) 17 having an insulating surface.
A cross-sectional view of a wiring having a single-layer structure made of a material 1701 containing tungsten as a main component is shown on the top of FIG. This wiring is formed by patterning a film formed using a target having a purity of 6N as a target and using a single gas of argon (Ar) as a sputtering gas. The substrate temperature was set to 300 ° C. or lower, and the pressure of the sputtering gas was set to 1.
The stress is controlled at 0 Pa to 3.0 Pa, and other conditions (such as sputter power) may be appropriately determined by the practitioner.

The wiring 1701 thus obtained contains argon in the wiring material, but hardly contains other impurity elements.
0.3 ppm or less, preferably 0.1 ppm or less, and the oxygen concentration can be 1 wt% or less, preferably 0.2 wt% or less, and the electric resistivity is 40 μΩ · cm or less.
Preferably not more than 20 μΩ · cm, typically 6 μΩ · cm.
cm to 15 μΩ · cm. Further, the stress of the film can be controlled within a range of −5 × 10 ^{10 to} 5 × 10 ¹⁰ dyn / cm ² . Further, the electrical resistivity does not change even if the heat treatment is performed at 800 ° C.

FIG. 17B shows a two-layer structure. Note that tungsten nitride (WNx) is used as a lower layer, and tungsten is used as an upper layer. Note that the tungsten nitride film 1702 has a thickness of 10 to 50 nm (preferably 10 to 30 n
m), and the thickness of the tungsten film 1703 is 200 to 400 n.
m (preferably 250 to 350 nm). In this embodiment, the layers are continuously formed by a sputtering method without exposure to the air.

FIG. 17C shows that a wiring 1704 made of a material containing tungsten as a main component and formed on a film (or substrate) 1700 having an insulating surface is formed on the insulating film 17.
It is an example covered with 05. The insulating film 1705 is a silicon nitride film,
Silicon oxide film, silicon oxynitride film SiOxNy (where 0 <
x, y <1) or a laminated film combining them may be used.

FIG. 17D shows an example in which the surface of a wiring 1706 formed of a material containing tungsten as a main component and formed on a film (or substrate) 1700 having an insulating surface is covered with a tungsten nitride film 1707. is there. FIG.
When the wiring in the state of FIG. 7A is subjected to nitriding treatment such as plasma nitridation, the structure of FIG. 17D is obtained.

FIG. 17E shows an example in which a wiring 1709 formed of a material containing tungsten as a main component and formed on a film (or substrate) 1700 having an insulating surface is surrounded by tungsten nitride films 1710 and 1708. is there. This structure has the same shape as that shown in the third embodiment. In addition,
When the wiring in the state of FIG. 17B is subjected to nitriding treatment such as plasma nitridation, the structure of FIG. 17E is obtained.

FIG. 17F shows an example in which the state shown in FIG. 17E is formed and then covered with an insulating film 1711. The insulating film 1711 may be formed using a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a stacked film including a combination thereof.

As described above, the present invention can be applied to various wiring structures. The configuration of this embodiment is the same as that of the first to sixth embodiments.
Can be freely combined with any of the configurations shown in FIG.

[Embodiment 8] In this embodiment, in an active matrix type liquid crystal display device having a diagonal width of 1 inch or less, a second interlayer insulating film is provided in a region where a gate line and an upper layer line overlap each other, and a parasitic capacitance is provided. The structure of an active matrix substrate in which is reduced is shown with reference to FIGS. In addition,
The basic structure is disclosed in Japanese Patent Application No. 11-1544 filed by the present applicant.
The structure is the same as that described in the No. 32 application.

As shown in FIG. 18, in this embodiment, in order to improve the aperture ratio, part or all of the gate electrode overlapping the channel formation region of the n-channel TFT 1804 constituting the pixel TFT and the second wiring (source). (A line or a drain line) 1854 and 1857. A first interlayer insulating film 1849 and a second interlayer insulating film 1850c are provided between the gate electrode and the second wirings 1854 and 1857.
To reduce the parasitic capacitance. The gate electrode and the second
The second interlayer insulating film 185 is selectively formed only in the region where the wiring overlaps.
0c is provided.

In FIG. 18, reference numeral 1859 denotes a third interlayer insulating film, 1860 denotes a light shielding film, and 1861 denotes a light shielding film 18.
60 is an oxide formed by anodic oxidation or plasma oxidation (in this embodiment, anodic oxidation). Reference numeral 1862 denotes a pixel electrode made of an indium tin oxide (ITO) film. Note that the pixel electrode 1863 is a pixel electrode of another adjacent pixel.

Further, the pixel electrode 1862 and the light shielding film 1860
Overlap with each other via the anodic oxide 1861 to form a storage capacity (capacity striation) 1864. The light shielding film 1
860 in floating state (electrically isolated state)
Or a fixed potential, preferably a common potential (intermediate potential of an image signal sent as data).

FIG. 19B shows a part of a top view of the pixel portion immediately after the formation of the second wiring (source line or drain line) 1854 and 1857 using common reference numerals. Also,
FIG. 19A is a top view immediately after the formation of the gate wiring.

A p-channel TFT 1801, an n-channel TFT 1802, and an n-channel TFT 1803
In a driver circuit including a semiconductor device and the like, a second interlayer insulating film 1850b may be selectively formed in a region where a gate wiring provided over an insulating film 1815 and a second wiring 1851 intersect and overlap. Note that FIG. 20B illustrates a top view of a driver circuit corresponding to FIG. 18 using common reference numerals. FIG. 20A is a top view immediately after the formation of the gate wiring.

The TFTs 1801 to 1801 shown in FIG.
The gate wiring 1804 is a tungsten nitride film 1702
A stacked structure of a tungsten film 1703 was employed. Since this gate wiring uses the sputtering method described in the embodiment mode,
The content of sodium in the wiring is 0.3 ppm or less, preferably 0.1 ppm or less, and the oxygen concentration is 1 wt.
%, Preferably 0.2 wt% or less, and the electrical resistivity could be 6 μm to 15 μΩ · cm.
The stress of the film is -1 × 10 ¹⁰ to 1 × 10 ¹⁰ dyn /
It could be controlled in the range of cm ² .

As described above, by using the sputtering method described in the embodiment mode, a wiring having low resistance and high reliability can be obtained, and the operation performance and reliability of the TFT can be greatly improved. .

[Embodiment 9] In this embodiment, a case where the present invention is applied to a reflection type liquid crystal display device manufactured on a silicon substrate will be described. This embodiment is different from the first embodiment in that
Instead of the active layer made of a crystalline silicon film, an n-type or p-type impurity element may be directly added to a silicon substrate (silicon wafer) to realize a TFT structure. In addition, since the pixel electrode is a reflection type, a metal film having high reflectance (for example, aluminum, silver, or an alloy thereof (Al-Ag alloy)) or the like may be used as a pixel electrode.

The structure of this embodiment can be freely combined with any of the structures of the first to eighth embodiments.

[Embodiment 10] The present invention relates to a conventional MOSFE.
It is also possible to form an interlayer insulating film on T and use it when forming a TFT thereon. That is, it is possible to realize a semiconductor device having a three-dimensional structure. It is also possible to use an SOI substrate such as SIMOX, Smart-Cut (registered trademark of SOITEC), or ELTRAN (registered trademark of Canon Inc.) as the substrate.

The structure of this embodiment can be freely combined with any of the structures of the first to ninth embodiments.

[Embodiment 11] The present invention can also be applied to an active matrix EL display.
An example is shown in FIG.

FIG. 21 is a circuit diagram of an active matrix type EL display. Reference numeral 11 denotes a pixel portion,
An X-direction drive circuit 12 and a Y-direction drive circuit 13
Is provided. Each pixel of the pixel section 11 includes a switching TFT 14, a storage capacitor 15, and a current controlling TFT1.
6, an organic EL element 17, and an X-direction signal line 18a (or 18b) and a Y-direction signal line 19
a (or 19b, 19c) are connected. The power supply lines 20a and 20b are connected to the current control TFT 16.

In the active matrix EL display of this embodiment, the TFTs used in the X-direction drive circuit 12 and the Y-direction drive circuit 13 are the p-channel TFTs 2 shown in FIG.
01 and an n-channel TFT 202 or 203 in combination. Further, the TFT of the switching TFT 14 and the TFT of the current control TFT 16 are replaced with the n-channel TFT 2 shown in FIG.
04.

The structure of this embodiment is similar to those of the first to tenth embodiments.
Any configuration can be freely combined.

[Embodiment 12] A liquid crystal display device manufactured according to the present invention can use various liquid crystal materials. Such materials include TN liquid crystal, PDLC (polymer dispersed liquid crystal), FLC (ferroelectric liquid crystal), AFLC
(An anti-strongly inducing electro-liquid crystal), or a mixture of FLC and AFLC.

For example, “H. Furue et al .; Charakteristi
cs and Drivng Scheme of Polymer-Stabilized Monosta
ble FLCD Exhibiting Fast Response Time and High Co
ntrast Ratio with Gray-Scale Capability, SID, 199
8 "," T. Yoshida et al .; A Full-Color Thresholdless "
Antiferroelectric LCD Exhibiting Wide Viewing Ang
le with Fast Response Time, 841, SID97DIGEST, 199
7 ", or the materials disclosed in US Pat. No. 5,594,569.

In particular, a thresholdless (non-threshold) antiferroelectric liquid crystal (Thresholdless Antiferroelectric LCD:
TL-AFLC) can be used to reduce the operating voltage of the liquid crystal to about ± 2.5 V.
In some cases, about 8 V may be enough. That is, the driver circuit and the pixel portion can be operated at the same power supply voltage, and the power consumption of the entire liquid crystal display device can be reduced.

Some thresholdless antiferroelectric liquid crystals exhibit V-shaped electro-optical response characteristics, and those having a driving voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) are also available. Have been found.

Here, the characteristics of the light transmittance with respect to the applied voltage of the thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optical response are shown in FIG. The vertical axis of the graph shown in FIG. 22 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. The transmission axis of the polarizing plate on the incident side of the liquid crystal panel is set substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal which substantially matches the rubbing direction of the liquid crystal panel. The transmission axis of the exit-side polarizing plate is set to be substantially perpendicular (crossed Nicols) to the transmission axis of the incidence-side polarizing plate.

Further, ferroelectric liquid crystals and antiferroelectric liquid crystals are
There is an advantage that the response speed is faster than that of the N liquid crystal. Since the crystalline TFT used in the above embodiment can realize a TFT having a very high operation speed, a high image response speed utilizing the high response speed of the ferroelectric liquid crystal or the antiferroelectric liquid crystal can be realized. It is possible to realize a liquid crystal display device.

It is needless to say that it is effective to use the liquid crystal display device of this embodiment as a display for electronic equipment such as a personal computer.

The configuration of the present embodiment is similar to those of the first to tenth embodiments.
Any configuration can be freely combined.

[Embodiment 13] The TFT formed by carrying out the present invention can be used for various electro-optical devices.
That is, the present invention can be applied to all electronic apparatuses in which these electro-optical devices are incorporated as display units.

Such electronic devices include a video camera, a digital camera, a head-mounted display (goggle type display), a wearable display,
Examples include a car navigation system, a personal computer, and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). One example of them is shown in FIG.

FIG. 23A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal driving circuits.

FIG. 23B shows a video camera, which includes a main body 2101, a display section 2102, an audio input section 2103, operation switches 2104, a battery 2105, and an image receiving section 210.
6. The present invention can be applied to the display portion 2102, the audio input portion 2103, and other signal driving circuits.

FIG. 23C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display section 2205. The invention of the present application is a display unit 2205.
And other signal drive circuits.

FIG. 23D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 The present invention can be applied to the display portion 2302 and other signal driver circuits.

FIG. 23E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Dig) as a recording medium.
Tear Versatile Disc), CD, etc., can be used to enjoy music, movies, games and the Internet. The present invention can be applied to the display portion 2402 and other signal driver circuits.

FIG. 23F shows a digital camera, which comprises a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, and an image receiving section (not shown).
The present invention can be applied to the display portion 2502 and other signal driver circuits.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the embodiments 1 to 12.

[Embodiment 14] A TFT formed by carrying out the present invention can be used for various electro-optical devices.
That is, the present invention can be applied to all electronic apparatuses in which these electro-optical devices are incorporated as display units.

As such an electronic device, there is a projector (rear type or front type). One example of them is shown in FIG.

FIG. 24A shows a front type projector, which comprises a display 2601 and a screen 2602. The present invention can be applied to a display device and other signal driving circuits.

FIG. 24B shows a rear type projector, which includes a main body 2701, a display device 2702, and a mirror 270.
3. It comprises a screen 2704. The present invention can be applied to a display device and other signal driving circuits.

FIG. 24C is a diagram showing an example of the structure of the display devices 2601 and 2702 in FIGS. 24A and 24B. Display devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 24D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 24D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of this embodiment can be realized by using any combination of the embodiments 1 to 8 and the twelfth embodiment.

[Embodiment 15] The present invention is not limited to the TFT structure, but can be used for gate wiring, source wiring and drain wiring of various TFT structures. In this embodiment, an example in which the present invention is used for a gate wiring of an inversely staggered TFT will be described.

FIG. 32 shows an example of an inverted stagger type TFT. 32, reference numeral 1901 denotes a substrate, 1902 denotes a gate electrode, 1903a and 1903b denote gate insulating films,
Reference numeral 1904 denotes a channel formation region, 1905 and 1906 denote high-concentration impurity regions (source or drain regions), 1
907 and 1908 are low concentration impurity regions (LDD regions),
Reference numeral 1909 denotes an insulating layer for protecting a channel formation region;
0 is an interlayer insulating film, and 1911 and 1912 are electrodes (source electrodes or drain electrodes) connected to the high-concentration impurity regions.

As a means for forming the gate electrode 1902, a conductive film having a thickness in the range of 10 to 1000 nm, preferably 30 to 300 nm is formed by the sputtering method of the present invention, and then formed by a known patterning technique.

In addition, a gate insulating film 1903 having a laminated structure
a, 1903b. Lower gate insulating film 1903
As a, a silicon nitride film or the like for effectively preventing diffusion of impurities from the substrate or the gate wiring is formed to a thickness of 10 nm to 60 nm.
It was formed in a thickness range of nm. However, it is not limited to a laminated structure and may be a single layer.

Although an n-channel TFT using phosphorus as an impurity element for imparting n-type to a semiconductor was manufactured here, boron was used as an impurity element for imparting p-type instead of the impurity element for imparting n-type. If used, p-channel type T
An FT can be made. Although an example in which a low-concentration impurity region is provided is shown here, the low-concentration impurity region may be omitted if there is no problem in the reliability of the TFT.

Further, not only the gate electrode but also the electrode 191
1, 1912, a film using the sputtering method of the present invention may be used.

A driver circuit and a pixel portion can be formed using a basic logic circuit using such a TFT.

This embodiment can be freely combined with any one of Embodiments 1 to 12.

[0170]

According to the present invention, the amount of sodium contained in wiring is 0.03 ppm or less, preferably 0.01% or less.
ppm or less and low electric resistivity (40 μΩ ·
cm or less) and a stress of −5 × 10 ¹⁰ dyn / cm ²
~ 5 × 10 ¹⁰ dyn / cm ² , preferably -2 × 10 ¹⁰
dyn / cm ^{2 to} 2 × 10 ¹⁰ dyn / cm ² , more preferably −1 × 10 ¹⁰ dyn / cm ² to 1 × 10 ¹⁰ dyn
/ Cm ² can be formed.

The wiring of the present invention has a low electric resistivity (40 μΩ · cm or less) even when subjected to a heat treatment at about 800 ° C.
Can be maintained.

In addition, by forming tungsten nitride on the surface of a wiring containing tungsten as a main component, a wiring having low resistance and high reliability can be obtained, and a semiconductor device (specifically, an electro-optical device here) can be obtained. Operating performance and reliability can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 5 is a cross-sectional view of a pixel TFT, a storage capacitor, and a TFT of a driving circuit.

FIG. 6 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 7 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 8 is a top view illustrating a manufacturing process of a TFT of a driver circuit.

FIG. 9 is a top view illustrating a manufacturing process of a pixel TFT.

FIG. 10 is a top view illustrating input / output terminals and a wiring circuit arrangement of a liquid crystal display device.

FIG. 11 is a cross-sectional view illustrating a structure of a liquid crystal display device.

FIG. 12 is a perspective view illustrating a structure of a liquid crystal display device.

FIG. 13 is a top view illustrating pixels in a pixel portion.

FIG. 14 is a circuit block diagram of a liquid crystal display device.

FIG. 15 is a diagram showing a positional relationship between a gate electrode and an LDD region.

FIG. 16 illustrates a connection between a gate electrode and a gate wiring.

FIG. 17 is a cross-sectional view illustrating a wiring structure.

FIG. 18 shows a pixel TFT, a storage capacitor, and a TFT of a driving circuit.
FIG.

FIG. 19 is a part of a top view of a pixel TFT.

FIG. 20 is a top view of a TFT of a driver circuit.

FIG. 21 illustrates a structure of an active matrix EL display device.

FIG. 22 is a graph showing characteristics of light transmittance with respect to an applied voltage of a thresholdless antiferroelectric mixed liquid crystal.

FIG. 23 illustrates an example of an electronic device.

FIG. 24 illustrates an example of an electronic device.

FIG. 25 is a diagram showing the results of GDMS analysis.

FIG. 26 is a diagram showing a relationship between a sputtering pressure and a stress.

FIG. 27 is a diagram showing a relationship between sputtering pressure and electric resistivity.

FIG. 28 is an explanatory diagram of tensile stress and compressive stress.

FIG. 29 is a diagram showing a contact chain for measuring a contact resistance.

FIG. 30 is a diagram showing a relationship between sputtering power and stress.

FIG. 31 is a diagram showing a relationship between sputtering power and electric resistivity.

FIG. 32 is a cross-sectional view of a TFT.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/285 H04N 5/66 102A 5F033 301 H01L 21/88 M 5F040 29/78 G02F 1/136 500 5F110 29 / 786 H01L 29/78 301G H04N 5/66 102 617M F term (reference) 2H092 HA06 HA12 JA24 JA26 JB64 KB04 MA05 MA08 MA25 NA28 PA02 PA06 RA05 RA10 4K029 BA02 BA21 BA58 BB02 BC03 BD01 CA05 DC03 DC04 4M104 BB01 BB02 BB27 BB28 BB30 BB31 BB32 BB33 BB39 BB40 CC05 DD16 DD17 DD26 DD40 DD41 DD65 DD79 DD80 EE06 EE12 EE17 EE18 FF06 FF13 FF18 FF22 GG09 GG10 GG19 DA20 GG19 HA08 HA10 5F033 GG04 HH04 HH08 HH09 HH11 HH14 HH17 HH18 HH1 9 HH20 HH21 HH22 HH23 HH26 HH27 HH28 HH29 HH30 HH32 HH33 HH34 HH35 JJ01 JJ09 JJ18 KK01 MM05 MM08 MM11 MM12 PP15 QQ08 QQ09 QQ10 QQ11 QQ19 QQ37 QQ73 QQ02 XXVRR RR06 RR04 XXV XX28 XX34 5F040 DA26 DB03 EB13 EC04 EC07 EC08 EJ03 5F110 AA03 AA26 BB02 BB04 CC02 CC08 DD02 DD03 DD13 DD14 DD15 DD17 DD25 EE01 EE02 EE03 EE04 EE05 EE06 EE09 EE14 EE28 EE36 FF02 GG03 FF02 GG03 FF02 GG02 FF02 GG02 FF02 GG03 FF02 GG02 FF02 FF02 GG02 FF02 FF02 GG02 GG45 GG51 HJ01 HJ04 HJ12 HJ23

Claims (25)

[Claims] A wiring material containing tungsten or a tungsten compound as a main component, wherein said wiring material contains 90% or more of argon as an inert element, and said wiring material has a sodium content of 0.1%. A wiring material having a content of 3 ppm or less. 2. The method according to claim 1, wherein the tungsten compound is one kind of element selected from Ta, Ti, Mo, Cr, Nb, and Si, or a compound of plural kinds of elements and tungsten. Wiring material to be used. 3. The wiring material according to claim 1, wherein the wiring material has an electric resistivity of 40 μΩ · cm or less. 4. W, Ta, Ti, Mo, Cr, Nb, Si
A metal film containing one kind of element selected from or a plurality of kinds of elements, a metal compound film containing the above element as a main component, an alloy film combining the above elements, or the above metal film, a metal compound film or an alloy film. A wiring made of a laminated film obtained by laminating the obtained thin films, wherein the wiring contains 90% or more of argon as an inert element in the wiring, and the content of sodium in the wiring is 0.3 ppm or less. A semiconductor device characterized by the above-mentioned. 5. A semiconductor device provided with a wiring including a film containing tungsten or a tungsten compound as a main component, wherein the wiring includes argon as an inert element in the wiring.
A semiconductor device containing 0% or more, and the content of sodium in the wiring is 0.3 ppm or less. 6. A semiconductor device provided with a wiring having a laminated structure including a film containing tungsten or a tungsten compound as a main component and a nitride film of tungsten, wherein the wiring is an inert element in the wiring. A semiconductor device comprising 90% or more of argon and having a sodium content of 0.3 ppm or less in the wiring. 7. A semiconductor device having a wiring having a stacked structure including a silicon film to which an impurity element imparting a conductivity type is added, a film containing tungsten or a tungsten compound as a main component, and a tungsten nitride film. Wherein the wiring contains 90% or more of argon as an inert element in the wiring, and the content of sodium in the wiring is 0.3 ppm or less. 8. The semiconductor device according to claim 4, wherein said wiring is formed by a sputtering method using argon as a sputtering gas. 9. The method according to claim 4, wherein the inert element other than argon contained in the wiring is 1a.
semiconductor device characterized by being at most toms%. 10. The method according to claim 4, wherein
Inactive elements other than argon contained in the wiring,
A semiconductor device characterized by being 0.1 atom% or less. 11. The semiconductor device according to claim 9, wherein said inert element other than argon is Xe or Kr. 12. The film according to claim 5, wherein an internal stress of the film containing tungsten or a tungsten compound as a main component is −1 × 10 ¹⁰ dyn / cm ^2.
Wherein a is ^{~1 × 10 1 0 dyn / cm} 2. 13. The semiconductor device according to claim 4, wherein a line width of said wiring is 5 μm or less. 14. The semiconductor device according to claim 4, wherein the thickness of the wiring is 0.1 μm or more and 0.7 μm or less. 15. The semiconductor device according to claim 4, wherein said wiring is used as a gate wiring of a TFT. 16. A contact area between the wiring and the aluminum wiring according to any one of claims 4 to 15, wherein the contact area is 1 μm square.
A semiconductor device provided with a wiring, wherein a resistance value per unit is 40Ω or less. 17. A semiconductor device according to claim 4, wherein the semiconductor device is an active matrix type liquid crystal display, an active matrix type EL display or an active matrix type EC display. 18. The semiconductor device according to claim 4, wherein the semiconductor device is a video camera, a digital camera, a projector, a goggle type display, a car navigation, a personal computer, or a personal digital assistant. 19. A method for manufacturing a semiconductor device including at least wiring on an insulating surface, wherein the wiring is formed by a step of forming a tungsten film by a sputtering method and a step of patterning the tungsten film. Of manufacturing a semiconductor device. 20. The method for manufacturing a semiconductor device according to claim 19, wherein the sputtering method uses a tungsten target having a purity of 4N or more. 21. The method for manufacturing a semiconductor device according to claim 19, wherein the sputtering method uses a tungsten alloy target having a purity of 4N or more. 22. The method for manufacturing a semiconductor device according to claim 19, wherein the sputtering method is a sputtering method using only argon as a sputtering gas. 23. The method for manufacturing a semiconductor device according to claim 19, wherein the sputtering method comprises setting the substrate temperature to 300 ° C. or lower. 24. The sputtering method according to claim 19, wherein the gas pressure is 0.1 Pa to 3.0 P.
a, a method for manufacturing a semiconductor device. 25. The sputtering method according to claim 19, wherein the gas pressure is 1.0 Pa to 2.0 P.
a, a method for manufacturing a semiconductor device.