JP2002083812A5 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2002083812A5
JP2002083812A5 JP2000194104A JP2000194104A JP2002083812A5 JP 2002083812 A5 JP2002083812 A5 JP 2002083812A5 JP 2000194104 A JP2000194104 A JP 2000194104A JP 2000194104 A JP2000194104 A JP 2000194104A JP 2002083812 A5 JP2002083812 A5 JP 2002083812A5
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JP
Japan
Prior art keywords
wiring
film
semiconductor device
dyn
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Prior art date
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Application number
JP2000194104A
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Japanese (ja)
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JP2002083812A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2000194104A priority Critical patent/JP2002083812A/en
Priority claimed from JP2000194104A external-priority patent/JP2002083812A/en
Priority to US09/604,997 priority patent/US6661096B1/en
Publication of JP2002083812A publication Critical patent/JP2002083812A/en
Priority to US10/672,521 priority patent/US7226822B2/en
Priority to US11/786,880 priority patent/US7816191B2/en
Publication of JP2002083812A5 publication Critical patent/JP2002083812A5/en
Withdrawn legal-status Critical Current

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Description

【特許請求の範囲】
【請求項1】
Ta、Ti、Mo、Cr、Nb、Siから選ばれた一種の元素、または複数種の元素とタングステンとの化合物を主成分とする膜を有する配線を備え
前記配線はアルゴンを含
記配線に含まれるナトリウムの含有量は0.3ppm以下であることを特徴とする半導体装置。
【請求項2】
Ta、Ti、Mo、Cr、Nb、Siから選ばれた一種の元素、または複数種の元素とタングステンとの化合物を主成分とする膜と、タングステンの窒化物膜とを含む積層構造を有する配線を備え
前記配線はアルゴンを含
記配線に含まれるナトリウムの含有量は0.3ppm以下であることを特徴とする半導体装置。
【請求項3】
導電型を付与する不純物元素が添加されたシリコン膜と、
Ta、Ti、Mo、Cr、Nb、Siから選ばれた一種の元素、または複数種の元素とタングステンとの化合物を主成分とする膜と、タングステンの窒化物膜とを含む積層構造を有する配線と、を備え、
前記配線はアルゴンを含
記配線に含まれるナトリウムの含有量は0.3ppm以下であることを特徴とする半導体装置。
【請求項4】
請求項3において、
前記シリコン膜を介して、前記配線の下にゲート絶縁膜を有することを特徴とする半導体装置。
【請求項5】
請求項乃至請求項4のいずれか一において、
前記Ta、Ti、Mo、Cr、Nb、Siから選ばれた一種の元素、または複数種の元素とタングステンとの化合物を主成分とする膜の内部応力は、−×1010dyn/cm×1010dyn/cmであることを特徴とする半導体装置。
【請求項6】
W、Ta、Ti、Mo、Cr、Nb、Siから選ばれた一種の元素、または複数種の元素を含む金属膜、前記元素を主成分とする金属化合物膜、前記元素を組み合わせた合金膜、もしくは前記金属膜、金属化合物膜または合金膜から選ばれた薄膜を積層した積層膜からなる配線を備え、
前記配線はアルゴンを含
記配線に含まれるナトリウムの含有量は0.3ppm以下であることを特徴とする半導体装置。
【請求項7】
請求項1乃至請求項6のいずれか一項において、
前記配線に含まれるアルゴンは、前記配線に含まれる不活性元素の90%以上であることを特徴とする半導体装置。
【請求項8】
請求項乃至請求項7のいずれか一項において、
前記配線TFTのゲート配線を含むことを特徴とする半導体装置。
【請求項9】
請求項1乃至請求項2および請求項5乃至請求項8のいずれか一項において、
前記TFTは、ゲート絶縁膜を介して前記ゲート配線上に設けられた半導体膜を有することを特徴とする半導体装置。
【請求項10】
請求項1乃至請求項8のいずれか一項において、
前記ゲート配線上に設けられた第1の絶縁膜と、
前記第1の絶縁膜上であって、前記ゲート配線の一部または全部と、ソース線またはドレイン線とが重なる領域に設けられた第2の絶縁膜と、を有することを特徴とする半導体装置。
【請求項11】
請求項乃至請求項10のいずれか一において、
前記配線に含まれるアルゴン以外の不活性元素は、1atoms%以下であることを特徴とする半導体装置。
【請求項12】
請求項乃至請求項11のいずれか一において、
前記配線に含まれるアルゴン以外の不活性元素は、0.1atoms%以下であることを特徴とする半導体装置。
【請求項13】
請求項11または請求項12において、
前記アルゴン以外の不活性元素は、XeまたはKrであることを特徴とする半導体装置。
【請求項14】
請求項乃至請求項13のいずれか一において、
前記配線の線幅は5μm以下であることを特徴とする半導体装置。
【請求項15】
請求項乃至請求項14のいずれか一において、
前記配線の膜厚は0.1μm0.7μmであることを特徴とする半導体装置。
【請求項16】
請求項乃至請求項15のいずれか一において、
前記配線との接触面積1μm あたりの抵抗値40Ω以下であるアルミニウム配線を有することを特徴とする半導体装置。
【請求項17】
請求項乃至請求項16に記載された半導体装置は、アクティブマトリクス型液晶ディスプレイ、アクティブマトリクス型ELディスプレイまたはアクティブマトリクス型ECディスプレイであることを特徴とする半導体装置。
【請求項18】
請求項乃至請求項17に記載された半導体装置は、ビデオカメラ、デジタルカメラ、プロジェクター、ゴーグル型ディスプレイ、カーナビゲーション、パーソナルコンピュータ、または携帯情報端末であることを特徴とする半導体装置。
[Claims]
(1)
A wiring having a film mainly containing one kind of element selected from Ta, Ti, Mo, Cr, Nb, and Si, or a compound of plural kinds of elements and tungsten ,
The wiring is seen including a an argon,
Wherein a pre-Symbol content of sodium contained in the wiring is less than 0.3 ppm.
(2)
Wiring having a laminated structure including a film mainly composed of one element selected from Ta, Ti, Mo, Cr, Nb, and Si, or a compound of plural kinds of elements and tungsten, and a tungsten nitride film. equipped with a,
The wiring is seen including a an argon,
Wherein a pre-Symbol content of sodium contained in the wiring is less than 0.3 ppm.
(3)
A silicon film to which an impurity element imparting a conductivity type is added,
Wiring having a laminated structure including a film mainly composed of one element selected from Ta, Ti, Mo, Cr, Nb, and Si, or a compound of plural kinds of elements and tungsten, and a tungsten nitride film. And
The wiring is seen including a an argon,
Wherein a pre-Symbol content of sodium contained in the wiring is less than 0.3 ppm.
(4)
In claim 3,
A semiconductor device having a gate insulating film under the wiring via the silicon film.
(5)
In any one of claims 1 to 4,
The Ta, Ti, Mo, Cr, Nb, element one selected from Si or more elements and the internal stress of the film composed mainly of compounds of tungsten, may, - 5 × 10 10 dyn / cm 2 A semiconductor device characterized by having a density of 5 × 10 10 dyn / cm 2 .
6.
A metal film containing one kind of element selected from W, Ta, Ti, Mo, Cr, Nb, and Si, or a plurality of kinds of elements, a metal compound film containing the above elements as a main component, an alloy film combining the above elements, Or, the metal film, a metal compound film or an alloy film comprising a wiring formed of a laminated film laminated thin film selected from an alloy film
The wiring is seen including a an argon,
Wherein a pre content of sodium contained in the Sharing, ABS line is less than 0.3 ppm.
7.
In any one of claims 1 to 6,
A semiconductor device, wherein argon contained in the wiring is 90% or more of an inert element contained in the wiring.
Claim 8.
In any one of claims 1 to 7,
The semiconductor device, wherein the wiring includes a gate wiring of a TFT.
9.
In any one of claims 1 to 2 and claims 5 to 8,
A semiconductor device, wherein the TFT has a semiconductor film provided on the gate wiring with a gate insulating film interposed therebetween.
10.
In any one of claims 1 to 8,
A first insulating film provided on the gate wiring;
A semiconductor device provided on the first insulating film, a second insulating film provided in a region where part or all of the gate wiring overlaps with a source line or a drain line. .
11.
In any one of claims 1 to 10,
Inert element other than argon contained in the distribution line, wherein a is less 1atoms%.
12.
In any one of claims 1 to 11,
Inert element other than argon contained in the distribution line, wherein a is less 0.1atoms%.
Claim 13
In Claim 11 or Claim 12 ,
A semiconductor device, wherein the inert element other than argon is Xe or Kr.
14.
In any one of claims 1 to 13,
The semiconductor device according to claim 1, wherein a line width of the wiring is 5 μm or less.
15.
In any one of claims 1 to 14,
Wherein a thickness of the wiring is 0.1μm ~ 0.7μ m.
16.
In any one of claims 1 to 15,
The resistance per contact area 1 [mu] m 2 of the wiring is you characterized by having an aluminum wiring is not more than 40Ω semiconductors devices.
17.
Semiconductor equipment according to claim 1 to claim 16, wherein a active matrix type liquid crystal display, an active matrix type EL display or active matrix type EC display.
18.
Semiconductor equipment according to claim 1 to claim 17, a video camera, a digital camera, a projector, a goggle type display, a car navigation, a semiconductor device which is a personal computer or a portable information terminal.

本発明は、膜中に含まれるナトリウムが0.3ppm以下であり、且つ、熱処理後も低い電気抵抗率(40μΩ・cm以下)を有し、応力が−5×1010dyn/cm〜5×1010dyn/cm、好ましくは−1×1010dyn/cm〜1×1010dyn/cmに制御されたタングステン膜をTFTのゲート配線材料やその他の配線材料として用いることにより、TFTを備えた半導体装置の動作性能や信頼性を大幅に向上させることができる。 In the present invention, sodium contained in the film is 0.3 ppm or less, and has a low electric resistivity (40 μΩ · cm or less) even after the heat treatment, and a stress of −5 × 10 10 dyn / cm 2 to By using a tungsten film controlled to 5 × 10 10 dyn / cm 2 , preferably −1 × 10 10 dyn / cm 2 to 1 × 10 10 dyn / cm 2 as a gate wiring material or other wiring material of a TFT. In addition, the operating performance and reliability of a semiconductor device having a TFT can be significantly improved.

【0170】
【発明の効果】
本願発明を用いることで配線に含まれるナトリウムが0.3ppm以下、好ましくは0.1ppm以下であり、且つ、低い電気抵抗率(40μΩ・cm以下)を有し、応力が−5×1010dyn/cm〜5×1010dyn/cm、好ましくは−2×1010dyn/cm〜2×1010dyn/cm、さらに好ましくは−1×1010dyn/cm〜1×1010dyn/cmに制御された配線を形成することができる。

[0170]
【The invention's effect】
By using the present invention, sodium contained in the wiring is 0.3 ppm or less, preferably 0.1 ppm or less, has low electric resistivity (40 μΩ · cm or less), and has a stress of −5 × 10 5 10 dyn / cm 2 to 5 × 10 10 dyn / cm 2 , preferably −2 × 10 10 dyn / cm 2 to 2 × 10 10 dyn / cm 2 , more preferably −1 × 10 10 dyn / cm 2 to 1 Wiring controlled to × 10 10 dyn / cm 2 can be formed.

JP2000194104A 1999-06-29 2000-06-28 Wiring material and semiconductor device with the wiring material and its manufacturing device Withdrawn JP2002083812A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000194104A JP2002083812A (en) 1999-06-29 2000-06-28 Wiring material and semiconductor device with the wiring material and its manufacturing device
US09/604,997 US6661096B1 (en) 1999-06-29 2000-11-21 Wiring material semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
US10/672,521 US7226822B2 (en) 1999-06-29 2003-09-26 Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
US11/786,880 US7816191B2 (en) 1999-06-29 2007-04-13 Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP11-183258 1999-06-29
JP18325899 1999-06-29
JP2000-187342 2000-06-22
JP2000187342 2000-06-22
JP2000194104A JP2002083812A (en) 1999-06-29 2000-06-28 Wiring material and semiconductor device with the wiring material and its manufacturing device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011193912A Division JP5509166B2 (en) 1999-06-29 2011-09-06 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JP2002083812A JP2002083812A (en) 2002-03-22
JP2002083812A5 true JP2002083812A5 (en) 2007-08-23

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CN101312605B (en) * 2003-02-04 2010-09-29 精工爱普生株式会社 Wiring substrate, electro-optical device and their manufacturing methods
US6790719B1 (en) * 2003-04-09 2004-09-14 Freescale Semiconductor, Inc. Process for forming dual metal gate structures
KR101018757B1 (en) * 2003-09-18 2011-03-04 삼성전자주식회사 Manufacturing method of thin film transistor array panel
US7001844B2 (en) * 2004-04-30 2006-02-21 International Business Machines Corporation Material for contact etch layer to enhance device performance
US20080185667A1 (en) * 2004-09-17 2008-08-07 Kenichi Yoshino Thin Film Semiconductor Device and Method for Manufacturing the Same
JP4371230B2 (en) * 2005-01-14 2009-11-25 信越化学工業株式会社 Photomask blank manufacturing method
DE602006000392T2 (en) 2005-09-06 2008-05-08 Yamaha Hatsudoki Kabushiki Kaisha, Iwata Exhaust pipe for an internal combustion engine
JP4521382B2 (en) * 2005-09-06 2010-08-11 ヤマハ発動機株式会社 EXHAUST PIPE FOR INTERNAL COMBUSTION ENGINE, INTERNAL COMBUSTION ENGINE EQUIPPED WITH THE SAME
JP2007191761A (en) * 2006-01-19 2007-08-02 Idemitsu Kosan Co Ltd Stacked structure, electrode for electric circuit using the same and method for producing the same
KR100882834B1 (en) * 2007-03-14 2009-02-10 샤프 가부시키가이샤 Thin film semiconductor device and manufacturing method thereof
WO2011089844A1 (en) 2010-01-24 2011-07-28 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
JP2011258811A (en) * 2010-06-10 2011-12-22 Ulvac Japan Ltd Method for manufacturing semiconductor device
US8693097B2 (en) * 2010-09-03 2014-04-08 Guardian Industries Corp. Temperable three layer antireflective coating, coated article including temperable three layer antireflective coating, and/or method of making the same
JP2012114233A (en) * 2010-11-24 2012-06-14 Ulvac Japan Ltd Method of manufacturing semiconductor device

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JP2941828B2 (en) * 1988-12-21 1999-08-30 株式会社東芝 Refractory metal silicide target and method for producing the same
JP3294041B2 (en) * 1994-02-21 2002-06-17 株式会社東芝 Semiconductor device

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