TW386222B - Electric device having non-light emitting type display and method for making the electric device - Google Patents

Abstract

Using thin film transistors (TFTs), an active matrix circuit, a driver circuit for driving the active matrix circuit or the like are formed on one substrate. Circuits such as a central processing unit (CPU) and a memory, necessary to drive an electric device, are formed using single crystalline semiconductor integarted circuit chips. After the semiconductor integrated circuit chips are adhered to the substrate, the chips are connected with wirings formed on the substrate by a chip on glass (COG) method, a wire bonding method or the like, to manufacture the electric device having a liquid crystal display(LCD) on one substrate.

Description

1. Description of the invention (1) Background of the invention A7 B7 1. Field of the invention The present invention relates to a driving matrix circuit composed of an electric device and a TFT formed by manufacturing the electric device (T F T). 2. Description of related techniques Recently, by means of a liquid crystal portable electric device (personal display *, in detail, an active matrix type liquid crystal display device. For a non-light emitting type display device such as a liquid crystal display device, an active matrix circuit is formed by a thin film transistor On the substrate, in detail, the main display is formed on the same substrate to drive and control the electrical device of the present invention. The main display is thin and light, and the liquid crystal display is used as various computers, word processors, electronic notebooks, etc.). Each pixel device has excellent display characteristics, so it is used in many Denso (please read the precautions on the back before filling this page). The central standard staff of the f department has printed various active moments with TFTs. Circuit wafers are bonded, etc.) to separate semiconductors, so the semiconductor device wiring (wiring) has a width of 1 0 0, so there is a connection area Element-pitch array LCD • One display (first type) active matrix circuit and external single crystal semiconductor . Because TAB (with automatic chip and semiconductor package connected to the glass substrate, the part is quite large. Since the degree of extension from the active matrix circuit is reduced to increase the aperture ratio, and the total number of wires exceeds the problem of wire connection The thermal expansion coefficient between the connection between the bottom wire and the external chip is different from that of the TAB tape. The coefficient of thermal expansion is different from 0 mm. Therefore, it cannot be used for a display with a resolution of 60 0 and the display cannot be reduced. Standards are applicable to China National Standard (CNS) A4 (210x297 mm) -4-

1. Description of the invention (1) Background of the invention A7 B7 1. Field of the invention The present invention relates to a driving matrix circuit composed of an electric device and a TFT formed by manufacturing the electric device (T F T). 2. Description of related techniques Recently, by means of a liquid crystal portable electric device (personal display *, in detail, an active matrix type liquid crystal display device. For a non-light emitting type display device such as a liquid crystal display device, an active matrix circuit is formed by a thin film transistor On the substrate, in detail, the main display is formed on the same substrate to drive and control the electrical device of the present invention. The main display is thin and light. Each pixel device has excellent display characteristics, so it is used in many Denso (please read the precautions on the back before filling this page). The central standard staff of the f department has printed various active moments with TFTs. Circuit wafers are bonded, etc.) to separate semiconductors, so the semiconductor device wiring (wiring) has a width of 1 0 0, so there is a connection area Element-pitch array LCD • One display (first type) active matrix circuit and external single crystal semiconductor . Because TAB (with automatic chip and semiconductor package connected to the glass substrate, the part is quite large. Since the degree of extension from the active matrix circuit is reduced to increase the aperture ratio, and the total number of wires exceeds the problem of wire connection The thermal expansion coefficient between the connection between the bottom wire and the external chip is different from that of the TAB tape. The coefficient of thermal expansion is different from 0 mm. Therefore, it cannot be used for a display with a resolution of 60 0 and the display cannot be reduced. Standards are applicable to China National Standard (CNS) A4 specifications (210x297 mm) -4-A7 B7 V. Description of the invention (2> And use TF τ of amorphous silicon which can be formed at low temperature for this display. (Please first Read the notes on the back and fill in this page again) Another display (second type) ¥ thin film integrated body circuit, which has active moment I, circuit, and body / driver mixed red Y decoder ^ driver (using TF Τ ..Formed on the same-base) of the Fudong circuit. Because the above = part by f f. The conductor is not used, so the indicator changes-get ~ Gu Dang small. Because there is no need to connect a lot of wiring, so It is better to shrink the display. This display In order to reduce the size of the display, the second display is better than the first display. However, the second display is further reduced, lightened, Insufficient thinning. That is, in the brain, the main substrate of the central-central processing unit (a variety of semiconductor wafers such as daggers, main memory, image signal processing units, and Yingyingjiyi are formed outside the LCD panel) Motherboard), so you must use two substrates (or motherboard and LCD panel). In order to further reduce, reduce, and thin the display, use only one • ...------ -The board replaces two boards. Summary of the invention printed by the Bayong Consumer Cooperative of the Central Bureau of the Ministry of Economics The present invention uses the above-mentioned main board with the semiconductor crystal on at least one substrate of the liquid crystal display ¥, to achieve the reduction of the display, Lighten, thin, liquid and crystalline materials are held between a pair of substrates. These wafers are located on the substrate (board) that forms the active matrix circuit. Thin film transistors (TFTs) form the driving circuit that drives the active matrix circuit. Ming, providing electrical equipment, including: the base; at least one paper size using the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 5. Description of the invention (A7 B7 Shell Ministry of Economic Affairs, China Standards Bureau) The cooperative prints an active matrix circuit of a thin film transistor; the driving tantalum array circuit includes at least another thin film "crystalline__ 丽 _ 动 电路 ^ controlling at least one semiconductor integrated circuit chip, of which the active matrix Circuits, drive circuits, and semiconductor integrated circuit wafers are formed on the substrate. Schematic diagram Figure 1 is a block diagram of a photovoltaic device; Figure 2 shows an example of wire bonding; Figure 3 is a liquid crystal display of Embodiments 1 and 2 of the present invention Schematic diagram of the panel: Figures 4A and 4B show examples of FCOG; Figures 殳 A to 5G show the manufacturing process of the TFT circuit substrate of the embodiment and Figure ♦ Figures 6A to 6G show the manufacturing process of the TF butt circuit substrate of the embodiment j Figure 1 A to 7G show the manufacturing process of the TFT circuit substrate of Example 5. Figures 8A to 8 I and 9 A to 9 I show the manufacturing method of the TFT circuit of Example 6. Figures 10A to 10C are the top of the TFT circuit of Example 6. View, section, electrical FIG. 11A to 11D show the manufacturing process of the TFT circuit substrate of the seventh embodiment. This paper size applies to Chinese national standards (CNS > A4 size (210x297 mm). Please read the note on the back.)

I Binding A7 B7 V. Description of the invention (4) Detailed description of the preferred embodiment.. + (Please read the notes on the back before filling this page) Figure 1 shows the concept of the present invention. Using a TFT on a substrate (plate) 1 5 made of glass (also used as a substrate for a liquid crystal display), a multi-matrix matrix circuit 1.4 having multiple pixels and a relay circuit driving the active matrix circuit 14 are formed. , Circuit, each pixel includes a thin film transistor (TFT) 1 1, a pixel electrode 1 2, and an auxiliary capacitor 1 3. The driving circuit X decoder / driver 7 5, Y decoder / driver 76, and χγ divider 74. The driving circuit may include an X Y divider 74 or an X γ divider 74 may be included in the wafer.

• I has a structure that is 40 ohms from that of the active matrix circuit. I T can constitute the electric chapter that drives the active moment I circuit, that is, the peripheral circuit. The substantially identical structure represents the T F T ′ of at least one of the active matrix circuit of the interpolar material, the material of the present invention, and the material of the channel forming region. Complementary circuits, only N-channel TFTs (without P-channel T: F D), and only P. Channel-type TF T can constitute this peripheral circuit. Therefore, circuits that use TFTs can be configured. 〆Other chips are provided separately On the substrate 15. These wafers are connected by wire bonding,-'V ·. COG (including flip chip on glass, F COG), etc. --- In the sample of the Ministry of Economic Affairs of the Bureau of Plastics and Rubber Cooperatives, ^^ _ _. Circuit. In Figure 1, calibration memory 7 1, memory 7 3, CPU (Central Processing Unit) 7 2, input port 70, as the chip provided by the above method, another chip can be provided. Wire bonding in progress The shape of the cross-section of FIG. 2 is obtained. That is, the wafer 2 2 · a terminal portion 23 formed upward is mounted on the active matrix circuit 0 of the generating circuit, and the terminals and terminals 2.1 of the circuit are made of metal. Connection. Junction J 4 Connection History L Chip 2 Sub-section 2 3 ° Tree-Grease 2 5 Seal (cover) This part applies to China National Standard (CNS) A4 (210X 297 mm) A7 B7 V. Description of the invention ( 5) In order to protect the connection part from external electricity, 撃 '. To ensure the stability of the connection / attachment of the terminal, the terminal electric Huan 2 1 table is provided. In the aluminum wire cage, the resin J 2 is thicker because of the J rise, 2 5 at the terminal connection portion. In F. C 0 G. Of f 4 A and 4 B, the wafer 4 2 is oriented to The terminal part 43 formed below is mounted on the glass substrate 40 for manufacturing the circuit, and the terminal electrode 41 of the circuit is connected by the flange 4 4 (Fig. 4A) or the metal particles (Fig. 4B). The terminal portion 43 is formed. The resin 4 5 seals this portion to fix the wafer 4 2 to the substrate 40. Therefore, since the terminal connection portion has a thickness approximately corresponding to the thickness of the wafer, materials other than the thin display can be manufactured. For example, a transparent conductive oxide film (IT 0 (Indium Tin Oxide), etc.) can be used for a terminal on a glass substrate. When an active matrix circuit of a liquid crystal display is formed on a sloped glass substrate, since a transparent conductive oxide film is used in many cases It constitutes most of the upper-layer wiring, so FC 0 G is better in this respect. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) Input port 7 0 is from the outside ( (Eg host computer) receives the input signal and converts the received input signal The circuit that forms an image signal. Correction memory 71 is an inherent memory in the active matrix panel, which is used to correct the input signal according to the characteristics of the active matrix panel. In particular, the correction memory 71 is an invariant memory that stores the inherent characteristics of each pixel. Information 'When a point defect is generated in a pixel of a photovoltaic device, a correction signal is generated for the pixel next to the pixel where the point defect is generated, thereby compensating for the point defect. When the pixel is darker than the surrounding pixels, the pixel The surrounding pixels have the same brightness signal. Since the pixel defect information is different in each active matrix panel, the information stored in the correction memory 71 is different in each active matrix panel. The CPU 7 2 and the memory 7 3 have the same functions as those who share the computer. The memory is RAM (. Random Access Memory). The storage corresponds to each pixel. The paper size applies the Chinese National Standard (CMS) A4 specification (210 X 297 male). Ii) A7 B7 printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Image information of the invention description (6). [Embodiment 1] Fig. 3 is a diagram of the embodiment. In FIG. 3, the base (plate) 2L 9 and the lid bottom (-.plate) 30 are opposed to each other and the liquid crystal material is held between the substrates 29 and 30. Using the TFT, the active matrix circuit 3 i and the peripheral drive circuits 3 ″ 2 to 34 of the active matrix circuit 31 are formed on a substrate 30 such as a glass substrate. The main memory chip 3.6., Mu (micro processing unit) 3 7 or CPU (Central Processing Unit) memory 3 8 is attached to the surface of the substrate 3 0 forming the circuits 3 1 to 3 4 and is electrically connected to the circuits 3 1 to 3 4. When the ..chip is connected to the substrate by FCOG, I TO terminal block (wiring connection pad) 3 9 (corresponding to the wiring part 4 1 of FIGS. 4 A and 4 B) is a portion 3 5 formed on the base 3 0. In the embodiment, FIG. 4 A and FIG. 4 B-shaped contacts. In FIG. 4A, the conductive bumps (flange) 4 formed on the electrode portion 4 3 of the wafer 4 2 are electrically connected to the wiring portion 41 on the substrate 4 and the organic resin 45 is used. The wafer 4 2 is held on the substrate 40. The gold formed by electroless plating can be used as the flange 4 4. In FIG. 4, conductive resin (such as gold particles) 4 6 is used as the organic resin 4 5 and the substrate 4 〇Attached to the wafer 4 2. Therefore, the wiring portion 41 is brought into contact with the conductive (metal) test piece 4 6 distributed between the wafer 42 and the electrode portion 43 for circuit connection. The photocurable resin, Organic resins, such as heat-curable resins and natural curable resins, are used as adhesives. 5. After the wafer is attached, the liquid and crystal materials are applied to the liquid crystal display. (Please read the notes on the back before filling this page)

A7 B7 V. Description of the invention (7) After the above processing, the CPU and the memory are formed on the liquid crystal display substrate, and a substrate is used to constitute an electric device such as a personal computer. (Please read the precautions on the back before filling in this page) [Embodiment 2] The panel of FIG. 3 is generated, the active matrix circuit 3.1 and the peripheral driving circuits 3 2 to 3 4 are formed on the substrate 30 by TFTs. The main memory chip 36, 熥 卩 113 7 (or 〇1;), and the correction memory 3 8 are attached to the surface of the substrate 3 0 forming the circuits 3 1 to 3 4 and are electrically connected to a connection made of an aluminum alloy thin film <1 line The terminal portion (wiring connection pad) 3 9 (corresponding to the terminal electrode 2 1) is formed on the substrate 40 by wire bonding in FIG. 2. Fine gold wire is used as the bonding wire. [Embodiment 3] &quot; The chip is attached to the substrate of the T ^ T circuit (monolithic active matrix circuit) by FCOG to constitute a more enhanced circuit. The process of the monolithic active matrix circuit will be described later using FIGS. 5A to 5G. 1 0 0 0 to 3 0 0 0A. A thick silicon oxide film was formed on the substrate (Coming 7 5 9) 501. This oxide film was printed by the Central Samples Bureau of the Ministry of Economic Affairs, and was printed by Shelley Consumer Cooperative. The method for forming this oxide film may include sputtering or plasma CVD (chemical vapor deposition) in an atmosphere containing oxygen. The amorphous or crystalline silicon film is formed by plasma CVD or low-pressure CVD (LPC V D) to a thickness of 300 to 1500 A, preferably 500 to 1000 A. To form a crystalline silicon film, after the amorphous silicon film is formed, it can be irradiated (photoannealed) with a laser or a strong light equivalent to a laser, or long-term thermally annealed above 500 ° C. After thermally annealed crystallization, light annealing can be used to promote crystallization. In the thermally annealed crystal, an element (catalytic element) that promotes the crystallization of silicon may be added.

This paper size applies to China National Standards (CNS) A4 specifications (210X297 mm) Q A7 _ ^ _______ B7 ____ 5. Description of the invention (Q) 〇), such as nickel. The silicon film is etched to form the TFT active layers 503 and 504 of the peripheral driving circuit and the TFT active layer 504 of the active matrix circuit as island regions. Furthermore, a gate insulating film of $ 0 6 is formed by sputtering a silicon oxide having a thickness of 500 to 2000 A in an oxygen-containing atmosphere. The method of forming the gate insulating film 506 may include plasma CVD. The gate insulation film must have a sufficient withstand voltage. This is because the electric field is applied between the gate and the silicon active layer during the anodizing process. Therefore, nitrous oxide (N ** O) or oxygen (O2) and silane (SiH4) are suitable for the case where the gate insulating film is formed by a silicon oxide film obtained by plasma CVD. (Figure 5 A)

2 0 0 0A to 5 &quot; m thick ('preferably 2 0 0 0 to 6 0 0 0A) aluminum film (including 0.1 to 0.5¼% by weight of 铳) is formed on the substrate by sputtering, and then etched Form the gate (or blue line) 5 0 7 to 5 1 0. The gate wire 5 0 9 is connected to the anodized wiring (not returned). The gates 507 and 508 of the peripheral logic circuit are insulated from the anodized wiring. (Fig. 5B) The substrate is immersed in the electrolyte, and then the current flows into the anodized wiring, which is printed by the Central Laboratories of the Ministry of Economic Affairs and the Pai Gong Consumer Cooperative (please read the precautions on the back before filling out this page) Polar wire 5 0 9 And gate 5 1 0 anodized. Anodizing conditions are described in Japanese Patent Laid-Open No. 5-2 6 7 6 6 7. Therefore, the thicknesses of the anodic oxides 5 1 1 and 5 1 2 obtained on the upper and side surfaces of the gate lines 509 and 5 1 0 depend on the voltage to be applied, and in the embodiment are 2000 A. In most neutral solutions, the anodic oxide obtained by anodization is thin and hard, and has high pressure resistance. The withstand voltage is equal to or less than 70% of the maximum voltage to be applied during anodization. This anodic oxide is called a barrier type anodic oxide. (This paper size applies to China National Standard (CNS) A4 specifications (210X297 cm), A7 B7 V. Description of invention (9) Figure 5 C.)

The gate portion (gate and surrounding anodic oxide film) is used as a cover for automatic alignment, and impurities are introduced into the island-shaped TFT active layer by ion doping 503 and 504. In this doping, after using phosphine (p Η 3) as the doping gas-like phosphorus to introduce the entire surface, only the TF Τ active layer 5 0 3 is covered with photoresist, and diborane (B2Η 6) is used as the dopant. The doping gas introduces boron into the TF T active layers 504 and 505. The dose is 4 X 1 0 14 to 4 X 1 0 15 atoms / cm in the dish, and 1 X, 10 15 to 1 · 8 X 1 0 15 atoms / cm 3 in boron. The dose of boron is higher than that of phosphorus. Accordingly, N-type regions 5 1 3 and P-type regions 5 1 4 and 5115 are formed. (Fig. 5D) KrF excimer light (248 nm wavelength and 20 n s pulse width) is irradiated to improve the crystallinity of the portion where the crystallinity is deteriorated due to the introduction of impurities into the impurity region. The laser energy density is 2'0 0 to 40 OmJ / cm2, preferably 2 50 to 30 OmJ / cm2. Therefore, the N-type and P-type regions are activated. The sheet resistance in these areas is 200 to 8 0 Ω / square. This treatment can be performed by thermal annealing in the thermal resistance range of the gate. Printed by the Central Consumers ’Cooperative of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) 3 0 0 to 6 〇 〇 OA thick silicon oxide film is formed by plasma CVD to form an interlayer insulator 5 1 6. Multiple layers of silicon nitride film (or silicon oxide film) can be used as the interlayer insulator 5 1 6. The interlayer insulator 5116 is etched by wet etching, and contact holes 5 1 7 to 5 1 9 are formed in the N-type and P-type regions. At the same time, a 'hole 5 2 0' is formed in the gate (gate line) 5 0 9. Since the anodic oxide film 511 serves as a barrier, the etching is stopped, and the gate line 509 is not yet etched with uranium. (Figure 5 E) -2. The pattern is again formed in the contact hole by light lithography. This paper is applicable to China National Standards (CNS) Congxie (21 () &gt; &lt; 297 public shame) -12- A7 B7 _ 5. Description of the invention (10) Then, a chromic acid-containing etchant is used to etch, for example, a mixed solution of chromic acid (1 to 5%) and phosphoric acid (or nitric acid or acetic acid) to form a contact hole 5 2 1. (Figure 5 F) Sputtering a 2 0 0 0 S 6 Ο Ο Ο Ο thick titanium film, and then etching to form the electrode wiring of the peripheral circuit 5 2_. 2 to 5 2 4. The data line of the active matrix circuit 5 2 5. The pixels 5 2 6 of the pixel TFT. Connect green 5 2 3 and connect gate line 5 0 9. . Sputtering to form an I TO film with a thickness of 500 to 150 A, and then etch ′ to form a pixel electrode 52 7. A silicon nitride film with a thickness of 0.0 to 300 A is 5 2 8 to form a passivation film. Therefore, peripheral logic circuits and active matrix circuits are integrated. (Fig. 5G) The silicon nitride film 5 2 8 connected to the terminal portion (corresponding to the portion 4 1) of the external IC chip is etched to expose the I TO wiring pad of the terminal k connection portion. Figure 4 A and 4 B: F C ◦ G is attached to IC chip. [Embodiment 4] Printed by the Central Standard of the Ministry of Economic Affairs of the Bayer Consumer Cooperative (please read the precautions on the back before filling out this page) Figure 6 A to 6 G illustrates the IC chip attached to the LCD monolithic active matrix circuit Method of TFT circuit substrate formed by F COG. CMOS circuits are used as peripheral circuits. Only the NTFT is displayed as the peripheral circuit TFT, the peripheral logic circuits are displayed on the left, and the active matrix circuit is displayed on the right. A 200 Å thick basic silicon oxide film 602 is formed on a glass substrate by plasma CVD. The source gases for plasma CVD are silane (5 i Η 4). And nitrous oxide (N 2 0). The base temperature of the film formation is based on the paper standard, using the Chinese National Standard (CNS) Α4 size (210 X 297 mm) -13-Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (n) 3 8 0 to 5 0 ° C, for example 4 3 0 ° C, the silicon oxide film 6 2 2 formed has a relatively low etching rate and is solid. This is because—nitrogen oxide is used as a raw material gas, so a silicon oxide / nitride nitride film containing 1 to 10% nitrogen is obtained. Ester-added buffered hydrofluoric acid (ABHF) (hydrofluoric acid: ammonium fluoride: acetic acid = 1- .:: 50: 50) is used at 23 ° C, and the standard etching rate is 80 to 100. 0A / minute. Plasma CVD forms a 500 A thick amorphous silicon film. A silicon oxide film was formed on the surface of the amorphous silicon film by thermal annealing at 55 ° C for 1 hour in an oxygen-containing atmosphere (estimated about 40 to 100 A). By spin coating, a 1 to 100 ppm nickel ester acid solution is used to form an extremely thin film of nickel acetate. First, a thin silicon oxide film is formed on the surface of the amorphous silicon film, and the solution is distributed on the surface of the amorphous silicon film. ’Thermal annealing at 5 50 ° C for 4 hours in a nitrogen-containing atmosphere. Nickel ester is decomposed at about 400 ° C to obtain nickel. Since the nickel acetate film is roughly attached to the amorphous silicon film, nickel diffuses to the amorphous silicon film by thermal annealing. Therefore, the amorphous silicon film is crystallized to form a crystalline silicon region.

XeC 1 excimer laser light (30.8 nm wavelength) shines on the silicon film. The laser energy density is from 250 to 300.111 / (: 1112, which further improves the crystallinity of the crystalline silicon film. Furthermore, to relax the stress and strain by laser irradiation, thermal annealing is performed again at 5 50 ° C for 4 hours. The silicon film is etched to form island-shaped active layers 603 and 604. 1 2 0 0 A thick silicon oxide film 65 is formed by sputtering to form a gate insulating film. Sputtered to form 4 0 0 A thick aluminum ( Contains 0.2 to 0.3% by weight of 铳) film. The surface is anodized to form a thickness of 100 to 300 A. This paper size is applicable to China National Standard (CNS) specifications (210 X 297 mm) ( Please read the notes on the back before filling in this page) d -14-A7 B7 V. Description of the invention (12) _ (Please read the notes on the back before filling in this page) Alumina film (not shown). Due to oxidation The aluminum film is present, so the aluminum film has high viscosity to the photoresist. To prevent the leakage of the current photoresist, the porous anodic oxide is formed on the gate side in the anodizing process described below. Spin coating is used to form the photoresist. (Such as Τ〇ky 〇0 products of Hka company 0 卩? Ruler 8 0 0 / 3_.0 port), and then form the gates 6 09 and 6 1 1 and the gate line 6 1 0. The gate of the peripheral circuit 6 0 9 and gate line 61 0 are insulated from gate 6 11 of the active matrix circuit. Photoresistors (covers) 6 6 to 6 8 for etching are present (Fig. 6A).

• I In the state that the photoresistors 6 0 6 to 6 0 8 are still in the state, the current flows through the gate line 6 1 0 and the gate electrode 6 1 1 for porous anodization, and the gate line 6 1 0 and the gate electrode 6 1 The sides of 1 form porous anodic oxides 6 1 2 and 6 1 3. An acid solution of 3 to 20% (e.g. 'citric acid, oxalic acid, phosphoric acid, chromic acid 9 &gt; · or sulfuric acid) is used for anodization. A voltage of 10 to '3 OV is applied to the gate. In the example, printed in an oxalic acid solution (at 30 ° C ρΗ = 0.9 to 1.0) at the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs at 10V for 20 to 80 minutes. The anodizing time controls the thickness of the anodic oxide. By anodization using an acid solution, a porous anodic oxide is formed. The thickness of the porous anodic oxide is 3000 to 100 A, such as 500 A. (Fig. 6B) After removing the photoresist 6 06 to 6 0 8, current is passed through the gate line 610 to perform barrier anodization, and 1 and 1 are formed on the side and upper surfaces of the gate line 61 and the gate 611 respectively. 2 0 0 A thick thin barrier type anodic oxide films 614 and 615. (Fig. 6C) Using porous anodic oxides 6 1 2 and 6 1 3 as a cover, the silicon oxide film 6.05 is etched by dry etching to form a gate insulating film 6 1 6 to this paper standard using Chinese national standards (CNS) A4 size (210X297 mm) ~ —1 R. Printed by the Consumer Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs A7 B7_ _

V. Description of the invention (J 1086 1 8. This etching may include plasma mode of isotropic etching or reactive ion etching mode of anisotropic etching. Fully increase the selection ratio of silicon to silicon oxide, and do not over-etch the active layer When C 1 F 4 is used as an etching gas, the anodic oxide is not etched, and only the silicon oxide film 6 0 5 is formed. The silicon oxide films 6 1 7 and 6 1 8 are formed on the porous anodic oxides 6 1 2 and 6 13Έ. Still not etched. (Figure 6D) Using a mixed solution of phosphoric acid, ester acid, and nitric acid, only the porous anodic oxides 6 12 and 6 1 3. The mixed solution hardly etches the barrier anodic oxides 6 1 4 and 6 1 5. Since the mixed solution is used to etch aluminum, a photoresist is used to protect the gate 609 of the peripheral circuit portion to mask the peripheral circuit portion. Therefore, in comparison with Example 3, a photolithography process is additionally added. By using a gate insulating film 6 1 ”6 and 6 1 8 doped with ions, impurities (phosphorus and boron) are introduced into the active layer. Although only NMOS is shown, but also

Doped with boron. In phosphorus doping, the acceleration voltage is quite low (10 to 3 OKeV) and the dose is quite high (5X1 014 to 5X1 015 atoms / cm3). Due to the low acceleration voltage, the ion introduction depth is shallow, and phosphorus is mainly introduced into the regions 6 1 9 and 6 2 0 that expose the silicon layer.

Phosphorus is introduced at a rather high acceleration voltage of 60 to 95 KeV at a relatively low dose of 1 X 1 012 to IX 1014 atoms / cm3. Due to the high acceleration voltage, the depth of ion introduction is deep, and phosphorus is introduced into the region 6 2 1 covered with the gate insulating film. As a result, regions 6 1 9 and 6 2 0 infiltrated with high concentration of phosphorus and regions 6 2 1 doped with low concentration of phosphorus are formed. That is, in the pixel T F T, a so-called double-drain structure can be obtained. The same treatment can be performed in boron. 0._-',' _______ This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) T 丨 ^^ 丨 Γ — — -®-pack! (Please read the notes on the back before filling out this page) Order • Ια. Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the invention (14) Thermal annealing at 4 50 ° C for 1 hour, activation Doped impurities. Since nickel &amp; is a crystallization promoting element, it can be activated at temperatures below normal activation. (Fig. 6E) A multilayer film 6_2 with a silicon oxide film (2.0 0A thick) and a silicon nitride film (4000A thick). The first intermediate rhenium insulator is formed by plasma CVD, and the contact hole is formed by dry-feed etching. 6 3 2 to 6 2 7. (Figure 6F) A three-layer metal film with titanium (500 A thick), silver (4 0 0 A thick), and titanium (5 ο 0 A thick) is deposited by sputtering and then etched to form electrode wiring 6 2 8 To 6 3 1. In addition, by plasma CVD, a 2000 A thick silicon oxide film 6 3 2 is deposited as a second interlayer insulator, a contact hole is formed at the drain electrode 6 3 1 of the pixel TFT, and IT 0 forms a pixel electrode. 6 3 3. Therefore, a monolithic active matrix circuit can be generated. (Fig. 6G) In the substrate treated as described above, the IC chip is mounted on the I TO terminal pads (corresponding to part 41) of the external IC chip, and is adhered by the FCOG of Figs. 4A and 4B. [Embodiment 5] The chip was attached to the substrate of a TFT circuit (monolithic active matrix circuit) by wire bonding, and constituted a modified circuit. 7A to 7D show an active matrix circuit process of the embodiment. In FIGS. 7A to 7D, the left side is the peripheral logic circuit area, and the right side is the active matrix circuit area. 2 0 0 Π A thickness of a certain hydride film 7 0.1 1 deposited on glass paper by sputtering. Applicable to China National Standard (CNS) A4 specifications; (210X297 mm) _ 17 i i. · -11 # equipment丨 | (Please read the notes on the back before filling this page) Order A7 _____B7__ V. Description of the invention (1C) 15 (Please read the notes on the back before filling this page) on the glass substrate (not shown). A 50 μA thick I TO film is formed on the basic oxide film 7 0 1 by sputtering, and then the wiring of the peripheral logic circuit area 7 0 2 to 7 0 4 and the wiring of the active matrix circuit area 7 0 5 and The pixel electrode 7 0 β 0 5 0 to 15 1 0 A thick amorphous silicon film is formed by plasma CVD or LP CVD, and silane or disilane is used as the raw material gas. The oxygen concentration of the amorphous silicon film is preferably 10 18 · atoms / cm 3 or less. Phosphorus and boron are doped with ion doping similar to those made by known CMO S. That is, after phosphorus doping, photoresist masks the area where the N-channel TTF is formed, and boron is then doped into the area where the P-channel TTF is formed. The doping gas for phosphorus doping is phosphine (p H3) and the doping gas for boron is diborane (B 2 Η 6). Accelerated electric calendar is preferably 5 to 30 κ V in phosphorus. Dose 1 X 1 〇14 to 5 1 0 15 atoms / cm 3, for example, 2 X 10 14 atoms / cm 3 in phosphorus and 5 X 1 0 14 atoms / cm 3 0 in boron as the channel forming region of each TFT Parts (between the source and the drain) are etched to form N-type semiconductor regions 7 0 7, 7 0 8, 7 1 1, 7 12 and P-type semiconductor regions 7 9 and 7 1 0. A 100 to 500 A (for example, 2000 A) thick amorphous hydrogenated silicon film 7 13 is formed on these regions by plasma CVD. In FIG. 7A, a non-adhesive cover 7 1 4 that does not contact the film 7 1 3 is irradiated with Kr F excimer electroradiation light (24 8 n m ′ wavelength and 20 ns pulse width) to make the periphery of the film 7 1 3 The circuit area (left) crystallizes. Laser energy density is from 200 to 40,000. 11 / (: 1112, preferably from 2 50 to taa (CNS) (210 X 297 ^ *) 'A7 B7 V. Description of the invention (16) 3 0 OmJ / cm2. Due to the irradiated light, the light does not reach the area covered by the cover 7 14 (including the active matrix circuit area), so the area is still amorphous silicon. The area irradiated with laser is in the film 7 1 3 and the area 7 0 7 to 7 1 0 crystal.. Silicon film (N-type and P-type semiconductor regions 7 7 to 7 1 0 and essentially cut film 7 1 3) Uranium is carved into an island shape, forming an island-like region of peripheral circuits 7 2 1 To 7 2 3. At the same time, the source 7 1 5 and the drain 7 1 6 of the N-channel TFT of the peripheral logic circuit are also formed, and the source 7 1 8 and 7 1 of the TFT of the peripheral logic circuit 7. The source 719 and the drain 720 of the N-channel TFT of the active matrix circuit. (Figure 7B) Using nitrous oxide (N2O) and oxygen (02) as raw materials, plasma CVD to form 1 2 0 0 A thick silicon oxide film 7 2 4. Since the film 7 2 4 is used as a gate insulating film or a dielectric substance of a capacitor, the film must have a sufficiently low interface level density and a high withstand voltage. In the embodiment, Silane and nitrous oxide were 0 0 SCCM was introduced into the reaction chamber. The substrate temperature was 4 3 0 ° C, the reaction pressure was 0.3 Torr, and the applied power was 13 .56 Μ Η z was 2 50 W. These conditions depend on the reaction device to be used. Formation The film formation speed of the silicon oxide film 7 2 4 under the above conditions is about 100 〇A / minute. When using a mixed solution of hydrofluoric acid, acetic acid, and ammonium fluoride at a ratio of 1: 50: 50 (at 20 ° C) ), The etching rate is about 1000 A / min. 2000 to 8000 A (for example, 3,000 A) thick titanium film is deposited by sputtering, and then etched to form a gate electrode. · 7 2 5 to 7 2_ 7 and holding capacitor electrode 7 2 8. The size of this paper is applicable to China National Standard (CNS) A4 (210X297 mm). -19-| ------- \ ---- packing-(Please read the precautions on the back before (Fill in this page) Order the central standard of the Ministry of Economic Affairs and print the A7 B7 of the Cooperative Cooperative. V. Description of the invention (17) 3 0 0 0A silicon nitride film 7 2 9 is formed by plasma CVD. Therefore, NS channel type and P channel type TFTs (peripheral p-Si N-ch TFT and peripheral p — Si P-ch. TFT), crystalline silicon that can form peripheral logic circuits] ^ channel type non Crystal silicon TFT (pixel a.-Si N-c h T F T}), holding capacitor. (Figure 7C) The TTF structure of the peripheral logic circuit may be different from the active matrix circuit. For example, in the offset structure of FIG. 7D where the TFT gate and the drain of the active matrix circuit are separated from each other, the OFF current can be further reduced. In order to perform the same high-speed operation as the peripheral logic circuits, the semiconductor has to be crystallized, the source and the drain are also crystallized, and the sheet resistance is low. Although the laser is irradiated to manufacture peripheral logic circuits, the above requirements are satisfied because the channel-shaped area and the portions corresponding to the source and the drain are crystallized. In order to further promote the crystallization of the source and drain electrodes, catalytic elements that promote amorphous crystals (such as nickel, platinum, palladium, cobalt, or iron) can be used at a concentration of 1 X 1 0 17 to 2 X 1 0 μ atoms / cm 3 Add silicon film. In the substrate treated as described above, the silicon nitride film 7 2 9 connected to the terminal portion (corresponding to the portion 2 1) of the external IC chip is etched to expose the titanium connection pad of the terminal connection portion, and the RC chip is connected by wire bonding in FIG. 2. [Embodiment 6] FIGS. 8A to 8I show cross sections of an active matrix circuit section, and FIGS. 9A to 91 show cross sections of a peripheral circuit section. Figure 1 〇a is a top view of the active matrix _ circuit, Figures 8 · I and 9 I show the line 圄 1 OA A — B — This paper size is applicable to China National Standard (CNS) A4 (210X 297) (Concurrent) ^ ~ 20-(Please read the notes on the back before filling out this page)

Printed by Shellfish Consumer Cooperation of the Central Bureau of Standards, Ministry of Economic Affairs Α7 Β7 V. Description of the invention (). 18 ′ C section. Figure χ 0 b shows a cross section along line a-b of Figure 10A. Figure 10c shows the circuit configuration of the active matrix circuit. The first-gate wiring electrodes 802 to 805 are formed on a green surface of a glass substrate on which a 10 G thick silicon nitride film (not shown) is formed. A polycrystalline silicon film with a thickness of 300 A, which is doped with phosphorus to reduce resistance, is etched to form gate wiring electrodes 802 to 805. Low-pressure CVD forms a polycrystalline silicon film. There is a polycrystalline state when this film is formed. To obtain a polycrystalline silicon film, there are the following methods except the above method. That is, after forming an essentially amorphous silicon film by plasma CVD or low-pressure CVD, impurities such as phosphorus are introduced into the silicon film by ion doping. Furthermore, thermal annealing is performed at 500 to 600 ° C. In thermal annealing, elements that promote crystallization, such as nickel, can be slightly incorporated. In the embodiment, silicon is used, but various metal silicides can be used. Plasma CVD forms a silicon nitride film 806 with a thickness of 300 to 600 A (for example, 400 A), which is also used as a gate insulating film. Plasma CVD forms an amorphous sand film having a thickness of 3.0 to 100 A (for example, 500 A), and is then etched to form island silicon regions 807 to 809. (Figures 8 A and 9 A) Plasma CVD forms a silicon nitride film 8 1 0 to 3 0 to 6 0 0 A (for example, 2 0 0 A), which is also used as a gate insulating film. The laser light strikes only the peripheral circuit portion, and crystallizes the island-shaped silicon films 808 and 809. Laser is XeCl excimer laser (308nm wavelength). The laser irradiation energy density and the number of pulses vary depending on the characteristics of the silicon films 808 and 809 and the silicon nitride film 810. Etching the silicon nitride film 8 0 6 and 8 1 0 to form the paper size to reach the-gate electrode, using China National Standard (CNS) M specifications (210X297 mm) ^ ----- ^ ----- --- β Pack II (Please read the notes on the back before filling this page) Order the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, India, and the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, printed by A7 B7 5. Description of the invention (19 ) Contact hole for the wire (not shown). This contact hole is used to form a contact between the first gate connection and the second gate connection (formed on the first gate connection, corresponding to the contact 8 4 5 as shown in FIGS. 10A and 10B). After the contact hole is formed, an aluminum film 8 1 1 with a thickness of 3000 to 800 OA (for example, 30000 A) is formed by sputtering. When the aluminum film 8 1 1 contains 0.1 to 0.5% by weight of rhenium (Sc), generation of hillocks can be prevented (see FIGS. 8 B and 9 B). The aluminum film 8 1 1 is etched to form a second gate wiring electrode 8 1 2 to 8 1 5. Therefore, a contact between the first gate wiring and the second gate wiring is formed through the formed contact hole. The contact hole must be completely covered with the second gate wiring. This is because when the first gate wiring made of silicon is exposed at the contact hole, current flows through the exposed portion during the anodizing process without anodizing. (Figure 8. and 9C) In the electrolyte, a current is sent to the second gate terminal electrodes 8 1 to 8 1 5. An ethylene glycol solution obtained by adding ammonia to 3 to 10% tartaric acid and having a pH of 6.8 to 7.2 was used. When the solution is about 10 ° C below the room temperature, an oxide film with high quality is formed. Therefore, barrier anodic oxides 8 16 to 8 1 9 are formed on the upper and side surfaces of the second gate wiring electrode. The thickness of the anodic oxide is proportional to the applied voltage, and preferably 100 to 3 0 0A. A 20000A thick anodic oxide was formed at 150V. To obtain an anodic oxide with a thickness of more than 3 00 A, more than 2 500 V must be applied. But this affects the T F T characteristics. (Figures 8D and 9D) By dry etching, the silicon nitride film 8 1 0 is automatically aligned and etched. But because the anodic oxide 8 1 6 to 8 1 9 is not etched, the gate insulating film 8 2 0 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21,0X297 mm) (Please read the note on the back first (Fill in this page again)

-Equipment ------ Order I io · -22-A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2 ()) to 8.,. 2 3 is still at the second gate The wiring electrodes 8 1 2 to 8 1 5 and the island-shaped political film 8 07 to 8 0 9. (Figures 8 E and 9 E) By ion doping, the gate portion is automatically aligned (gates 8 i 3 to 8 1 5 and anodic oxides 8 1 7 to 8 1 9 next to it), N-type and P-type impurities are introduced into the island-shaped silicon film 807 to 809, forming N-type impurity regions (source / drain regions) 8 2 4 to 8 2 7 and P-type impurity regions 8 2 8 and 8 2 9. The doping gas doped with N-type impurities is hydrogen nitride (ph3), and the doping gas doped with P-type impurities is diborane (B2H6). The dose is 5X 1 0 14 to 5 X 1 0 15 atoms / cm3, and the acceleration voltage is 10 to 3 OKeV. Irradiate KrF excimer electroradiation light (2 8 nm wavelength and 20 n s pulse width) to activate the introduction of foreign ions in the silicon film 807 to 809. (Figs. 8F and 9F) A metal such as a titanium film 830 having a thickness of 50 to 500 A is formed on the entire surface by sputtering. (Figures 8G and 9G) At 450 to 500 eC (for example, 500 ° C) for 10 to 60 minutes, titanium reacts with silicon to form silicide (titanium silicide) regions 8 3 1 to 8 3 6. In this thermal annealing, doped impurities are further activated. Laser annealing with laser light irradiation, lamp annealing with visible light irradiation or near-infrared light irradiation, and thermal annealing with silicide treatment can be performed. The titanium film 830 was etched using an etching solution obtained by mixing hydrogen peroxide, ammonia, and water at a ratio of 5: 2: 2, respectively. Since the titanium film (for example, the titanium film formed on the silicon nitride film 806 and the anodic oxide film) that does not contact the active layer is left in a metallic state, it can be etched in this etching process. On the other hand, titanium silicide Does not etch, so it is still. (Figures 8A and 9H) (Please read the precautions on the back before filling this page)

IP package. The size of the paper is in accordance with Chinese National Standard (CNS) A4 (.210X297mm) A7 B7 V. Description of the invention '(21) 5 〇 〇 0A thick silicon oxide film formed by CVD on the entire surface as First Intermediate Layer Insulator 8 3 7. The contact holes are formed at the source and the drain of the TFT. After the first interlayer insulator is formed, it is annealed at 400 ° C. for 10 to 30 minutes. The wiring electrodes 8 3 8 to 8 4 1 are formed, and the pixel electrodes 842 are formed using an ITO film. In order to prevent moisture, active ions, etc. from entering the TFT from the outside, the plasma

CVD forms a silicon nitride film with a thickness of 2000 to 5 〇 〇A (for example, 3 〇 〇 0 A) 8 4 3, the pixel portion. 8 4 4 and the terminal portion (not shown) connected to the external IC chip is opened. The I TO film is exposed. (Figures 8 I and 9 I) Through the above processing, the wiring cross section 8 4 7 of the active matrix circuit, the TFT connected to the pixel, the N-channel TFT 8 4 9 and the P-channel TFT 8 50 of the peripheral circuit are formed. A monolithic active matrix circuit is obtained. FIG. 10A is a top view of a TFT provided with a pixel portion. The gate line of the extended self-scanning driver appears to be a single line in FIG. 10A. However, the first gate line 8 0 2 is formed in parallel with the second gate line 8 1 2. The first and second gate lines are interconnected via a contact 8 4 5. In the active matrix circuit of the embodiment, a contact is formed for a TFT. Although one of the first and second gate lines 80 2 and 8 1 2 is damaged, the whole remains unchanged. In the embodiment, as shown in FIG. 10A, the contact is formed at a branch portion where the gate line is branched. This is because when providing a pad area (a connection area with a thick width) to form a contact, the branch does not need to provide special space, so it is better in _ configuration. The size of this paper applies to Chinese National Standard (CNS) M specifications (21.0X297 mm) --------- packing— (Please read the precautions on the back before filling this page)

1T

-ID Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economy -24-A7. B7 V. Description of the Invention (22) Figure 1 OB shows the cross-sectional structure along the line a-b of the gate line of Figure 10 A. Fig. 10c shows an active matrix circuit having a plurality of circuits of Fig. 10a. The gate lines 8 1 2 and 80 2 also branch to wirings 8 4 6 which extend below the on-line pixel electrode. The capacitor is formed between the wiring 8 4 6 and the pixel electrode, parallel to the liquid crystal capacitor formed by the 5 pixel electrode on the circuit. In the processed substrate, the IC chip is mounted on the terminal portion (corresponding to part 41) of the I TO connected to the external IC chip, and is attached to the IC chip by F C 0 G of FIGS. 4A and 4B. [Example 7] An IC chip was connected to a monolithic active matrix circuit (TFT circuit) substrate, and an active matrix circuit using amorphous silicon (a-Si) TF and a peripheral circuit using crystalline silicon TFT were formed on the same glass substrate . Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page). Figures 11A to 11D show the manufacturing process of the monolithic active matrix circuit of the embodiment. A silicon oxide film having a thickness of 1000 to 3000 A is formed on a glass substrate 9 01 to become a basic oxide film 9 02. With the plasma V D or L P C V D, the amorphous silicon film 903 is deposited to a thickness of 300 to 1500 A, such as 500 A. In addition, a silicon oxide film (or a silicon nitride film) having a thickness of 50 to 100 A (for example, 2000 A) is formed by a plasma CVD to form a protective film 904. Irradiated with Kr F excimer electroluminescence light (2 4 8 nm wavelength and enhanced crystallinity of the silicon film 9 0 3. The laser energy density is 2 0 to 4 0 OmJ / cm2, preferably 2 5 0 to 3 0 OmJ / cm2. (Figure 1 1 A) This paper size applies Chinese National Standard (CNS) Λ4 specification (210X297 mm) ': -25-A7 B7 V. Description of the invention (23) Protective film 9 0 4 is removed and exposed The silicon film 903 is formed in an island shape to form an island silicon region 905 of an N-channel TFT and an island silicon region 906 of a P-channel TFT. Furthermore, sputtering is performed in an oxygen-containing atmosphere, or Plasma CVD is used to decompose and deposit TE 0 S to form a gate insulating film. 9 0 7 ° 'Sputtered to form 2 0 0 0_6 to 5 thick film, and then etched to form gates 9 0 8 and 9 0 9. At the same time, the gate electrode of the inverse staggered TFT of the active matrix portion 9 1 0 ° (Fig. 1 B) is immersed in the electrolyte, sends the current to the gate electrode, and forms an anodic oxide layer 9 next to the gate electrode. 1 1 to 9 1 3. The anodic oxide film of the TFT (left side) in the peripheral circuit area is thin to increase the TFT mobility, and the anodic oxide film thickness of the TFT of the active matrix circuit (the right-side staggered TFT) is to prevent the gate electrode. In the embodiment, the anodic oxide film is 2 000 to 2 5 0 0 A thick. (Figure Γ 1 C) The gate part (gate and the anodic oxide film next to it) is used for automatic alignment. For the mask, impurities are introduced into the island-shaped cut-out areas of each TFT by ions 905 and 906. That is, using phosphorus (PH3) as the doping gas, phosphorus is introduced into the entire surface first. The island is only masked by the photoresist Boron was introduced into the island-like silicon region 906 after the sol-like silicon region 905. The dose was 2X1 0i5 to 8X1 atoms / cm3 in phosphorus, and 4 X 1 0 15 to 5 X 1015 atoms / cm3 in boron. The dose of boron is higher than that of phosphorous. Irradiate K / r F excimer electroradiation light (wavelength of 2 4 8 nm and pulse width of 20 ns to improve the crystallinity of the part whose crystallinity is deteriorated due to the introduction of impurities. The laser energy density is 2 0 0 to 4 0 OmJ / cm2, preferably this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) _______Pack II (Please read the precautions on the back before filling this page) Printed by the Standards Bureau's Consumer Cooperatives A7 B7 printed by the Consumers' Cooperatives of the Central Prospectus Bureau of the Ministry of Economic Affairs 5. Description of the invention (24) 2500 to 300111] / (: 1112. ( 11D) As a result, N-type regions 9 1 4 and 9 1 5 and P-type regions 9 1 6 and 9 1 7 are formed. The sheet resistance of these regions is 2 0 to 8 0 0 Ω / square. By plasma CVD A silicon nitride film with a thickness of 3 0 &gt; 0 0A is formed on the entire surface to form an intermediate layer insulator 918. The silicon nitride film is an interlayer insulator for peripheral circuits. However, since the silicon nitride film is used as the TFT gate of the active matrix circuit, attention must be paid to the film manufacturing. A 100 to 5 0 A (eg, 2 0 A) thick amorphous silicon layer 9 1 9 is formed on the gate 9 1 0 of the active matrix portion, and then a single crystal silicon layer formed by plasma CVD ( 5,000 to 10,000 A thick), forming a source 920 and a drain 921 of an amorphous silicon TFT. A transparent conductive material such as I T 0 is used for the T F T of the active matrix portion to form a pixel electrode θ 2 5 〇 contact holes are formed at the source and drain of each TF T of the peripheral circuit portion,

Forming aluminum wiring 9 2 2 to 9 2 4. An N-channel type TFT and a P-channel type T F T are used on the left to make a phaser circuit. Anneal at 350 ° C for 2 hours in a hydrogen-containing atmosphere to reduce dangling bonds on the silicon film. Through the above processing, peripheral circuits and active matrix circuits are integrated. In the embodiment, the de-interleaved TF T is used as the amorphous silicon TFT of the active matrix circuit, and the light does not enter the channel portion. This is because the conductivity of amorphous silicon is changed by light irradiation. In the processed substrate, the IC chip was connected to the terminal portion of the aluminum wiring of the external IC chip (corresponding to part 2 1) using the wire bonding method of FIG. 2. ___ This paper size applies Chinese National Standard (CNS) Λ4 specification (210X297 mm) '(Please read the precautions on the back before filling this page) &gt; ΤΓ

Claims (1)

Amendment A8 B8 C8 D8 _ Supplementary VI. Patent Application Scope No. 8 4 1 1 2 5 5 5k Patent Application Chinese Patent Application Scope Amendment February 1988 Amendment 1. An electrical device comprising: an insulating substrate; An active matrix circuit including at least one thin film transistor formed on a first surface of the insulating substrate: a driving circuit including at least another thin film transistor formed on the first surface of the insulating substrate as a drive The active matrix circuit; a counting substrate facing the first surface of the insulating substrate, and a liquid crystal material located between the substrate and the surface, wherein the insulating substrate extends beyond at least one side edge of the counting substrate to provide An extension part; and at least one semiconductor integrated circuit chip, which is located on the first surface of the insulating substrate extension part and is operated to be connected with the driving circuit, wherein the at least one thin film transistor and the at least one other The thin film transistor system is formed from a common semiconductor film, and the film is formed on the first surface of the insulating substrate. 2. The device according to item 1 of the patent application scope, wherein the semiconductor integrated circuit chip is connected to the driving circuit by wire bonding. 3. If the device of the scope of patent application 1 ', where the semiconductor integrated circuit chip is connected to the drive circuit by COG (wafer on glass) · 4. If the device of the scope of patent application 1 is the semiconductor The integrated circuit chip includes a central processing unit. 5. If the device in the scope of patent application No. 1 'where the semiconductor volume paper size, use China National Standard (CNS) A4 specification (210X297 mm) (Please read the back first (Please note this page before filling in this page.) Language: Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Amendment A8 B8 C8 D8 _ Supplementary VI. Patent Application Scope No. 8 4 1 1 2 5 5 5k Patent Application Chinese Patent Application Scope Amendment February 1988 Amendment 1. An electrical device comprising: an insulating substrate; An active matrix circuit including at least one thin film transistor formed on a first surface of the insulating substrate: a driving circuit including at least another thin film transistor formed on the first surface of the insulating substrate as a drive The active matrix circuit; a counting substrate facing the first surface of the insulating substrate, and a liquid crystal material located between the substrate and the surface, wherein the insulating substrate extends beyond at least one side edge of the counting substrate to provide An extension part; and at least one semiconductor integrated circuit chip, which is located on the first surface of the insulating substrate extension part and is operated to be connected with the driving circuit, wherein the at least one thin film transistor and the at least one other The thin film transistor system is formed from a common semiconductor film, and the film is formed on the first surface of the insulating substrate. 2. The device according to item 1 of the patent application scope, wherein the semiconductor integrated circuit chip is connected to the driving circuit by wire bonding. 3. If the device of the scope of patent application 1 ', where the semiconductor integrated circuit chip is connected to the drive circuit by COG (wafer on glass) · 4. If the device of the scope of patent application 1 is the semiconductor The integrated circuit chip includes a central processing unit. 5. If the device in the scope of patent application No. 1 'where the semiconductor volume paper size, use China National Standard (CNS) A4 specification (210X297 mm) (Please read the back first (Please note this page before filling in this page.) Language: Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs of the Consumer Cooperative Association A8 Β8 C8 D8 VI. Patent application scope The body circuit chip contains a memory · / 6. As for the device in the scope of patent application No. 1, wherein the insulating substrate includes a glass substrate · 7. A liquid crystal display device * comprising:-a substrate having a first surface; an active matrix circuit including at least one thin film transistor formed on the first surface of the substrate; a driving circuit including at least another thin film transistor To drive an active matrix circuit formed on the first surface of the substrate; and at least one semiconductor integrated circuit chip, which is located on the first surface of the integrated body, and is operated to connect the driving circuit, wherein the at least one The thin film transistor and the at least another thin film transistor system are formed from a common semiconductor film, the film is formed on the first surface of the substrate *, and the at least one thin film transistor of the active matrix circuit is in the channel region and the attracting electrode There is at least one slightly doped suction pole between the castors. 8. The device of claim 7 in the scope of patent application, wherein the single crystal semiconductor bulk circuit chip includes a central processing unit. 9. The device according to item 7 of the scope of patent application, wherein the single-crystal semiconductor volumetric circuit chip includes a memory. 10. A liquid crystal display device including: an insulating substrate; an active matrix circuit including at least one thin film transistor; a driving circuit including at least another thin film transistor to drive the active matrix circuit; And this paper size applies to China's national standard (CNS> M size (210X297mm) _ 2-(Please read the precautions on the back before filling out this page) Order 8 8 8 8 ABCD Employees' Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Printing 6. Scope of patent application—control circuit to control the driving circuit, the control circuit is operated to be connected with the driving circuit: wherein the active matrix circuit, the driving circuit and the control circuit are formed on an insulating substrate And wherein the control circuit has at least one semiconductor integrated circuit wafer; and wherein the at least one thin film transistor and the at least another thin film transistor system are formed from a common semiconductor film, the film is formed on an insulating substrate. 1 1. A liquid crystal display device comprising: an insulating substrate; an active matrix circuit, including At least one thin-film transistor; a driving circuit including at least another thin-film transistor to drive the active matrix circuit; and a semiconductor integrated circuit chip bonded to the insulating substrate and operated to Connected to the driving circuit, wherein the active matrix circuit and the driving circuit are formed from a common semiconductor film, the film is formed on an insulating substrate. 1 2. An electrical device, including: a base. The bottom has An insulating surface: a plurality of thin film transistors are formed on the insulating surface. The plurality of thin film transistor systems are formed from a common semiconductor thin film. The film is formed on the insulating surface: and at least one single-silicon semiconductor product. The body circuit chip is formed on the insulating surface; &gt; The paper size is applicable to the Chinese national standard (CNS &gt; A4 size (210x297 mm) _ 3 2 '&quot; ) A8 B8 C8 D8 printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics. Patent application scope. At least one of the thin film transistors &amp; is an active matrix circuit. The active matrix circuit is driven, and the semiconductor integrated circuit chip is used as a control circuit to control the driving circuit, and the common semiconductor film is a semiconductor film containing amorphous silicon doped on the insulating surface. It is crystallized and formed 03. If the device of the scope of patent application No. 12 in which the integrated body includes a glass substrate 14. If the device of the scope of patent application No. 12 in which the single crystal silicon semiconductor integrated circuit wafer It is connected with the driving circuit by wire connection. "15. For the device in the scope of patent application No. 12, where the single crystal silicon semiconductor integrated circuit chip is connected to the driving circuit by COG (chip on glass) 》 16. An electric device comprising: a first substrate; an active matrix circuit formed on the first substrate with at least one thin film transistor Upper; a driving circuit formed on the first substrate as at least another thin film transistor driving the active matrix circuit; a second substrate facing the first substrate with a gap therebetween; the The first substrate extends beyond at least one side edge of the second substrate to provide an extended portion; and a semiconductor integrated circuit wafer is positioned above the extended portion of the first substrate and is operated to communicate with The driving circuit is connected 'This paper size is applicable to China National Standard (CNS) A4 (210X297mm) _ 4 (Please read the precautions on the back before filling this page) A8 B8 C8 D8 6. Scope of patent application The at least one thin film transistor and the other thin film transistor system are formed from a common semiconductor thin film, and the film is obtained by incorporating amorphous silicon on the first substrate. A semiconductor film of silicon is crystallized. 17. The device according to item 16 of the scope of patent application, wherein the other non-single-crystal silicon thin film transistor system is a complementary type. 18. The device according to item 16 of the scope of patent application, wherein the other non-single-crystal silicon thin film transistor only has a P-type FT. 19. The device according to item 16 of the patent application, wherein the other non-single-crystal silicon thin film transistor has only N-type TFT ^ 20. The device according to item 1 of the patent application, wherein the thin film of the active circuit The transistor has the same structure as the thin film transistor of the driving circuit. 2 1. The device according to item 7 of the scope of patent application, wherein the thin film transistor of the active circuit has the same structure as the thin film transistor of the driving circuit. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) 22. For the device in the scope of patent application No. 12, where the thin film transistor of the active circuit has the same The thin film transistor of the driving circuit has the same structure. A 23. The device according to item 16 of the application, wherein the thin film transistor of the active circuit has the same structure as the thin film transistor f of the driving circuit. 2 4. A liquid crystal display device comprising: a first substrate having an insulating surface; an active matrix circuit including a first plurality of thin film transistors, and using a Chinese paper standard (CNS &gt; A4 specification ( 210X297 mm) _ 5-~ '' Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives printed A8 B8 C8 D8 々, the patent application scope is molded on the insulating surface of the first substrate; a drive circuit, including a second A plurality of thin film transistors are formed on the insulating surface of the first substrate to drive the active matrix circuit. A second substrate faces the first substrate with a liquid crystal material therebetween, and the first substrate has an extension. The portion is extended beyond at least one side edge of the second substrate; at least one semiconductor integrated circuit wafer is located on the extended portion of the first substrate and is operated to be in contact with the driving circuit Connection, wherein the first and second plurality of thin film transistor systems are formed from a common semiconductor film, the film is formed on the first substrate, and each of the first plurality of thin films is formed The crystal has at least one micro-doped attractor between a channel region and an attractor region. 25. The liquid crystal display device according to item 24 of the patent application, wherein the semiconductor film includes polycrystalline silicon. The liquid crystal display device of item 24, wherein the semiconductor integrated circuit chip is a memory. 27. For the liquid crystal display device of item 24 of the patent application scope, wherein the semiconductor integrated circuit chip is a c P u. — 28. -A liquid crystal display device comprising:-a first substrate having an insulating surface;-an active matrix circuit including a first plurality of thin film transistors formed on the insulating surface of the first substrate; a driving circuit including a driving circuit for driving the active The second plurality of thin-film transistors formed on the insulating surface of the first substrate by a rectangular circuit; This paper size is applicable to China National Standard (CNS) A4 specification (210 father 297 male &quot; ^) (Please read the back first (Notes for filling in this page) Printed by the Consumers 'Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A8 Βδ C8 _. _ D8 VI. Patent application scope-A second substrate, sandwiched by a liquid crystal material and facing the first substrate' the first substrate has an extension exceeding An external part of at least one side edge of the second substrate; at least one semiconductor die circuit chip disposed on the external part of the first substrate and operatively connected to the driving circuit, wherein each of the first The thin film transistor system is a bottom-type transistor, and an electrode is arranged at the bottom of the area where the transistor is passed, and each of the second majority of thin film transistor systems is a top-gate transistor, and has been The electrode is arranged above the access area of the transistor. 29. A liquid crystal display device as described in item 28 of the scope of patent application, wherein each channel region of the first majority of thin film transistors is amorphous, and each of the second majority of thin film transistors has a channel region. The channel region is crystalline. 30. A liquid crystal display device comprising: a first substrate having an insulating surface; an active matrix including a first plurality of thin film electrodes formed on the insulating surface of the first substrate A crystal; a driving circuit including a second plurality of thin-film transistors formed on the insulating surface of the first substrate as the driving matrix circuit; a second substrate facing the first substrate with a liquid crystal material interposed therebetween A substrate, the first substrate having an external portion extending beyond at least one side edge of the second substrate; at least one semiconductor integrated circuit chip disposed on the external portion of the first substrate and operatively connected to the first substrate Drive circuit '_ This paper size is applicable to China National Standard (CNS) A4 specification (210x 297 mm) -7-(Please read the precautions on the back before filling this page) A8 B8. C8 D8 6. The scope of patent application Where the semiconductor substrate circuit chip is selected from the group consisting of correction memory, memory, CPU, and input port · 31. As described in item 30 of the scope of patent application A liquid crystal display device, wherein the channel region of each of the first plurality of thin film transistors is amorphous, and the channel region of each of the second plurality of thin film transistors is crystalline. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs This paper uses the Chinese National Standard (CNS) A4 specification (210X297) 逋 8-