CN1248318C - Electronic device with non-luminous display - Google Patents
Electronic device with non-luminous display Download PDFInfo
- Publication number
- CN1248318C CN1248318C CN 01135491 CN01135491A CN1248318C CN 1248318 C CN1248318 C CN 1248318C CN 01135491 CN01135491 CN 01135491 CN 01135491 A CN01135491 A CN 01135491A CN 1248318 C CN1248318 C CN 1248318C
- Authority
- CN
- China
- Prior art keywords
- grid
- semiconductor device
- forms
- film
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
Thin film transistors (TFTs), an active matrix circuit, a driver circuit for driving the active matrix circuit or the like are formed on one substrate. Circuits such as a central processing unit (CPU) and a memory, necessary to drive an electric device, are formed using single crystalling semiconductor integrated circuit chips. After the semiconductor integrated circuit chips are adhered to the substrate, the chips are connected with wirings formed on the substrate by a chip on glass (COG) method, a wire bonding method or the like, to manufacture the electric device having a liquid crystal display (LCD) on one substrate.
Description
The present invention relates to a kind of electronic installation that has such as the non-light emitting type display of LCD, the active matrix circuit that wherein on a substrate, has thin-film transistor (TFTs) to constitute.Especially, the active matrix circuit in the electronic equipment of the present invention carries out drive controlling by one drive circuit, and this drive circuit constitutes by being formed on same on-chip TFTS.
Recently, thin and light LCD is used to do the display of various portable electron devices (as personal computer, word processor, electronic memo or the like).Especially the active matrix-type liquid crystal display device of controlling each pixel with TFTS has remarkable display performance, so it is widely used in the many kinds of electronic installations.
Active matrix-type liquid crystal display device has polytype.First kind of display (first kind) has an active matrix circuit that is made of TFTS and its drive circuit, and this drive circuit is that the single crystal semiconductor integrated circuit (IC) chip by the outside constitutes.Owing in this component unit, must semiconductor chip and its part semiconductor shell round glass substrate be coupled together, so display is relatively big with TAB (automatic splicing tape) etc.And, because the lead-in wire live width (interconnection) stretched of active matrix circuit will reduce, improving gap (slit) ratio, and, therefore aspect the connection that goes between technical difficulty is being arranged because the lead-in wire sum surpasses 1000.And the coupling part need take than large tracts of land.Because thermal coefficient of expansion between the lead-in wire in lead-in wire and the external chip in the glass substrate, go between in the glass substrate and the belt of TAB between thermal coefficient of expansion be mutually different, require alignment precision to be approximately 60 μ m.Therefore, it can not be used for pixel and be spaced apart 60 μ m or littler high resolution display, and can not realize the further miniaturization of display, the non-crystalline silicon tft that causes this display will use low temperature to make.
Another kind of (second class) display has a thin film integrated circuit, and this integrated circuit includes and is formed on active matrix circuit and the drive circuit that same on-chip TFTS constitutes, such as X-decoder/driver and Y-decoder/driver.Owing to do not use the semiconductor chip of said external type in this display, so display is smaller.Owing to do not need to connect many lead-in wires, therefore have superiority aspect the display miniaturization.In this display, must adopt the TFTS of the silicon crystal formation of its drive circuit superior performance.
Therefore, aspect the display miniaturization, second class display is better than first kind display.But second class display also is difficult to do attenuate, loss of weight and miniaturization further.That is to say, in personal computer, various semiconductor chips such as CPU (CPU), main storage, the picture intelligence processing unit, video memory or the like is formed on the main substrate (mainboard) outside the LCD plates, so must use two substrates or circuit board (mainboard and display board) at least.In order further to make the display miniaturization, attenuate and loss of weight need to replace two boards with a plate.
At least one substrate that the present invention is placed in LCD by the semiconductor chip with above-mentioned mainboard finished miniaturization, attenuate and the loss of weight of display, and the liquid crystal material of LCD wherein is sandwiched between two substrates.These chip preparations have on the substrate of active matrix circuit.And the drive circuit that drives active matrix circuit is made of thin-film transistor (TFTS).
According to the present invention, a kind of electronic installation that provides comprises: a substrate; One contains the active matrix circuit of a thin-film transistor at least; Contain the drive circuit that another thin-film transistor at least is used to drive this active matrix circuit; Be used to control the semiconductor integrated circuit chip of this drive circuit with at least one, active matrix circuit wherein, drive circuit and semiconductor integrated circuit chip are formed on this substrate.
Fig. 1 is the block diagram of an electron-optical arrangement;
Fig. 2 is the example that lead-in wire connects;
Fig. 3 is the schematic diagram of the present invention the 1st and the 2nd embodiment display panels;
Fig. 4 A and 4B have represented the example of FCOG;
Fig. 5 A to 5G has represented to make among the embodiment 3 process of TFT circuit board;
Fig. 6 A to 6G has represented to make among the embodiment 4 process of TFT circuit board;
Fig. 7 A to 7D has represented to make among the embodiment 5 process of TFT circuit board;
Fig. 8 A to 8I and 9A to 9I have represented to make among the embodiment 6 process of TFT circuit board:
Figure 10 A to 10C is respectively top view, cutaway view and the circuit diagram thereof of the TFT circuit board among the embodiment 6; And
Figure 11 A to 11D has represented to make among the embodiment 7 process of TFT circuit board.
Fig. 1 has represented basic principle of the present invention.Wherein, each pixel all contains the active matrix circuit 14 of a thin-film transistor (TFT) 11, a pixel capacitors 12 and an auxiliary capacitor 13 such one group of pixel, be made of the TFTS on the glass substrate 15 with its drive circuit that is used to drive this active matrix circuit 14, glass substrate wherein is also as liquid crystal display substrate.Drive circuit has 75, one Y-decoder/drivers 76 of an X-decoder/driver and an X-Y separator 74.Drive circuit can comprise X-Y separator 74, but the X-Y separator also can be included in the chip.
Drive the circuit of active matrix circuit, promptly external circuit can constitute with the TFTS that has with the basic identical structure of active matrix circuit.Essentially identical structure represent gate electrode material, door insulating film material and passage form district's material have at least one with used consistent of active matrix circuit.And this external circuit can constitute with the complementary type circuit, has only N-road type TFT (not adopting P-road type TFT), and P-road type TFT is perhaps only arranged.So, constituted the circuit that adopts TFT.
Other chip also prepares on substrate 15.These chips by terminal conjunction method, comprise and adopt the glass-based chip methods such as (COG) of glass-based flip-chip (FCOG) to be connected with circuit on the substrate 15.In Fig. 1, patch memory 71, memory 73, CPU (CPU) 72 and input port 70 can be the chips of method for preparing, also can be the chips of other kinds of preparation.
In terminal conjunction method, can obtain the cross sectional shape among Fig. 2.That is: chip 22 is installed on the glass substrate 20 by a contact portions that forms up 23, on this glass substrate 20 circuit is arranged, and the contact electrode 21 of this circuit divides 23 to be connected by metal bond lead-in wire 24 with the power part of chip 22.With resin 25 sealing (coverings) this part, avoid extraneous with the protection coupling part and collide.For the connection of permanent retaining contact or bonding, what the surface of contact electrode 21 need be with metal as aluminium.In terminal conjunction method, because resin 25 exceeds the contact coupling part widely, so resin 25 is thicker.
In the FCOG of Fig. 4 A and 4B, chip 42 is placed on the glass substrate 40 by the contact portions that forms down, preparation has a circuit on this glass substrate 40, and the contact electrode 41 of this circuit is connected with the contact portions down of chip 42 by a thrust 44 (Fig. 4 A) or metal particle 46 (Fig. 4 B).This part is sealed with resin 45, so that chip 42 is fixed on the substrate 40.Like this, because contact coupling part thickness is suitable with chip thickness basically, thereby can make thin display.Material except that aluminium, (ITO (indium tin oxide target) or the like) can be used for the contact on the glass substrate as transparent conductive oxide film.Usually, when being formed on the active matrix circuit of LCD on the glass substrate, owing to all constitute the superiors' lead-in wire under many situations with transparent conductive oxide film, so FCOG has its superiority at this this respect.
Fig. 3 is the schematic diagram of present embodiment LCD panel.In Fig. 3, substrate (circuit board) 29 is staggered relatively with substrate (circuit board) 30, and liquid crystal material is sandwiched between substrate 29 and 30.Active matrix circuit 31 and the external drive circuit 32 to 34 that is used to drive this active matrix circuit 31 are made of as the TFTS on the glass substrate substrate 30.And, main storage chip 36, MPU (microprocessing unit) 37 or CPU (CPU) reach patch memory 38 and are bonded on the substrate 30 with circuit 31 to 34, and be electrically connected with circuit 31 to 34.When linking chip on the substrate, be formed with the lead-in wire end (lead-in wire connection welding) 39 (corresponding) of ITO material in 35 parts of substrate 30 with the lead portion 41 of Fig. 4 A and 4B by FCOG.
In this embodiment, adopted the tie point that shape shown in Fig. 4 A and the 4B is arranged.In Fig. 4 A, conductive prominence (protrusion) 44 is formed on the electrode part 43 of chip 42, and is electrically connected with lead portion 41 on the substrate 40, with organic resin 45 chip 42 is fixed on the substrate 40.The gold that electroless coating forms can be used as protrusion 44.
In Fig. 4 B, chip 42 is by being mixed with electrically conductive particles, adheres on the substrate 40 as the organic resin 45 of golden particulate 46.So, be distributed in conduction (metal) particulate 46 contact lead-wire parts 41 between chip 42 and the electrode part 43 by allowing, circuit is coupled together.Be used for bonding organic resin 45 and can adopt photocurable resin, thermic cured resin, spontaneous curing resin or the like.Glue after the chip, liquid crystal material is injected in the LCD.
After above-mentioned steps is finished, CPU and memory are formed on the substrate of LCD, so that constitute the electronic equipment such as personal computer with a substrate.
[embodiment 2]
Prepare the panel of Fig. 3.Active matrix circuit 31 and external drive circuit 32 to 34 are made of the TFTS on the substrate 30.Main storage chip 36, MPU37 (or CPU), and patch memory 38 is bonded on substrate 30 surfaces that are formed with circuit 32 to 34, and be electrically connected with the lead-in wire end (lead-in wire connection welding) 39 (corresponding with termination electrode 21) of aluminum alloy films, and these chips are to be formed on the substrate 40 with the terminal conjunction method among Fig. 2.Golden fine rule is used as this bonding wire.
[embodiment 3]
With FCOG chip is adhered on TFT circuit (monolithic type active matrix circuit) plate, to constitute further improved circuit.Making the process of monolithic type active matrix circuit will utilize Fig. 5 A to 5G to be described hereinafter.Thickness is that the silicon oxide film of 1000 to 3000 has constituted the basic oxide-film 502 on the substrate (healthy and free from worry 7059) 501.The method that forms this oxide-film can be included in and contain sputter in the oxygen air, perhaps plasma CVD (chemical vapor deposition) film forming.
Forming thickness with plasma CVD or low pressure chemical vapor deposition (LPCVD) is 300 to 1500 , is preferably amorphous or the crystal film of 500 to 1000 .In order to form crystalline silicon film, after having formed amorphous silicon film, with laser or be equivalent to the strong illumination (photo-annealing) of laser, perhaps carry out thermal annealing and continue one long period at 500 ℃ or higher temperature.After the thermal annealing crystallization, photo-annealing can be done further perfect to crystal.In the thermal annealing crystallization process, can add a kind of element (catalytic elements) to promote the crystallization of silicon.
The etching silicon fiml is with the external drive circuit TFT active layer 503 that forms island areas and 504 and active matrix circuit TFT active layer 504.Then, in containing the oxygen air, form the thick silicon oxide film of one deck 500 to 2000 as gate insulating film 506 by sputter.The method that forms gate insulating film 506 also comprises the plasma CVD method.
Gate insulating film should have sufficiently high withstand voltage.This is because in anode oxidation process, will add a big electric field between grid and the silicon active layer.Therefore, under the situation of the silicon oxide film that makes with plasma CVD, preferably use nitrous oxide (N as gate insulating film
2O) or oxygen and single silane (Fig. 5 A).
Forming a layer thickness with sputtering method on substrate is 2000 to 5 μ m, and the aluminium film (containing 0.1 to 0.5wt% scandium) that 2000 to 6000 are preferably etches grid (or grid line) 507 to 510 then.Grid line 509 designs for being connected with anodic oxidation lead-in wire (not shown).The grid 507 of outer logical circuit and 508 and anodic oxidation lead-in wire be electrically insulated from one another, (Fig. 5 B).
Substrate is immersed in the electrolytic solution, by allowing oxidation current flow through grid 509 and grid 510 makes its anodic oxidation.Anodic oxidation condition has been disclosed in the open 5-267 of Japan Patent, in 667.So, on the upper surface of grid line 509 and grid 510 and side surface, will form anodic oxide 511 and 512.Anodic oxide 511 and 512 thickness depend on added voltage, and present embodiment is thick to be 2000 .
In near neutral solution, the resulting anodic oxide of anodic oxidation is careful and hard and have very high withstand voltage.This is withstand voltage to equal and is higher than 70% of maximum voltage that anode oxidation process adds.This anodic oxide is called the barrier type anodic oxide, (Fig. 5 c).
By ion doping, as partly aiming at mask, impurity is imported in island TFT active layer 503 and 504 with grid part (anode oxide film around grid and the grid).In this doping process, with hydrogen phosphide (PH
3) as impurity gas phosphorus is imported after the whole surface, cover TFT active layer 503 with resist, and with diborane (B
2H
6) for impurity gas boron is imported in TFT active layer 504 and 505.Dosage is: phosphorus 4 * 10
14To 4 * 10
15Atomicity/centimetre
2With boron 1 * 10
15To 8 * 10
15Atomicity/centimetre
2The dosage of boron is bigger than phosphorus.So formed N-type district 513 and P- type district 514 and 515, (Fig. 5 D).
With laser (wavelength 248nm, the N pulse duration 20ns) irradiation of KrF laser, become bad to improve because of impurity imports to the crystal property that causes in the doped region.The energy density of this laser be 200 to 400 millis burnt/centimetre
2, 250 to 300 milli Jiao/centimetre
2For suitable.So N-type district and P-type district are activated.These regional face resistance are 200 to 800 ohm-sq.This process can be finished by thermal annealing in the heat-resisting scope of grid.
With the plasma CVD method silicon oxide film that to form a thickness be 3000 to 6000 as intermediate insulating layer 516.The silicon nitride film of sandwich construction (or silicon oxide film) can be used as intermediate insulating layer with silicon nitride film.With this intermediate insulating layer 516 of Wen Kefa etching, in N-type and P-type zone, to form contact hole 517 and 519.Simultaneously, in grid (grid line) 509, form hole 520.Because anode oxide film 511 is barrier layers, thus etching prevented, thereby grid line 509 is not etched away, (Fig. 5 E).
Then, in contact hole, form the pattern of contact hole 520, then with the etching agent that contains chromic acid,, carry out etching, to form contact hole 521, (Fig. 5 F) such as the mixed solution of chromic acid (1 to 5%) with phosphoric acid (perhaps nitric acid, or acetate) by photoetching.
Forming thickness with sputtering method is the titanium film of 2000 to 6000 , forms external circuit, the data wire 525 of active matrix circuit and the contact conductor 522 to 524 of pixel TFT electrode through etching then.Lead-in wire 523 is connected with grid line 509.
Forming thickness with sputtering method is the ITO film of 500 to 1500 , etches pixel capacitors 527 then.The silicon nitride film 528 that forms a layer thickness and be 1000 to 3000 is as passivating film.So outer logic circuit has been integrated into active matrix circuit, (Fig. 5 G).
Etch away the silicon nitride film 528 that is connected place, end (corresponding to part 41) with the external integrated chip, to expose the ITO lead solder-joint of junction, end.Integrated circuit (IC) chip is adhered to by FCOG among Fig. 4 A and the 4B.
[embodiment 4]
Integrated circuit (IC) chip adhered to the method on the TFT circuit substrate that contains the monolithic type liquid crystal display active matrix circuit that FC0G constitutes, will make description in conjunction with Fig. 6 A to 6G.Cmos circuit is used as external circuit.Represent external circuit TFT with NTFT, outer logic circuit is illustrated in the left side, and active matrix circuit is illustrated in the right side.
With the plasma CVD silica basement membrane 602 that to form a thickness on glass substrate be 2000 .Unstrpped gas is single silane (SiH in the plasma CVD
4) and nitrous oxide.Substrate temperature was 380 to 500 ℃ when film formed, such as 430 ℃.The silicon oxide film 602 that forms has lower etch rate, and harder.This is because nitrous oxide is done unstrpped gas, can obtain containing the oxide/nitride silicon fiml of 1 to 10% nitrogen.Because of acetate add buffer hydrofluoric acid (ABHF) (hydrofluoric acid: ammonium fluoride: acetate=1: 50: 50), under 23 ℃ of conditions common etch rate be 800 to 1100 /minute.
Forming thickness with plasma CVD is the amorphous silicon film of 500 .Thermal annealing 1 hour under 550 ℃ of temperature in containing the oxygen air is to form the silicon oxide film that one deck (is estimated about 40 to 100 ) as thin as a wafer on the amorphous silicon film surface.Use spin-coating method, utilize nickel acetate solution formation one deck nickel acetate film as thin as a wafer of 1 to 100ppm.At first, on amorphous silicon film, form the thin silicon oxide film of one deck, so as on the amorphous silicon film surface coating solution.
Thermal annealing 4 hours under 550 ℃ of temperature in nitrogen containing atmosphere.Under about 400 ℃ of temperature, decompose nickel acetate, to obtain nickel simple substance.Because the nickel acetate film comes down to be bonded on the amorphous silicon film, so thermal annealing is diffused in the amorphous silicon film nickel.So amorphous silicon film has been formed the silicon metal district by crystallization.
Light (wavelength 308nm) irradiation silicon fiml with the Xecl laser.The energy density of this laser be 250 to 300 millis burnt/centimetre
2, in order that allow the silicon fiml degree of crystallinity of crystallization be further enhanced.In order to alleviate the overstrain that laser radiation causes, thermal annealing 4 hours under 550 ℃ of temperature once more.
The etching silicon fiml forms island active layer 603 and 604.Form 1200 thick silicon oxide film 605 as gate insulating film by sputter.
Form the thick aluminium film of 4000 (containing 0.2 to 0.3wt% scandium) by sputter.This surface forms the thick pellumina (not shown) of one deck 100 to 300 through anodized.Owing to exist pellumina, aluminium film and photoresist can be bonding well.And, can prevent photoresist electric leakage, locate so that in following anode oxidation process, make the porous type anodic oxide be formed on grid avris etc. well.
(as: product of Tokyo OHKA Co., Ltd, OFPR800/30CP) spin coating is good, forms grid 609 and 611 and the pattern of grid line 610 then photoresist.The grid 609 of external circuit and grid line 610 are electric insulations with the grid 611 of active matrix circuit.During the etching, photoresist (mask) 606 to 608 plays a role, (Fig. 6 A).
Under the situation that keeps photoresist 606 to 608, allow electric current flow through grid line 610 and grid 611, form porous anodic oxide 612 and 613 with avris at grid line 610 and grid 611.Such as citric acid, oxalic acid, phosphoric acid, the solution of chromic acid or sulfuric acid can be used for anode oxidation process.Institute's making alive is 10 to 30V on the grid.In this embodiment, in oxalic acid solution (pH=0.9 to 1.0,30 ℃), add the anodized that 10V voltage carries out 20 to 80 minutes.The thickness of anodic oxide is controlled by anodizing time.Through the anodized of peracid solutions, just formed porous anodic oxide.The thickness of porous anodic oxide is 3000 to 10000 , such as, 5000 , (Fig. 6 B).
Remove photoresist 606 after 608, allow electric current flow through grid line 610 and carry out the barrier layer anodic oxidation, with form at the upper surface of grid line 610 and grid 611 and avris 1200 thick carefully stop stratotype anodic oxide coating 614 and 615, (Fig. 6 C).
, do and carve etch silicon oxide-film 605 as mask with porous anodic oxide 612 and 613, to form gate insulating film 616 to 618.This etching method comprises the plasma pattern of isotropic etching or the ionic reaction etch mode of anisotropic etching.Should be noted that making effective layer by the separation rate of making great efforts raising silicon and silica is not very important by overetch.When using CF
4During as etching gas, have only silicon oxide film 605 to be etched, and anodic oxide is unaffected.Silicon oxide film 617 and 618 below the porous anodic oxide 612 and 613 is not etched yet, and is retained (Fig. 6 D).
Mixed solution with phosphoric acid, acetate and nitric acid only carries out etching to porous anodic oxide 612 and 613.And barrier layer anodic oxide 614 and 615 is hardly by this mixed solution etching.Because this mixed solution can etching aluminium, thus to make mask to outside circuit part with photoresist, with the grid 609 of protection external circuit part.So, then carry out photoetching treatment with reference to embodiment.
By grid level film 616 and 618 is carried out ion doping, impurity (phosphorus and boron) is imported in the active layer.Although only show NMOS among the figure, also can mix boron.In mixing the phosphorus process, accelerating voltage lower (10 to 30Kev), dosage then big (5 * 10
14To 5 * 10
15Atomicity/centimetre
2).Because accelerating voltage is low,, thereby phosphorus is entered into exposing the main region 619 and 620 of silicon layer so the iontophoresis degree of depth is just shallow.
With lower dosage 1 * 10
12To 1 * 10
14Atomicity/centimetre
2Import phosphorus with higher accelerating voltage 60 to 95Kev.Because accelerating voltage height, the iontophoresis degree of depth are just dark, cause phosphorus to enter into the zone 621 that gate insulating film covers.So, formed high concentration phosphorus doped regions 619 and 620, and low phosphorus doped regions 621.That is: in pixel TFT, can obtain to be called the structure of two drain electrodes.For boron, can handle in the same way.
Under 450 ℃ of temperature, carry out 1 hour thermal annealing, the impurity that mixes with activation.Promote element owing to do crystallization, so can activate (Fig. 6 E) with the temperature that is lower than general activation processing with nickel.
Form multilayer film 622 by plasma CVD, be used as first inner insulating layer, do quarter then, to form contact hole 623 to 627, (Fig. 6 F) with silicon oxide film (200 are thick) and silicon nitride film (4000 are thick).
Contain titanium (500 are thick) with the sputter coating handle, the three-layered metal film of aluminium (4000 are thick) and titanium (500 are thick), etching forms contact conductor 628 to 631 again.Plate the thick silicon oxide film of 2000 632 with plasma CVD method again,, and in the drain electrode 631 of pixel TFT, form contact hole, so that form pixel capacitors 633 with ITO as second inner insulating layer.So, can make monolithic type active matrix circuit (Fig. 6 G).
In the above-mentioned substrate that makes, can be contained in integrated circuit (IC) chip the ITO lead solder-joint place of end (counterpart 41), this place links to each other with the external integrated chip with FCOG among the 4B by Fig. 4 A and adheres to.
[embodiment 5]
With terminal conjunction method adhesive die attachment to TFT circuit (monolithic type active matrix circuit) substrate, from but constitute an improved circuit.Fig. 7 A to 7D has represented to make the process of present embodiment active matrix circuit.In Fig. 7 A to 7D, the left side is an outer logic circuit, and the right side is the active matrix circuit district.
By sputter, go up the oxide basement membrane 701 of plating one bed thickness 2000 at glass substrate (not shown).On oxide basement membrane 701, form the thick ITO film of one deck 500 with sputtering method again, etch the lead-in wire 702 to 704 in outer logic circuit district and the pixel capacitors 706 and the lead-in wire 705 in active matrix circuit district then.
With single silane or disilane as unstrpped gas, with plasma CVD or LPCVD method form one thick be that 500 to 1500 are with amorphous silicon film.The concentration of oxygen suits 10 in the amorphous silicon film
18Atomicity/centimetre
3Or still less.
Mix hydrogen phosphide and boron with the ion doping method that is similar in the known CMOS making.That is, after phosphorus is impregnated in, mask is carried out in the zone that forms N-channel-style TFT, then boron is doped in the zone that is formed with P-channel-style TFT with photoresist.
The impurity gas of Doping Phosphorus is hydrogen phosphide (PH
3), and the used impurity gas of doped with boron is diborane (B
2H
6).The accelerating voltage of phosphorus and boron is suitably 5-to 30KV.The dosage of phosphorus is 1 * 10
14To 5 * 10
15Atomicity/centimetre
2, be suitably 2 * 10
14Atomicity/centimetre
2, and the dosage of boron is 5 * 10
14Atomicity/centimetre
2
The part (source electrode with drain electrode between) that each TFT passage forms the district is etched, with formation N-N-type semiconductor N district 707,708,711 and 712 and P-N-type semiconductor N district 709 and 710.Use plasma CVD method, forming thickness on these zones is 100 to 500 , for example is the intrinsic amorphous silicon hydride film 713 of 200 .
In Fig. 7 A, the light (wavelength 248nm, pulse duration 20ns) of using the KrF laser is to shining with film 713 discontiguous non-sticky masks 714, so that outside circuit region (left side) crystallization in the film 713.The energy density of laser be 200 to 400 millis burnt/centimetre
2, 250 to 300 milli Jiao/centimetre
2Preferably.Because laser do not shine the zone (comprising the active matrix circuit district) that mask 714 is blocked, thus should keep the amorphous silicon state in the zone, and the zone that laser radiation is arrived, not only film 713 but also zone 707 to 710 are all by crystallization.
Silicon fiml (N-type and P-N-type semiconductor N district 707 to 710 and intrinsic silicon films 713) is etched to the island shape, to form the island areas 721 to 723 of external circuit.Simultaneously, source electrode 715 among the outer logic circuit N-channel-style TFT and drain electrode 716, source electrode 718 among the outer logic circuit P-channel-style TFT and drain electrode 717, and the source electrode among the active matrix circuit N-channel-style TFT 719 also is formed (Fig. 7 B) with drain electrode 720.
With nitrous oxide (N
2O) and oxygen (O
2) as raw material, form the silicon oxide film 724 of thickness 1200 with plasma CVD method.Because film 724 is made gate insulating film or keep capacitor dielectric to use, so this film must have enough low phase boundary potential density and high withstand voltage.In the present embodiment, single silane and nitrous oxide are introduced in the reaction vessel under 10SCCM and 100SCCM situation respectively.The base stage temperature is 430 ℃, and reaction pressure is 0.3Torr, and power supply is 13.56MHZ 250W.These conditions depend on used reaction unit.
Formed silicon oxide film 724 under the above-mentioned condition, the speed of its formation be about 1000 /minute.When adopting hydrofluoric acid, during solution that acetate and ammonium fluoride mix by 1: 50: 50 ratio, etching speed be about 1000 /minute.Plating a bed thickness with sputter is 2000 to 8000 , as the titanium film of 3000 , etches electrode 725 to 727 then and keeps capacitance electrode 728.
Forming thickness with plasma CVD method is 3000 silicon nitride films 729, as passivating film.So, the N-channel-style of outer logic circuit crystalline silicon and P-channel-style TFTS (outside P-Si N-ch TFT and outside P-Si, P-ch TFT) and the N-channel-style non-crystalline silicon tft of active matrix circuit (pixel a-si N-ch TFT) and keep electric capacity can be formed (Fig. 7 C).
The TFT structure of outer logic circuit can be different from active matrix circuit.Such as, the misconstruction among Fig. 7 D, wherein its grid of the TFT of active matrix circuit is formed on and opens X of drain electrode position at interval partially, thereby can further reduce breaking current.
In order to realize the high-speed cruising identical with outer logic circuit speed, semiconductor should be a crystal, and source electrode and drain electrode also should be that crystal and film resistor resistance are low.Although prepare outer logic circuit by laser irradiation, because passage forms all crystal changes of district and source electrode and the corresponding part of drain electrode, so requirement can be met.In order further to improve the degree of crystallinity of source electrode and drain electrode, can be by 1 * 10
17To 2 * 10
19Atomicity/centimetre
3Concentration, in silicon fiml, add in order to promoting the catalytic elements of amorphous silicon crystallization, as nickel, platinum, palladium, cobalt or iron.
In the above-mentioned substrate that makes, the place, end (corresponding to part 21) that links to each other with the external integrated chip, silicon nitride film 729 is etched away, and exposes the titanium lead solder-joint of coupling part, termination, and couples together with terminal conjunction method among Fig. 2 and integrated circuit (IC) chip.
[embodiment 6]
Fig. 8 A to 8I has represented the cross section of active matrix circuit part, and Fig. 9 A to 9I has represented the cross section of external circuit part.Figure 10 A is the top view of the active matrix circuit that makes, and Fig. 8 I and Fig. 9 I are the sectional views along Figure 10 A-B-C line, and Figure 10 B represents along the cross section of Figure 10 Aa-b line.Figure 10 C has represented the circuit layout of gained active matrix circuit.
At first, on the insulating surface 801 of glass substrate, form grid lead 802 to 805, on this substrate, form the thick silicon nitride film (not shown) of 1000 .By the etch polysilicon film, form grid lead, and polysilicon film has reduced because of the doping resistance of phosphorus, and thickness is 3000 .This polysilicon film forms with the low pressure chemical vapor deposition method and maintenance polycrystalline attitude in this film forming process.
For obtaining polysilicon film, following method can replace said method.Promptly after forming intrinsic amorphous silicon, will import in the silicon fiml such as the impurity of phosphorus through methods such as ion dopings with plasma or low pressure chemical vapor deposition method.Again through 500 to 600 ℃ thermal annealing.When thermal annealing, crystallization promotes element, as nickel, can add micro-ly.In the present embodiment, employing is silicon.Also can be with the silicide of various metals.
Form 3000 to 6000 with plasma CVD method, as the thick silicon nitride film 806 of 4000 , with it as gate insulating film.Form 300 to 1000 with plasma CVD method, as the thick amorphous silicon film of 500 , etch island shape silicon area 807 to 809 then, (Fig. 8 A and 9A).
Also can form 3000 to 6000 , as the thick silicon nitride film 810 of 2000 , as gate insulating film with plasma CVD method.With laser radiation external circuit part, make island film 808 and 809 crystallizations.The laser that this laser sends for the Xecl laser (wavelength 308nm).The radiant energy density of this laser and umber of pulse according to silicon fiml 808 and 809 and silicon nitride film 810 become.
Etch silicon nitride film 806 and 810 forms the contact hole (not shown) that reaches the first grid lead-in wire deeply.This contact hole is used to constitute contacting between first grid line and second grid line, and second grid line is formed on first grid line and is corresponding with contact portion 845, shown in Figure 10 A and 10B.
Form after the contact hole, form 3000 to 8000 by sputter, as the thick aluminium film 811 of 5000 .When aluminium film 811 contains 0.1 to 0.5wt% scandium (Sc), can prevent the generation of hillock, (Fig. 8 B and 9B).
In electrolytic solution, add an electric current at second grid lead-in wire 812 to 815.Can adopt 6.8 to 7.2pH values, and by ammoniacal liquor being added the glycol solution that makes in 3 to 10% the winestone acid solution.When solution temperature during, can form oxide film of high quality than low about 10 ℃ of room temperature.So, form anodic oxide barrier layer 816 to 819 at the upper surface and the side surface of second grid lead-in wire.The thickness of anodic oxide is proportional to institute's making alive, is suitably 1000 to 3000 .When 150V, will form the thick anodic oxide of 2000 .For obtaining 3000 or thicker anodic oxide, just must add 250V or higher voltage.But this can influence the characteristic of TFT, (Fig. 8 D and 9D).
With method at dried quarter, autoregistration ground etch silicon nitride film 810.But because etching anodic oxide 816 to 819 not, so gate insulating film 820 and 823 is retained between second grid line 812 to 815 and the island silicon fiml 807 to 809 (Fig. 8 E and 9E).
Utilize grid part (anodic oxide 817 to 819 around grid 813 to 815 and this grid) autoregistration N-type and P-type impurity to be incorporated in the island silicon fiml 807 to 809 in the ion doping mode, to form N-type doped region (source/drain regions 0824 to 827 and P-type doped region 828 and 829.Impurity gas in the N-type doping impurity process is hydrogen phosphide (PH
3), the impurity gas in the P-type doping impurity process is Boroethane (B
2H
6).Dosage is 5 * 10
14To 5 * 10
15Atomicity/centimetre
2, quicken the erosion amount and be 10 to 30kev.With the irradiation of the laser (wavelength 248nm, pulse duration 20ns) of KrF laser, import to foreign ion in the silicon fiml 807 to 809, (Fig. 8 F and 9F) to activate ripple.
On whole surface, form the thick metal film 830 of 50 to 500 with sputtering method, as titanium film, (Fig. 8 G and 9G).
By 450 to 500 ℃, as thermal annealing under 500 ℃ of temperature 10 to 60 minutes, titanium and silicon are reacted, to form silicide (titanium silicide) district 831 to 836.In this thermal annealing process, the impurity that mixes is further activated.Except adopting the thermal annealing that forms silicide, can also carry out the laser annealing of laser radiation, and the lamp anneal of radiation of visible light or near infrared light.
With the etching solution that hydrogen peroxide, ammoniacal liquor and water mix by 5: 2: 2 ratio, etching titanium film 830.Owing to do not remain on metallic state, so be corroded in its erosion process at the moment with the contacted titanium film of active layer (as: being formed on the titanium film on silicon nitride film 806 and the anodic oxide coating) that exposes.On the other hand, titanium silicide can not be etched away, thereby remains, (Fig. 8 H and 9H).
Forming thick with the CVD method on whole surface is the silicon oxide film of 5000 , is used as first inner insulating layer 837.Source electrode and drain electrode at TFT form contact hole.After first inner insulating layer formed, annealing was 10 to 30 minutes under 400 ℃ of temperature, formed aluminium matter contact conductor 838 to 841, and formed the pixel capacitors 842 of ITO film.
In order not allow water, active ion etc. enter in the TFT from the outside, form 2000 to 5000 with plasma CVD method, as the thick silicon nitride film 843 of 3000 , and pixel parts 844 and the port section (not shown) that is being connected external circuit and external integrated chip, then open wide to expose the ITO film, (Fig. 8 I and 9I).
Utilize said process, can form active matrix circuit lead-in wire cross section 847, the TFT848 that is connected with pixel, and N-channel-style TFT849 and P-channel-style TFT850 in the external circuit are to obtain an one chip active matrix circuit.
Figure 10 A is the top view that the TFT of a pixel parts is arranged.Obviously, in Figure 10 A, the grid line that stretches out from scanner driver is a line.But, first grid line 802 be positioned at abreast second grid line 812 below.First and second grid lines interconnect by contact portion 845.A TFT has a contact portion in the active matrix circuit of this embodiment.
Although one of first and second grid lines are dotted lines, be not sliver all below.In this embodiment, shown in Figure 10 A, the component that separates at grid line has a contact portion.This is because this component can not take special space in the weld zone that constitutes contact portion, and must do global optimization.
Figure 10 B has represented that the a-b line that extends along grid line among Figure 10 A cuts out cross section structure.Figure 10 C has represented to have among Figure 10 A the active matrix circuit of one group of single circuit.Grid line 812 and 802 also separately extends to lead-in wire 846 places of stretching below the capable pixel capacitors on top.The lead-in wire 846 and pixel capacitors between an electric capacity is arranged, and with circuit in liquid crystal capacitance that pixel capacitors forms settle in parallel to each other.In the substrate of making, integrated circuit (IC) chip is installed in the ITO end (for part 41) that is used to connect the external integrated chip, and with the FCOG method of Fig. 4 A and 4B integrated circuit (IC) chip is adhered to this place.
[embodiment 7]
Integrated circuit (IC) chip is connected on monolithic type active matrix circuit (TFT circuit) substrate, and this substrate is to have formed active matrix circuit that contains amorphous silicon (a-Si) TFTS and the external circuit that contains crystalline silicon TFTS on same glass substrate.
Figure 11 A to 11D has represented to make the process of present embodiment monolithic type active matrix circuit.Forming thick on glass substrate 901 is that the silicon oxide film of 1000 to 3000 is as oxidation basement membrane 903.With plasma CVD or LPCVD method, deposit 300 to 1500 , as the thick amorphous silicon film 903 of 500 .Then form 50 to 1000 , as the thick silicon oxide film of 200 (or silicon nitride film), with as diaphragm 904 with plasma CVD method.
With the laser radiation (wavelength 248nm, pulse duration 20ns) of KrF laser, to improve the degree of crystallinity of silicon fiml 903.Laser energy density be 200 to 400 millis burnt/centimetre
2, 250 to 300 milli Jiao/centimetre
2Be more suitable for (Figure 11 A).
Remove diaphragm 904, expose silicon fiml 903 and form island-shaped pattern, with the island silicon area 905 of formation N-channel-style TFT and the island silicon area 906 of P-channel-style TFT.Sputter or by decomposing and plasma cvd deposition one deck FEOS in oxygen-containing atmosphere again, and formation gate insulating film 907.
Sputter forms the thick aluminium film of 2000 to 5 μ m, forms grid 908 and 909 through etching again.Simultaneously, the anti-irregular type TFT grid 910 of active matrix part also is formed (Figure 11 B).
Substrate is immersed in the electrolyte, on a grid degree, add an electric current, around this grid, to form anodic oxide coating 911 to 913.The anode oxide film of external circuit TFT (left side) should approach, so that the mobility of kind TFT, and the anode oxide film of active matrix circuit TFT (the anti-irregular type TFT on right side) should be thick in to prevent electric leakage of the grid.In this embodiment, two kinds of anodic oxidation film thicknesses are 2000 to 2500 .(Figure 11 C).
, foreign ion is doped in the island silicon area 905 and 906 of each TFT as self-aligned mask with grid part (grid and the anodic oxide around it).Promptly with hydrogen phosphide (PH
3) be impurity gas, at first phosphorus is imported in the whole surface.Afterwards, only island silicon area 905 usefulness photoresists are made mask, then boron is only imported in the island silicon area 906.The dosage of phosphorus is 2 * 10
15To 8 * 10
15Atomicity/centimetre
2, and the dosage of boron is 4 * 10
15To 10 * 10
15Atomicity/centimetre
2The dosage of boron is bigger than phosphorus.
(wavelength 248nm, pulse duration 20ns) shines with KrF laser, causes that to improve because of impurity imports degree of crystallinity becomes the degree of crystallinity of bad part.Laser energy density be 200 to 400 millis burnt/centimetre
2, be more suitable for be 250 to 300 millis burnt/centimetre
2, (Figure 11 D).
Therefore, N-type district 914 and 915 and P- type district 916 and 917 have been formed.The face resistance in these districts be 200 to 800 Ω/square.
Use plasma CVD method, on whole surface, form the thick silicon nitride film of 3000 as inner insulating layer 918.This silicon nitride film is the inner insulating layer of external circuit.But because the grid of this silicon nitride film double as active matrix circuit TFT, so must carefully make this film.
Forming thick on active matrix circuit grid 910 is 100 to 500 , and as the amorphous silicon film 919 of 200 , the microcrystal silicon layer made from plasma CVD method (500 to 1000 are thick) constitutes source electrode 920 and the drain electrode 921 of amorphous TFT then.In the TFT of active matrix circuit, use transparent conductive material, form pixel capacitors 925 as ITO.
Externally form contact hole in the source electrode of each TFT of circuit part and the drain electrode, so that form aluminium matter lead-in wire 922 to 924.N-channel-style TFT and P-channel-style TFT with the left side make routine circuitry phase.In hydrogeneous atmosphere, under 350 ℃ of temperature, annealed 2 hours, to reduce the dead key of silicon fiml.Utilize said method, external circuit and active matrix circuit have integrated.
In this embodiment, anti-irregular type TFT is used for the non-crystalline silicon tft of active matrix circuit, thereby light can not shine in the channel part.This is because the conductivity of amorphous silicon becomes with illumination.In the substrate that makes, by terminal conjunction method shown in Figure 2, integrated circuit (IC) chip is connected to aluminium matter lead-in wire end (counterpart 21), this aluminum lead is also connecting outside integrated circuit (IC) chip.
Claims (51)
1. semiconductor device, it is included at least one thin-film transistor that forms on the substrate, and described thin-film transistor comprises:
First grid;
First grid dielectric film, it forms on described first grid;
The semiconductor layer that forms on described first grid between them is described first grid dielectric film and place; Described semiconductor layer comprises at least one pair of doped region and insertion channel region therebetween;
Second gate insulating film, it forms on described semiconductor layer;
The second grid that forms on described channel region between them is described second gate insulating film and place;
An interlayer dielectric that comprises silicon nitride, it covers described at least second grid,
Be electrically connected on the pixel capacitors of one of described a pair of doped region,
Wherein, the described channel region of described thin-film transistor is a crystal shape,
Wherein, the edge of the described interlayer dielectric of described pixel capacitors extend through.
2. semiconductor device according to claim 1 is characterized in that: described substrate is a glass substrate.
3. semiconductor device according to claim 1 is characterized in that: a dielectric film that comprises silicon nitride, it forms under described first grid.
4. semiconductor device according to claim 1 is characterized in that: described first grid comprises silicon or metal silicide.
5. semiconductor device according to claim 1 is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
6. semiconductor device with active matrix circuit and external circuit, active matrix circuit comprises the first film transistor on the substrate, and external circuit comprises second thin-film transistor on this substrate, is used to drive described active matrix circuit; Each described first and second thin-film transistor comprises:
First grid;
First grid dielectric film, it forms on described first grid;
The semiconductor layer that forms on described first grid between them is described first grid dielectric film and place; Described semiconductor layer comprises at least one pair of doped region and insertion channel region therebetween;
Second gate insulating film, it forms on described semiconductor layer;
The second grid that forms on described channel region between them is described second gate insulating film and place;
An interlayer dielectric that comprises silicon nitride, it covers the second grid of described the first transistor and covers described second thin-film transistor.
7. semiconductor device according to claim 6 is characterized in that: described substrate is a glass substrate.
8. semiconductor device according to claim 6 is characterized in that: a dielectric film that comprises silicon nitride, it forms under described first grid.
9. semiconductor device according to claim 6 is characterized in that: described first grid comprises silicon or metal silicide.
10. semiconductor device according to claim 6 is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
11. a semiconductor device, it is included at least one thin-film transistor that forms on the substrate, and described thin-film transistor comprises:
First grid;
First grid dielectric film, it forms on described first grid;
The semiconductor layer that forms on described first grid between them is described first grid dielectric film and place; Described semiconductor layer comprises at least one pair of doped region and insertion channel region therebetween;
Second gate insulating film, it forms on described semiconductor layer;
The second grid that forms on described channel region between them is described second gate insulating film and place;
An interlayer dielectric that comprises silicon nitride, it covers described at least second grid;
Wherein, this is overlapped to doped region and this first grid,
Wherein, the described channel region of described thin-film transistor is a crystal shape.
12. semiconductor device according to claim 11 is characterized in that: described substrate is a glass substrate.
13. semiconductor device according to claim 11 is characterized in that: a dielectric film that comprises silicon nitride, it forms under described first grid.
14. semiconductor device according to claim 11 is characterized in that: described first grid comprises silicon or metal silicide.
15. semiconductor device according to claim 11 is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
16. a semiconductor device, it is included at least one thin-film transistor that forms on the substrate, and described thin-film transistor comprises:
First grid;
First grid dielectric film, it forms on described first grid;
The semiconductor layer that forms on described first grid between them is described first grid dielectric film and place; Described semiconductor layer comprises at least one pair of doped region and insertion channel region therebetween;
Second gate insulating film, it forms on described semiconductor layer;
The second grid that forms on described channel region between them is described second gate insulating film and place;
An interlayer dielectric that comprises silicon nitride, it covers described at least second grid;
Wherein, described first grid extends beyond the lateral margin of described second grid on orientation,
Wherein, the described channel region of described thin-film transistor is a crystal shape.
17. semiconductor device according to claim 16 is characterized in that: described substrate is a glass substrate.
18. semiconductor device according to claim 16 is characterized in that: a dielectric film that comprises silicon nitride, it forms under described first grid.
19. semiconductor device according to claim 16 is characterized in that: described first grid comprises silicon or metal silicide.
20. semiconductor device according to claim 16 is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
21. a semiconductor device, it is included at least one thin-film transistor that forms on the substrate, and described thin-film transistor comprises:
First grid;
First grid dielectric film, it forms on described first grid;
The semiconductor layer that forms on described first grid between them is described first grid dielectric film and place; Described semiconductor layer comprises at least one pair of first doped region, inserts the channel region between above-mentioned first doped region, and this second doped region to first doped region of a pair of vicinity;
Second gate insulating film, it forms on described semiconductor layer;
The second grid that forms on described channel region between them is described second gate insulating film and place;
An interlayer dielectric that comprises silicon nitride, it covers described at least second grid;
Wherein, this is overlapped to first doped region and described first grid,
Wherein, the described channel region of described thin-film transistor is a crystal shape.
22. semiconductor device according to claim 21 is characterized in that: described substrate is a glass substrate.
23. semiconductor device according to claim 21 is characterized in that: a dielectric film that comprises silicon nitride, it forms under described first grid.
24. semiconductor device according to claim 21 is characterized in that: described first grid comprises silicon or metal silicide.
25. semiconductor device according to claim 21 is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
26. semiconductor device according to claim 21 is characterized in that: described second doped region comprises metal silicide.
27. the semiconductor device with active matrix circuit and external circuit, active matrix circuit comprise the first film transistor on the substrate, and external circuit comprises second thin-film transistor on this substrate, is used to drive described active matrix circuit; Each described first and second thin-film transistor comprises:
First grid;
First grid dielectric film, it forms on described first grid;
The semiconductor layer that forms on described first grid between them is described first grid dielectric film and place; Described semiconductor layer comprises at least one pair of doped region and insertion channel region therebetween;
Second gate insulating film, it forms on described semiconductor layer;
The second grid that forms on described channel region between them is described second gate insulating film and place;
An interlayer dielectric that comprises silicon nitride, it covers the second grid of described the first transistor and covers described second thin-film transistor;
Wherein, in each described first and second thin-film transistor, this is overlapped to doped region and described first grid.
28. semiconductor device according to claim 27 is characterized in that: described substrate is a glass substrate.
29. semiconductor device according to claim 27 is characterized in that: a dielectric film that comprises silicon nitride, it forms under described first grid.
30. semiconductor device according to claim 27 is characterized in that: described first grid comprises silicon or metal silicide.
31. semiconductor device according to claim 27 is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
32. the semiconductor device with active matrix circuit and external circuit, active matrix circuit comprise the first film transistor on the substrate, and external circuit comprises second thin-film transistor on this substrate, is used to drive described active matrix circuit; Each described first and second thin-film transistor comprises:
First grid;
First grid dielectric film, it forms on described first grid;
The semiconductor layer that forms on described first grid between them is described first grid dielectric film and place; Described semiconductor layer comprises at least one pair of doped region and insertion channel region therebetween;
Second gate insulating film, it forms on described semiconductor layer;
The second grid that forms on described channel region between them is described second gate insulating film and place;
An interlayer dielectric that comprises silicon nitride, it covers the second grid of described the first transistor and covers described second thin-film transistor;
Wherein, in each described first and second thin-film transistor, described first grid extends beyond the lateral margin of described second grid on orientation.
33. semiconductor device according to claim 32 is characterized in that: described substrate is a glass substrate.
34. semiconductor device according to claim 32 is characterized in that: a dielectric film that comprises silicon nitride, it forms under described first grid.
35. semiconductor device according to claim 32 is characterized in that: described first grid comprises silicon or metal silicide.
36. semiconductor device according to claim 32 is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
37. the semiconductor device with active matrix circuit and external circuit, active matrix circuit comprise the first film transistor on the substrate, and external circuit comprises second thin-film transistor on this substrate, is used to drive described active matrix circuit; Each described first and second thin-film transistor comprises:
First grid;
First grid dielectric film, it forms on described first grid;
The semiconductor layer that forms on described first grid between them is described first grid dielectric film and place; Described semiconductor layer comprises at least one pair of first doped region, inserts the channel region between described first doped region, and this second doped region to first doped region of a pair of vicinity;
Second gate insulating film, it forms on described semiconductor layer;
The second grid that forms on described channel region between them is described second gate insulating film and place;
An interlayer dielectric that comprises silicon nitride, it covers the second grid of described the first transistor and covers described second thin-film transistor;
Wherein, in each described first and second thin-film transistor, this is overlapped to first doped region and described first grid.
38. according to the described semiconductor device of claim 37, it is characterized in that: described substrate is a glass substrate.
39. according to the described semiconductor device of claim 37, it is characterized in that: a dielectric film that comprises silicon nitride, it forms under described first grid.
40. according to the described semiconductor device of claim 37, it is characterized in that: described first grid comprises silicon or metal silicide.
41. according to the described semiconductor device of claim 37, it is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
42. according to the described semiconductor device of claim 37, it is characterized in that: described second doped region comprises metal silicide.
43. the semiconductor device with active matrix circuit and external circuit, active matrix circuit comprise the first film transistor on the substrate, and external circuit comprises second thin-film transistor on this substrate, is used to drive described active matrix circuit; Each described first and second thin-film transistor comprises:
A semiconductor layer, it comprises at least one pair of doped region and insertion channel region therebetween,
A gate insulating film, its contiguous described semiconductor layer;
The grid of a described channel region of vicinity between them is described gate insulating film and place; And
An interlayer dielectric that comprises silicon nitride, it covers the second grid of described the first transistor and covers described second thin-film transistor;
Wherein, the transistorized channel region of described the first film is an amorphous, and the channel region of described second thin-film transistor is a crystal shape.
44. according to the described semiconductor device of claim 43, it is characterized in that: described substrate is a glass substrate.
45. according to the described semiconductor device of claim 43, it is characterized in that: described grid is to be positioned under the described semiconductor layer.
46. according to the described semiconductor device of claim 43, it is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
47. the semiconductor device with active matrix circuit and external circuit, active matrix circuit comprise the first film transistor on the substrate, and external circuit comprises second thin-film transistor on this substrate, is used to drive described active matrix circuit; Each described first and second thin-film transistor comprises:
First grid;
First grid dielectric film, it forms on described first grid;
The semiconductor layer that forms on described first grid between them is described first grid dielectric film and place; Described semiconductor layer comprises at least one pair of doped region and insertion channel region therebetween;
Second gate insulating film, it forms on described semiconductor layer;
The second grid that forms on described channel region between them is described second gate insulating film and place;
An interlayer dielectric that comprises silicon nitride, it covers the second grid of described the first transistor and covers described second thin-film transistor;
Wherein, the transistorized channel region of described the first film is an amorphous, and the channel region of described second thin-film transistor is a crystal shape.
48. according to the described semiconductor device of claim 47, it is characterized in that: described substrate is a glass substrate.
49. according to the described semiconductor device of claim 47, it is characterized in that: a dielectric film that comprises silicon nitride, it forms under described first grid.
50. according to the described semiconductor device of claim 47, it is characterized in that: described first grid comprises silicon or metal silicide.
51. according to the described semiconductor device of claim 47, it is characterized in that: described interlayer dielectric has the thickness of 2000 to 5000 .
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP329652/94 | 1994-12-02 | ||
| JP329652/1994 | 1994-12-02 | ||
| JP32965294A JPH07209672A (en) | 1993-12-03 | 1994-12-02 | Electronic device with light nonemission type display |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 95121886 Division CN1092803C (en) | 1994-12-02 | 1995-12-01 | Electric device having non-light emitting type display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1395317A CN1395317A (en) | 2003-02-05 |
| CN1248318C true CN1248318C (en) | 2006-03-29 |
Family
ID=18223743
Family Applications (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01135492 Expired - Lifetime CN1237622C (en) | 1994-12-02 | 1995-12-01 | Electronic device with non-luminous display |
| CNB2005101250255A Expired - Lifetime CN100539139C (en) | 1994-12-02 | 1995-12-01 | The electronic installation that non-light emitting type display is arranged |
| CN 95121886 Expired - Lifetime CN1092803C (en) | 1994-12-02 | 1995-12-01 | Electric device having non-light emitting type display |
| CN 01135491 Expired - Lifetime CN1248318C (en) | 1994-12-02 | 1995-12-01 | Electronic device with non-luminous display |
Family Applications Before (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01135492 Expired - Lifetime CN1237622C (en) | 1994-12-02 | 1995-12-01 | Electronic device with non-luminous display |
| CNB2005101250255A Expired - Lifetime CN100539139C (en) | 1994-12-02 | 1995-12-01 | The electronic installation that non-light emitting type display is arranged |
| CN 95121886 Expired - Lifetime CN1092803C (en) | 1994-12-02 | 1995-12-01 | Electric device having non-light emitting type display |
Country Status (2)
| Country | Link |
|---|---|
| CN (4) | CN1237622C (en) |
| TW (3) | TW394922B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002175056A (en) * | 2000-12-07 | 2002-06-21 | Hitachi Ltd | Liquid crystal display |
| JP2005101527A (en) * | 2003-08-21 | 2005-04-14 | Seiko Epson Corp | Electronic component mounting structure, electrooptic device, electronic equipment, and method of mounting electronic component |
| KR101052960B1 (en) * | 2004-04-29 | 2011-07-29 | 엘지디스플레이 주식회사 | Semi-transmissive polysilicon liquid crystal display device manufacturing method |
| CN100405143C (en) * | 2005-05-19 | 2008-07-23 | 友达光电股份有限公司 | Liquid crystal module |
| CN102270415A (en) * | 2010-06-04 | 2011-12-07 | 刘舸 | Built-in system type TFT-LCD (thin film transistor-liquid crystal display) liquid crystal display module |
| CN102331645B (en) * | 2011-10-11 | 2013-11-06 | 信利半导体有限公司 | Liquid crystal display and manufacturing method thereof |
| CN102842586B (en) * | 2012-08-15 | 2019-02-26 | 京东方科技集团股份有限公司 | Display base plate, display panel and display device |
| CN106940506A (en) * | 2017-05-12 | 2017-07-11 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3123616B2 (en) * | 1991-10-09 | 2001-01-15 | キヤノン株式会社 | Liquid crystal display device mounting method |
-
1995
- 1995-11-24 TW TW88101919A patent/TW394922B/en not_active IP Right Cessation
- 1995-11-24 TW TW84112555A patent/TW386222B/en not_active IP Right Cessation
- 1995-11-24 TW TW88101918A patent/TW396329B/en not_active IP Right Cessation
- 1995-12-01 CN CN 01135492 patent/CN1237622C/en not_active Expired - Lifetime
- 1995-12-01 CN CNB2005101250255A patent/CN100539139C/en not_active Expired - Lifetime
- 1995-12-01 CN CN 95121886 patent/CN1092803C/en not_active Expired - Lifetime
- 1995-12-01 CN CN 01135491 patent/CN1248318C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1092803C (en) | 2002-10-16 |
| CN1154488A (en) | 1997-07-16 |
| CN100539139C (en) | 2009-09-09 |
| TW386222B (en) | 2000-04-01 |
| CN1237622C (en) | 2006-01-18 |
| CN1395317A (en) | 2003-02-05 |
| CN1395318A (en) | 2003-02-05 |
| TW394922B (en) | 2000-06-21 |
| TW396329B (en) | 2000-07-01 |
| CN1790710A (en) | 2006-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1249506C (en) | Electronic circuit | |
| CN1249818C (en) | Semiconductor device and manufacturing method for the same | |
| US7081938B1 (en) | Electro-optical device and method for manufacturing the same | |
| CN1106694C (en) | Semiconductor device and method of manufacturing the same | |
| CN1081022A (en) | A kind of semiconductor device and manufacture method thereof | |
| CN1727977A (en) | Thin film transistor array substrate and method of producing the same | |
| CN1143395C (en) | Semiconductor device and its associated ICs | |
| CN1248318C (en) | Electronic device with non-luminous display | |
| JPH07209672A (en) | Electronic device with light nonemission type display | |
| CN1577434A (en) | Thin film semiconductor device and method for producing thin film semiconductor device | |
| CN1811570A (en) | Thin film transistor array panel, liquid crystal display including the panel and manufacturing method thereof | |
| KR100390112B1 (en) | A semiconductor device | |
| CN1933164A (en) | Semiconductor device and a manufacturing method for the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20060329 |
|
| EXPY | Termination of patent right or utility model |