JP2003324105A - Electrode substrate, electrooptic device, manufacturing method of electrode substrate, and manufacturing method of electrooptic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an electrode substrate having no wiring defect and to obtain an electrooptic device having no display defect and having an excellent displaying characteristic, in manufacturing methods of the electrode substrate and the electrooptic device which have wirings made of aluminum materials. <P>SOLUTION: On a substrate 60, a semiconductor layer 1 is formed and a gate insulation film 2 is so formed by etching using BHF whose rate is not higher than 4 nm/second as to cover the layer 1 and the substrate 60 therewith. Then, on the gate insulation film 2, a titanium film 34, a film 35 containing aluminum, and a titanium nitride film 36 are formed in succession. Thereafter, the laminated film comprising the titanium film 34, the film 35 containing aluminum, and the titanium nitride film 36 is so patterned as to obtain wiring 33. By restricting the quality of the gate insulation film in this way, the crystal orienting state of the titanium film is controlled, and the flat aluminum film 35 having favorable crystal quality which is oriented preferentially to a crystal orientation (111) plane can be formed, and further, the wiring wherein the generation of hillock is suppressed can be obtained. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode substrate and an electro-optical device, and more particularly to an electrode substrate and an electro-optical device in which hillock generation is suppressed when a wiring having a laminated structure of titanium and aluminum is provided. Belongs to the device.

[0002]

2. Description of the Related Art Generally, a thin film transistor (hereinafter referred to as TF
T. In the case of an active matrix type liquid crystal device having a switching element as a switching element, an electro-optical material such as a liquid crystal layer is sandwiched between a TFT array substrate and a counter substrate.

Such a TFT array substrate has a plurality of scanning lines and a plurality of data lines arranged to intersect each other on the substrate, and a scanning line and a data line arranged at each intersection of the scanning lines and the data lines. It is composed of a thin film transistor electrically connected and a pixel electrode electrically connected to the thin film transistor. The thin film transistor is configured by disposing a gate electrode, which is in the same layer as the scanning line and electrically connected to the semiconductor layer, with the gate insulating film interposed therebetween. And
A source electrode and a drain electrode, which are in the same layer as the data line, are formed thereover via an insulating film, and the data line and the source electrode are electrically connected.

In the meantime, when the liquid crystal device is used in a device such as a portable information terminal, there has been a strong demand in recent years to reduce its power consumption as much as possible. In order to reduce the power consumption of the TFT array substrate that constitutes the liquid crystal device, it is effective to reduce the resistance of the scanning lines that are wiring. Therefore, attention has been paid to the use of low-resistance aluminum instead of the conventionally used materials such as chromium and tantalum. Since it is necessary to pay attention to heat resistance and chemical resistance of aluminum due to its characteristics, a wiring having a laminated structure in which a titanium layer is arranged as a lower layer of aluminum and a titanium nitride layer is arranged as an upper layer is used.

The TFT array substrate having the wiring having the laminated structure of titanium, aluminum and titanium nitride as described above is formed through the following forming steps.

First, a semiconductor layer to be a channel region made of polysilicon is formed on a glass substrate, and a gate insulating film made of a SiO ₂ film (silicon oxide film) is formed. Next, a titanium film, an aluminum film, and a titanium nitride film are sequentially laminated on the entire surface of the gate insulating film to form a laminated film.
By patterning this laminated film into a predetermined shape, a scanning line having a gate electrode is formed at a position facing the channel region. After that, an insulating film is formed over the gate insulating film so as to cover the scan line and the gate electrode, and over the insulating film,
A source electrode, a drain electrode, and a data line are formed.

[0007]

However, in the TFT array substrate formed by the above-mentioned manufacturing method, there is a problem that even if a titanium nitride layer is laminated on an aluminum layer, protrusions called hillocks are formed. When this hillock occurs, the hillock may break through the insulating film covering the scan line, and the data line and the scan line formed over the insulating film may be short-circuited. When a short circuit occurs, the pixel electrodes electrically connected to the short-circuited scan line and data line cannot perform arbitrary display, and line defects occur in the respective line directions of the scan line and the data line, thus improving the display quality of the liquid crystal device. There was a problem of significantly lowering it.

Regarding the hillocks as described above, Japanese Patent Application Laid-Open No. HEI-1
The following technology is described in 0-135462. That is, focusing on the fact that hillocks increase due to the desorption of water absorbed by the insulating film disposed under the wiring, a film for inhibiting the desorption of water is provided between the wiring and the insulating film. It is a technique of intervening. However, this technique can prevent the increase of hillocks, but cannot solve the fundamental problem itself of hillock generation.

The present invention has been made in view of the above-mentioned problems, and when using a wiring having a titanium layer and a layer containing aluminum, generation of hillocks is suppressed, and a high-quality electrode substrate having no short circuit failure and An object is to provide an electro-optical device.

[0010]

According to the present invention, the crystal orientation plane (0
By using a wiring in which a layer containing aluminum preferentially oriented in the (111) crystal orientation plane is laminated on a titanium layer preferentially oriented in (02), it is possible to form a wiring having good flatness and suppressing generation of hillocks. It was discovered by a person.

That is, the substrate of the present invention has a titanium layer preferentially oriented to the crystal orientation plane (002) formed on the substrate and a crystal orientation plane (1) formed by being formed on the titanium layer.
11) is provided with a wiring in which a layer containing aluminum preferentially oriented is laminated.

According to this structure, the crystal orientation (11
1) It is possible to obtain a layer containing aluminum preferentially oriented in the plane, and it is possible to obtain a wiring which is flat and has good film quality in which hillock generation is suppressed. When a layer containing aluminum has a crystal structure in which a single crystal orientation (111) plane is preferentially oriented, generation of hillocks is small. Since the crystal orientation (111) plane of this aluminum-containing layer has a good interplanar matching with the crystal orientation (002) plane of the titanium layer, a layer containing aluminum on the titanium layer preferentially oriented to the crystal orientation (002) plane. Forming a crystal orientation (111)
A layer containing aluminum with a single preferential orientation in the plane can be obtained. As the layer containing aluminum, there is a simple substance of aluminum, for example, an aluminum alloy such as an alloy of aluminum and copper.

Further, the wiring is characterized in that a layer containing titanium is laminated on the layer containing aluminum. According to such a configuration, there is an effect that the layer containing aluminum can be protected by the layer containing titanium and the generation of hillocks can be further suppressed. When titanium nitride is used, its crystal system is preferably a cubic system to obtain a hillock suppressing effect.

Further, a first wiring composed of the wiring and a second wiring crossing the first wiring with an insulating film interposed are arranged on the substrate. According to such a configuration, since the occurrence of hillocks in the first wiring is suppressed, there is an effect that a short circuit between the first wiring and the second wiring due to hillocks is prevented and a substrate having no short circuit defect is obtained.

Further, it is characterized in that a semiconductor layer having a channel region and a gate electrode formed in the same layer as the wiring at a position facing the channel region are provided on the substrate. According to such a configuration, even when the gate electrode of the switching element having the semiconductor layer is formed, a gate electrode in which hillock generation is suppressed can be obtained similarly to the above wiring, and a switching element having good switching characteristics can be obtained. Further, it has an effect of obtaining a substrate for an electro-optical device having wiring having a good film quality.

Further, the electro-optical device substrate of the present invention has a semiconductor layer having a channel region arranged on the substrate and a crystal orientation plane (0) arranged so as to face the channel region.
No. 02), and a gate electrode formed by laminating a layer containing aluminum preferentially oriented on a crystal orientation plane (111) by being formed on the titanium layer. And According to such a configuration, when the gate electrode of the switching element having the semiconductor layer is formed, it is possible to obtain a flat gate electrode in which hillock generation is suppressed. Therefore, for an electro-optical device having a switching element having good switching characteristics. It has the effect of obtaining a substrate.

Further, the gate electrode is characterized in that a layer containing titanium is laminated on the layer containing aluminum. According to such a configuration, there is an effect that the generation of hillocks can be further suppressed.

Further, the above-mentioned electro-optical device substrate is characterized in that the titanium layer has a film thickness of 40 nm or more. With such a structure, a flat titanium layer having good crystallinity can be obtained as a base layer of a layer containing aluminum by setting the film thickness to 40 nm or more. Therefore, even when a layer containing aluminum is stacked. In addition, a flat surface can be obtained, and the wiring or gate electrode having a uniform film quality can be obtained within the surface of the substrate. Here, the thickness of the titanium layer is preferably 100 nm or less in consideration of its resistivity.

An electro-optical device according to the present invention is characterized by having the above-mentioned substrate and a counter electrode arranged so as to face the substrate. According to such a configuration, it is possible to obtain an electro-optical device that has a reduced power consumption, a large screen, and high definition, and has good display characteristics without display variations.

The substrate manufacturing method of the present invention comprises the steps of forming a silicon oxide film on the substrate, forming a titanium film preferentially oriented in the crystal orientation plane (002) on the silicon oxide film, And a step of forming a laminated film by forming a film containing aluminum preferentially oriented in the crystal orientation plane (111) on the titanium film.

According to this structure, the crystal orientation (11
It is possible to obtain a film containing aluminum having a single preferential orientation on the 1) plane, and to obtain a flat film containing aluminum with good film quality in which hillock generation is suppressed. And
By patterning a film having a laminated film of such a titanium film and a film containing aluminum into a predetermined shape, it is possible to obtain a wiring having good film quality and a gate electrode of a switching element. When a film containing aluminum has a crystal structure having a single preferential orientation in the crystal orientation (111) plane, hillocks are less generated, and the crystal orientation (111) plane of the film containing aluminum has a crystal orientation ( 002) plane and the interplanar spacing are well matched. Therefore, by forming a film containing aluminum on a titanium film preferentially oriented to the crystal orientation (002) plane, the crystal orientation (111)
It is possible to obtain a film containing aluminum with a single preferential orientation in the plane. As the film containing aluminum, there is a simple substance of aluminum, for example, an aluminum alloy such as an alloy of aluminum and copper.

The method further comprises the step of forming a film containing titanium on the film containing aluminum to form a laminated film. With such a configuration, it is possible to protect the layer containing aluminum and further suppress the generation of hillocks.

The method further comprises the step of patterning the laminated film into a predetermined shape to form a first wiring, and the step of insulating the first wiring and forming a second wiring intersecting with the first wiring. And According to such a configuration, since the occurrence of hillocks in the first wiring is suppressed, there is an effect that a short circuit between the first wiring and the second wiring due to hillocks is prevented and a substrate having no short circuit defect is obtained.

Further, a semiconductor layer having a channel region and the silicon oxide film covering the semiconductor layer are formed on the substrate, and the laminated film is patterned to form a gate electrode at a position opposite to the semiconductor layer. The method comprises the step of forming. According to such a configuration, when the gate electrode of the switching element having the semiconductor layer is formed, a flat gate electrode in which hillock generation is suppressed can be obtained, and a switching element having good switching characteristics can be obtained.

Further, the titanium film has a film thickness of 40 nm or more. According to such a configuration,
By setting the film thickness to 40 nm or more, a flat titanium film having good crystallinity can be obtained as a base film of a true film containing aluminum. Therefore, even when laminating films containing aluminum, a flat surface can be obtained. This has the effect of obtaining a wiring or gate electrode having a uniform film quality in the plane of the substrate. Here, the thickness of the titanium film is preferably 100 nm or less in consideration of its resistivity.

A method of manufacturing an electro-optical device according to the present invention is a method of manufacturing an electro-optical device having a substrate and a counter electrode arranged to face the substrate, wherein the substrate is manufactured by the above-described manufacturing method. It is characterized by According to such a configuration, it is possible to obtain an electro-optical device that has a reduced power consumption, a large screen, and high definition, and has good display characteristics without display variations.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION (Method for Manufacturing Electrode Substrate) In the embodiments of the present invention, a semiconductor substrate having a semiconductor layer as an electrode substrate is taken as an example. Will be explained. FIG. 1 is a partial schematic view of a semiconductor substrate, and FIG. 2 is a diagram for explaining a manufacturing method thereof.

As shown in FIG. 1, the semiconductor substrate includes a substrate 60 made of, for example, glass, a polysilicon layer 1 arranged thereon, and a gate insulating film 2 made of a silicon oxide film arranged so as to cover the polysilicon layer 1. There is. Further, the wiring 33 is arranged at a position corresponding to a part of the polysilicon layer 1.
The wiring 33 has a three-layer structure, and is a titanium layer, an aluminum / copper alloy layer, and a titanium nitride layer from the bottom. By setting the thickness of the titanium layer to 40 nm or more, the crystallinity and flatness are good, and the orientation of the aluminum / copper alloy layer formed thereon can be improved. The thickness of the aluminum / copper alloy layer is 100 to 1000
nm, here 400 nm. The titanium nitride layer has a thickness of 50 to 150 nm, and when it is 50 nm or more, hillock generation can be suppressed.
m. In each drawing, in order to make each layer and each member recognizable in the drawing, the scale is different for each layer and each member.

Next, a method of manufacturing the semiconductor substrate will be described with reference to FIG.

As shown in FIG. 2A, an a-Si film having a thickness of about 30 to 100 nm is formed by a PECVD method or an LP (low pressure) CVD method, and an excimer laser beam is irradiated on the a-Si film to form crystals. Then, the polysilicon layer 1 is obtained by patterning into a predetermined shape.

Next, as shown in FIG. 2B, PECV
Method D (plasma enhanced chemical vapor depositio
n), the gate insulating film 2 made of a silicon oxide film having a film thickness of 50 to 120 nm, here 75 nm, is formed on the entire surface of the substrate using TEOS (tetraethyl orthosilicate) as a source gas. The gate insulating film 2 had an etching rate of 3.5 nm / sec with respect to the buffered hydrofluoric acid solution. After the gate insulating film 2 was formed, the substrate was washed with a cleaning liquid such as an alkaline cleaning liquid that does not easily corrode the silicon oxide film. Here, as the cleaning liquid, it is preferable to use a cleaning liquid such as an alkali type or a sulfuric acid type, without using a silicon oxide film eroding liquid such as dilute hydrogen fluoride. Next, FIG. 2 (c)
As shown in FIG.
An aluminum / copper alloy film 35 and a titanium nitride film 36 are sequentially stacked to form a film. Specifically, first, the substrate on which the semiconductor layer and the gate insulating film are formed is loaded into the reaction chamber,
A titanium film 34 having a thickness of m is formed. After forming the titanium film,
The substrate on which the titanium film 34 is formed is loaded into another reaction chamber, and the aluminum / copper alloy film 35 is formed on the titanium film 34 to a thickness of 400 nm. After the aluminum / copper alloy film is formed, the substrate is loaded from the reaction chamber into another reaction chamber. A mixed gas of argon and nitrogen is introduced into the reaction chamber, and a titanium nitride film 36 having a film thickness of 100 nm is formed using a titanium target. Next, as shown in FIG.
Titanium film 34 and aluminum so as to have a predetermined shape
The copper alloy film 35 and the titanium nitride film 36 are simultaneously patterned to obtain the wiring 33.

An evaluation of the crystal orientation of the titanium film at this time is shown in FIG. 15 (a). In the sample of FIG. 15A, a titanium single film is formed and evaluated in order to eliminate other signal components of the laminated film. The etching rate of the silicon oxide film used as the base film of titanium for the buffered hydrofluoric acid solution is about 3.
5 nm / sec. On the other hand, FIG. 15 shows an evaluation of crystal orientation by similarly forming a titanium single film on a silicon oxide film having an etching rate of about 9 nm / sec with respect to a buffered hydrofluoric acid solution.
It is (b). As can be seen by comparing the two, FIG.
The signal intensity of the sample in (a) shows a value that is twice or more that in FIG. 15 (b). That is, it means that the crystallinity of titanium is improved by forming a titanium film on a silicon oxide film having a low etching rate for a buffered hydrofluoric acid solution.

Further, an aluminum / copper alloy film is formed on the titanium film and the crystal orientation is evaluated as shown in FIG.
(A) and (b). The etching rate of the silicon oxide film used as the base film for the buffered hydrofluoric acid solution is shown in FIG.
(A) is about 3.5 nm / sec, and FIG. 16 (b) is about 9 nm / sec.
nm / sec. As can be seen by comparing the two, FIG.
The signal intensity of the sample of 5 (a) is about 1.5 in FIG. 15b (b).
It shows a doubled value. That is, when a titanium film and an aluminum / copper alloy film are formed by laminating on a silicon oxide film having a small etching rate for a buffered hydrofluoric acid solution, it means that not only titanium but also the crystallinity of the aluminum / copper alloy film is improved. There is.

The aluminum / copper alloy film 3 after film formation
In the crystal structure of No. 5, the crystal orientation (111) plane was preferentially oriented, and the crystal orientation (200) plane was not detected. Here, the crystallinity is determined by an X-ray diffractometer (device name: RINIT-1
400).

The wiring 33 formed through such a manufacturing process is a film in which the crystal structure of aluminum is preferentially oriented to the crystal orientation (111) plane as described above and has excellent crystallinity. At this time, good flatness can be obtained, and a short circuit between the wiring 33 and a wiring (not shown) formed on the wiring 33 via an insulating film (not shown) is prevented in advance. , It was possible to manufacture a highly reliable semiconductor substrate.

FIG. 17 shows a sample obtained by laminating an aluminum / copper alloy film on a titanium film and evaluating the surface average roughness by AFM. The etching rate of the silicon oxide film used as the base film for the buffered hydrofluoric acid solution is about 3.5 nm / sec in FIG. 17A and about 9 nm / sec in FIG. 16B. These means that when a titanium film and an aluminum / copper alloy film are formed by laminating on a silicon oxide film having a low etching rate for a buffered hydrofluoric acid solution, a film having good flatness can be formed.

Further, the semiconductor substrate formed through such a manufacturing process could suppress the generation of wiring hillock even after a high temperature treatment process of, for example, 400 ° C. or higher in the subsequent process.

FIG. 18 shows a sample obtained by laminating a titanium film, an aluminum / copper alloy film, and a titanium nitride film on a silicon oxide film having an etching rate of about 3.5 nm / sec with respect to a buffered hydrofluoric acid solution, and heat-treating the sample at 450 ° C. for 3 hours. It is a photograph showing the state. It can be seen that good flatness is maintained even after the heat treatment.

FIG. 19 shows the surface condition of a laminated film in which a silicon oxide film, a titanium film, an aluminum / copper alloy film, and a titanium nitride film having an etching rate by BHF of 3.5 nm / sec are sequentially laminated on a glass substrate. . In FIG. 19A, the titanium film has a thickness of 400 nm, and in FIG. 19B, the titanium film has a thickness of 200 nm. As shown in the figure, it can be seen that the surface roughness of the laminated film is reduced by increasing the thickness of the titanium film that is the lower layer of the aluminum alloy film.

In the above embodiment and experimental results, the aluminum-copper alloy was used as the film containing aluminum.
It may be an aluminum simple substance or an aluminum alloy made of an alloy with a metal other than copper.

(Method for Manufacturing Electro-Optical Device) In this embodiment, a liquid crystal device is taken as an example of an electro-optical device using a switching element. A thin film transistor is used as a switching element, and a gate electrode of the thin film transistor and scanning as a wiring are used. In the line and the layer consisting of this and the same layer,
The titanium film of the embodiment of the electrode substrate described above, aluminum
A film formed by patterning a laminated film of a copper alloy film and a titanium nitride film is used.

Hereinafter, in this embodiment, FIG. 3 to FIG.
Will be described with reference to.

FIG. 3 is an equivalent circuit of various elements, wirings, etc. in a plurality of pixels formed in a matrix which form an image forming area of a liquid crystal device. FIG. 4 is a plan view of a plurality of pixel groups in a display area of a TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed. 5 is a vertical cross-sectional view of the display area and the peripheral drive circuit area of the liquid crystal device, and the vertical cross-sectional view of the pixel area is a cross-sectional view taken along the line AA ′ of FIG. In each drawing, in order to make each layer and each member recognizable in the drawing, the scale is different for each layer and each member.

In FIG. 3, the liquid crystal device comprises a display area and a peripheral drive circuit area for controlling the display area.

The display area is a capacitance line 3b arranged in parallel.
And the scanning lines 3, the data lines 6 arranged to intersect the scanning lines 3, the pixel electrodes 9a arranged in a matrix at each intersection of the scanning lines 3 and the data lines 6, and the pixel electrodes 9a.
And a thin film transistor (hereinafter referred to as a TFT) 30 for controlling the. The source of the TFT 30 is electrically connected to the data line 6 to which the image signal is supplied, and the gate of the TFT 30 is electrically connected to the scanning line 3 to which the scanning signal is supplied. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30, which is a switching element, for a certain period, the image signals S1 and S supplied from the data line 6 are obtained.
2, ..., Sn are written at a predetermined timing. The image signals S1, S2, ..., Sn having a predetermined level written in the liquid crystal via the pixel electrode 9a are held for a certain period of time with the counter electrode (described later) formed on the counter substrate (described later). .

On the other hand, the peripheral drive circuit area is composed of the scanning line drive circuit 104, the data line drive circuit 101, the sampling circuit 301, and the precharge circuit 201. The scanning line driving circuit 104 supplies the scanning signals G1, G2, ..., G to the scanning lines 3 at a predetermined timing based on the power supplied from the external control circuit, the reference clock CLY, its inverted clock, and the like.
m is applied in a pulse-wise line-sequential manner. Data line drive circuit 1
Reference numeral 01 denotes the data line 6 in accordance with the timing at which the scanning line driving circuit 104 applies the scanning signals G1, G2, ..., Gm based on the power supplied from the external control circuit, the reference clock CLX, its inverted clock, and the like. Transfer signal X from the shift register as a sampling circuit drive signal for each
, Xn are supplied to the sampling circuit 301 via the sampling circuit drive signal line 306 at a predetermined timing. The precharge circuit 201 includes, for example, a TFT 202 as a switching element for each data line 6, the precharge signal line 204 is connected to the drain or source electrode of the TFT 202, and the precharge circuit drive signal line 206 is the TFT 202. Connected to the gate electrode of. During operation, the precharge signal N is supplied from an external power source via the precharge signal line 204.
A power supply of a predetermined voltage necessary for writing RS is supplied, and a precharge signal is supplied at a timing preceding the supply of the image signals S1, S2, ..., Sn for each data line 6 via the precharge circuit drive signal line 206. A precharge circuit drive signal NRG is supplied from an external control circuit so as to write NRS. The precharge circuit 201 is preferably an image signal S1, S2, ..., S having an intermediate gradation level.
Precharge signal NRS (image auxiliary signal) corresponding to n
To supply. The sampling circuit 301 is a TFT 302
Is provided for each data line 6, and the image signal line 304 is T
It is connected to the source electrode of the FT 302, and the sampling circuit drive signal line 306 is connected to the gate electrode of the TFT 302. Then, via the image signal line 304,
When the image signals S1, S2, ..., Sn are input, these are sampled. That is, transfer signals X1, X2, ..., X as sampling circuit drive signals from the data line drive circuit 101 via the sampling circuit drive signal line 306.
When n is input, the image signals S1, S2, ..., Sn from the image signal lines 304 are sequentially applied to the data line 6a.

In this embodiment, since polysilicon is used as the semiconductor layer of the TFT 30 in the display area, the TFT used in the peripheral drive circuit and the TFT 30 in the display area are formed in the same step on the same substrate. However, it is also possible to form part of the peripheral drive circuit on a separate substrate and attach it externally.

In FIG. 4, a plurality of transparent pixel electrodes 9a are provided in a matrix on the TFT array substrate of the liquid crystal device, and the data lines 6 and the scanning lines are arranged along the vertical and horizontal boundaries of the pixel electrodes 9a. 3 (dotted line) and the capacitance line 3b (dotted line) are provided. The data line 6 is formed in a shape extending in the vertical direction, and the source 6a, which is a part of the data line 6, is described later in the semiconductor layer 1 (a diagonally lower left portion) formed of a polysilicon film via the contact hole 5a. The data line 6 is electrically connected to the source region and the data line 6 is the source 6a.
It is formed so that its width becomes wider in the vicinity. The drain 6b formed in the same layer as the data line 6 is electrically connected to a later-described drain region of the semiconductor layer 1 through the contact hole 5b, and the drain 6b is further connected through the contact hole 8 to the pixel electrode. It is electrically connected to 9a. Further, the scanning line 3 is arranged so as to face the channel region of the semiconductor layer 1, and the scanning line 3 functions as a gate electrode. In the present embodiment, there are two overlapping portions of the semiconductor layer 1 and the scanning line 3. There are two places and it has a double gate structure. In the drawing, the portion where the scanning line 3 and the semiconductor layer 1 overlap in a plane, that is, the semiconductor layer at the position corresponding to the gate electrode is hidden by the scanning line and is not shown. The capacitance line 3b extends in a substantially linear shape along the scanning line 3 and has a protruding portion protruding along the data line 6 from a position intersecting with the data line 6, and the semiconductor layer substantially corresponds to the protruding portion. Some are located. The capacitance line 3b planarly overlaps with a part of the pixel electrode 9a, forms a capacitance in this region, and further forms a capacitance with the pixel electrode 9a. The semiconductor layer 1 is extended below the data lines 6 and the scanning lines 3,
Similarly, the capacitance line 3 extending along the data line 6 and the scanning line 3
The capacitor is formed by being opposed to the portion b via the insulating film 2.

Next, as shown in the cross-sectional view of FIG. 5, the liquid crystal device 100 includes a liquid crystal layer 50 between the TFT array substrate 10 and a counter substrate 80 arranged to face the TFT array substrate 10.

In the display area of the TFT array substrate 10, a base film 12 made of silicon oxide and a semiconductor layer 1 made of polysilicon are arranged on a glass substrate 60. A gate insulating film 2 made of a silicon oxide film having an etching rate of BHF of 4 nm / sec or less is arranged on the semiconductor layer 1. On the gate insulating film 2, a scanning line 3 (not shown) having a layer structure in which a titanium layer, an aluminum / copper alloy layer, and a titanium nitride layer are laminated from the bottom, a gate electrode 3a that is a part of the scanning line, The capacitance line 3b is arranged. Then, the scanning line 3, the gate electrode 3a, and the capacitance line 3
The insulating film 4 is arranged so as to cover b. On the insulating film 4, a data line 6 formed in the same layer, a source 6a which is a part of the data line 6, and a drain 6b are arranged. The source 6a is electrically connected to a source region of the semiconductor layer 1 described later by a contact hole 5a formed in the gate insulating film 2 and the insulating film 4, and the drain 6b is a contact hole formed in the insulating film 4. 5b electrically connects to the drain region of the semiconductor layer 1 described later. Further, the interlayer insulating film 7 is arranged so as to cover the data line 6, the source 6a and the drain 6b, and the drain 6b is formed on the interlayer insulating film 7 by the contact hole 8 formed in the interlayer insulating film 7. It is electrically connected to the pixel electrode 9a made of a tin oxide film. Finally,
An alignment film 16 made of polyimide is arranged so as to cover the pixel electrodes. Here, the semiconductor layer 1 of the TFT in the display area
Has an LDD (lightly doped drain) structure, which will be described in detail later.

In the peripheral drive circuit area of the TFT array substrate 10, a complementary transistor structure is adopted. As shown in FIG. 5, the complementary transistor structure includes an N-channel TFT 130a and a P-channel TFT.
130b, the N-channel type semiconductor layer 1 and the P-channel type semiconductor layer 1 are arranged on the underlying layer 12 arranged on the glass substrate 60, and the gate, which is a gate insulating film, covers these. The insulating film 2 is arranged. The gate electrode 103 is arranged on the gate insulating film 2 at a position corresponding to the channel region of the semiconductor layer. Further, the insulating film 4 is arranged so as to cover the gate electrode 103, and the source electrodes 106a and 107a and the drain electrodes 106b and 107b arranged on the insulating film 4 respectively correspond to the corresponding semiconductor layer 1.
Is electrically connected to the source region or the drain region of the. Then, the interlayer insulating film 7 is arranged on the TFT having the complementary transistor structure. The semiconductor layer of the N-channel TFT has an LDD structure.

On the other hand, the counter substrate 80 is composed of a light-shielding film 23 formed in a matrix on the glass substrate 20, a counter electrode 21 made of an ITO film and sequentially formed to cover the light-shielding film 23, and an alignment film 16 made of polyimide. Has been done.

Next, a method of manufacturing the TFT array substrate will be described with reference to FIGS. 6 to 14 are cross sections in the display region and the peripheral circuit region, and the display region is a cross section taken along the line AA 'in FIG.

First, as shown in FIG. 6A, a SiO ₂ film of 200 to 200 is formed as a base film 12 on a glass substrate 60 by PE (plasma enhanced) CVD method or ECR (electron cyclotron resonance) CVD method. 500
It is formed with a thickness of about nm. This base film is free from impurities such as dirt on the surface of the glass substrate 60 and impurities contained in the glass substrate.
It has a function of preventing deterioration of the characteristics of the FT 30.

Next, as shown in FIG. 6B, PECV
An a-Si film 401a is laminated on the base film with a thickness of about 30 to 100 nm by the D method or the LP (low pressure) CVD method.

Next, as shown in FIG. 6C, a-Si
Excimer laser light such as KrF or XeCl is applied to the film 3 times.
By irradiating with 0 to 600 mJ / cm2, aS
The i film is crystallized to obtain a p-Si film 401b. The irradiation intensity and irradiation time of the excimer laser light are appropriately adjusted depending on the film thickness and film quality of the a-Si film. In this embodiment, since the polysilicon layer can be obtained at a low temperature by laser annealing, a glass substrate that is cheaper than a silicon substrate can be used as the substrate.

Next, as shown in FIG. 6D, a resist film 402 is formed in a shape corresponding to the semiconductor layer of the TFT in each of the display area and the peripheral drive circuit area.

Next, as shown in FIG. 7A, the p-Si film 401b is subjected to RIE (reactive ion etching) using a chlorine-based gas with the resist film 402 as a mask.
Etching is performed to form the p-Si layer 1. In addition to dry etching such as RIE, wet etching using a chemical solution such as etching using hydrofluoric nitric acid can also be used.

Next, as shown in FIG. 7B, after removing the resist film 402, PECVD is performed as shown in FIG. 7C.
By the method, TEOS (tetraethyl orthosilicate)
Using as a source gas, a gate insulating film 2 made of a silicon oxide film having a thickness of 50 to 120 nm, here 75 nm.
Is formed on the entire surface of the substrate. The gate insulating film 2 had an etching rate for BHF of about 3.5 nm / sec.

Next, as shown in FIG. 7D, a resist film 403 having a shape in which a portion of the semiconductor layer 1 in the display region corresponding to the region functioning as a capacitor is removed is formed.
Then, with the resist film 403 used as a mask, phosphorus ions of 5 × 10 ¹⁴ to 1 as impurities are formed by an ion implantation method.
Implanted into the semiconductor layer 1 at a dose of 0 ¹⁶ pieces / cm ² ,
The capacitance electrode 1f is formed. After the implantation, the resist film 403 is peeled off.

The silicon oxide film was cleaned with a cleaning liquid that is resistant to corrosion. Here, as the cleaning liquid, it is preferable to use a cleaning liquid such as an alkali-based or sulfuric acid-based liquid having low corrosiveness, without using a silicon oxide film corrosive liquid such as dilute hydrogen fluoride. The orientation can be maintained.

Next, as shown in FIG. 8A, a titanium film 34, an aluminum / copper alloy film 35, and a titanium nitride film 36 are sequentially deposited on the gate insulating film 2 by a sputtering method.

Next, as shown in FIG. 8B, scanning lines,
Resist film 404 having a shape corresponding to the gate electrode and the capacitance line
To form. Using this as a mask, as shown in FIG. 8C, the titanium film 34, the aluminum-copper alloy film 35, and the titanium nitride film 36 are etched by RIE using a fluorine-based or chlorine-based gas. After etching, the resist film 404 is peeled off, and as shown in FIG. 9A, a three-layer structure in which a titanium nitride layer is laminated in a laminated structure in which a lower layer is a titanium layer and an upper layer is an aluminum / copper alloy layer, The scanning line 3, the gate electrodes 3a and 103, and the capacitance line 3b are obtained.

Next, as shown in FIG. 9B, a P-channel type TFT covering the entire display area and in the peripheral circuit area.
A resist film 405 is formed by removing the resist only at the position corresponding to the semiconductor layer to be formed. After this, the resist film 4
05 and a gate electrode 10 corresponding to a P-channel TFT
3 is used as a mask, 5 × 10 ¹⁴ to 10 ¹⁶ / cm ² of boron ions are implanted into the semiconductor film 1 by an ion implantation method,
Channel region 1 self-aligned with gate electrode 103
A semiconductor layer 1 having a and source / drain regions 1g and 1h is obtained.

Next, as shown in FIG. 9C, the resist film 405 is stripped by (name of stripping solution).

After that, as shown in FIG. 9D, a resist film 406 is formed at a position corresponding to the semiconductor layer to be the P-channel TFT in the peripheral circuit region. Next, using the resist film 406, the gate electrode 3a, the gate electrode 103 corresponding to the N-channel TFT, and the capacitance line 3b as a mask, 1 × 10 ¹³ to 2 × 10 ¹⁴ phosphorus ions / cm 2 are applied to the semiconductor layer 1. Implant by the ion implantation method. As a result, in the peripheral circuit region, the channel region 1a self-aligned with the gate electrode 103, the high-concentration source region formed later, the low-concentration source region 1b having a lower impurity concentration than the high-concentration drain region, and the low-concentration drain region are formed. The semiconductor layer 1 corresponding to the N-channel TFT having 1c is obtained. Also, in the display area, two channel areas 1a are provided.
(Only one is shown), which has a high-concentration source region, a low-concentration source region 1b having a lower impurity concentration than the high-concentration drain region, and a low-concentration drain region 1c which are formed so as to sandwich these two channel regions. The semiconductor 1 is obtained.

Next, the resist film 406 is peeled off with a peeling solution. After that, as shown in FIG. 10A, a resist film 407 is formed. As shown in the figure, the resist film 40
Reference numeral 7 has a shape that covers the peripheral portions of the gate electrode 103 of the N-channel TFT in the peripheral drive circuit area and the gate electrode 3a in the display area, and also covers the semiconductor layer of the P-channel TFT. Then, using the resist film 407 as a mask, phosphorus ions are implanted into the semiconductor layer 1 by an ion implantation method at a dose amount of 5 × 10 ¹⁴ to 10 ¹⁶ / cm ² . After that, the resist film 407 is peeled off. As a result, as shown in FIG. 10B, the low concentration source region 1
b, a semiconductor layer having a high-concentration source region 1d having a higher impurity concentration than the low-concentration drain region 1c and a high-concentration drain region 1e can be obtained. Therefore, the TFT in the display area and the N-channel TFT in the peripheral drive circuit area are semiconductor layers having an LDD structure.

Next, as shown in FIG. 10C, PECV is performed so as to cover the gate electrodes 103, 3a and the capacitance line 3b.
Insulating film 4 made of SiO ₂ and having a thickness of 1500 nm by TE method using TEOS and ozone gas as source gases
To form. After that, in order to activate the impurity ions, activation heat treatment (activation annealing treatment) is performed under a temperature condition of 400 ° C.

Next, as shown in FIG. 10D, contact holes for connecting the source / drain regions of the respective TFTs in the peripheral circuit region to the source / drain regions to be formed later, and the TFTs in the display region. A resist film 409 patterned into a shape corresponding to a contact hole for connecting a source region and a source formed later and a contact hole for connecting a drain region of a TFT in the display region and a drain formed later is formed. Form.

As shown in FIG. 11A, the resist film 4
The insulating film 4 is etched using 09 as a mask to form contact holes 5, 5a, 5b. After that, the resist film 409 is peeled off to obtain the structure of FIG.

Next, as shown in FIG. 11C, an aluminum / titanium film 410 having a film thickness of 300 to 1000 nm is formed on the insulating film 4 by the PVD method. Furthermore,
As shown in FIG. 11D, on the aluminum film / titanium film 410, a resist film 411 having a shape in which the portions corresponding to the data lines, the sources, and the drains are removed is formed.

Next, as shown in FIG. 12A, the aluminum / titanium film 410 is etched by RIE using a chlorine-based gas with the resist film 411 as a mask, and then the resist film 411 is removed. As a result, FIG.
As shown in (b), in the peripheral circuit region, source electrodes 106a and 107a and drain electrodes 106b and 107 electrically connected to the source region and the drain region of the semiconductor layers of the N-channel TFT and the P-channel TFT, respectively.
get b. In the display region, the data line 6 and the drain electrode 6b which also function as the source electrode 6a and are electrically connected to the source region and the drain region of the semiconductor layer are obtained.

Next, as shown in FIG. 12C, an interlayer insulating film 7 is formed on the source electrode, the drain electrode, and the data line to form a T film.
PEC using a mixed gas of EOS and oxygen gas as a source gas
It is formed by the VD method. Here, as a method for forming the interlayer insulating film 7, an atmospheric pressure CVD method may be used, and as a raw material gas, a mixed gas of TEOS and ozone gas or a mixed gas of SiH ₄ and oxygen gas may be used. Good. Also,
Not only an inorganic film, but also an organic film such as an acrylic film can be used. In this case, a film having a larger film thickness than that of an inorganic film can be easily obtained, so that it can be used as a flattening film.

Next, as shown in FIG. 12D, a resist film 413 is formed on the interlayer insulating film 7 in which the resist is removed at a portion corresponding to a contact hole connecting the drain 6b and a pixel electrode to be formed later. Form. After that, FIG.
As shown in (a), the interlayer insulating film 7 is etched by the RIE method or the wet etching method using the resist film 413 as a mask, and the resist film 413 is peeled off.
As shown in FIG. 13B, the interlayer insulating film 7 having the contact holes 8 is obtained.

Next, as shown in FIG. 13C, an ITO film 414 having a thickness of about 50 to 200 nm is formed on the interlayer insulating film 7 by the sputtering method. After that, FIG.
As shown in (a), a resist film 415 corresponding to the pixel electrode shape is formed on the ITO film 414, and the ITO film 414 is wet-etched with aqua regia or HBr by using this, or CH ₄ or By dry etching by RIE using a gas such as HI, a pixel electrode 9a is obtained as shown in FIG. 14B.

As described above, in this embodiment, when the wiring having the laminated structure of the titanium layer and the aluminum / copper alloy layer is formed, the film quality of the silicon oxide film located below the wiring is limited. By controlling the crystal structure of the titanium film, the crystal structure of the aluminum / copper alloy film on which the titanium film is formed can be made a crystal structure that suppresses hillock generation. Accordingly, a thin film transistor without defects can be obtained, and a short circuit between the scan line and the data line is prevented, so that a liquid crystal device with no display defect and excellent display characteristics can be obtained.

[Brief description of drawings]

FIG. 1 shows a vertical sectional view of an electrode substrate according to an embodiment.

2A to 2D are process diagrams sequentially showing a manufacturing process of the electrode substrate of the embodiment.

FIG. 3 is an equivalent circuit of various elements, wirings and the like provided in a plurality of matrix-shaped pixels forming an image forming area in the liquid crystal device of the embodiment.

FIG. 4 is a plan view of a TFT array substrate on which a data line, a scanning line, and a pixel electrode are formed in a display area of the liquid crystal device of the embodiment.

5 is a vertical cross-sectional view of each of a peripheral circuit region and a display region of the liquid crystal device of the embodiment, which is a cross-sectional view taken along the line AA ′ in FIG.

FIG. 6 is a process chart (1) sequentially showing a manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 7 is a process diagram (No. 2) sequentially showing the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 8 is a process chart (No. 3) sequentially showing the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 9 is a process chart (No. 4) sequentially showing the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 10 is a step diagram (5) sequentially showing the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 11 is a process chart (sixth) sequentially showing the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 12 is a process chart (No. 7) sequentially showing the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 13 is a process chart (No. 8) that sequentially shows the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 14 is a process chart (9) showing the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment step by step.

FIG. 15 is a diagram showing a difference in crystal state of a titanium film due to a difference in film quality of a silicon oxide film.

FIG. 16 is a diagram showing a difference in crystal state between a titanium film and an aluminum / copper alloy laminated film due to a difference in film quality of a silicon oxide film.

FIG. 17 is a diagram showing a difference in surface roughness of a titanium film and an aluminum / copper alloy laminated film due to a difference in film quality of a silicon oxide film.

FIG. 18 is a diagram showing a state after heat treatment of a wiring film to which the present invention has been applied.

FIG. 19 is a diagram showing a difference in surface state of a laminated film due to a difference in film thickness of a titanium film.

[Explanation of symbols]

1 ... Semiconductor layer 2 ... Gate insulating film 3 ... Scan line 3a ... Gate electrode 4 ... Insulating film 6 ... Data line 6a ... Source electrode 7 ... Interlayer insulating film 9a ... Pixel electrode 33 ... Wiring 34 ... Titanium film 35 ... Aluminum / copper alloy film 36 ... Titanium nitride film 60 ... Substrate

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/786 H01L 29/58 GF term (reference) 2H090 HC12 JC07 LA01 LA03 LA04 2H092 GA11 JA24 JA34 JA37 JA46 MA05 MA07 MA28 MA30 NA16 NA25 PA01 PA02 PA06 4M104 AA01 AA08 BB01 BB02 BB14 BB36 BB37 CC01 CC05 DD08 DD09 DD16 DD20 DD26 DD33 DD37 DD43 DD64 DD65 DD78 DD81 FF13 GG09 GG10 GG14 GG14 GG14 GG10 GG14 GG10 HG10 H38 MM08 PP06 PP14 PP15 QQ08 QQ09 QQ10 QQ13 QQ19 QQ37 QQ59 QQ65 QQ73 QQ74 RR04 RR21 RR22 SS02 SS04 SS11 SS15 TT02 TT04 VV15 WW00 WW02 XX01 EE45 FF16 EE30 FF16 BB11 CC04 DD02 BB04 CC04 DD02 CC02 DD02 BB04 CC04 DD02 GG47 HJ01 HJ04 HJ13 HJ23 HL03 HL04 HL11 HL23 HM12 HM15 NN03 NN23 NN27 NN35 NN72 NN73 PP03 QQ11 QQ19

Claims (8)

[Claims] 1. A crystal orientation plane (00) formed on a substrate.
2. A substrate comprising: a wiring in which a titanium layer preferentially oriented in 2) and a layer containing aluminum preferentially oriented in a crystal orientation plane (111) formed on the titanium layer are laminated. 2. The substrate according to claim 1, wherein cubic titanium nitride is laminated on the layer containing aluminum. 3. A first wiring comprising the wiring on the substrate.
The substrate according to claim 1 or 2, wherein a wiring and a second wiring intersecting the first wiring via an insulating film are arranged. 4. A semiconductor layer having a channel region on the substrate, and a gate electrode formed in the same layer as the wiring at a position facing the channel region. Item 4. The electro-optical device substrate according to any one of items 3. 5. A semiconductor layer having a channel region arranged on a substrate, and a titanium layer arranged opposite to the channel region and preferentially oriented in a crystal orientation plane (002).
By being formed on the titanium layer, the crystal orientation plane (11
A substrate for an electro-optical device, comprising: a gate electrode formed by laminating a layer containing aluminum preferentially oriented in 1). 6. The substrate for an electro-optical device according to claim 5, wherein the gate electrode is formed by stacking cubic titanium nitride on a layer containing aluminum. 7. The substrate according to claim 1, wherein the titanium layer has a film thickness of 40 nm or more. 8. An electro-optical device comprising the substrate according to claim 1.