JP2020096192A - Display device - Google Patents

Abstract

To examine internal stress of a semiconductor device including a conductive film, which is affected by the internal stress of the conductive film.SOLUTION: A semiconductor device including an n-channel type TFT provided on an insulating surface is configured so that impurity elements are introduced to a conductive film, for instance, a gate electrode so that a semiconductor film is subjected to pulling stress. The semiconductor device including a p-channel type TFT provided on the insulating surface is configured so that the impurity elements are introduced to the conductive film, for instance, the gate electrode so that the semiconductor film is subjected to compression stress.SELECTED DRAWING: Figure 6

Description

The present invention relates to a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as a TFT) and a manufacturing method thereof. In particular, the present invention relates to an electro-optical device represented by a liquid crystal display device, a semiconductor device having such an electro-optical device mounted as a component, and a manufacturing method thereof. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

In recent years, T using a thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface
Development of a semiconductor device which constitutes an FT and has a large-area integrated circuit formed by the TFT is in progress. As a typical example thereof, an active matrix type liquid crystal display device and a light emitting device are known. In particular, since a TFT having a crystalline silicon film as an active region has high field effect mobility, it is possible to form various functional circuits.

For example, in an active matrix type liquid crystal display device, in order to control a pixel circuit for displaying an image for each functional block, a pixel circuit such as a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, a sampling circuit, etc. Drive circuit is formed on a single substrate.

The TFT has at least a semiconductor film, an insulating film made of a silicon oxide film, a silicon oxynitride film, or the like, and wiring made of various metal materials or the like. The wiring includes a source wiring, a gate wiring (including a gate electrode), and the like. Since the thickness of these films is about several to several hundreds nm, they can be called thin films.

These thin films are formed by a known film forming technique such as a CVD method (chemical vapor deposition method) or a sputtering method. However, it is known that the thin film has internal stress. The internal stress includes intrinsic stress and thermal stress due to the difference in thermal expansion coefficient between the thin film and the substrate.

The effect of thermal stress can be ignored by considering the material of the substrate, process temperature, pressure, etc., but the mechanism of occurrence of intrinsic stress is not always clear, but rather the growth process of the film or It is considered that the phase change and the composition change due to the subsequent heat treatment are complicatedly entangled with each other.

Generally, the internal stress includes a compressive stress and a tensile stress. As shown in FIG. 5(A),
When the thin film 311 is about to expand, the substrate 312 is compressed and formed so that the thin film 311 is on the outside, and this is called compressive stress. On the other hand, as shown in FIG. 5B, when the thin film 311 contracts with respect to the substrate 312, the substrate 312 is deformed with the thin film inside so as to pull it in a direction that hinders it, which is called tensile stress. I'm out. In general, the value of tensile stress is often indicated by +, and the value of compressive stress is often indicated by-.

Regarding the influence of such internal stress on the electrical characteristics of the transistor, for example, “0
． Effect of stress of etch stop nitride film on 13 μm CMOS transistor performance; 25 Special Issue on ULSI Devices (200
1) pp36-39". According to this, it is reported that the mobility of the NMOS transistor is improved when the channel formation region receives tensile stress, and the mobility of the PMOS transistor is improved when subjected to compressive stress.

As described above, the TFT wiring is also formed of a thin film. Therefore, the wiring also has internal stress, and peeling may occur when the internal stress is strong.
The gate electrode formed of the same material as the wiring is formed over the semiconductor film with the insulating film interposed therebetween. The internal stress of the gate electrode acts even on the semiconductor film, and strains are applied to the interface between the insulating film and the semiconductor film or to the semiconductor film, so that an electric resistance represented by a threshold voltage or field effect mobility is obtained. May adversely affect the physical characteristics.

The present invention is a technique for solving such a problem, and in an electro-optical device and a semiconductor device typified by an active matrix type liquid crystal display device having a wiring, the operating characteristics and reliability of the semiconductor device are improved. , The purpose is to improve the yield.

The present invention makes it possible to control the wiring to a desired internal stress by introducing an impurity element into the wiring of the TFT or by both introducing the impurity element and performing heat treatment. In particular, the present invention
It is extremely effective to apply it to the gate electrode. Further, it is possible to introduce an impurity element only in a desired region or perform heat treatment to control the internal stress to a desired value.

For example, by applying the present invention, the stress received by the channel forming region of the n-channel TFT can be set as tensile stress, and the stress received by the channel forming region of the p-channel TFT can be set as compressive stress. Further, the tensile stress in the channel formation region of the n-channel TFT is relatively stronger than that in the p-channel TFT, and the channel formation region of the p-channel TFT has the n-channel type. TFT
It is also possible to make the compressive stress relatively stronger than that of the channel forming region in. By doing so, it is possible to improve the electrical characteristics of the TFT and to significantly improve the operating characteristics of the semiconductor device.

The impurity element may be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. In such a method of introducing an impurity element, the energy of the ions that are implanted into the thin film is much larger than the binding energy of the element that forms the thin film. Therefore, the ions that are driven into the thin film are repelled from the lattice points to form the semiconductor film so that they are present at the lattice position, and the ions that are driven in and the atoms repelled from the lattice points are moved to the interstitial position. To exist in. Since the thin film stretches in this way, the compressive stress increases when the thin film has a compressive stress, and the tensile stress relaxes when the thin film has a tensile stress.

Further, the heat treatment causes the atoms existing at the interstitial positions to return to the lattice positions, so that the regularity of the atomic arrangement is improved. Therefore, since the thin film contracts, when the thin film has a tensile stress, the tensile stress increases, and when the thin film has a compressive stress, the compressive stress is relieved.

Furthermore, when the impurity element is introduced after the heat treatment, the accelerated ions are implanted into the film having the improved atomic ordering regularity, so that the ions do not collide with each other along the gap of the crystal lattice. It is possible to enter deep places. (Channeling) Therefore,
When introducing the impurity element to control the internal stress, the dose amount is small, and
It becomes possible to use a low acceleration voltage.

Further, when the heat treatment is performed after introducing the impurity element, more atoms are introduced into the thin film than the atoms forming the thin film, so the atoms existing in the interstitial position return to the lattice position more than There will be atoms. Therefore, since the shrinkage of the thin film is smaller than that in the case where the impurity element is not introduced, the amount of increase in tensile stress is also small. That is, when it is known that the heat treatment is performed in the subsequent step, the amount of change in internal stress can be reduced by introducing the impurity element in advance.

In this way, by introducing the impurity element or both introducing the impurity element and performing heat treatment, it becomes possible to control the internal stress to a desired value. Of course, the introduction of impurities and the heat treatment are not limited to once, and may be performed plural times. The present invention improves the operating characteristics and reliability of the semiconductor device by applying these characteristics to the wiring and controlling the stress of the wiring. In particular, by controlling the internal stress in the gate electrode of the TFT, the stress received by the semiconductor film can be controlled. Therefore, it is possible to improve the electrical characteristics represented by the threshold voltage and the field effect mobility. Further, since it is possible to control the stress of each gate electrode, it is also possible to suppress variations in electrical characteristics.

The manufacturing method of the present invention disclosed in this specification is characterized in that an impurity element is introduced into the conductive film so that the internal stress in the conductive film is ±1 GPa or less.

Further, another manufacturing method of the present invention is characterized in that an impurity element is introduced into the conductive film and the conductive film is subjected to heat treatment so that internal stress in the conductive film is ±1 GPa or less.

Another manufacturing method of the present invention is characterized in that the conductive film is heat-treated to introduce an impurity element into the conductive film so that the internal stress in the conductive film is less than or equal to ±1 GPa.

In each of the above manufacturing methods, the impurity element can be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like.

In each of the above manufacturing methods, the impurity element is not particularly limited, but is one or more kinds of elements selected from an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, and a rare gas element. Is desirable. The impurity element imparting n-type conductivity and the impurity element imparting p-type conductivity are indispensable in forming a source region and a drain region. Therefore, it is economical because it is not necessary to newly prepare another impurity element. In particular, when an impurity element is introduced into the gate electrode, it can be introduced at the same time as the step of introducing the impurity element into the source region and the drain region, which is preferable because it can be introduced without increasing the number of steps. Further, since the rare gas element is an inert element, it does not affect the electrical characteristics of the TFT, which is preferable.

Further, as the introduction amount of the impurity element is large, if the internal stress in the thin film is a compressive stress, the compressive stress increases, and if the internal stress in the thin film is a tensile stress, after the tensile stress is relaxed, It may also have a compressive stress. That is, depending on the amount of the impurity element introduced, the internal stress in the thin film may be a compressive stress or a tensile stress.

Further, in each of the above manufacturing methods, the value of the internal stress in the conductive film is preferably ±1 GPa or less. It is known that peeling occurs when the internal stress of the conductive film is strong, and in general, the guideline for suppressing the peeling is ±1 GPa or less. Of course, the occurrence of peeling greatly affects the conditions and the like for forming the conductive film.

Further, in each of the above manufacturing methods, the conductive film is not limited to a single layer and may have a stacked structure of two or more layers.

Further, in each of the above manufacturing methods, an RTA method, a laser annealing method, a thermal annealing method using a furnace annealing furnace, or the like can be applied to the heat treatment.

Further, the heat treatment has a great influence on changes in internal stress in the thin film depending on time and temperature. When the heat treatment time is longer and the heat treatment temperature is higher, the tensile stress is increased when the internal stress in the thin film is tensile stress, and the compressive stress is increased when the internal stress in the thin film is compressive stress. After relaxation, it may have tensile stress. That is, depending on the heat treatment conditions, the internal stress in the thin film may be compressive stress or tensile stress.

The structure of the present invention is shown below.

A semiconductor device having an n-channel TFT, wherein the n-channel TFT has a semiconductor film and a conductive film, the semiconductor film is subjected to tensile stress, and the conductive film has an impurity element introduced therein. Is characterized by.

A semiconductor device having a p-channel TFT, wherein the p-channel TFT has a semiconductor film and a conductive film, the semiconductor film is subjected to compressive stress, and the conductive film has an impurity element introduced therein. Is characterized by.

A semiconductor device having an n-channel TFT and a p-channel TFT, wherein the n-channel TFT includes a first semiconductor film and a first conductive film formed on the first semiconductor film. The p-channel TFT has a second semiconductor film and a second conductive film formed on the second semiconductor film, and the first semiconductor film receives tensile stress. And the second
Is subjected to compressive stress, and an impurity element is introduced into the first conductive film and the second conductive film.

In each of the above structures, the impurity element is not particularly limited, but is preferably one or more elements selected from an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, and a rare gas element. .. The impurity element imparting n-type conductivity and the impurity element imparting p-type conductivity are indispensable in forming a source region and a drain region. Therefore, it is economical because it is not necessary to newly prepare another impurity element. In particular, when an impurity element is introduced into the gate electrode, it can be introduced at the same time as the step of introducing the impurity element into the source region and the drain region, which is preferable because it can be introduced without increasing the number of steps. Further, since the rare gas element is an inert element, it does not affect the electrical characteristics of the TFT, which is preferable.

Further, it is characterized in that a semiconductor device typified by a liquid crystal display device or a light-emitting device is formed by using the TFT having the above-described configurations.

By adopting the configuration of the present invention, the following basic significance can be obtained.
(A) A simple method adapted to the conventional manufacturing process.
(B) It is possible to realize the formation of a wiring having a desired internal stress. Therefore, the stress in other films can also be reduced. Also, the wiring patterning process can be favorably performed.
(C) In addition to satisfying the above advantages, in a semiconductor device typified by an active matrix type liquid crystal display device, the operating characteristics and reliability of the semiconductor device can be improved, and the yield can be improved.

The figure which shows an example of the concept of this invention. The figure which shows an example of the concept of this invention. The figure which shows the example of the amount of change to the direction of the compressive stress by the introduction of an impurity element. The figure which shows the example of the amount of change to the direction of the tensile stress by heat processing. The figure explaining a tensile stress and a compressive stress. The figure which shows an example of the concept of this invention. The figure which shows an example of the concept of this invention. 7A to 7C are cross-sectional views illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. 7A to 7C are cross-sectional views illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. 7A to 7C are cross-sectional views illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. 7A to 7C are cross-sectional views illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. 7A to 7C are cross-sectional views illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. The top view which shows the structure of a pixel TFT. 7A to 7C are cross-sectional views illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. 6A to 6C are cross-sectional views illustrating a manufacturing process of an active matrix liquid crystal display device. 3A and 3B are cross-sectional views of a driver circuit and a pixel portion of a light emitting device. (A) A top view of a light emitting device. FIG. 6B is a cross-sectional structure diagram of a driver circuit and a pixel portion of the light emitting device. FIG. 10 illustrates an example of a semiconductor device. FIG. 10 illustrates an example of a semiconductor device. FIG. 10 illustrates an example of a semiconductor device. Sectional drawing which shows the manufacturing process of MOSFET. Sectional drawing which shows the manufacturing process of MOSFET. Sectional drawing which shows the manufacturing process of MOSFET.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG. In this embodiment, the present invention is applied to the TFT.
The case of application to the gate electrode of is described.

First, the base insulating film 11 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate or a stainless steel substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

As the base insulating film 11, the base insulating film 11 formed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, an example using a single layer structure as the base film 11 is shown, but a structure in which two or more layers of the insulating film are laminated may be used. The base insulating film 1
1 may not be formed.

Next, the semiconductor film 12 is formed on the base insulating film 11. As the semiconductor film 12, a semiconductor film having an amorphous structure is formed by known means (sputtering method, LPCVD method, plasma CVD method, or the like).
Then, a known crystallization process (laser crystallization method, thermal crystallization method, thermal crystallization method using a catalyst such as nickel, etc.) is performed to form a crystalline semiconductor film. This semiconductor film 12
Is formed with a thickness of 25 to 200 nm (preferably 30 to 100 nm). Although the material of the semiconductor film is not limited, it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

Then, the insulating film 13 is formed on the semiconductor film 12. The insulating film 13 is formed by a plasma CVD method, a sputtering method or the like to have a thickness of 40 to 150 nm and a single layer or a laminated structure of an insulating film containing silicon. The insulating film 13 becomes a gate insulating film.

Then, a film thickness of 250 to 600 is formed on the insulating film 13 by using a sputtering method, a plasma CVD method, or the like.
The conductive film 14 having a thickness of 10 nm is formed. Here, an example using a single layer structure as the conductive film 14 is shown, but a structure in which two or more layers of the conductive film are laminated may be used.

However, when the conductive film 14 is formed by the CVD method, the tensile stress 15 may be strong. Therefore, the impurity element is introduced to relax the internal stress in the conductive film 14 to a desired internal stress. The impurity element may be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. As the impurity element to be introduced, one or more elements selected from an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, and a rare gas element are used, and an acceleration voltage of 30 to 120 keV and a dose amount are used. The concentration is 1×10 ^{12 to} 9×10 ¹⁶ /cm ² , and the peak concentration is 1×10 ¹⁷ to 1×10 ²² /cm ³ .
(FIG. 1C) Of course, the optimum impurity element introduction conditions vary depending on the state of the conductive film and desired internal stress. Further, if the impurity element is introduced into only a desired region by using a mask made of resist, it is possible to change the internal stress only in the desired region.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be greatly improved.

[Embodiment 2]
An embodiment of the present invention will be described with reference to FIG. In this embodiment, a case will be described in which the internal stress is controlled by performing heat treatment after introducing the impurity element.

First, according to the first embodiment, an impurity element is introduced.

Subsequently, heat treatment is performed to increase the internal stress in the conductive film 14 if it is a tensile stress, and relax it if it is a compressive stress. The heat treatment may be performed by a known method such as a thermal annealing method using a furnace annealing furnace, a laser annealing method, or an RTA method. For example, if a thermal annealing method using a furnace annealing furnace is performed, it may be exposed to a nitrogen atmosphere at a temperature of about 500 to 1000° C. for about 3 minutes to 12 hours. Of course, the optimum heat treatment conditions vary depending on the state of the conductive film and the desired internal stress. Further, if heat treatment for a long time is performed at the same time as crystallization of a semiconductor film or activation of an impurity element in a manufacturing process of a TFT, it can be performed without increasing the number of steps, which is efficient.

Further, by performing heat treatment only on a desired region by a laser annealing method or the like, it is possible to change the internal stress only in the desired region.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be greatly improved.

[Third Embodiment]
An embodiment of the present invention will be described with reference to FIG. In this embodiment, a case will be described in which the internal stress is controlled by performing heat treatment after introducing the impurity element.

First, according to the first embodiment, formation of the insulating film 13 is performed.

Then, a film thickness of 250 to 600 is formed on the insulating film 13 by using a sputtering method, a plasma CVD method, or the like.
The conductive film 17 having a thickness of 10 nm is formed. Here, an example in which the conductive film 17 has a single-layer structure is shown, but a structure in which two or more conductive films are stacked may be used.

However, the conductive film 17 formed by the sputtering method may have a strong compressive stress 15. Therefore, heat treatment is performed to change the internal stress in the conductive film 17. The heat treatment may be a thermal annealing method using a furnace annealing furnace, an RTA method, a laser annealing method, or the like.
A known method may be used. (Fig. 2(B))

When heat treatment is subsequently performed, the internal stress in the conductive film 14 is increased if it is a tensile stress and relaxed if it is a compressive stress. (FIG. 2C) The heat treatment may be performed by a known method such as a thermal annealing method using a furnace annealing furnace, a laser annealing method, or an RTA method. For example, if a thermal annealing method using a furnace annealing furnace is performed, the temperature is 500 to 10
It may be exposed to a nitrogen atmosphere at about 00° C. for about 3 minutes to 12 hours. Of course, the optimum heat treatment conditions vary depending on the state of the conductive film and the desired internal stress.

Further, the impurity element is introduced to change the internal stress. The impurity element may be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. As the impurity element to be introduced, one or more elements selected from an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, and a rare gas element are used.
120 keV, dose amount 1×10 ^{12 to} 9×10 ¹⁶ /cm ² , peak concentration 1×1
It is performed so as to be 0 ¹⁷ to 1×10 ²² /cm ³ . (FIG. 2D) By introducing an impurity element after heat treatment, the internal stress can be changed with a small dose amount and a low acceleration voltage by channeling.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be greatly improved.

The present invention configured as described above will be described in more detail with reference to the following examples.

Examples of the present invention will be described below, but needless to say, the present invention is not limited to these examples.

An experiment conducted to show the effectiveness of the present invention will be described. Although W (tungsten) is used for the conductive film and Ar is used as the impurity element in this embodiment, the present invention is not particularly limited to these.

First, W was formed with a film thickness of 300 nm on the synthetic quartz substrate 10 by the sputtering method. Then, a silicon nitride oxide film having a film thickness of 70 nm (composition ratio Si=32.8%, O=63.
7%, H=3.5%), heat treatment was performed at 950° C. for 30 minutes. Then, the silicon oxynitride film was removed. The silicon oxynitride film is formed on W in order to prevent W from peeling due to heat treatment. The impurity element is introduced by the ion shower doping method, and the conditions are shown in Table 1. The introduction of the impurity element was performed under three conditions before the heat treatment, after the heat treatment, and after removing the silicon nitride oxide film. The result is shown in FIG. Here, when the change in internal stress is an increase in tensile stress, it is indicated as +, and when it is an increase in compressive stress, it is indicated as −.

From FIG. 3, it can be seen that when Ar is introduced, the internal stress changes in the direction of compressive stress under any condition. When the impurity element is introduced after the heat treatment, the crystallinity is improved by the heat treatment, so that the impurity element is easily introduced deep into the film, and the internal stress largely changes in the compressive stress direction. However, when Ar is introduced through the silicon oxynitride film, a substantial amount of Ar introduced in W is small, so that a change in compressive stress in the direction is small.

Next, FIG. 4 shows changes in internal stress before and after heat treatment in the above experiment. Also, the change in internal stress was investigated when only the heat treatment was performed without introducing the impurity element. From FIG. 4, at the acceleration voltage of 30 keV, the tensile stress increases more than when the impurity element is not introduced. It is considered that the tensile stress due to the heat treatment increased as much as the compressive stress increased due to the introduction of the impurity element. Further, at 80 keV, the change in tensile stress in the direction is small. Therefore, if the accelerating voltage is high, the impurity element is introduced into the film sufficiently deeply, and it is considered that the effect of the heat treatment is small.

As described above, it was confirmed that the introduction of the impurity element increases the compressive stress of the internal stress and the heat treatment increases the tensile stress of the internal stress. That is, the internal stress can be controlled by introducing the impurity element, or by introducing the impurity element and performing heat treatment, and a conductive film having a desired internal stress can be obtained.

In this embodiment, the case where the present invention is applied to a gate electrode of a TFT will be described with reference to FIG.

First, the base insulating film 11 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

As the base insulating film 11, the base insulating film 11 formed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, an example in which a single-layer structure is used as the base insulating film 11 is shown, but a structure in which two or more layers of the insulating film are stacked may be used. Note that the base insulating film may not be formed. In this embodiment, the silicon oxynitride film 11 (
The composition ratio Si=32%, O=27%, N=24%, H=17%) is formed.

Next, after forming a semiconductor film on the base insulating film 11, etching is performed to form the semiconductor layer 20,
You get 21. Here, it is assumed that the semiconductor layer 20 forms an n-channel TFT and the semiconductor layer 21 forms a p-channel TFT. As the semiconductor film, after a semiconductor film having an amorphous structure is formed by a known method (a sputtering method, an LPCVD method, a plasma CVD method, or the like), a known crystallization treatment (a laser crystallization method, a thermal crystallization method) is performed. Or a thermal crystallization method using a catalyst such as nickel) is performed to form a crystalline semiconductor film. The thickness of the semiconductor film 12 is 2
The thickness is 5 to 200 nm (preferably 30 to 100 nm). Although the material of the semiconductor film is not limited, it is preferably formed of silicon or a silicon germanium (SiGe) alloy.
In this embodiment, laser light is irradiated to form a semiconductor film having a crystal structure, and patterning is performed to form the semiconductor layers 20 and 21.

Then, the insulating film 22 that covers the semiconductor layer 12 is formed. The insulating film 22 is formed by a plasma CVD method or a sputtering method to have a thickness of 40 to 150 nm and a single layer or a laminated structure of an insulating film containing silicon. The insulating film 13 becomes a gate insulating film. In this embodiment, a silicon oxynitride film (composition ratio Si=32%, O=59%) having a thickness of 110 nm is formed by the plasma CVD method.
, N=7%, H=2%).

Subsequently, a film thickness of 250 to 600 is formed on the insulating film 22 by using a sputtering method, a plasma CVD method, or the like.
A conductive film 23 having a thickness of 10 nm is formed. Here, an example of using a single layer structure as the conductive film 23 is shown, but a structure in which two or more layers of the conductive film 23 are laminated may be used.
Further, the conductive film may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the above element as a main component. Also,
A semiconductor film typified by a polycrystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Alternatively, an AgPdCu alloy may be used. In this embodiment, the film thickness is 400 nm by the sputtering method.
Forming a Ta film. In addition, a film formed by a sputtering method often has compressive stress.

Then, the conductive film 23 is etched by a patterning process using a photolithography method to form a first conductive film 24 and a second conductive film 25. (Fig. 6 (
B))

Then, the first impurity element is introduced to form the impurity region 27 in the semiconductor film. The impurity element may be introduced by a plasma doping method, an ion implantation method, an ion shower doping method, or the like. In this embodiment, As is used as the impurity element imparting n-type.
Further, in the introduction of the first impurity element, the introduction amount of the first impurity element is set larger than the introduction amount of the impurity element of the second impurity element. By introducing the first impurity element, an impurity region 27 for functioning as an n-channel TFT is formed.
As is introduced into the first conductive film 24 and the second conductive film 25, and the compressive stress 15 increases.

Then, a second impurity element is introduced to form an impurity region 28 in the semiconductor film. At this time, since the semiconductor layer 20 forming the n-channel TFT is covered with the mask 26b made of a resist, the impurity element is not introduced. In this embodiment, B is used as the impurity element imparting p-type. By introducing the second impurity element, a p-channel TFT
Although the impurity region 28 for functioning as is formed, B is also introduced into the second conductive film 25, and the compressive stress 15 of the second conductive film 25 further increases.

In this way, the impurity region is formed, and more impurity elements are introduced into the second conductive film 25 than in the first conductive film 24.

Subsequently, heat treatment is performed to recover the crystallinity of the semiconductor film and activate the impurity element. In addition, the internal stress in the first conductive film 24 and the second conductive film 25 also changes due to the heat treatment. However, since the amounts of the impurity elements introduced into the first conductive film 24 and the second conductive film 25 are different, the internal stress after heat treatment is also different. Since the amount of the impurity element introduced into the first conductive film 24 is small, the tensile stress greatly changes in the increasing direction 16 by the heat treatment, and the internal stress in the first conductive film 24 becomes the tensile stress. for that reason,
The stress received by the semiconductor film forming the n-channel TFT becomes tensile stress. Also, the second
Since the amount of the impurity element introduced into the second conductive film 25 is large, the internal stress does not change much by the heat treatment, and the internal stress in the second conductive film 25 becomes a compressive stress. Therefore, the stress applied to the semiconductor film forming the n-channel TFT becomes a compressive stress.

In this manner, the internal stress of the conductive film is controlled so that the stress received by the semiconductor film forming the n-channel TFT is made tensile stress and the stress received by the semiconductor film forming the p-channel TFT is made compressive stress. You can When a TFT is manufactured using such a semiconductor film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be greatly improved.

In this embodiment, a case where the present invention is applied to wiring of a TFT will be described with reference to FIG.

A base insulating film is formed on a substrate, a semiconductor layer is formed on the base insulating film, an insulating film is formed so as to cover the semiconductor layer, and a conductive layer is formed on the semiconductor layer with the insulating film interposed therebetween. After that, an impurity element is introduced into the semiconductor film using the conductive layer as a mask. Alternatively, the method shown in the second embodiment may be followed.

Subsequently, an interlayer insulating film 29 made of an inorganic insulating film material or an organic insulating material is formed. Although the interlayer insulating film 29 has a single-layer structure in this embodiment, it may have a laminated structure of two or more layers.

Then, a conductive film electrically connected to each impurity region is formed. The conductive film may have high tensile stress. Therefore, an impurity element is introduced to change the internal stress of the conductive film in the direction of increasing the compressive stress. By controlling the internal stress by such a method, a conductive film having an internal stress of ±1 GPa or less can be formed, and patterning is performed to form the wirings 31 to 33.
Prevents the wiring pattern from shifting when forming the wiring pattern.

Further, the internal stress of the conductive layer thus formed is ±1 GPa or less, and the stress exerted on the interlayer insulating film and the semiconductor film can be reduced.
When a TFT is manufactured by using such a conductive layer, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be greatly improved.

In this embodiment, a case where the present invention is applied to a gate electrode of a TFT having a structure different from that of Embodiment 2 will be described with reference to FIG.

First, the conductive film 35 is formed on the substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature may be used.

Further, as the conductive film 35, a sputtering method, a plasma CVD method, or the like is used, and the film thickness is 250 to 6
After the conductive film 20 having a thickness of 00 nm is formed, a patterning process is performed by photolithography to form the conductive film 20. Here, an example in which a single layer structure is used as the conductive film 35 is shown, but a structure in which two or more layers of the conductive film are laminated may be used. Further, as the conductive film, Ta, W, Ti, Mo,
It may be formed of an element selected from Al, Cu, Cr and Nd, or an alloy material or a compound material containing the above element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Alternatively, an AgPdCu alloy may be used. In this embodiment, a film thickness of 40 is formed by the sputtering method.
An Al-Ti film of 0 nm is formed.

Then, an impurity element is introduced to increase the internal stress in the conductive film in the direction of increasing compressive stress.
Change to. This is a process that is performed in advance in order to relax the internal stress because the internal stress in the conductive film changes in the direction of increasing tensile stress due to the heat treatment in the subsequent step.

Then, an insulating film 36 that covers the conductive film 35 is formed. The insulating film 36 is formed by a plasma CVD method or a sputtering method to have a thickness of 40 to 150 nm and a single layer or a laminated structure of an insulating film containing silicon. The insulating film 36 becomes a gate insulating film. In this embodiment, a silicon oxynitride film (composition ratio Si=32%, O=59%, 110 nm thick) is formed by plasma CVD.
N=7%, H=2%).

Next, the semiconductor film 37 is formed on the insulating film 36. As the semiconductor film 37, after a semiconductor film having an amorphous structure is formed by a known method (a sputtering method, an LPCVD method, a plasma CVD method, or the like), a known crystallization treatment (a laser crystallization method, a thermal crystallization method) is performed. Or a thermal crystallization method using a catalyst such as nickel) is performed to form a crystalline semiconductor film. The semiconductor film 37 is formed to have a thickness of 25 to 200 nm (preferably 30 to 100 nm). Although the material of the semiconductor film is not limited, it is preferably formed of silicon or a silicon germanium (SiGe) alloy. In this embodiment, after a 55 nm amorphous silicon film is formed by using the plasma CVD method,
A solution containing nickel is held on the amorphous silicon film. This amorphous silicon film is dehydrogenated (50
After performing 0 degreeC, 1 hour), thermal crystallization (550 degreeC, 4 hours) is performed. By the heat treatment, the semiconductor film 37 becomes a semiconductor film having a crystalline structure. Further, since the impurity element is introduced in advance, the amount of change in internal stress in the conductive film 35 can be small.

The internal stress of the conductive film thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a conductive film, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be greatly improved.

In this embodiment, the present invention is applied to an insulated gate field effect transistor (MOSFET or IG).
An example of a case where a CMOS circuit is configured by applying it to a FET) will be described with reference to FIGS.

First, a single crystal silicon substrate 401 is prepared, an impurity element is injected, and a P-type well 402,
An N-type well 403 is formed. The single crystal silicon substrate may be P-type or N-type. Such a structure is a so-called twin tub structure, and the well concentration is 1×10 ¹⁸ /cm ³ or less (typically 1×10 ^{16 to} 5×10 ¹⁷ /cm ³ ).

Next, after the field oxide film 404 is formed by performing selective oxidation by a known LOCOS method or the like, a 30 nm thick oxide film (later gate insulating film) 4 is formed on the silicon surface by a thermal oxidation process.
Form 05. (Figure 21 (A))

Next, the first gate electrode 406 and the second gate electrode 407 are formed. In this embodiment, a conductive silicon film is used as a material for forming the gate electrode, but Ta,
An element selected from W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy material or a compound material containing the above element as a main component can be used.

After the formation of the first gate electrode 406 and the second gate electrode 407, a region to be a p-channel MOSFET (on the right side in the drawing) is covered with a resist mask 408 so that the single crystal silicon substrate 401 is n-type. The impurity element to be added is introduced. (FIG. 21B) As a method for introducing the impurity element, any one of a laser doping method, a plasma doping method, an ion implantation method, and an ion shower doping method is used, and the concentration is 5×10 ¹⁸ to 1×10 5.
^It is introduced so that it becomes ¹⁹ /cm ³ . In this example, As was used as the impurity element for imparting n-type conductivity.
To use. Part of the impurity regions 410 and 411 thus formed (end portion on the side in contact with the channel formation region) later functions as an LDD region of the n-channel MOSFET.

Next, a region to be the n-channel MOSFET is covered with a resist mask 412.
Then, an impurity element imparting p-type conductivity is introduced into the single crystal silicon substrate 401. (FIG. 21C) In this embodiment, B (boron) is used as the impurity element imparting n-type.
In this manner, the impurity regions 414 and 415 which later function as LDD regions of the p-channel MOSFET are formed.

After the state of FIG. 21C is obtained, next, a silicon oxide film (not shown) is deposited and etched back to form sidewalls 416 and 417. (Figure 22 (A)
)

Next, the region to be a p-channel MOSFET is covered again with a resist mask 418, and an impurity element imparting n-type is introduced at a concentration of 1×10 ²⁰ /cm ³ . Thus the source region 41
9, the drain region 420 is formed, and the LDD region 421 is formed under the sidewall 416. (Figure 22 (B))

Similarly, a region to be an n-channel MOSFET is covered with a resist mask 422, and an impurity element imparting p-type is introduced at a concentration of 1×10 ²⁰ /cm ³ . Thus, the drain region 42
3, the source region 424 is formed, and the LDD region 425 is formed under the sidewall 417. (FIG. 22C) Further, one or more elements selected from rare gas elements are introduced while being covered with the resist mask 422. In this way, the second gate electrode 40
A large amount of the impurity element is introduced into the first gate electrode 406. Thereby, the second
The gate electrode 407 has a compressive stress stronger than that of the first gate electrode 406, and the p-channel type M
The compressive stress received by the channel forming region in the OSFET is also stronger than the stress received by the channel forming region in the n-channel MOSFET.

After the state of FIG. 22C is obtained, first heat treatment is performed to activate the introduced impurity element.

Then, a titanium film is formed and second heat treatment is performed to form a titanium silicide layer 426 on the surfaces of the source region, the drain region, and the gate electrode. Of course, it is also possible to form a metal silicide using another metal film. After forming the silicide layer, the titanium film is removed.

The first gate electrode 406 and the second gate electrode 406 are formed by the first heat treatment and the second heat treatment.
Although the internal stress of the gate electrode 407 also changes, the change in the internal stress is small in the second gate electrode 407 because the amount of the introduced impurity element is larger than that in the first gate electrode 406. Therefore, the second
The gate electrode 407 has a compressive stress stronger than that of the first gate electrode 406.
The compressive stress received by the channel formation region in the FET is also stronger than the stress received by the channel formation region in the n-channel MOSFET.

Next, an interlayer insulating film 427 is formed, contact holes are opened, and source electrodes 428 and 42 are formed.
9, the drain electrode 430 is formed. Of course, it is also effective to perform hydrogenation after forming the electrodes.

Through the steps described above, a CMOS circuit as shown in FIG. 23 can be obtained. The electrical characteristics of the CMOS circuit in which the internal stress of the gate electrode is controlled are good, and the operating characteristics of the semiconductor device can be significantly improved.

In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS. In this specification, a substrate in which a pixel portion including a CMOS circuit and a driver circuit, a pixel TFT, and a storage capacitor is formed over one substrate is referred to as an active matrix substrate for convenience.

First, in this embodiment, a substrate 501 made of glass such as barium borosilicate glass typified by Corning #7059 glass or #1737 glass or aluminoborosilicate glass is used. Note that as the substrate 501, a quartz substrate, a single crystal silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used. In this embodiment, a synthetic quartz glass substrate is used.

Next, a lower light shielding film is formed on the quartz substrate 501. First, a film thickness of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is 10 to 150 nm (preferably 50 to 10 nm).
A base film of 0 nm) is formed. Then, Ta, W, Cr, which can withstand the processing temperature of this embodiment,
A lower light-shielding film is formed with a film thickness of about 300 nm by a conductive material such as Mo and its laminated structure. The lower light-shielding film also has a function as a gate wiring. In this embodiment, a crystalline silicon film having a film thickness of 75 nm is formed, and subsequently, WSix (x=2.0 to 2.8) having a film thickness of 150 nm is formed. 503 is formed. In this example,
Although the lower light-shielding film 503 has a single-layer structure, it may have a structure in which two or more insulating films are laminated.

Then, a base film 504 having a film thickness of 10 to 650 nm (preferably 50 to 600 nm) made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 501 and the lower light-shielding film 503. Although a single-layer structure is used as the base film 504 in this embodiment, a structure in which two or more insulating films are stacked may be used. In this embodiment, as the base film 504, a plasma CVD method is used, and a film thickness of 5 is formed by using SiH ₄ , NH ₃ , and N ₂ O as a reaction gas.
80 nm silicon oxynitride film 504 (composition ratio Si=32%, O=27%, N=24%, H=
17%) at 350°C.

Then, a semiconductor film 505 is formed over the base film 504. As the semiconductor film 505, a semiconductor film having an amorphous structure is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Although the material of the semiconductor film is not limited, it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

Then, a thermal crystallization method using a catalyst such as nickel is performed to crystallize the semiconductor film. In addition to the thermal crystallization method using a catalyst such as nickel, known crystallization treatments (laser crystallization method, thermal crystallization method, etc.) may be combined. In this embodiment, a nickel acetate solution (concentration of weight: 10 ppm, volume: 5 ml) is spin-coated on the entire surface of the film to form a metal-containing layer 405, and the metal-containing layer 405 is exposed to a nitrogen atmosphere at a temperature of 600 degrees for 12 hours.

When the laser crystallization method is also applied, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, a YVO ₄ laser, or the like can be used. In the case of using these lasers, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly focused by an optical system and is applied to a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 800 mJ/cm ² (typically 200 to 700 mJ/cm ² ). When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 1 to 300 Hz, and the laser energy density is set to 300 to 1000 mJ/cm ² (typically 350 to 800 mJ/cm ² ). Then, a laser beam converged linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the overlapping ratio (overlap ratio) of the linear laser beams at this time is set to 50 to 98%. Good.

Subsequently, gettering is performed in order to remove or reduce the metal element used for promoting crystallization from the semiconductor layer to be the active region. Regarding gettering, JP-A-10-27
The method disclosed in Japanese Patent No. 0363 may be applied. In this embodiment, a silicon oxide film having a film thickness of 50 nm is formed as a mask and is patterned to obtain a silicon oxide film 50 having a desired shape.
6a-506d are obtained. Then, an element selectively belonging to Group 15 (typically P
By introducing (phosphorus)) and performing heat treatment, the metal element can be removed from the semiconductor layer or reduced to such an extent that the semiconductor characteristics are not affected. A TFT having an active region manufactured in this manner has a low off-state current value and high crystallinity, which results in high field-effect mobility.
Good properties can be achieved.

Then, the crystalline semiconductor film is etched to form semiconductor layers 507a to 510a. (Fig. 9(D))

Next, it is preferable to remove the masks 506a to 506d, form a new insulating film 511, and perform heat treatment to improve the crystallinity of the semiconductor film to thermally oxidize the upper portion of the semiconductor layer. In this embodiment, a 20 nm silicon oxide film is formed by a low pressure CVD apparatus, and then heat treatment is performed in a furnace annealing furnace. By this treatment, the upper portions of the semiconductor layers 507a to 510a are oxidized. Then, when the oxidized portion of the silicon oxide film and the semiconductor layer is etched, semiconductor layers 507b to 510b with improved crystallinity are obtained.

After forming the semiconductor layers 507b to 510b, a slight amount of impurity element (boron or phosphorus) may be introduced in order to control the threshold value of the TFT.

Next, a first gate insulating film 511 which covers the semiconductor layers 507b to 510b is formed. The first gate insulating film 511 is formed by a plasma CVD method or a sputtering method and has a thickness of 20 to 15
It is formed of an insulating film containing silicon as 0 nm. In this embodiment, the plasma CVD method is used to produce 35
nm silicon oxynitride film (composition ratio Si=32%, O=59%, N=7%, H=2%)
Formed by. Of course, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho
Silica) and O ₂ are mixed, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W/cm ² to discharge. The silicon oxide film produced in this manner can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500° C.

Then, the gate insulating film is partially etched to expose the semiconductor layer 510a which is one of the electrodes of the storage capacitor, and an impurity element is introduced into the semiconductor layer 510a. (Fig. 10 (B
)) At this time, the resist 513 is formed in the other region, and the impurity element is not introduced. In this embodiment, P (phosphorus) is used as the impurity element, and the impurity element is introduced with an acceleration voltage of 10 keV and a dose amount of 5×10 ¹⁴ /cm ² .

Then, a second gate insulating film 512 is formed. The second gate insulating film 512 is formed of an insulating film containing silicon with a thickness of 20 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio Si=32%, O=59%, N=7%, H=2%) having a thickness of 50 nm is formed by the plasma CVD method.
Formed by. Of course, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used.

Then, after forming a contact for connecting to the lower light-shielding film, a first film having a thickness of 20 to 100 nm
And a second conductive film 516a having a film thickness of 100 to 400 nm are stacked.
In this embodiment, the first conductive film 515 made of a TaN film having a film thickness of 30 nm and the film thickness of 370 nm are used.
The second conductive film 516a made of the W film is laminated. The TaN film is formed by the sputtering method,
Sputtering was performed in a nitrogen-containing atmosphere using a Ta target. The W film is formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less.

In the present embodiment, the first conductive film 515 is TaN and the second conductive film 516a is W, but it is not particularly limited, and Ta, W, Ti, Mo, Al, Cu, Cr, Nd are all used. It may be formed of an element selected from the above, or an alloy material or a compound material containing the above element as a main component. Alternatively, a semiconductor film typified by a crystalline silicon film into which an impurity element such as phosphorus is introduced may be used. Alternatively, an AgPdCu alloy may be used. Further, the first conductive film is made of tantalum (Ta).
) Film, the second conductive film is a W film, and the first conductive film is titanium nitride (Ti).
N) film, the second conductive film is a W film, and the first conductive film is tantalum nitride (
A combination of a TaN) film and a second conductive film that is an Al film, a first conductive film that is a tantalum nitride (TaN) film, and a second conductive film that is a Cu film may be used.

Here, in order to make the internal stress in the second conductive film 516a desired, a third impurity element is introduced. The impurity element may be introduced by a plasma doping method, an ion implantation method, or an ion shower doping method. As a result, the compressive stress changes in the increasing direction, and the second conductive film 516b having a desired internal stress can be formed. (Fig. 10 (
D)) In this embodiment, the acceleration voltage is set to 70 keV, and the impurity element is introduced by using Ar.

Next, a resist mask (not shown) is formed using photolithography,
An etching process for forming electrodes and wirings is performed. In this embodiment, as an etching condition, an ICP (Inductively Coupled Plasma) etching method is used,
CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the gas flow rate ratio of each is 25/25/
With 10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-shaped electrode at a pressure of 1 Pa to generate plasma for etching. 150 on the substrate side (sample stage)
RF (13.56MHz) power of W is applied and a substantially negative self-bias voltage is applied.

Then, a fourth impurity element is introduced and an impurity element imparting n-type conductivity is introduced into the semiconductor layer. (FIG. 11A) The conditions for introducing the impurity element are 1×10 ^{13 to} 5×10 ¹⁴ /cm ²
And the acceleration voltage is 30 to 80 keV. In this embodiment, the dose amount is 1.5×10 ^13.
/Cm ² and the accelerating voltage is 60 keV. As the impurity element imparting n-type, an element belonging to Group 15 is used, typically phosphorus (P) or arsenic (As). Here, phosphorus (P) is used.
) Is used. In this case, the conductive layers 517 to 521 serve as masks for the impurity element imparting n-type, and the low concentration impurity regions 523 to 524 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the low-concentration impurity regions 523 to 524 in a concentration range of 1×10 ¹⁸ to 1×10 ²⁰ /cm ³ . Here, a mask 522 made of a resist is formed in the semiconductor layer forming the p-channel TFT, and an impurity element imparting n-type conductivity is not introduced.

Next, the mask made of resist is removed, a new mask is formed, and a fifth impurity element is introduced as shown in FIG. The conditions for introducing the impurity element are a dose amount of 1×10 ¹³ to 1×10 ¹⁵ /cm ² and an acceleration voltage of 30 to 120 keV. At this time, a mask 525b is formed so as not to introduce an impurity element imparting n-type to the semiconductor layer forming the p-channel TFT, and the semiconductor layer for forming the n-channel TFT is selectively high-concentrated. Masks 525a and 525c are formed to form impurity regions. In this embodiment, the dose amount is set to 2×10 ¹⁵ /cm ² and the acceleration voltage is set to 50 keV. Thus, the high concentration impurity regions 526 and 529 are formed.

Next, after removing the resist mask, a new resist mask 532 is formed.
After forming a and 532b, as shown in FIG. 11C, a sixth impurity element is introduced. The introduction of the sixth impurity element forms an impurity region 533 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to a semiconductor layer which is an active layer of a p-channel TFT. The second conductive layer 518 is used as a mask for the impurity element, and an impurity element imparting p-type conductivity is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity region 533 is used.
Is formed by an ion shower doping method using diborane (B ₂ H ₆ ). The conditions of the ion shower doping method are a dose amount of 1×10 ¹³ to 1×10 ¹⁴ /cm ² and an acceleration voltage of 30 to 1
It is performed as 20 keV. When the sixth impurity element is introduced, the semiconductor layer forming the n-channel TFT is covered with resist masks 532a and 532b.

Next, the mask made of resist is removed, a new mask is formed, and a seventh impurity element is introduced as shown in FIG. The conditions for introducing the impurity element are a dose amount of 1×10 ¹³ to 1×10 ¹⁵ /cm ² and an acceleration voltage of 20 to 120 keV. At this time, masks 534a and 534c are formed in order to prevent the introduction of the impurity element imparting p-type into the semiconductor layer forming the n-channel TFT, and the semiconductor layer for forming the p-channel TFT is selectively formed. A mask 534b is formed to form a high concentration impurity region. In this embodiment, the dose amount is set to 1×10 ¹⁵ /cm ² and the acceleration voltage is set to 40 keV. Thus, the high concentration impurity region 535 is formed.

Through the above steps, the high-concentration impurity region and the low-concentration impurity region are formed in each semiconductor layer.

Then, the mask 534 made of resist is removed to form a first interlayer insulating film 538. The first interlayer insulating film 538 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method.
In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method. Of course, the first interlayer insulating film 538 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Next, as shown in FIG. 12B, heat treatment is performed to recover the crystallinity of the semiconductor layers and activate the impurity elements added to the respective semiconductor layers. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, 400 to 700° C., typically 500 to 55, in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less.
The activation treatment may be performed at 0° C. In this embodiment, the activation treatment is performed by heat treatment at 550° C. for 4 hours. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA
Law) can be applied.

In addition, heat treatment may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, heat treatment is performed after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) to protect the wiring and the like as in this embodiment. Is preferably performed.

When heat treatment (heat treatment at 300 to 550° C. for 1 to 12 hours) is performed, hydrogenation can be performed. This step is a step of terminating the dangling bond of the semiconductor layer with hydrogen contained in the first interlayer insulating film 461. Of course, the semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. As other means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or 300 to 450 in an atmosphere containing 3 to 100% hydrogen is used.
You may perform heat processing for 1 to 12 hours at (degreeC).

Then, a second interlayer insulating film 539 made of an inorganic insulating film material or an organic insulating material is formed over the first interlayer insulating film 538. In this embodiment, a silicon nitride oxide film with a thickness of 1 μm is formed.

Then, in the driver circuit 555, the wiring 54 electrically connected to each impurity region
0 to 542 are formed. In the pixel portion 556, source wirings 543 and 545 and a drain electrode 544 are formed. Note that these wirings have a Ti film with a thickness of 50 nm and a film thickness of 5
A laminated film of an alloy film of 00 nm (alloy film of Al and Ti) is formed by patterning.

FIG. 13 shows a top view of the state manufactured up to this point. The same reference numerals are used for the portions corresponding to FIGS. 9 to 12. The chain line AA′ in FIG. 12C corresponds to the cross-sectional view taken along the chain line AA′ in FIG. 13. A chain line BB′ in FIG. 12C corresponds to a cross-sectional view taken along the chain line BB′ in FIG. 13.

Next, a third interlayer insulating film 560 made of an inorganic insulating film material or an organic insulating material is formed over the second interlayer insulating film 539. In this embodiment, a silicon nitride oxide film with a thickness of 1.8 μm is formed.

A light-shielding film 561 or 562 is formed by patterning a film having a high light-shielding property such as Al, Ti, W, Cr, or black resin on the third interlayer insulating film 539 into a desired shape. This light-shielding film 5
61 and 562 are arranged in a mesh shape so as to shield the portions other than the opening of the pixel from light. Further, a fourth interlayer insulating film 563 is formed of an inorganic insulating material so as to cover the light shielding film 117.

Then, a contact hole communicating with the connection wiring 544 is formed and a transparent conductive film such as ITO is formed.
The pixel electrodes 564 and 565 are formed by forming a film having a thickness of 00 nm and patterning it into a desired shape.

As described above, an active matrix substrate is completed in which the driving circuit 555 having the n-channel TFT 551 and the p-channel TFT 552, and the pixel portion 556 having the pixel TFT 553 and the storage capacitor 554 are formed on the same substrate.

The internal stress of the gate electrode thus formed becomes a desired internal stress, and the stress exerted on the semiconductor film can be reduced. When a TFT is manufactured using such a gate electrode, its electrical characteristics become good, and the operating characteristics of the semiconductor device can be greatly improved.

Note that this embodiment can be freely combined with Embodiment 2 or Embodiment 3.
Of course, it is also possible to fabricate an active matrix substrate using the TFT formed in the fourth embodiment and the MOSFET formed in the fifth embodiment.

In this example, a process of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Example 6 will be described below. FIG. 15 is used for the description.

First, according to Example 6, after obtaining the active matrix substrate in the state of FIG. 14B, an alignment film 567 is formed on the active matrix substrate and at least on the pixel electrodes 564 and 565, and rubbing treatment is performed. In this embodiment, before forming the alignment film 567, an organic resin film such as an acrylic resin film is patterned to form columnar spacers 572 at desired positions for holding the substrate distance. Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Next, the counter substrate 569 is prepared. Next, the coloring layer 570 and the planarization film 573 are formed over the counter substrate 569.

Next, a counter electrode 576 made of a transparent conductive film was formed on the planarization film 573 at least in the pixel portion, an alignment film 574 was formed over the entire surface of the counter substrate, and a rubbing treatment was performed.

Then, the active matrix substrate in which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 568. A filler is mixed in the sealing material 568, and the two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 575 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material 575. Thus, the reflection type liquid crystal display device shown in FIG. 15 is completed. Then, if necessary, the active matrix substrate or the counter substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, the FPC was attached using a known technique.

In the liquid crystal display device manufactured as described above, since the internal stress of the gate electrode is controlled to a desired value, the stress exerted on the semiconductor film can be reduced, and the operating characteristics of the liquid crystal display device can be reduced. Can also be significantly improved. Then, such a liquid crystal display device can be used as a display portion of various electronic devices.

Note that this embodiment can be freely combined with the second embodiment, the third embodiment, or the sixth embodiment.

In this example, an example of manufacturing a light emitting device using the present invention will be described. In the present specification, the light emitting device includes a display panel in which a light emitting element formed on a substrate is enclosed between the substrate and a cover material, and a display module in which an IC (Integrated Circuit) is mounted on the display panel. It is a generic term. Note that the light emitting element has a layer (light emitting layer) containing an organic compound capable of obtaining luminescence (Electro Luminescence) generated by applying an electric field, an anode layer, and a cathode layer. Luminescence in organic compounds includes luminescence when returning from a singlet excited state to a ground state (fluorescence) and luminescence when returning from a triplet excited state to a ground state (phosphorescence).
And includes light emission of either or both of them.

FIG. 16 is a cross-sectional view of the light emitting device of this example. 16, the driver circuit provided on the substrate 700 is formed using the CMOS circuit of FIG. Therefore, for the description of the structure, the description of the n-channel TFT 551 and the p-channel TFT 552 may be referred to, but the internal stress is controlled by introducing Ar into the gate electrodes of the n-channel TFT 551 and the p-channel TFT 552. The stress exerted on the semiconductor film is reduced. Therefore, it is possible to improve the electrical characteristics of the TFT. Although a single gate structure is used in this embodiment, a double gate structure or a triple gate structure may be used.

The switching TFT 603 provided on the substrate 700 is an n-channel type T shown in FIG.
It is formed using FT551. Therefore, for the description of the structure, the description of the n-channel TFT 551 may be referred to. However, the internal stress is controlled by introducing Ar into the gate electrode of the n-channel TFT 551, and the stress exerted on the semiconductor film is reduced. is there. Therefore, it is possible to improve the electrical characteristics of the TFT.

Although the double gate structure in which two channel forming regions are formed in this embodiment, a single gate structure in which one channel forming region is formed or a triple gate structure in which three channel forming regions are formed may be used.

The wirings 701 and 703 function as a source wiring of the CMOS circuit and the wiring 702 functions as a drain wiring. The wiring 704 functions as a wiring for electrically connecting a source wiring (not shown) and a source region of the switching TFT, and a wiring 705 electrically connects a drain wiring (not shown) and a drain region of the switching TFT. Function as wiring to connect to.

Note that the current control TFT 604 is formed using the p-channel TFT 552 in FIG. 12C. Therefore, for the description of the structure, refer to the description of the p-channel TFT 552.
Internal stress is controlled by introducing Ar into the gate electrode of the channel type TFT 552,
The stress exerted on the semiconductor film is reduced. Therefore, it is possible to improve the electrical characteristics of the TFT. Although a single gate structure is used in this embodiment, a double gate structure or a triple gate structure may be used.

The wiring 706 is a source wiring (corresponding to a current supply line) of the current control TFT and is an electrode electrically connected to the pixel electrode 711.

Reference numeral 711 is a pixel electrode (anode of a light emitting element) formed of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film. The pixel electrode 711 is formed on the flat interlayer insulating film 710 before forming the wiring. In this embodiment, the flattening film 7 made of resin is used.
It is very important to flatten the step due to the TFT by using 10. Since the light emitting layer formed later is very thin, the light emitting failure may occur due to the presence of the step. Therefore, it is desirable to flatten the light emitting layer before forming the pixel electrode so that the light emitting layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG.
The bank 712 may be formed by patterning an insulating film containing 100 to 400 nm of silicon or an organic resin film.

Since the bank 712 is an insulating film, it is necessary to pay attention to electrostatic breakdown of the element during film formation. In this embodiment, carbon particles or metal particles are added to the insulating film that is the material of the bank 712 to lower the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1×10 ⁶ to 1×1.
The addition amount of carbon particles or metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1×10 ⁸ to 1×10 ¹⁰ Ωm).

A light emitting layer 713 is formed on the pixel electrode 711. Although only one pixel is shown in FIG. 16, light emitting layers corresponding to each color of R (red), G (green), and B (blue) are separately formed in this embodiment. Further, in this embodiment, the low molecular weight organic light emitting material is formed by the vapor deposition method.
Specifically, a 20-nm-thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70-nm-thick tris-8-quinolinolato aluminum complex (Alq ₃
) The film has a laminated structure.
The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene, or DCM1 to Alq ₃ .

However, the above example is an example of an organic light emitting material that can be used as a light emitting layer, and it is not necessary to limit to this. The light emitting layer (charge transporting layer or charge injecting layer) may be freely combined to form a light emitting layer (a layer for emitting light and for moving carriers therefor). For example, although the example in which the low molecular weight organic light emitting material is used as the light emitting layer is shown in this embodiment, a high molecular weight organic light emitting material may be used. Further, it is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer.
Known materials can be used as these organic light emitting materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the light emitting layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, known MgAg film (
An alloy film of magnesium and silver) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

The light emitting element 715 is completed when the cathode 714 is formed. Note that the light-emitting element 715 here refers to a diode formed of the pixel electrode (anode) 711, the light-emitting layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating films are used as a single layer or a stacked layer in which they are combined.

At this time, it is preferable to use a film having good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range of room temperature to 100° C. or lower, it can be easily formed over the light-emitting layer 713 having low heat resistance. Further, the DLC film has a high oxygen blocking effect and can suppress oxidation of the light emitting layer 713. Therefore, it is possible to prevent the problem that the light emitting layer 713 is oxidized during the subsequent sealing step.

Further, a sealing material 717 is provided on the passivation film 716 and a cover material 718 is attached. An ultraviolet curable resin may be used as the sealing material 717, and it is effective to provide a substance having a moisture absorption effect or a substance having an antioxidant effect inside. In this embodiment, the cover material 718 is a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) having carbon films (preferably diamond-like carbon films) formed on both sides.

Thus, the light emitting device having the structure as shown in FIG. 16 is completed. Note that it is effective to continuously perform the steps from the formation of the bank 712 to the formation of the passivation film 716 using a multi-chamber system (or in-line system) film formation apparatus without exposing to the atmosphere. .. Further, it is also possible to further develop and continuously process up to the step of attaching the cover material 718 without exposing to the atmosphere.

Although only the configurations of the pixel portion and the driving circuit are shown in the present embodiment, according to the manufacturing process of the present embodiment, other logic circuits such as a signal dividing circuit, a D/A converter, an operational amplifier and a γ correction circuit are also shown. Can be formed on the same insulator, and further a memory and a microprocessor can be formed.

Further, the light emitting device of this embodiment after the sealing (or encapsulation) step for protecting the light emitting element is performed will be described with reference to FIG. Note that the reference numerals used in FIG. 16 are quoted as needed.

FIG. 17A is a top view showing a state where the light-emitting element is sealed, and FIG. 17B is FIG.
It is sectional drawing which cut|disconnected 7(A) by CC'. Reference numeral 801 indicated by a dotted line is a source side driver circuit, 806 is a pixel portion, and 807 is a gate side driver circuit. 901 is a cover material, and 902
Is a first sealing material, 903 is a second sealing material, and a sealing material 907 is provided inside the first sealing material 902.

Reference numeral 904 denotes a wiring for transmitting a signal input to the source side drive circuit 801 and the gate side drive circuit 807, which receives a video signal and a clock signal from an FPC (flexible printed circuit) 905 which is an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to this FPC. The light emitting device in this specification includes not only the light emitting device body but also the FPC or P
The state in which the WB is attached is also included.

Next, a cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate side driver circuit 807 are formed above the substrate 700, and the pixel portion 806 includes the current control TFT 60.
4 and a pixel electrode 711 electrically connected to its drain. Further, the gate side drive circuit 807 includes an n-channel TFT 601 and a p-channel TFT 6
It is formed by using a CMOS circuit (see FIG. 16) in which 02 and 02 are combined.

The pixel electrode 711 functions as an anode of the light emitting element. Banks 712 are formed at both ends of the pixel electrode 711, and the light emitting layer 713 and the cathode 714 of the light emitting element are formed on the pixel electrode 711.
Is formed.

The cathode 714 also functions as a wiring common to all pixels, and is connected to the FPC 9 via the connection wiring 904.
05 is electrically connected. Further, all the elements included in the pixel portion 806 and the gate side driver circuit 807 are covered with the cathode 714 and the passivation film 567.

Further, the cover material 901 is attached by the first sealing material 902. A spacer made of a resin film may be provided in order to secure a space between the cover material 901 and the light emitting element.
A sealing material 907 is filled inside the first sealing material 902. An epoxy resin is preferably used as the first sealing material 902 and the sealing material 907. Further, it is desirable that the first sealing material 902 is a material that does not allow moisture and oxygen to permeate as much as possible. further,
A substance having a moisture absorption effect or a substance having an antioxidant effect may be contained inside the sealing material 907.

The sealing material 907 provided so as to cover the light emitting element also functions as an adhesive for bonding the cover material 901. Further, in the present embodiment, FRP (Fiberglass-Reinforced Plastics), PVF (Polyvinyl Fluoride), Mylar, polyester or acrylic can be used as the material of the plastic substrate 901a constituting the cover material 901.

Further, after the cover material 901 is bonded using the sealing material 907, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. The second sealing material 903 is the first sealing material 90.
The same material as 2 can be used.

By encapsulating the light emitting element in the sealing material 907 with the above structure, the light emitting element can be completely shielded from the outside, and a substance such as moisture or oxygen which promotes deterioration due to oxidation of the light emitting layer enters from the outside. Can be prevented. Therefore, a highly reliable light emitting device can be obtained.

In the light-emitting device manufactured as described above, since the internal stress of the gate electrode is controlled to a desired value, it is possible to reduce the stress exerted on the semiconductor film and the operating characteristics of the light-emitting device are significantly improved. Can be improved. And such a light emitting device can be used as a display part of various electronic devices.

Note that this embodiment can be freely combined with the second embodiment, the third embodiment, or the sixth embodiment.

The CMOS circuit and the pixel portion formed by applying the present invention can be used for various electro-optical devices (active matrix type liquid crystal display device, active matrix type EC display device, active matrix type light emitting device). That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in the display section.

Such electronic devices include video cameras, digital cameras, projectors, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples of these are shown in FIGS. 18, 19 and 20.

FIG. 18A shows a personal computer, which includes a main body 3001, an image input unit 3002,
A display portion 3003, a keyboard 3004, and the like are included. The present invention can be applied to the display portion 3003.

FIG. 18B illustrates a video camera, which includes a main body 3101, a display portion 3102, a voice input portion 31.
03, operation switch 3104, battery 3105, image receiving unit 3106 and the like. The present invention can be applied to the display portion 3102.

FIG. 18C illustrates a mobile computer (mobile computer), which has a main body 3201.
A camera unit 3202, an image receiving unit 3203, operation switches 3204, a display unit 3205, and the like. The present invention can be applied to the display portion 3205.

FIG. 18D shows a goggle type display which includes a main body 3301, a display portion 3302, an arm portion 3303, and the like. The present invention can be applied to the display portion 3302.

FIG. 18E shows a player using a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, which includes a main body 3401, a display portion 3402, a speaker portion 3403, a recording medium 3404.
Including an operation switch 3405 and the like. This player uses a DVD (Di
It is possible to listen to music, listen to movies, play games, and use the Internet by using a digital versatile disc), a CD, or the like. The present invention can be applied to the display portion 3402.

FIG. 18F illustrates a digital camera, which includes a main body 3501, a display portion 3502, and an eyepiece portion 350.
3, an operation switch 3504, an image receiving unit (not shown), and the like. The present invention can be applied to the display portion 3502.

FIG. 19A shows a front type projector, which includes a projection device 3601 and a screen 36.
Including 02 etc. The present invention can be applied to the liquid crystal display device 3808 which constitutes a part of the projection device 3601 and other drive circuits.

FIG. 19B illustrates a rear type projector, which includes a main body 3701, a projection device 3702, a mirror 3703, a screen 3704, and the like. The present invention can be applied to the liquid crystal display device 3808 which constitutes a part of the projection device 2702 and other drive circuits.

Note that FIG. 19C is a projection device 3601 in FIG. 19A and FIG.
It is a figure which showed an example of the structure of 3702. The projection devices 3601 and 3702 are the light source optical system 3
801, mirrors 3802, 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a retardation plate 3809, and a projection optical system 3810. The projection optical system 2810 is composed of an optical system including a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited and may be, for example, a single-plate type. In addition, the practitioner appropriately uses an optical lens, a film having a polarization function, or a film having a polarization function in the optical path indicated by an arrow in FIG.
An optical system such as a film for adjusting the phase difference or an IR film may be provided.

19D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 19C. In this embodiment, the light source optical system 3801 includes a reflector 3811 and a light source 38.
12, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. The light source optical system shown in FIG. 19D is an example and is not particularly limited.
For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 19, a case where a transmissive electro-optical device is used is shown, and application examples in a reflective electro-optical device and a light emitting device are not shown.

FIG. 20A illustrates a mobile phone including a main body 3901, a voice output portion 3902, and a voice input portion 39.
03, display unit 3904, operation switch 3905, antenna 3906 and the like. The present invention can be applied to the display portion 3904.

FIG. 20B illustrates a portable book (electronic book) including a main body 4001 and display portions 4002 and 400.
3, a storage medium 4004, an operation switch 4005, an antenna 4006 and the like. The present invention can be applied to the display portions 4002 and 4003.

FIG. 20C illustrates a display, which includes a main body 4101, a support base 4102, a display portion 4103.
Including etc. The present invention can be applied to the display portion 4103. The display of the present invention is particularly advantageous when it has a large screen, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. Further, the electronic device of the present embodiment can be realized by using the configuration of any combination of Embodiments 2 to 7. The eighth embodiment can also be applied to the electronic device shown in FIGS. 18 and 20.

Claims (1)

Have a transistor,
The transistor is a display device having a first crystalline semiconductor film in which a channel is formed, a gate electrode, a source electrode, and a drain electrode,
A first conductive film having a mesh shape in a plan view,
A second conductive film, a third conductive film, and a second crystalline semiconductor film arranged below the first conductive film,
The first conductive film has a light-shielding property,
The second conductive film is disposed in the same layer as the drain electrode,
The third conductive film is disposed in the same layer as the gate electrode,
The display device in which the second crystalline semiconductor film is arranged in the same layer as the first crystalline semiconductor film.

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